Index: /ctrl/firmware/Main/CubeMX/charger.ioc
===================================================================
--- /ctrl/firmware/Main/CubeMX/charger.ioc	(revision 9)
+++ /ctrl/firmware/Main/CubeMX/charger.ioc	(revision 10)
@@ -1,679 +1,42 @@
 #MicroXplorer Configuration settings - do not modify
-ADC1.Channel-0\#ChannelRegularConversion=ADC_CHANNEL_14
-ADC1.ClockPrescaler=ADC_CLOCK_ASYNC_DIV4
-ADC1.IPParameters=Rank-0\#ChannelRegularConversion,Channel-0\#ChannelRegularConversion,SamplingTime-0\#ChannelRegularConversion,OffsetNumber-0\#ChannelRegularConversion,OffsetSignedSaturation-0\#ChannelRegularConversion,NbrOfConversionFlag,ClockPrescaler,master
-ADC1.NbrOfConversionFlag=1
-ADC1.OffsetNumber-0\#ChannelRegularConversion=ADC_OFFSET_NONE
-ADC1.OffsetSignedSaturation-0\#ChannelRegularConversion=DISABLE
-ADC1.Rank-0\#ChannelRegularConversion=1
-ADC1.SamplingTime-0\#ChannelRegularConversion=ADC_SAMPLETIME_1CYCLE_5
-ADC1.master=1
-ADC2.Channel-0\#ChannelRegularConversion=ADC_CHANNEL_3
-ADC2.ClockPrescaler=ADC_CLOCK_ASYNC_DIV4
-ADC2.IPParameters=Rank-0\#ChannelRegularConversion,Channel-0\#ChannelRegularConversion,SingleDiff-0\#ChannelRegularConversion,SamplingTime-0\#ChannelRegularConversion,OffsetNumber-0\#ChannelRegularConversion,OffsetSignedSaturation-0\#ChannelRegularConversion,NbrOfConversionFlag,ClockPrescaler
-ADC2.NbrOfConversionFlag=1
-ADC2.OffsetNumber-0\#ChannelRegularConversion=ADC_OFFSET_NONE
-ADC2.OffsetSignedSaturation-0\#ChannelRegularConversion=DISABLE
-ADC2.Rank-0\#ChannelRegularConversion=1
-ADC2.SamplingTime-0\#ChannelRegularConversion=ADC_SAMPLETIME_1CYCLE_5
-ADC2.SingleDiff-0\#ChannelRegularConversion=ADC_DIFFERENTIAL_ENDED
-ADC3.Channel-0\#ChannelRegularConversion=ADC_CHANNEL_1
-ADC3.ClockPrescaler=ADC_CLOCK_ASYNC_DIV4
-ADC3.IPParameters=Rank-0\#ChannelRegularConversion,Channel-0\#ChannelRegularConversion,SamplingTime-0\#ChannelRegularConversion,OffsetNumber-0\#ChannelRegularConversion,OffsetSign-0\#ChannelRegularConversion,NbrOfConversionFlag,ClockPrescaler
-ADC3.NbrOfConversionFlag=1
-ADC3.OffsetNumber-0\#ChannelRegularConversion=ADC_OFFSET_NONE
-ADC3.OffsetSign-0\#ChannelRegularConversion=ADC3_OFFSET_SIGN_NEGATIVE
-ADC3.Rank-0\#ChannelRegularConversion=1
-ADC3.SamplingTime-0\#ChannelRegularConversion=ADC3_SAMPLETIME_2CYCLES_5
 CAD.formats=
 CAD.pinconfig=
 CAD.provider=
-DAC1.DAC_Channel-DAC_OUT1=DAC_CHANNEL_1
-DAC1.DAC_Channel-DAC_OUT2=DAC_CHANNEL_2
-DAC1.IPParameters=DAC_Channel-DAC_OUT1,DAC_Channel-DAC_OUT2
-FDCAN1.CalculateBaudRateNominal=312500
-FDCAN1.CalculateTimeBitNominal=3200
-FDCAN1.CalculateTimeQuantumNominal=640.0
-FDCAN1.IPParameters=CalculateTimeQuantumNominal,CalculateTimeBitNominal,CalculateBaudRateNominal
+CORTEX_M7.IPParameters=default_mode_Activation
+CORTEX_M7.default_mode_Activation=1
 File.Version=6
 GPIO.groupedBy=
-I2C1.IPParameters=Timing,Timeout
-I2C1.Timeout=0x00008131
-I2C1.Timing=0x00606092
-I2C2.IPParameters=Timing
-I2C2.Timing=0x00606092
 KeepUserPlacement=false
+MMTAppRegionsCount=0
+MMTConfigApplied=false
 Mcu.CPN=STM32H723ZET6
 Mcu.Family=STM32H7
-Mcu.IP0=ADC1
-Mcu.IP1=ADC2
-Mcu.IP10=NVIC
-Mcu.IP11=RCC
-Mcu.IP12=RTC
-Mcu.IP13=SDMMC1
-Mcu.IP14=SPI2
-Mcu.IP15=SPI4
-Mcu.IP16=SYS
-Mcu.IP17=TIM1
-Mcu.IP18=TIM3
-Mcu.IP19=TIM15
-Mcu.IP2=ADC3
-Mcu.IP20=TIM24
-Mcu.IP21=UART5
-Mcu.IP22=UART7
-Mcu.IP23=UART8
-Mcu.IP24=USART2
-Mcu.IP25=USART3
-Mcu.IP26=USART10
-Mcu.IP27=USB_OTG_HS
-Mcu.IP28=VREFBUF
-Mcu.IP3=CORTEX_M7
-Mcu.IP4=DAC1
-Mcu.IP5=DEBUG
-Mcu.IP6=DTS
-Mcu.IP7=FDCAN1
-Mcu.IP8=I2C1
-Mcu.IP9=I2C2
-Mcu.IPNb=29
+Mcu.IP0=CORTEX_M7
+Mcu.IP1=MEMORYMAP
+Mcu.IP2=NVIC
+Mcu.IP3=RCC
+Mcu.IP4=SYS
+Mcu.IPNb=5
 Mcu.Name=STM32H723ZETx
 Mcu.Package=LQFP144
-Mcu.Pin0=PE2
-Mcu.Pin1=PE3
-Mcu.Pin10=PF2
-Mcu.Pin100=PG11
-Mcu.Pin101=PG12
-Mcu.Pin102=PG13
-Mcu.Pin103=PG14
-Mcu.Pin104=PG15
-Mcu.Pin105=PB3(JTDO/TRACESWO)
-Mcu.Pin106=PB4(NJTRST)
-Mcu.Pin107=PB5
-Mcu.Pin108=PB6
-Mcu.Pin109=PB7
-Mcu.Pin11=PF3
-Mcu.Pin110=PB8
-Mcu.Pin111=PB9
-Mcu.Pin112=PE0
-Mcu.Pin113=PE1
-Mcu.Pin114=VP_ADC3_Vbat_Input
-Mcu.Pin115=VP_DTS_VS-DTS
-Mcu.Pin116=VP_RTC_VS_RTC_Activate
-Mcu.Pin117=VP_SYS_VS_Systick
-Mcu.Pin118=VP_VREFBUF_V_VREFBUF
-Mcu.Pin119=VP_STMicroelectronics.X-CUBE-DISPLAY_VS_BoardOoPartJjDISPLAY_3.0.0_3.0.0
-Mcu.Pin12=PF4
-Mcu.Pin120=VP_STMicroelectronics.X-CUBE-DISPLAY_VS_DeviceJjDISPLAY_3.0.0_3.0.0
-Mcu.Pin121=VP_STMicroelectronics.X-CUBE-AZRTOS-H7_VS_RTOSJjThreadX_6.2.1_3.2.0
-Mcu.Pin122=VP_STMicroelectronics.X-CUBE-AZRTOS-H7_VS_FileOoSystemJjFileX_6.2.1_3.2.0
-Mcu.Pin123=VP_STMicroelectronics.X-CUBE-AZRTOS-H7_VS_FileOoSystemJjInterfaces_3.2.0_3.2.0
-Mcu.Pin124=VP_STMicroelectronics.X-CUBE-AZRTOS-H7_VS_USBJjUSBX_6.2.1_3.2.0
-Mcu.Pin13=PF5
-Mcu.Pin14=PF6
-Mcu.Pin15=PF7
-Mcu.Pin16=PF8
-Mcu.Pin17=PF9
-Mcu.Pin18=PF10
-Mcu.Pin19=PH0-OSC_IN
-Mcu.Pin2=PE4
-Mcu.Pin20=PH1-OSC_OUT
-Mcu.Pin21=PC0
-Mcu.Pin22=PC1
-Mcu.Pin23=PC2_C
-Mcu.Pin24=PC3_C
-Mcu.Pin25=PA0
-Mcu.Pin26=PA1
-Mcu.Pin27=PA2
-Mcu.Pin28=PA3
-Mcu.Pin29=PA4
-Mcu.Pin3=PE5
-Mcu.Pin30=PA5
-Mcu.Pin31=PA6
-Mcu.Pin32=PA7
-Mcu.Pin33=PC4
-Mcu.Pin34=PC5
-Mcu.Pin35=PB0
-Mcu.Pin36=PB1
-Mcu.Pin37=PB2
-Mcu.Pin38=PF11
-Mcu.Pin39=PF12
-Mcu.Pin4=PE6
-Mcu.Pin40=PF13
-Mcu.Pin41=PF14
-Mcu.Pin42=PF15
-Mcu.Pin43=PG0
-Mcu.Pin44=PG1
-Mcu.Pin45=PE7
-Mcu.Pin46=PE8
-Mcu.Pin47=PE9
-Mcu.Pin48=PE10
-Mcu.Pin49=PE11
-Mcu.Pin5=PC13
-Mcu.Pin50=PE12
-Mcu.Pin51=PE13
-Mcu.Pin52=PE14
-Mcu.Pin53=PE15
-Mcu.Pin54=PB10
-Mcu.Pin55=PB11
-Mcu.Pin56=PB12
-Mcu.Pin57=PB13
-Mcu.Pin58=PB14
-Mcu.Pin59=PB15
-Mcu.Pin6=PC14-OSC32_IN
-Mcu.Pin60=PD8
-Mcu.Pin61=PD9
-Mcu.Pin62=PD10
-Mcu.Pin63=PD11
-Mcu.Pin64=PD12
-Mcu.Pin65=PD13
-Mcu.Pin66=PD14
-Mcu.Pin67=PD15
-Mcu.Pin68=PG2
-Mcu.Pin69=PG3
-Mcu.Pin7=PC15-OSC32_OUT
-Mcu.Pin70=PG4
-Mcu.Pin71=PG5
-Mcu.Pin72=PG6
-Mcu.Pin73=PG7
-Mcu.Pin74=PG8
-Mcu.Pin75=PC6
-Mcu.Pin76=PC7
-Mcu.Pin77=PC8
-Mcu.Pin78=PC9
-Mcu.Pin79=PA8
-Mcu.Pin8=PF0
-Mcu.Pin80=PA9
-Mcu.Pin81=PA10
-Mcu.Pin82=PA11
-Mcu.Pin83=PA12
-Mcu.Pin84=PA13(JTMS/SWDIO)
-Mcu.Pin85=PA14(JTCK/SWCLK)
-Mcu.Pin86=PA15(JTDI)
-Mcu.Pin87=PC10
-Mcu.Pin88=PC11
-Mcu.Pin89=PC12
-Mcu.Pin9=PF1
-Mcu.Pin90=PD0
-Mcu.Pin91=PD1
-Mcu.Pin92=PD2
-Mcu.Pin93=PD3
-Mcu.Pin94=PD4
-Mcu.Pin95=PD5
-Mcu.Pin96=PD6
-Mcu.Pin97=PD7
-Mcu.Pin98=PG9
-Mcu.Pin99=PG10
-Mcu.PinsNb=125
-Mcu.ThirdParty0=STMicroelectronics.X-CUBE-AZRTOS-H7.3.2.0
-Mcu.ThirdParty1=STMicroelectronics.X-CUBE-DISPLAY.3.0.0
-Mcu.ThirdPartyNb=2
-Mcu.UserConstants=NAME,SINGLE_WIRE_TEMP
+Mcu.Pin0=VP_SYS_VS_Systick
+Mcu.Pin1=VP_MEMORYMAP_VS_MEMORYMAP
+Mcu.PinsNb=2
+Mcu.ThirdPartyNb=0
+Mcu.UserConstants=
 Mcu.UserName=STM32H723ZETx
-MxCube.Version=6.10.0
-MxDb.Version=DB.6.0.100
-NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false\:false
-NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false\:false
+MxCube.Version=6.13.0
+MxDb.Version=DB.6.0.130
+NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
+NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
 NVIC.ForceEnableDMAVector=true
-NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false\:false
-NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false\:false
-NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false\:false
-NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:false\:false\:false\:false\:false
+NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
+NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
+NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
+NVIC.PendSV_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
 NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4
-NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:false\:false\:false\:false\:false
-NVIC.SavedPendsvIrqHandlerGenerated=true
-NVIC.SavedSvcallIrqHandlerGenerated=true
-NVIC.SavedSystickIrqHandlerGenerated=true
-NVIC.SysTick_IRQn=true\:0\:0\:false\:false\:false\:false\:false\:true\:false
-NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false\:false
-PA0.GPIOParameters=GPIO_Label
-PA0.GPIO_Label=ADC1_INP16_I_OUT_MPP2+
-PA0.Mode=IN16-Differential
-PA0.Signal=ADC1_INP16
-PA1.GPIOParameters=GPIO_Label
-PA1.GPIO_Label=ADC1_INN16_I_OUT_MPP2-
-PA1.Mode=IN16-Differential
-PA1.Signal=ADC1_INN16
-PA10.GPIOParameters=GPIO_Label
-PA10.GPIO_Label=GPIO_OUTPUT_USB_PWR_EN
-PA10.Locked=true
-PA10.Signal=GPIO_Output
-PA11.Mode=Device_Only_FS
-PA11.Signal=USB_OTG_HS_DM
-PA12.Mode=Device_Only_FS
-PA12.Signal=USB_OTG_HS_DP
-PA13(JTMS/SWDIO).Mode=Trace_Asynchronous_SW
-PA13(JTMS/SWDIO).Signal=DEBUG_JTMS-SWDIO
-PA14(JTCK/SWCLK).Mode=Trace_Asynchronous_SW
-PA14(JTCK/SWCLK).Signal=DEBUG_JTCK-SWCLK
-PA15(JTDI).GPIOParameters=GPIO_Label
-PA15(JTDI).GPIO_Label=UART7_1WIRE_TEMP
-PA15(JTDI).Locked=true
-PA15(JTDI).Mode=Half_duplex(single_wire_mode)
-PA15(JTDI).Signal=UART7_TX
-PA2.GPIOParameters=GPIO_Label
-PA2.GPIO_Label=ADC1_INP14_U_IN_MPP2
-PA2.Signal=ADCx_INP14
-PA3.GPIOParameters=GPIO_Label
-PA3.GPIO_Label=ADC1_INP15_U_IN_MPP1
-PA3.Signal=ADCx_INP15
-PA4.Signal=COMP_DAC11_group
-PA5.Signal=COMP_DAC12_group
-PA6.GPIOParameters=GPIO_Label
-PA6.GPIO_Label=ADC2_INP3_I_OUT_MPP1+
-PA6.Locked=true
-PA6.Signal=ADCx_INP3
-PA7.GPIOParameters=GPIO_Label
-PA7.GPIO_Label=ADC2_INN3_I_OUT_MPP1-
-PA7.Locked=true
-PA7.Signal=ADCx_INN3
-PA8.GPIOParameters=GPIO_Label
-PA8.GPIO_Label=GPIO_INPUT_DETECT_SD
-PA8.Locked=true
-PA8.Signal=GPIO_Input
-PA9.GPIOParameters=GPIO_Label
-PA9.GPIO_Label=USB_UFP
-PA9.Locked=true
-PA9.Signal=GPIO_Input
-PB0.GPIOParameters=GPIO_Label
-PB0.GPIO_Label=ADC2_INN5_U_BATT-
-PB0.Signal=ADCx_INN5
-PB1.GPIOParameters=GPIO_Label
-PB1.GPIO_Label=ADC2_INP5_U_BATT+
-PB1.Signal=ADCx_INP5
-PB10.GPIOParameters=GPIO_Label
-PB10.GPIO_Label=SPI2_SCK_ETH
-PB10.Mode=Full_Duplex_Master
-PB10.Signal=SPI2_SCK
-PB11.GPIOParameters=GPIO_Label
-PB11.GPIO_Label=GPIO_OUT_OUTPUT_CTRL
-PB11.Locked=true
-PB11.Signal=GPIO_Output
-PB12.GPIOParameters=GPIO_Label
-PB12.GPIO_Label=UART5_RX_EXP
-PB12.Mode=Asynchronous
-PB12.Signal=UART5_RX
-PB13.GPIOParameters=GPIO_Label
-PB13.GPIO_Label=UART5_TX_EXP
-PB13.Locked=true
-PB13.Mode=Asynchronous
-PB13.Signal=UART5_TX
-PB14.GPIOParameters=GPIO_Label
-PB14.GPIO_Label=SPI2_MISO_ETH
-PB14.Locked=true
-PB14.Mode=Full_Duplex_Master
-PB14.Signal=SPI2_MISO
-PB15.GPIOParameters=GPIO_Label
-PB15.GPIO_Label=SPI2_MOSI_ETH
-PB15.Locked=true
-PB15.Mode=Full_Duplex_Master
-PB15.Signal=SPI2_MOSI
-PB2.GPIOParameters=GPIO_Label
-PB2.GPIO_Label=GPIO_OUT_M_SWITCH
-PB2.Locked=true
-PB2.Signal=GPIO_Output
-PB3(JTDO/TRACESWO).Mode=Trace_Asynchronous_SW
-PB3(JTDO/TRACESWO).Signal=DEBUG_JTDO-SWO
-PB4(NJTRST).GPIOParameters=GPIO_Label
-PB4(NJTRST).GPIO_Label=SPI2_NSS_ETH
-PB4(NJTRST).Mode=NSS_Signal_Hard_Output
-PB4(NJTRST).Signal=SPI2_NSS
-PB5.GPIOParameters=GPIO_Label
-PB5.GPIO_Label=GPIO_OUTPUT_SPI2_EN_EXP
-PB5.Locked=true
-PB5.Signal=GPIO_Output
-PB6.GPIOParameters=GPIO_Label
-PB6.GPIO_Label=I2C1_SCL_BME_EXP
-PB6.Mode=SMBus-two-wire-Interface
-PB6.Signal=I2C1_SCL
-PB7.GPIOParameters=GPIO_Label
-PB7.GPIO_Label=I2C1_SDA_BME_EXP
-PB7.Mode=SMBus-two-wire-Interface
-PB7.Signal=I2C1_SDA
-PB8.GPIOParameters=GPIO_Label
-PB8.GPIO_Label=GPIO_EXTI8_INT_ETH
-PB8.Locked=true
-PB8.Signal=GPXTI8
-PB9.GPIOParameters=GPIO_Label
-PB9.GPIO_Label=GPIO_OUTPUT_RST_ETH
-PB9.Locked=true
-PB9.Signal=GPIO_Output
-PC0.GPIOParameters=GPIO_Label
-PC0.GPIO_Label=ADC3_INP10_U_OUT_MPP1
-PC0.Signal=ADCx_INP10
-PC1.GPIOParameters=GPIO_Label
-PC1.GPIO_Label=ADC3_INP11_U_OUT_MPP2
-PC1.Signal=ADCx_INP11
-PC10.Mode=SD_4_bits_Wide_bus
-PC10.Signal=SDMMC1_D2
-PC11.Mode=SD_4_bits_Wide_bus
-PC11.Signal=SDMMC1_D3
-PC12.Mode=SD_4_bits_Wide_bus
-PC12.Signal=SDMMC1_CK
-PC13.GPIOParameters=GPIO_Label
-PC13.GPIO_Label=GPIO_INPUT_CURRENT_PROTECTION
-PC13.Locked=true
-PC13.Signal=GPIO_Input
-PC14-OSC32_IN.Mode=LSE-External-Oscillator
-PC14-OSC32_IN.Signal=RCC_OSC32_IN
-PC15-OSC32_OUT.Mode=LSE-External-Oscillator
-PC15-OSC32_OUT.Signal=RCC_OSC32_OUT
-PC2_C.GPIOParameters=GPIO_Label
-PC2_C.GPIO_Label=ADC3_INP0_SENSOR_LIGHT
-PC2_C.Mode=IN0-Single-Ended
-PC2_C.Signal=ADC3_INP0
-PC3_C.GPIOParameters=GPIO_Label
-PC3_C.GPIO_Label=ADC3_INP1_SENSOR_TEMP_HEATSINK
-PC3_C.Mode=IN1-Single-Ended
-PC3_C.Signal=ADC3_INP1
-PC4.GPIOParameters=GPIO_Label
-PC4.GPIO_Label=ADC2_INP4_I_OUT+
-PC4.Locked=true
-PC4.Signal=ADCx_INP4
-PC5.GPIOParameters=GPIO_Label
-PC5.GPIO_Label=ADC2_INN4_I_OUT-
-PC5.Locked=true
-PC5.Signal=ADCx_INN4
-PC6.GPIOParameters=GPIO_Label
-PC6.GPIO_Label=TIM3_CH1_FAN_TACHO
-PC6.Locked=true
-PC6.Signal=S_TIM3_CH1
-PC7.GPIOParameters=GPIO_Label
-PC7.GPIO_Label=TIM3_CH2_PWM_FAN
-PC7.Signal=S_TIM3_CH2
-PC8.Mode=SD_4_bits_Wide_bus
-PC8.Signal=SDMMC1_D0
-PC9.Mode=SD_4_bits_Wide_bus
-PC9.Signal=SDMMC1_D1
-PCC.Checker=true
-PCC.Line=STM32H723/733
-PCC.MCU=STM32H723ZETx
-PCC.PartNumber=STM32H723ZETx
-PCC.Seq0=2
-PCC.Seq0.Step0.Average_Current=38.97 mA
-PCC.Seq0.Step0.CPU_Frequency=168 MHz
-PCC.Seq0.Step0.Category=In DS Table
-PCC.Seq0.Step0.DMIPS=359.52002
-PCC.Seq0.Step0.Duration=0.1 ms
-PCC.Seq0.Step0.Frequency=8 MHz
-PCC.Seq0.Step0.Memory=SRAM1/FlashMode-ON/Cache
-PCC.Seq0.Step0.Mode=RUN
-PCC.Seq0.Step0.Oscillator=HSE BYP PLL
-PCC.Seq0.Step0.Peripherals=SDMMC1 ADC1 ADC2 DAC1 FDCAN1 I2C1 I2C2 SPI2 SPI4 TIM1 TIM3 TIM15 TIM24 UART4 UART5 UART7 UART8 UART9 USART2 USART3 USB_OTG_HS ADC3 GPIOA GPIOB GPIOC GPIOD GPIOE GPIOF GPIOG GPIOH SYS VREFBUF
-PCC.Seq0.Step0.SubMode1=DRUN
-PCC.Seq0.Step0.SubMode2=DRUN
-PCC.Seq0.Step0.SubMode3=DRUN
-PCC.Seq0.Step0.TaMax=119.34
-PCC.Seq0.Step0.User's_Consumption=0 mA
-PCC.Seq0.Step0.Vcore=VOS3\: Scale3-Low
-PCC.Seq0.Step0.Vdd=3.3
-PCC.Seq0.Step0.Voltage_Source=Battery
-PCC.Seq0.Step1.Average_Current=94.5 \u00B5A
-PCC.Seq0.Step1.CPU_Frequency=0 Hz
-PCC.Seq0.Step1.Category=In DS Table
-PCC.Seq0.Step1.DMIPS=0.0
-PCC.Seq0.Step1.Duration=0.9 ms
-PCC.Seq0.Step1.Frequency=0 Hz
-PCC.Seq0.Step1.Memory=NA
-PCC.Seq0.Step1.Mode=STOP
-PCC.Seq0.Step1.Oscillator=ALL_CLOCKS_OFF
-PCC.Seq0.Step1.Peripherals=
-PCC.Seq0.Step1.SubMode1=DSTANDBY
-PCC.Seq0.Step1.SubMode2=DSTANDBY
-PCC.Seq0.Step1.SubMode3=DSTOP
-PCC.Seq0.Step1.TaMax=124.99
-PCC.Seq0.Step1.User's_Consumption=0 mA
-PCC.Seq0.Step1.Vcore=SVOS5\: System-Scale5
-PCC.Seq0.Step1.Vdd=3.0
-PCC.Seq0.Step1.Voltage_Source=Battery
-PCC.Series=STM32H7
-PCC.Temperature=25
-PCC.Vdd=3.0
-PD0.Mode=FDCAN_Activate
-PD0.Signal=FDCAN1_RX
-PD1.Mode=FDCAN_Activate
-PD1.Signal=FDCAN1_TX
-PD10.GPIOParameters=GPIO_Label
-PD10.GPIO_Label=GPIO_OUT_GSM_PWR
-PD10.Locked=true
-PD10.Signal=GPIO_Output
-PD11.GPIOParameters=GPIO_Label
-PD11.GPIO_Label=USART3_CTS_GSM
-PD11.Locked=true
-PD11.Mode=CTS_RTS
-PD11.Signal=USART3_CTS
-PD12.GPIOParameters=GPIO_Label
-PD12.GPIO_Label=USART3_RTS_GSM
-PD12.Locked=true
-PD12.Mode=CTS_RTS
-PD12.Signal=USART3_RTS
-PD13.GPIOParameters=GPIO_Label
-PD13.GPIO_Label=GPIO_INPUT_GSM_STATUS
-PD13.Locked=true
-PD13.Signal=GPIO_Input
-PD14.GPIOParameters=GPIO_Label
-PD14.GPIO_Label=GPIO_INPUT_SENSOR1_ID1
-PD14.Locked=true
-PD14.Signal=GPIO_Input
-PD15.GPIOParameters=GPIO_Label
-PD15.GPIO_Label=GPIO_INPUT_SENSOR1_ID2
-PD15.Locked=true
-PD15.Signal=GPIO_Input
-PD2.Mode=SD_4_bits_Wide_bus
-PD2.Signal=SDMMC1_CMD
-PD3.GPIOParameters=GPIO_Label
-PD3.GPIO_Label=GPIO_OUTPUT_ETH_POWER_EN
-PD3.Locked=true
-PD3.Signal=GPIO_Output
-PD4.GPIOParameters=GPIO_Label
-PD4.GPIO_Label=USART2_DE_MODBUS_SLAVE
-PD4.Locked=true
-PD4.Mode=Hardware Flow Control (RS485)
-PD4.Signal=USART2_DE
-PD5.GPIOParameters=GPIO_Label
-PD5.GPIO_Label=USART2_TX_MODBUS_SLAVE
-PD5.Locked=true
-PD5.Mode=Asynchronous
-PD5.Signal=USART2_TX
-PD6.GPIOParameters=GPIO_Label
-PD6.GPIO_Label=USART2_RX_MODBUS_SLAVE_RX
-PD6.Locked=true
-PD6.Mode=Asynchronous
-PD6.Signal=USART2_RX
-PD7.GPIOParameters=GPIO_Label
-PD7.GPIO_Label=GPIO_OUTPUT_LED_OUTPUT_ON
-PD7.Locked=true
-PD7.Signal=GPIO_Output
-PD8.GPIOParameters=GPIO_Label
-PD8.GPIO_Label=USART3_TX_GSM
-PD8.Locked=true
-PD8.Mode=Asynchronous
-PD8.Signal=USART3_TX
-PD9.GPIOParameters=GPIO_Label
-PD9.GPIO_Label=USART3_RX_GSM
-PD9.Locked=true
-PD9.Mode=Asynchronous
-PD9.Signal=USART3_RX
-PE0.Locked=true
-PE0.Mode=Asynchronous
-PE0.Signal=UART8_RX
-PE1.Locked=true
-PE1.Mode=Asynchronous
-PE1.Signal=UART8_TX
-PE10.GPIOParameters=GPIO_Label
-PE10.GPIO_Label=USB_PWR_FAIL
-PE10.Locked=true
-PE10.Signal=GPIO_Input
-PE11.GPIOParameters=GPIO_Label
-PE11.GPIO_Label=SPI4_NSS_DISPLAY
-PE11.Locked=true
-PE11.Mode=NSS_Signal_Hard_Output
-PE11.Signal=SPI4_NSS
-PE12.GPIOParameters=GPIO_Label
-PE12.GPIO_Label=SPI4_SCK_DISPLAY
-PE12.Locked=true
-PE12.Mode=Simplex_Bidirectional_Master
-PE12.Signal=SPI4_SCK
-PE13.GPIOParameters=GPIO_Label
-PE13.GPIO_Label=TIM1_CH3_PWM_DISPLAY_LIGHT
-PE13.Signal=S_TIM1_CH3
-PE14.GPIOParameters=GPIO_Label
-PE14.GPIO_Label=SPI4_MOSI_DISPLAY
-PE14.Locked=true
-PE14.Mode=Simplex_Bidirectional_Master
-PE14.Signal=SPI4_MOSI
-PE15.GPIOParameters=GPIO_Label
-PE15.GPIO_Label=GPIO_OUTPUT_DISPLAY_A0GPIO_OUTPUT_DISPLAY_RST
-PE15.Locked=true
-PE15.Signal=GPIO_Output
-PE2.GPIOParameters=GPIO_Label
-PE2.GPIO_Label=USART10_RX_MODBUS_MASTER
-PE2.Mode=Asynchronous
-PE2.Signal=USART10_RX
-PE3.GPIOParameters=GPIO_Label
-PE3.GPIO_Label=USART10_TX_MODBUS_MASTER
-PE3.Mode=Asynchronous
-PE3.Signal=USART10_TX
-PE4.Mode=Output Compare1 CH1 CH1N
-PE4.Signal=TIM15_CH1N
-PE5.Signal=S_TIM15_CH1
-PE6.GPIOParameters=GPIO_Label
-PE6.GPIO_Label=GPIO_OUTPUT_LED_TX1
-PE6.Locked=true
-PE6.Signal=GPIO_Output
-PE7.GPIOParameters=GPIO_Label
-PE7.GPIO_Label=GPIO_OUTPUT_15V_PWR_EN
-PE7.Locked=true
-PE7.Signal=GPIO_Output
-PE8.Mode=Output Compare1 CH1 CH1N
-PE8.Signal=TIM1_CH1N
-PE9.Signal=S_TIM1_CH1
-PF0.GPIOParameters=GPIO_Label
-PF0.GPIO_Label=I2C2_SDA_EEPROM
-PF0.Mode=I2C
-PF0.Signal=I2C2_SDA
-PF1.GPIOParameters=GPIO_Label
-PF1.GPIO_Label=I2C2_SCL_EEPROM
-PF1.Mode=I2C
-PF1.Signal=I2C2_SCL
-PF10.GPIOParameters=GPIO_Label
-PF10.GPIO_Label=ADC3_INP6_EXT_IN1
-PF10.Mode=IN6-Single-Ended
-PF10.Signal=ADC3_INP6
-PF11.GPIOParameters=GPIO_Label
-PF11.GPIO_Label=TIM24_CH1_OUT1
-PF11.Mode=PWM Generation1 CH1
-PF11.Signal=TIM24_CH1
-PF12.GPIOParameters=GPIO_Label
-PF12.GPIO_Label=TIM24_CH2_OUT2
-PF12.Signal=S_TIM24_CH2
-PF13.GPIOParameters=GPIO_Label
-PF13.GPIO_Label=TIM24_CH3_OUT3
-PF13.Signal=S_TIM24_CH3
-PF14.GPIOParameters=GPIO_Label
-PF14.GPIO_Label=TIM24_CH4_OUT4
-PF14.Signal=S_TIM24_CH4
-PF15.GPIOParameters=GPIO_Label
-PF15.GPIO_Label=GPIO_OUTPUT_4V_PWR_EN
-PF15.Locked=true
-PF15.Signal=GPIO_Output
-PF2.GPIOParameters=GPIO_Label
-PF2.GPIO_Label=GPIO_OUTPUT_CAN_MODE
-PF2.Locked=true
-PF2.Signal=GPIO_Output
-PF3.GPIOParameters=GPIO_Label
-PF3.GPIO_Label=ADC3_INP5_EXT_SHUNT2+
-PF3.Mode=IN5-Differential
-PF3.Signal=ADC3_INP5
-PF4.GPIOParameters=GPIO_Label
-PF4.GPIO_Label=ADC3_INN5_EXT_SHUNT2-
-PF4.Mode=IN5-Differential
-PF4.Signal=ADC3_INN5
-PF5.GPIOParameters=GPIO_Label
-PF5.GPIO_Label=ADC3_INP4_EXT_SHUNT+
-PF5.Mode=IN4-Differential
-PF5.Signal=ADC3_INP4
-PF6.GPIOParameters=GPIO_Label
-PF6.GPIO_Label=ADC3_INN4_EXT_SHUNT1-
-PF6.Mode=IN4-Differential
-PF6.Signal=ADC3_INN4
-PF7.GPIOParameters=GPIO_Label
-PF7.GPIO_Label=ADC3_INP3_EXT_IN4
-PF7.Mode=IN3-Single-Ended
-PF7.Signal=ADC3_INP3
-PF8.GPIOParameters=GPIO_Label
-PF8.GPIO_Label=ADC3_INP7_EXT_IN3
-PF8.Mode=IN7-Single-Ended
-PF8.Signal=ADC3_INP7
-PF9.GPIOParameters=GPIO_Label
-PF9.GPIO_Label=ADC3_INP2_EXT_IN2
-PF9.Mode=IN2-Single-Ended
-PF9.Signal=ADC3_INP2
-PG0.GPIOParameters=GPIO_Label
-PG0.GPIO_Label=GPIO_OUTPUT_5V_PWR_EN
-PG0.Locked=true
-PG0.Signal=GPIO_Output
-PG1.GPIOParameters=GPIO_Label
-PG1.GPIO_Label=GPIO_OUTPUT_10V_PWR_EN
-PG1.Locked=true
-PG1.Signal=GPIO_Output
-PG10.GPIOParameters=GPIO_Label
-PG10.GPIO_Label=GPIO_OUTPUT_LED_CHARGE
-PG10.Locked=true
-PG10.Signal=GPIO_Output
-PG11.GPIOParameters=GPIO_Label
-PG11.GPIO_Label=GPIO_OUTPUT_LED_RX2
-PG11.Locked=true
-PG11.Signal=GPIO_Output
-PG12.GPIOParameters=GPIO_Label
-PG12.GPIO_Label=GPIO_OUTPUT_LED_RX1
-PG12.Locked=true
-PG12.Signal=GPIO_Output
-PG13.GPIOParameters=GPIO_Label
-PG13.GPIO_Label=GPIO_OUTPUT_LED_TX2
-PG13.Locked=true
-PG13.Signal=GPIO_Output
-PG14.GPIOParameters=GPIO_Label
-PG14.GPIO_Label=USART10_DE_MODBUS_MASTER
-PG14.Mode=Hardware Flow Control (RS485)
-PG14.Signal=USART10_DE
-PG15.GPIOParameters=GPIO_Label
-PG15.GPIO_Label=GPIO_OUT_BUZZER
-PG15.Locked=true
-PG15.Signal=GPIO_Output
-PG2.GPIOParameters=GPIO_Label
-PG2.GPIO_Label=GPIO_INPUT_BTN_UP
-PG2.Locked=true
-PG2.Signal=GPIO_Input
-PG3.GPIOParameters=GPIO_Label
-PG3.GPIO_Label=GPIO_INPUT_BTN_DOWN
-PG3.Locked=true
-PG3.Signal=GPIO_Input
-PG4.GPIOParameters=GPIO_Label
-PG4.GPIO_Label=GPIO_INPUT_BTN_LEFT
-PG4.Locked=true
-PG4.Signal=GPIO_Input
-PG5.GPIOParameters=GPIO_Label
-PG5.GPIO_Label=GPIO_INPUT_BTN_RIGHT
-PG5.Locked=true
-PG5.Signal=GPIO_Input
-PG6.GPIOParameters=GPIO_Label
-PG6.GPIO_Label=GPIO_INPUT_BTN_OK
-PG6.Locked=true
-PG6.Signal=GPIO_Input
-PG7.GPIOParameters=GPIO_Label
-PG7.GPIO_Label=GPIO_INPUT_SENSOR2_ID1
-PG7.Locked=true
-PG7.Signal=GPIO_Input
-PG8.GPIOParameters=GPIO_Label
-PG8.GPIO_Label=GPIO_INPUT_SENSOR2_ID2
-PG8.Locked=true
-PG8.Signal=GPIO_Input
-PG9.GPIOParameters=GPIO_Label
-PG9.GPIO_Label=GPIO_OUTPUT_LED_ERROR
-PG9.Locked=true
-PG9.Signal=GPIO_Output
-PH0-OSC_IN.Mode=HSE-External-Oscillator
-PH0-OSC_IN.Signal=RCC_OSC_IN
-PH1-OSC_OUT.Mode=HSE-External-Oscillator
-PH1-OSC_OUT.Signal=RCC_OSC_OUT
+NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
+NVIC.SysTick_IRQn=true\:15\:0\:false\:false\:true\:false\:true\:false
+NVIC.UsageFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false
 PinOutPanel.RotationAngle=0
 ProjectManager.AskForMigrate=true
@@ -686,10 +49,10 @@
 ProjectManager.DeletePrevious=true
 ProjectManager.DeviceId=STM32H723ZETx
-ProjectManager.FirmwarePackage=STM32Cube FW_H7 V1.11.1
+ProjectManager.FirmwarePackage=STM32Cube FW_H7 V1.12.0
 ProjectManager.FreePins=false
 ProjectManager.HalAssertFull=false
 ProjectManager.HeapSize=0x200
 ProjectManager.KeepUserCode=true
-ProjectManager.LastFirmware=false
+ProjectManager.LastFirmware=true
 ProjectManager.LibraryCopy=0
 ProjectManager.MainLocation=Core/Src
@@ -697,6 +60,6 @@
 ProjectManager.PreviousToolchain=
 ProjectManager.ProjectBuild=false
-ProjectManager.ProjectFileName=firmware.ioc
-ProjectManager.ProjectName=firmware
+ProjectManager.ProjectFileName=charger.ioc
+ProjectManager.ProjectName=charger
 ProjectManager.ProjectStructure=
 ProjectManager.RegisterCallBack=
@@ -707,211 +70,72 @@
 ProjectManager.UAScriptBeforePath=
 ProjectManager.UnderRoot=false
-ProjectManager.functionlistsort=1-SystemClock_Config-RCC-false-HAL-false,2-MX_GPIO_Init-GPIO-false-HAL-true,3-MX_ADC1_Init-ADC1-false-HAL-true,4-MX_ADC2_Init-ADC2-false-HAL-true,5-MX_ADC3_Init-ADC3-false-HAL-true,6-MX_DAC1_Init-DAC1-false-HAL-true,7-MX_DTS_Init-DTS-false-HAL-true,8-MX_FDCAN1_Init-FDCAN1-false-HAL-true,9-MX_I2C1_SMBUS_Init-I2C1-false-HAL-true,10-MX_I2C2_Init-I2C2-false-HAL-true,11-MX_RTC_Init-RTC-false-HAL-true,12-MX_SDMMC1_SD_Init-SDMMC1-false-HAL-true,13-MX_SPI2_Init-SPI2-false-HAL-true,14-MX_SPI4_Init-SPI4-false-HAL-true,15-MX_TIM1_Init-TIM1-false-HAL-true,16-MX_TIM3_Init-TIM3-false-HAL-true,17-MX_TIM15_Init-TIM15-false-HAL-true,18-MX_TIM24_Init-TIM24-false-HAL-true,19-MX_UART5_Init-UART5-false-HAL-true,20-MX_UART7_Init-UART7-false-HAL-true,21-MX_USART2_UART_Init-USART2-false-HAL-true,22-MX_USART3_UART_Init-USART3-false-HAL-true,23-MX_USB_OTG_HS_PCD_Init-USB_OTG_HS-false-HAL-true,24-MX_USART10_UART_Init-USART10-false-HAL-true,25-MX_UART8_Init-UART8-false-HAL-true,0-MX_CORTEX_M7_Init-CORTEX_M7-false-HAL-true,0-MX_VREFBUF_Init-VREFBUF-false-HAL-true
-RCC.ADCCLockSelection=RCC_ADCCLKSOURCE_PLL3
-RCC.ADCFreq_Value=25000000
-RCC.AHB12Freq_Value=100000000
-RCC.AHB4Freq_Value=100000000
-RCC.APB1Freq_Value=100000000
-RCC.APB2Freq_Value=100000000
-RCC.APB3Freq_Value=100000000
-RCC.APB4Freq_Value=100000000
-RCC.AXIClockFreq_Value=100000000
+ProjectManager.functionlistsort=1-SystemClock_Config-RCC-false-HAL-false,0-MX_CORTEX_M7_Init-CORTEX_M7-false-HAL-true
+RCC.ADCFreq_Value=129000000
+RCC.AHB12Freq_Value=64000000
+RCC.AHB4Freq_Value=64000000
+RCC.APB1Freq_Value=64000000
+RCC.APB2Freq_Value=64000000
+RCC.APB3Freq_Value=64000000
+RCC.APB4Freq_Value=64000000
+RCC.AXIClockFreq_Value=64000000
 RCC.CECFreq_Value=32000
 RCC.CKPERFreq_Value=64000000
-RCC.CortexFreq_Value=100000000
-RCC.CpuClockFreq_Value=100000000
-RCC.D1CPREFreq_Value=100000000
-RCC.DFSDMACLkFreq_Value=25000000
-RCC.DFSDMFreq_Value=100000000
-RCC.DIVM1=25
-RCC.DIVM2=25
-RCC.DIVM3=25
-RCC.DIVN1=200
-RCC.DIVN2=200
-RCC.DIVN3=200
-RCC.DIVP1Freq_Value=100000000
-RCC.DIVP2Freq_Value=100000000
-RCC.DIVP3=4
-RCC.DIVP3Freq_Value=50000000
-RCC.DIVQ1=8
-RCC.DIVQ1Freq_Value=25000000
-RCC.DIVQ2=4
-RCC.DIVQ2Freq_Value=50000000
-RCC.DIVQ3=8
-RCC.DIVQ3Freq_Value=25000000
-RCC.DIVR1Freq_Value=100000000
-RCC.DIVR2Freq_Value=100000000
-RCC.DIVR3=8
-RCC.DIVR3Freq_Value=25000000
-RCC.FDCANFreq_Value=25000000
-RCC.FMCFreq_Value=100000000
+RCC.CortexFreq_Value=64000000
+RCC.CpuClockFreq_Value=64000000
+RCC.D1CPREFreq_Value=64000000
+RCC.DFSDMACLkFreq_Value=129000000
+RCC.DFSDMFreq_Value=64000000
+RCC.DIVP1Freq_Value=129000000
+RCC.DIVP2Freq_Value=129000000
+RCC.DIVP3Freq_Value=129000000
+RCC.DIVQ1Freq_Value=129000000
+RCC.DIVQ2Freq_Value=129000000
+RCC.DIVQ3Freq_Value=129000000
+RCC.DIVR1Freq_Value=129000000
+RCC.DIVR2Freq_Value=129000000
+RCC.DIVR3Freq_Value=129000000
+RCC.FDCANFreq_Value=129000000
+RCC.FMCFreq_Value=64000000
 RCC.FamilyName=M
-RCC.HCLK3ClockFreq_Value=100000000
-RCC.HCLKFreq_Value=100000000
-RCC.HSE_VALUE=25000000
-RCC.I2C123CLockSelection=RCC_I2C1235CLKSOURCE_PLL3
-RCC.I2C123Freq_Value=25000000
-RCC.I2C4Freq_Value=100000000
-RCC.IPParameters=ADCCLockSelection,ADCFreq_Value,AHB12Freq_Value,AHB4Freq_Value,APB1Freq_Value,APB2Freq_Value,APB3Freq_Value,APB4Freq_Value,AXIClockFreq_Value,CECFreq_Value,CKPERFreq_Value,CortexFreq_Value,CpuClockFreq_Value,D1CPREFreq_Value,DFSDMACLkFreq_Value,DFSDMFreq_Value,DIVM1,DIVM2,DIVM3,DIVN1,DIVN2,DIVN3,DIVP1Freq_Value,DIVP2Freq_Value,DIVP3,DIVP3Freq_Value,DIVQ1,DIVQ1Freq_Value,DIVQ2,DIVQ2Freq_Value,DIVQ3,DIVQ3Freq_Value,DIVR1Freq_Value,DIVR2Freq_Value,DIVR3,DIVR3Freq_Value,FDCANFreq_Value,FMCFreq_Value,FamilyName,HCLK3ClockFreq_Value,HCLKFreq_Value,HSE_VALUE,I2C123CLockSelection,I2C123Freq_Value,I2C4Freq_Value,LPTIM1Freq_Value,LPTIM2Freq_Value,LPTIM345Freq_Value,LPUART1Freq_Value,LTDCFreq_Value,MCO1PinFreq_Value,MCO2PinFreq_Value,PLL3_VCI_Range-AdvancedSettings,PLL3_VCO_SEL-AdvancedSettings,QSPIFreq_Value,RNGFreq_Value,RTCClockSelection,RTCFreq_Value,SAI1Freq_Value,SAI4AFreq_Value,SAI4BFreq_Value,SDMMCFreq_Value,SPDIFRXFreq_Value,SPI123CLockSelection,SPI123Freq_Value,SPI45Freq_Value,SPI6Freq_Value,SWPMI1Freq_Value,SYSCLKFreq_VALUE,SYSCLKSource,Spi45ClockSelection,Tim1OutputFreq_Value,Tim2OutputFreq_Value,TraceFreq_Value,USART16CLockSelection,USART16Freq_Value,USART234578CLockSelection,USART234578Freq_Value,USBFreq_Value,VCO1OutputFreq_Value,VCO2OutputFreq_Value,VCO3OutputFreq_Value,VCOInput1Freq_Value,VCOInput2Freq_Value,VCOInput3Freq_Value
-RCC.LPTIM1Freq_Value=100000000
-RCC.LPTIM2Freq_Value=100000000
-RCC.LPTIM345Freq_Value=100000000
-RCC.LPUART1Freq_Value=100000000
-RCC.LTDCFreq_Value=25000000
+RCC.HCLK3ClockFreq_Value=64000000
+RCC.HCLKFreq_Value=64000000
+RCC.I2C123Freq_Value=64000000
+RCC.I2C4Freq_Value=64000000
+RCC.IPParameters=ADCFreq_Value,AHB12Freq_Value,AHB4Freq_Value,APB1Freq_Value,APB2Freq_Value,APB3Freq_Value,APB4Freq_Value,AXIClockFreq_Value,CECFreq_Value,CKPERFreq_Value,CortexFreq_Value,CpuClockFreq_Value,D1CPREFreq_Value,DFSDMACLkFreq_Value,DFSDMFreq_Value,DIVP1Freq_Value,DIVP2Freq_Value,DIVP3Freq_Value,DIVQ1Freq_Value,DIVQ2Freq_Value,DIVQ3Freq_Value,DIVR1Freq_Value,DIVR2Freq_Value,DIVR3Freq_Value,FDCANFreq_Value,FMCFreq_Value,FamilyName,HCLK3ClockFreq_Value,HCLKFreq_Value,I2C123Freq_Value,I2C4Freq_Value,LPTIM1Freq_Value,LPTIM2Freq_Value,LPTIM345Freq_Value,LPUART1Freq_Value,LTDCFreq_Value,MCO1PinFreq_Value,MCO2PinFreq_Value,QSPIFreq_Value,RNGFreq_Value,RTCFreq_Value,SAI1Freq_Value,SAI4AFreq_Value,SAI4BFreq_Value,SDMMCFreq_Value,SPDIFRXFreq_Value,SPI123Freq_Value,SPI45Freq_Value,SPI6Freq_Value,SWPMI1Freq_Value,SYSCLKFreq_VALUE,Tim1OutputFreq_Value,Tim2OutputFreq_Value,TraceFreq_Value,USART16Freq_Value,USART234578Freq_Value,USBFreq_Value,VCO1OutputFreq_Value,VCO2OutputFreq_Value,VCO3OutputFreq_Value,VCOInput1Freq_Value,VCOInput2Freq_Value,VCOInput3Freq_Value
+RCC.LPTIM1Freq_Value=64000000
+RCC.LPTIM2Freq_Value=64000000
+RCC.LPTIM345Freq_Value=64000000
+RCC.LPUART1Freq_Value=64000000
+RCC.LTDCFreq_Value=129000000
 RCC.MCO1PinFreq_Value=64000000
-RCC.MCO2PinFreq_Value=100000000
-RCC.PLL3_VCI_Range-AdvancedSettings=RCC_PLL3VCIRANGE_0
-RCC.PLL3_VCO_SEL-AdvancedSettings=RCC_PLL3VCOMEDIUM
-RCC.QSPIFreq_Value=100000000
+RCC.MCO2PinFreq_Value=64000000
+RCC.QSPIFreq_Value=64000000
 RCC.RNGFreq_Value=48000000
-RCC.RTCClockSelection=RCC_RTCCLKSOURCE_LSE
-RCC.RTCFreq_Value=32768
-RCC.SAI1Freq_Value=25000000
-RCC.SAI4AFreq_Value=25000000
-RCC.SAI4BFreq_Value=25000000
-RCC.SDMMCFreq_Value=25000000
-RCC.SPDIFRXFreq_Value=25000000
-RCC.SPI123CLockSelection=RCC_SPI123CLKSOURCE_PLL3
-RCC.SPI123Freq_Value=50000000
-RCC.SPI45Freq_Value=50000000
-RCC.SPI6Freq_Value=100000000
-RCC.SWPMI1Freq_Value=100000000
-RCC.SYSCLKFreq_VALUE=100000000
-RCC.SYSCLKSource=RCC_SYSCLKSOURCE_PLLCLK
-RCC.Spi45ClockSelection=RCC_SPI45CLKSOURCE_PLL2
-RCC.Tim1OutputFreq_Value=100000000
-RCC.Tim2OutputFreq_Value=100000000
-RCC.TraceFreq_Value=100000000
-RCC.USART16CLockSelection=RCC_USART16910CLKSOURCE_PLL3
-RCC.USART16Freq_Value=25000000
-RCC.USART234578CLockSelection=RCC_USART234578CLKSOURCE_PLL3
-RCC.USART234578Freq_Value=25000000
-RCC.USBFreq_Value=25000000
-RCC.VCO1OutputFreq_Value=200000000
-RCC.VCO2OutputFreq_Value=200000000
-RCC.VCO3OutputFreq_Value=200000000
-RCC.VCOInput1Freq_Value=1000000
-RCC.VCOInput2Freq_Value=1000000
-RCC.VCOInput3Freq_Value=1000000
-SH.ADCx_INN3.0=ADC2_INN3,IN3-Differential
-SH.ADCx_INN3.ConfNb=1
-SH.ADCx_INN4.0=ADC2_INN4,IN4-Differential
-SH.ADCx_INN4.ConfNb=1
-SH.ADCx_INN5.0=ADC2_INN5,IN5-Differential
-SH.ADCx_INN5.ConfNb=1
-SH.ADCx_INP10.0=ADC3_INP10,IN10-Single-Ended
-SH.ADCx_INP10.ConfNb=1
-SH.ADCx_INP11.0=ADC3_INP11,IN11-Single-Ended
-SH.ADCx_INP11.ConfNb=1
-SH.ADCx_INP14.0=ADC1_INP14,IN14-Single-Ended
-SH.ADCx_INP14.ConfNb=1
-SH.ADCx_INP15.0=ADC1_INP15,IN15-Single-Ended
-SH.ADCx_INP15.ConfNb=1
-SH.ADCx_INP3.0=ADC2_INP3,IN3-Differential
-SH.ADCx_INP3.ConfNb=1
-SH.ADCx_INP4.0=ADC2_INP4,IN4-Differential
-SH.ADCx_INP4.ConfNb=1
-SH.ADCx_INP5.0=ADC2_INP5,IN5-Differential
-SH.ADCx_INP5.ConfNb=1
-SH.COMP_DAC11_group.0=DAC1_OUT1,DAC_OUT1
-SH.COMP_DAC11_group.ConfNb=1
-SH.COMP_DAC12_group.0=DAC1_OUT2,DAC_OUT2
-SH.COMP_DAC12_group.ConfNb=1
-SH.GPXTI8.0=GPIO_EXTI8
-SH.GPXTI8.ConfNb=1
-SH.S_TIM15_CH1.0=TIM15_CH1,Output Compare1 CH1 CH1N
-SH.S_TIM15_CH1.ConfNb=1
-SH.S_TIM1_CH1.0=TIM1_CH1,Output Compare1 CH1 CH1N
-SH.S_TIM1_CH1.ConfNb=1
-SH.S_TIM1_CH3.0=TIM1_CH3,PWM Generation3 CH3
-SH.S_TIM1_CH3.ConfNb=1
-SH.S_TIM24_CH2.0=TIM24_CH2,PWM Generation2 CH2
-SH.S_TIM24_CH2.ConfNb=1
-SH.S_TIM24_CH3.0=TIM24_CH3,PWM Generation3 CH3
-SH.S_TIM24_CH3.ConfNb=1
-SH.S_TIM24_CH4.0=TIM24_CH4,PWM Generation4 CH4
-SH.S_TIM24_CH4.ConfNb=1
-SH.S_TIM3_CH1.0=TIM3_CH1,PWM Generation1 CH1
-SH.S_TIM3_CH1.ConfNb=1
-SH.S_TIM3_CH2.0=TIM3_CH2,Input_Capture2_from_TI2
-SH.S_TIM3_CH2.ConfNb=1
-SPI2.CalculateBaudRate=25.0 MBits/s
-SPI2.Direction=SPI_DIRECTION_2LINES
-SPI2.IPParameters=VirtualType,Mode,Direction,CalculateBaudRate,VirtualNSS
-SPI2.Mode=SPI_MODE_MASTER
-SPI2.VirtualNSS=VM_NSSHARD
-SPI2.VirtualType=VM_MASTER
-SPI4.CalculateBaudRate=25.0 MBits/s
-SPI4.Direction=SPI_DIRECTION_1LINE
-SPI4.IPParameters=VirtualType,Mode,Direction,CalculateBaudRate,VirtualNSS
-SPI4.Mode=SPI_MODE_MASTER
-SPI4.VirtualNSS=VM_NSSHARD
-SPI4.VirtualType=VM_MASTER
-STMicroelectronics.X-CUBE-AZRTOS-H7.3.2.0.FileOoSystemJjFileX_Checked=true
-STMicroelectronics.X-CUBE-AZRTOS-H7.3.2.0.FileOoSystemJjInterfaces_Checked=true
-STMicroelectronics.X-CUBE-AZRTOS-H7.3.2.0.FileXCcFileOoSystemJjFileXJjCore=true
-STMicroelectronics.X-CUBE-AZRTOS-H7.3.2.0.IPParameters=ThreadXCcRTOSJjThreadXJjLowOoPowerOosupport,ThreadXCcRTOSJjThreadXJjPerformanceInfo,ThreadXCcRTOSJjThreadXJjTraceXOosupport,ThreadXCcRTOSJjThreadXJjCore,InterfacesCcFileOoSystemJjFileXOoSDOointerface,FileXCcFileOoSystemJjFileXJjCore,USBXCcUSBJjUSBXJjUXOoDeviceOoClassOoDFU,USBXCcUSBJjUSBXJjUXOoDeviceOoClassOoSTORAGE
-STMicroelectronics.X-CUBE-AZRTOS-H7.3.2.0.InterfacesCcFileOoSystemJjFileXOoSDOointerface=true
-STMicroelectronics.X-CUBE-AZRTOS-H7.3.2.0.RTOSJjThreadX_Checked=true
-STMicroelectronics.X-CUBE-AZRTOS-H7.3.2.0.ThreadXCcRTOSJjThreadXJjCore=true
-STMicroelectronics.X-CUBE-AZRTOS-H7.3.2.0.ThreadXCcRTOSJjThreadXJjLowOoPowerOosupport=true
-STMicroelectronics.X-CUBE-AZRTOS-H7.3.2.0.ThreadXCcRTOSJjThreadXJjPerformanceInfo=true
-STMicroelectronics.X-CUBE-AZRTOS-H7.3.2.0.ThreadXCcRTOSJjThreadXJjTraceXOosupport=true
-STMicroelectronics.X-CUBE-AZRTOS-H7.3.2.0.USBJjUSBX_Checked=true
-STMicroelectronics.X-CUBE-AZRTOS-H7.3.2.0.USBXCcUSBJjUSBXJjUXOoDeviceOoClassOoDFU=true
-STMicroelectronics.X-CUBE-AZRTOS-H7.3.2.0.USBXCcUSBJjUSBXJjUXOoDeviceOoClassOoSTORAGE=true
-STMicroelectronics.X-CUBE-AZRTOS-H7.3.2.0_IsAnAzureRtosMw=true
-STMicroelectronics.X-CUBE-AZRTOS-H7.3.2.0_SwParameter=InterfacesCcFileOoSystemJjFileXOoSDOointerface\:true;ThreadXCcRTOSJjThreadXJjLowOoPowerOosupport\:true;ThreadXCcRTOSJjThreadXJjPerformanceInfo\:true;ThreadXCcRTOSJjThreadXJjTraceXOosupport\:true;FileXCcFileOoSystemJjFileXJjCore\:true;ThreadXCcRTOSJjThreadXJjCore\:true;USBXCcUSBJjUSBXJjUXOoDeviceOoClassOoDFU\:true;USBXCcUSBJjUSBXJjUXOoDeviceOoClassOoSTORAGE\:true;
-STMicroelectronics.X-CUBE-DISPLAY.3.0.0.BoardOoPartJjDISPLAY_Checked=true
-STMicroelectronics.X-CUBE-DISPLAY.3.0.0.DISPLAYCcBoardOoPartJjLCDJjCustom=SPI
-STMicroelectronics.X-CUBE-DISPLAY.3.0.0.DISPLAYCcDeviceJjApplication=CustomIiApplication
-STMicroelectronics.X-CUBE-DISPLAY.3.0.0.DeviceJjDISPLAY_Checked=true
-STMicroelectronics.X-CUBE-DISPLAY.3.0.0.IPParameters=DISPLAYCcBoardOoPartJjLCDJjCustom,DISPLAYCcDeviceJjApplication
-STMicroelectronics.X-CUBE-DISPLAY.3.0.0_IsPackSelfContextualization=true
-STMicroelectronics.X-CUBE-DISPLAY.3.0.0_SwParameter=DISPLAYCcBoardOoPartJjLCDJjCustom\:SPI;DISPLAYCcDeviceJjApplication\:CustomIiApplication;
-TIM1.Channel-Output\ Compare1\ CH1\ CH1N=TIM_CHANNEL_1
-TIM1.Channel-PWM\ Generation3\ CH3=TIM_CHANNEL_3
-TIM1.IPParameters=Channel-Output Compare1 CH1 CH1N,Channel-PWM Generation3 CH3
-TIM15.Channel-Output\ Compare1\ CH1\ CH1N=TIM_CHANNEL_1
-TIM15.IPParameters=Channel-Output Compare1 CH1 CH1N
-TIM24.Channel-PWM\ Generation1\ CH1=TIM_CHANNEL_1
-TIM24.Channel-PWM\ Generation2\ CH2=TIM_CHANNEL_2
-TIM24.Channel-PWM\ Generation3\ CH3=TIM_CHANNEL_3
-TIM24.Channel-PWM\ Generation4\ CH4=TIM_CHANNEL_4
-TIM24.IPParameters=Channel-PWM Generation1 CH1,Channel-PWM Generation2 CH2,Channel-PWM Generation3 CH3,Channel-PWM Generation4 CH4
-TIM3.Channel-Input_Capture2_from_TI2=TIM_CHANNEL_2
-TIM3.Channel-PWM\ Generation1\ CH1=TIM_CHANNEL_1
-TIM3.IPParameters=Channel-PWM Generation1 CH1,Channel-Input_Capture2_from_TI2
-USART10.IPParameters=VirtualMode-Asynchronous,VirtualMode-Hardware Flow Control (RS485)
-USART10.VirtualMode-Asynchronous=VM_ASYNC
-USART10.VirtualMode-Hardware\ Flow\ Control\ (RS485)=VM_ASYNC
-USART2.IPParameters=VirtualMode-Asynchronous,VirtualMode-Hardware Flow Control (RS485)
-USART2.VirtualMode-Asynchronous=VM_ASYNC
-USART2.VirtualMode-Hardware\ Flow\ Control\ (RS485)=VM_ASYNC
-USART3.IPParameters=VirtualMode-Asynchronous
-USART3.VirtualMode-Asynchronous=VM_ASYNC
-USB_OTG_HS.IPParameters=VirtualMode-Device_Only_FS
-USB_OTG_HS.VirtualMode-Device_Only_FS=Device_Only_FS
-VP_ADC3_Vbat_Input.Mode=IN-Vbat
-VP_ADC3_Vbat_Input.Signal=ADC3_Vbat_Input
-VP_DTS_VS-DTS.Mode=DTS
-VP_DTS_VS-DTS.Signal=DTS_VS-DTS
-VP_RTC_VS_RTC_Activate.Mode=RTC_Enabled
-VP_RTC_VS_RTC_Activate.Signal=RTC_VS_RTC_Activate
-VP_STMicroelectronics.X-CUBE-AZRTOS-H7_VS_FileOoSystemJjFileX_6.2.1_3.2.0.Mode=FileOoSystemJjFileX
-VP_STMicroelectronics.X-CUBE-AZRTOS-H7_VS_FileOoSystemJjFileX_6.2.1_3.2.0.Signal=STMicroelectronics.X-CUBE-AZRTOS-H7_VS_FileOoSystemJjFileX_6.2.1_3.2.0
-VP_STMicroelectronics.X-CUBE-AZRTOS-H7_VS_FileOoSystemJjInterfaces_3.2.0_3.2.0.Mode=FileOoSystemJjInterfaces
-VP_STMicroelectronics.X-CUBE-AZRTOS-H7_VS_FileOoSystemJjInterfaces_3.2.0_3.2.0.Signal=STMicroelectronics.X-CUBE-AZRTOS-H7_VS_FileOoSystemJjInterfaces_3.2.0_3.2.0
-VP_STMicroelectronics.X-CUBE-AZRTOS-H7_VS_RTOSJjThreadX_6.2.1_3.2.0.Mode=RTOSJjThreadX
-VP_STMicroelectronics.X-CUBE-AZRTOS-H7_VS_RTOSJjThreadX_6.2.1_3.2.0.Signal=STMicroelectronics.X-CUBE-AZRTOS-H7_VS_RTOSJjThreadX_6.2.1_3.2.0
-VP_STMicroelectronics.X-CUBE-AZRTOS-H7_VS_USBJjUSBX_6.2.1_3.2.0.Mode=USBJjUSBX
-VP_STMicroelectronics.X-CUBE-AZRTOS-H7_VS_USBJjUSBX_6.2.1_3.2.0.Signal=STMicroelectronics.X-CUBE-AZRTOS-H7_VS_USBJjUSBX_6.2.1_3.2.0
-VP_STMicroelectronics.X-CUBE-DISPLAY_VS_BoardOoPartJjDISPLAY_3.0.0_3.0.0.Mode=BoardOoPartJjDISPLAY
-VP_STMicroelectronics.X-CUBE-DISPLAY_VS_BoardOoPartJjDISPLAY_3.0.0_3.0.0.Signal=STMicroelectronics.X-CUBE-DISPLAY_VS_BoardOoPartJjDISPLAY_3.0.0_3.0.0
-VP_STMicroelectronics.X-CUBE-DISPLAY_VS_DeviceJjDISPLAY_3.0.0_3.0.0.Mode=DeviceJjDISPLAY
-VP_STMicroelectronics.X-CUBE-DISPLAY_VS_DeviceJjDISPLAY_3.0.0_3.0.0.Signal=STMicroelectronics.X-CUBE-DISPLAY_VS_DeviceJjDISPLAY_3.0.0_3.0.0
+RCC.RTCFreq_Value=32000
+RCC.SAI1Freq_Value=129000000
+RCC.SAI4AFreq_Value=129000000
+RCC.SAI4BFreq_Value=129000000
+RCC.SDMMCFreq_Value=129000000
+RCC.SPDIFRXFreq_Value=129000000
+RCC.SPI123Freq_Value=129000000
+RCC.SPI45Freq_Value=64000000
+RCC.SPI6Freq_Value=64000000
+RCC.SWPMI1Freq_Value=64000000
+RCC.SYSCLKFreq_VALUE=64000000
+RCC.Tim1OutputFreq_Value=64000000
+RCC.Tim2OutputFreq_Value=64000000
+RCC.TraceFreq_Value=64000000
+RCC.USART16Freq_Value=64000000
+RCC.USART234578Freq_Value=64000000
+RCC.USBFreq_Value=129000000
+RCC.VCO1OutputFreq_Value=258000000
+RCC.VCO2OutputFreq_Value=258000000
+RCC.VCO3OutputFreq_Value=258000000
+RCC.VCOInput1Freq_Value=2000000
+RCC.VCOInput2Freq_Value=2000000
+RCC.VCOInput3Freq_Value=2000000
+VP_MEMORYMAP_VS_MEMORYMAP.Mode=CurAppReg
+VP_MEMORYMAP_VS_MEMORYMAP.Signal=MEMORYMAP_VS_MEMORYMAP
 VP_SYS_VS_Systick.Mode=SysTick
 VP_SYS_VS_Systick.Signal=SYS_VS_Systick
-VP_VREFBUF_V_VREFBUF.Mode=ExternalMode
-VP_VREFBUF_V_VREFBUF.Signal=VREFBUF_V_VREFBUF
 board=custom
Index: /ctrl/firmware/Main/SES/STM32H723ZETx_MemoryMap.xml
===================================================================
--- /ctrl/firmware/Main/SES/STM32H723ZETx_MemoryMap.xml	(revision 10)
+++ /ctrl/firmware/Main/SES/STM32H723ZETx_MemoryMap.xml	(revision 10)
@@ -0,0 +1,10 @@
+<!DOCTYPE Board_Memory_Definition_File>
+<root name="STM32H723ZETx">
+  <MemorySegment name="ITCM_RAM1" start="0x00000000" size="0x00010000" access="Read/Write" />
+  <MemorySegment name="FLASH1" start="0x08000000" size="0x00080000" access="ReadOnly" />
+  <MemorySegment name="DTCM_RAM1" start="0x20000000" size="0x00020000" access="Read/Write" />
+  <MemorySegment name="AXI_RAM1" start="0x24000000" size="0x00020000" access="Read/Write" />
+  <MemorySegment name="RAM1" start="0x30000000" size="0x00008000" access="Read/Write" />
+  <MemorySegment name="RAM2" start="0x38000000" size="0x00004000" access="Read/Write" />
+  <MemorySegment name="Backup_RAM1" start="0x38800000" size="0x00001000" access="Read/Write" />
+</root>
Index: /ctrl/firmware/Main/SES/STM32H723_Registers.xml
===================================================================
--- /ctrl/firmware/Main/SES/STM32H723_Registers.xml	(revision 10)
+++ /ctrl/firmware/Main/SES/STM32H723_Registers.xml	(revision 10)
@@ -0,0 +1,24502 @@
+<!DOCTYPE Register_Definition_File>
+<Processor name="STM32H723" description="STM32H723">
+  <RegisterGroup name="AC" description="Access control" start="0xE000EF90">
+    <Register name="ITCMCR" description="Instruction and Data Tightly-Coupled Memory Control Registers" start="+0x0" size="4" access="Read/Write" reset_value="0X00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="EN" start="0" size="1" />
+      <BitField name="RMW" description="RMW" start="1" size="1" />
+      <BitField name="RETEN" description="RETEN" start="2" size="1" />
+      <BitField name="SZ" description="SZ" start="3" size="4" />
+    </Register>
+    <Register name="DTCMCR" description="Instruction and Data Tightly-Coupled Memory Control Registers" start="+0x4" size="4" access="Read/Write" reset_value="0X00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="EN" start="0" size="1" />
+      <BitField name="RMW" description="RMW" start="1" size="1" />
+      <BitField name="RETEN" description="RETEN" start="2" size="1" />
+      <BitField name="SZ" description="SZ" start="3" size="4" />
+    </Register>
+    <Register name="AHBPCR" description="AHBP Control register" start="+0x8" size="4" access="Read/Write" reset_value="0X00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="EN" start="0" size="1" />
+      <BitField name="SZ" description="SZ" start="1" size="3" />
+    </Register>
+    <Register name="CACR" description="Auxiliary Cache Control register" start="+0xC" size="4" access="Read/Write" reset_value="0X00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SIWT" description="SIWT" start="0" size="1" />
+      <BitField name="ECCEN" description="ECCEN" start="1" size="1" />
+      <BitField name="FORCEWT" description="FORCEWT" start="2" size="1" />
+    </Register>
+    <Register name="AHBSCR" description="AHB Slave Control register" start="+0x10" size="4" access="Read/Write" reset_value="0X00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CTL" description="CTL" start="0" size="2" />
+      <BitField name="TPRI" description="TPRI" start="2" size="9" />
+      <BitField name="INITCOUNT" description="INITCOUNT" start="11" size="5" />
+    </Register>
+    <Register name="ABFSR" description="Auxiliary Bus Fault Status register" start="+0x18" size="4" access="Read/Write" reset_value="0X00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ITCM" description="ITCM" start="0" size="1" />
+      <BitField name="DTCM" description="DTCM" start="1" size="1" />
+      <BitField name="AHBP" description="AHBP" start="2" size="1" />
+      <BitField name="AXIM" description="AXIM" start="3" size="1" />
+      <BitField name="EPPB" description="EPPB" start="4" size="1" />
+      <BitField name="AXIMTYPE" description="AXIMTYPE" start="8" size="2" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="ADC1" description="Analog to Digital Converter" start="0x40022000">
+    <Register name="ADC_ISR" description="ADC interrupt and status register " start="+0x0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ADRDY" description="ADC ready This bit is set by hardware after the ADC has been enabled (bit ADEN=1) and when the ADC reaches a state where it is ready to accept conversion requests. It is cleared by software writing 1 to it." start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="ADC not yet ready to start conversion (or the flag event was already acknowledged and cleared by software)" start="0x0" />
+        <Enum name="B_0x1" description="ADC is ready to start conversion" start="0x1" />
+      </BitField>
+      <BitField name="EOSMP" description="End of sampling flag This bit is set by hardware during the conversion of any channel (only for regular channels), at the end of the sampling phase." start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="not at the end of the sampling phase (or the flag event was already acknowledged and cleared by software)" start="0x0" />
+        <Enum name="B_0x1" description="End of sampling phase reached" start="0x1" />
+      </BitField>
+      <BitField name="EOC" description="End of conversion flag This bit is set by hardware at the end of each regular conversion of a channel when a new data is available in the ADC_DR register. It is cleared by software writing 1 to it or by reading the ADC_DR register" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Regular channel conversion not complete (or the flag event was already acknowledged and cleared by software)" start="0x0" />
+        <Enum name="B_0x1" description="Regular channel conversion complete" start="0x1" />
+      </BitField>
+      <BitField name="EOS" description="End of regular sequence flag This bit is set by hardware at the end of the conversions of a regular sequence of channels. It is cleared by software writing 1 to it." start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Regular Conversions sequence not complete (or the flag event was already acknowledged and cleared by software)" start="0x0" />
+        <Enum name="B_0x1" description="Regular Conversions sequence complete" start="0x1" />
+      </BitField>
+      <BitField name="OVR" description="ADC overrun This bit is set by hardware when an overrun occurs on a regular channel, meaning that a new conversion has completed while the EOC flag was already set. It is cleared by software writing 1 to it." start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No overrun occurred (or the flag event was already acknowledged and cleared by software)" start="0x0" />
+        <Enum name="B_0x1" description="Overrun has occurred" start="0x1" />
+      </BitField>
+      <BitField name="JEOC" description="Injected channel end of conversion flag This bit is set by hardware at the end of each injected conversion of a channel when a new data is available in the corresponding ADC_JDRy register. It is cleared by software writing 1 to it or by reading the corresponding ADC_JDRy register" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Injected channel conversion not complete (or the flag event was already acknowledged and cleared by software)" start="0x0" />
+        <Enum name="B_0x1" description="Injected channel conversion complete" start="0x1" />
+      </BitField>
+      <BitField name="JEOS" description="Injected channel end of sequence flag This bit is set by hardware at the end of the conversions of all injected channels in the group. It is cleared by software writing 1 to it." start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Injected conversion sequence not complete (or the flag event was already acknowledged and cleared by software)" start="0x0" />
+        <Enum name="B_0x1" description="Injected conversions complete" start="0x1" />
+      </BitField>
+      <BitField name="AWD1" description="Analog watchdog 1 flag This bit is set by hardware when the converted voltage crosses the values programmed in the fields LT1[11:0] and HT1[11:0] of ADC_TR1 register. It is cleared by software. writing 1 to it." start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No analog watchdog 1 event occurred (or the flag event was already acknowledged and cleared by software)" start="0x0" />
+        <Enum name="B_0x1" description="Analog watchdog 1 event occurred" start="0x1" />
+      </BitField>
+      <BitField name="AWD2" description="Analog watchdog 2 flag This bit is set by hardware when the converted voltage crosses the values programmed in the fields LT2[7:0] and HT2[7:0] of ADC_TR2 register. It is cleared by software writing 1 to it." start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No analog watchdog 2 event occurred (or the flag event was already acknowledged and cleared by software)" start="0x0" />
+        <Enum name="B_0x1" description="Analog watchdog 2 event occurred" start="0x1" />
+      </BitField>
+      <BitField name="AWD3" description="Analog watchdog 3 flag This bit is set by hardware when the converted voltage crosses the values programmed in the fields LT3[7:0] and HT3[7:0] of ADC_TR3 register. It is cleared by software writing 1 to it." start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No analog watchdog 3 event occurred (or the flag event was already acknowledged and cleared by software)" start="0x0" />
+        <Enum name="B_0x1" description="Analog watchdog 3 event occurred" start="0x1" />
+      </BitField>
+      <BitField name="JQOVF" description="Injected context queue overflow This bit is set by hardware when an Overflow of the Injected Queue of Context occurs. It is cleared by software writing 1 to it. Refer to for more information." start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No injected context queue overflow occurred (or the flag event was already acknowledged and cleared by software)" start="0x0" />
+        <Enum name="B_0x1" description="Injected context queue overflow has occurred" start="0x1" />
+      </BitField>
+      <BitField name="LDORDY" description="ADC LDO output voltage ready bit This bit is set and cleared by hardware. It indicates that the ADC internal LDO output is ready and that the ADC can be enabled or calibrated. Note: Refer to for the availability of the LDO regulator." start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ADC LDO voltage regulator disabled" start="0x0" />
+        <Enum name="B_0x1" description="ADC LDO voltage regulator enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="ADC_IER" description="ADC interrupt enable register " start="+0x4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ADRDYIE" description="ADC ready interrupt enable This bit is set and cleared by software to enable/disable the ADC Ready interrupt. Note: The software is allowed to write this bit only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing)." start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="ADRDY interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="ADRDY interrupt enabled. An interrupt is generated when the ADRDY bit is set." start="0x1" />
+      </BitField>
+      <BitField name="EOSMPIE" description="End of sampling flag interrupt enable for regular conversions This bit is set and cleared by software to enable/disable the end of the sampling phase interrupt for regular conversions. Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no regular conversion is ongoing)." start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="EOSMP interrupt disabled." start="0x0" />
+        <Enum name="B_0x1" description="EOSMP interrupt enabled. An interrupt is generated when the EOSMP bit is set." start="0x1" />
+      </BitField>
+      <BitField name="EOCIE" description="End of regular conversion interrupt enable This bit is set and cleared by software to enable/disable the end of a regular conversion interrupt. Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no regular conversion is ongoing)." start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="EOC interrupt disabled." start="0x0" />
+        <Enum name="B_0x1" description="EOC interrupt enabled. An interrupt is generated when the EOC bit is set." start="0x1" />
+      </BitField>
+      <BitField name="EOSIE" description="End of regular sequence of conversions interrupt enable This bit is set and cleared by software to enable/disable the end of regular sequence of conversions interrupt. Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no regular conversion is ongoing)." start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="EOS interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="EOS interrupt enabled. An interrupt is generated when the EOS bit is set." start="0x1" />
+      </BitField>
+      <BitField name="OVRIE" description="Overrun interrupt enable This bit is set and cleared by software to enable/disable the Overrun interrupt of a regular conversion. Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no regular conversion is ongoing)." start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Overrun interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Overrun interrupt enabled. An interrupt is generated when the OVR bit is set." start="0x1" />
+      </BitField>
+      <BitField name="JEOCIE" description="End of injected conversion interrupt enable This bit is set and cleared by software to enable/disable the end of an injected conversion interrupt. Note: The software is allowed to write this bit only when JADSTART is cleared to 0 (no injected conversion is ongoing)." start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="JEOC interrupt disabled." start="0x0" />
+        <Enum name="B_0x1" description="JEOC interrupt enabled. An interrupt is generated when the JEOC bit is set." start="0x1" />
+      </BitField>
+      <BitField name="JEOSIE" description="End of injected sequence of conversions interrupt enable This bit is set and cleared by software to enable/disable the end of injected sequence of conversions interrupt. Note: The software is allowed to write this bit only when JADSTART=0 (which ensures that no injected conversion is ongoing)." start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="JEOS interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="JEOS interrupt enabled. An interrupt is generated when the JEOS bit is set." start="0x1" />
+      </BitField>
+      <BitField name="AWD1IE" description="Analog watchdog 1 interrupt enable This bit is set and cleared by software to enable/disable the analog watchdog 1 interrupt. Note: The software is allowed to write this bit only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing)." start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Analog watchdog 1 interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Analog watchdog 1 interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="AWD2IE" description="Analog watchdog 2 interrupt enable This bit is set and cleared by software to enable/disable the analog watchdog 2 interrupt. Note: The software is allowed to write this bit only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing)." start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Analog watchdog 2 interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Analog watchdog 2 interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="AWD3IE" description="Analog watchdog 3 interrupt enable This bit is set and cleared by software to enable/disable the analog watchdog 2 interrupt. Note: The software is allowed to write this bit only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing)." start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Analog watchdog 3 interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Analog watchdog 3 interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="JQOVFIE" description="Injected context queue overflow interrupt enable This bit is set and cleared by software to enable/disable the Injected Context Queue Overflow interrupt. Note: The software is allowed to write this bit only when JADSTART=0 (which ensures that no injected conversion is ongoing)." start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Injected Context Queue Overflow interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Injected Context Queue Overflow interrupt enabled. An interrupt is generated when the JQOVF bit is set." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="ADC_CR" description="ADC control register " start="+0x8" size="4" reset_value="0x20000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ADEN" description="ADC enable control This bit is set by software to enable the ADC. The ADC will be effectively ready to operate once the flag ADRDY has been set. It is cleared by hardware when the ADC is disabled, after the execution of the ADDIS command. Note: The software is allowed to set ADEN only when all bits of ADC_CR registers are 0 (ADCAL=0, JADSTART=0, ADSTART=0, ADSTP=0, ADDIS=0 and ADEN=0) except for bit ADVREGEN which must be 1 (and the software must have wait for the startup time of the voltage regulator)" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="ADC is disabled (OFF state)" start="0x0" />
+        <Enum name="B_0x1" description="Write 1 to enable the ADC." start="0x1" />
+      </BitField>
+      <BitField name="ADDIS" description="ADC disable command This bit is set by software to disable the ADC (ADDIS command) and put it into power-down state (OFF state). It is cleared by hardware once the ADC is effectively disabled (ADEN is also cleared by hardware at this time). Note: The software is allowed to set ADDIS only when ADEN=1 and both ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing)" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no ADDIS command ongoing" start="0x0" />
+        <Enum name="B_0x1" description="Write 1 to disable the ADC. Read 1 means that an ADDIS command is in progress. " start="0x1" />
+      </BitField>
+      <BitField name="ADSTART" description="ADC start of regular conversion This bit is set by software to start ADC conversion of regular channels. Depending on the configuration bits EXTEN, a conversion will start immediately (software trigger configuration) or once a regular hardware trigger event occurs (hardware trigger configuration). It is cleared by hardware: in single conversion mode (CONT=0, DISCEN=0) when software trigger is selected (EXTEN=0x0): at the assertion of the End of Regular Conversion Sequence (EOS) flag. In discontinuous conversion mode (CONT=0, DISCEN=1), when the software trigger is selected (EXTEN=0x0): at the end of conversion (EOC) flag. in all other cases: after the execution of the ADSTP command, at the same time that ADSTP is cleared by hardware. Note: The software is allowed to set ADSTART only when ADEN=1 and ADDIS=0 (ADC is enabled and there is no pending request to disable the ADC) In auto-injection mode (JAUTO=1), regular and auto-injected conversions are started by setting bit ADSTART (JADSTART must be kept cleared)" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No ADC regular conversion is ongoing." start="0x0" />
+        <Enum name="B_0x1" description="Write 1 to start regular conversions. Read 1 means that the ADC is operating and eventually converting a regular channel." start="0x1" />
+      </BitField>
+      <BitField name="JADSTART" description="ADC start of injected conversion This bit is set by software to start ADC conversion of injected channels. Depending on the configuration bits JEXTEN, a conversion will start immediately (software trigger configuration) or once an injected hardware trigger event occurs (hardware trigger configuration). It is cleared by hardware: in single conversion mode when software trigger is selected (JEXTSEL=0x0): at the assertion of the End of Injected Conversion Sequence (JEOS) flag. in all cases: after the execution of the JADSTP command, at the same time that JADSTP is cleared by hardware. Note: The software is allowed to set JADSTART only when ADEN=1 and ADDIS=0 (ADC is enabled and there is no pending request to disable the ADC). In auto-injection mode (JAUTO=1), regular and auto-injected conversions are started by setting bit ADSTART (JADSTART must be kept cleared)" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No ADC injected conversion is ongoing." start="0x0" />
+        <Enum name="B_0x1" description="Write 1 to start injected conversions. Read 1 means that the ADC is operating and eventually converting an injected channel." start="0x1" />
+      </BitField>
+      <BitField name="ADSTP" description="ADC stop of regular conversion command This bit is set by software to stop and discard an ongoing regular conversion (ADSTP Command). It is cleared by hardware when the conversion is effectively discarded and the ADC regular sequence and triggers can be re-configured. The ADC is then ready to accept a new start of regular conversions (ADSTART command). Note: The software is allowed to set ADSTP only when ADSTART=1 and ADDIS=0 (ADC is enabled and eventually converting a regular conversion and there is no pending request to disable the ADC). In auto-injection mode (JAUTO=1), setting ADSTP bit aborts both regular and injected conversions (do not use JADSTP). In dual ADC regular simultaneous mode and interleaved mode, the bit ADSTP of the master ADC must be used to stop regular conversions. The other ADSTP bit is inactive." start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No ADC stop regular conversion command ongoing" start="0x0" />
+        <Enum name="B_0x1" description="Write 1 to stop regular conversions ongoing. Read 1 means that an ADSTP command is in progress." start="0x1" />
+      </BitField>
+      <BitField name="JADSTP" description="ADC stop of injected conversion command This bit is set by software to stop and discard an ongoing injected conversion (JADSTP Command). It is cleared by hardware when the conversion is effectively discarded and the ADC injected sequence and triggers can be re-configured. The ADC is then ready to accept a new start of injected conversions (JADSTART command). Note: The software is allowed to set JADSTP only when JADSTART=1 and ADDIS=0 (ADC is enabled and eventually converting an injected conversion and there is no pending request to disable the ADC). In auto-injection mode (JAUTO=1), setting ADSTP bit aborts both regular and injected conversions (do not use JADSTP)" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No ADC stop injected conversion command ongoing" start="0x0" />
+        <Enum name="B_0x1" description="Write 1 to stop injected conversions ongoing. Read 1 means that an ADSTP command is in progress." start="0x1" />
+      </BitField>
+      <BitField name="BOOST" description="Boost mode control This bitfield is set and cleared by software to enable/disable the Boost mode. Note: The software is allowed to write this bit only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing). When dual mode is enabled (bits DAMDF of ADCx_CCR register are not equal to zero), the BOOST bitfield of the slave ADC is no more writable and its content must be equal to the master ADC BOOST bitfield." start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="used when ADC clock ≤ 6.25 MHz" start="0x0" />
+        <Enum name="B_0x1" description="used when 6.25 MHz &lt; ADC clock frequency≤ 12.5 MHz" start="0x1" />
+        <Enum name="B_0x2" description="used when 12.5 MHz &lt; ADC clock ≤25.0 MHz" start="0x2" />
+        <Enum name="B_0x3" description="used when 25.0 MHz &lt; ADC clock ≤ 50.0 MHz" start="0x3" />
+      </BitField>
+      <BitField name="ADCALLIN" description="Linearity calibration This bit is set and cleared by software to enable the Linearity calibration. Note: The software is allowed to write this bit only when the ADC is disabled and is not calibrating (ADCAL=0, JADSTART=0, JADSTP=0, ADSTART=0, ADSTP=0, ADDIS=0 and ADEN=0)." start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Writing ADCAL will launch a calibration without the Linearity calibration." start="0x0" />
+        <Enum name="B_0x1" description="Writing ADCAL will launch a calibration with he Linearity calibration." start="0x1" />
+      </BitField>
+      <BitField name="LINCALRDYW1" description="Linearity calibration ready Word 1 Refer to LINCALRDYW6 description. Note: ADC_CALFACT2[29:0] corresponds linearity correction factor bits[29:0]. The software is allowed to toggle this bit only if the LINCALRDYW6, LINCALRDYW5, LINCALRDYW4, LINCALRDYW3 and LINCALRDYW2 bits are left unchanged." start="22" size="1" access="Read/Write" />
+      <BitField name="LINCALRDYW2" description="Linearity calibration ready Word 2 Refer to LINCALRDYW6 description. Note: ADC_CALFACT2[29:0] corresponds linearity correction factor bits[59:30]. The software is allowed to toggle this bit only if the LINCALRDYW6, LINCALRDYW5, LINCALRDYW4, LINCALRDYW3 and LINCALRDYW1 bits are left unchanged." start="23" size="1" access="Read/Write" />
+      <BitField name="LINCALRDYW3" description="Linearity calibration ready Word 3 Refer to LINCALRDYW6 description. Note: ADC_CALFACT2[29:0] corresponds linearity correction factor bits[89:60]. The software is allowed to toggle this bit only if the LINCALRDYW6, LINCALRDYW5, LINCALRDYW4, LINCALRDYW2 and LINCALRDYW1 bits are left unchanged." start="24" size="1" access="Read/Write" />
+      <BitField name="LINCALRDYW4" description="Linearity calibration ready Word 4 Refer to LINCALRDYW6 description. Note: ADC_CALFACT2[29:0] correspond linearity correction factor bits[119:90]. The software is allowed to toggle this bit only if the LINCALRDYW6, LINCALRDYW5, LINCALRDYW3, LINCALRDYW2 and LINCALRDYW1 bits are left unchanged." start="25" size="1" access="Read/Write" />
+      <BitField name="LINCALRDYW5" description="Linearity calibration ready Word 5 Refer to LINCALRDYW6 description. Note: ADC_CALFACT2[29:0] corresponds linearity correction factor bits[149:120]. The software is allowed to toggle this bit only if the LINCALRDYW6, LINCALRDYW5, LINCALRDYW3, LINCALRDYW2 and LINCALRDYW1 bits are left unchanged." start="26" size="1" access="Read/Write" />
+      <BitField name="LINCALRDYW6" description="Linearity calibration ready Word 6 This control / status bit allows to read/write the 6th linearity calibration factor. When the linearity calibration is complete, this bit is set. A bit clear will launch the transfer of the linearity factor 6 into the LINCALFACT[29:0] of the ADC_CALFACT2 register. The bit will be reset by hardware when the ADC_CALFACT2 register can be read (software must poll the bit until it is cleared). When the LINCALRDYW6 bit is reset, a new linearity factor 6 value can be written into the LINCALFACT[29:0] of the ADC_CALFACT2 register. A bit set will launch the linearity factor 6 update and the bit will be effectively set by hardware once the update will be done (software must poll the bit until it is set to indicate the write is effective). Note: ADC_CALFACT2[29:10] contains 0. ADC_CALFACT2[9:0] corresponds linearity correction factor bits[159:150]. The software is allowed to toggle this bit only if the LINCALRDYW5, LINCALRDYW4, LINCALRDYW3, LINCALRDYW2 and LINCALRDYW1 bits are left unchanged, see chapter for details. The software is allowed to update the linearity calibration factor by writing LINCALRDYWx only when ADEN=1 and ADSTART=0 and JADSTART=0 (ADC enabled and no conversion is ongoing)" start="27" size="1" access="Read/Write" />
+      <BitField name="ADVREGEN" description="ADC voltage regulator enable This bits is set by software to enable the ADC voltage regulator. Before performing any operation such as launching a calibration or enabling the ADC, the ADC voltage regulator must first be enabled and the software must wait for the regulator start-up time. For more details about the ADC voltage regulator enable and disable sequences, refer to (ADVREGEN). The software can program this bitfield only when the ADC is disabled (ADCAL=0, JADSTART=0, ADSTART=0, ADSTP=0, ADDIS=0 and ADEN=0)." start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="ADC Voltage regulator disabled" start="0x0" />
+        <Enum name="B_0x1" description="ADC Voltage regulator enabled." start="0x1" />
+      </BitField>
+      <BitField name="DEEPPWD" description="Deep-power-down enable This bit is set and cleared by software to put the ADC in deep-power-down mode. Note: The software is allowed to write this bit only when the ADC is disabled (ADCAL=0, JADSTART=0, JADSTP=0, ADSTART=0, ADSTP=0, ADDIS=0 and ADEN=0)." start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="ADC not in deep-power down" start="0x0" />
+        <Enum name="B_0x1" description="ADC in deep-power-down (default reset state)" start="0x1" />
+      </BitField>
+      <BitField name="ADCALDIF" description="Differential mode for calibration This bit is set and cleared by software to configure the single-ended or differential inputs mode for the calibration. Note: The software is allowed to write this bit only when the ADC is disabled and is not calibrating (ADCAL=0, JADSTART=0, JADSTP=0, ADSTART=0, ADSTP=0, ADDIS=0 and ADEN=0)." start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Writing ADCAL will launch a calibration in Single-ended inputs Mode." start="0x0" />
+        <Enum name="B_0x1" description="Writing ADCAL will launch a calibration in Differential inputs Mode." start="0x1" />
+      </BitField>
+      <BitField name="ADCAL" description="ADC calibration This bit is set by software to start the calibration of the ADC. Program first the bit ADCALDIF to determine if this calibration applies for single-ended or differential inputs mode. It is cleared by hardware after calibration is complete. Note: The software is allowed to launch a calibration by setting ADCAL only when ADEN=0. The software is allowed to update the calibration factor by writing ADC_CALFACT only when ADEN=1 and ADSTART=0 and JADSTART=0 (ADC enabled and no conversion is ongoing)" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Calibration complete" start="0x0" />
+        <Enum name="B_0x1" description="Write 1 to calibrate the ADC. Read at 1 means that a calibration in progress." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="ADC_CFGR" description="ADC configuration register " start="+0xc" size="4" reset_value="0x80000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DMNGT" description="Data Management configuration This bit is set and cleared by software to select how ADC interface output data are managed. Note: The software is allowed to write this bit only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing). In dual-ADC modes, this bit is not relevant and replaced by control bit DAMDF of the ADCx_CCR register." start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Regular conversion data stored in DR only" start="0x0" />
+        <Enum name="B_0x1" description="DMA One Shot Mode selected" start="0x1" />
+        <Enum name="B_0x2" description="DFSDM mode selected" start="0x2" />
+        <Enum name="B_0x3" description="DMA Circular Mode selected" start="0x3" />
+      </BitField>
+      <BitField name="RES" description="Data resolution These bits are written by software to select the resolution of the conversion. Others: Reserved, must not be used. Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing)." start="2" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="16 bits" start="0x0" />
+        <Enum name="B_0x1" description="14 bits in legacy mode (not optimized power consumption)" start="0x1" />
+        <Enum name="B_0x2" description="12 bits in legacy mode (not optimized power consumption)" start="0x2" />
+        <Enum name="B_0x5" description="14 bits" start="0x5" />
+        <Enum name="B_0x6" description="12 bits" start="0x6" />
+        <Enum name="B_0x3" description="10 bits" start="0x3" />
+        <Enum name="B_0x7" description="8 bits" start="0x7" />
+      </BitField>
+      <BitField name="EXTSEL" description="External trigger selection for regular group These bits select the external event used to trigger the start of conversion of a regular group: ... Note: The software is allowed to write these bits only when ADSTART=0 (which ensures that no regular conversion is ongoing)." start="5" size="5" access="Read/Write">
+        <Enum name="B_0x0" description="Event 0" start="0x0" />
+        <Enum name="B_0x1" description="Event 1" start="0x1" />
+        <Enum name="B_0x2" description="Event 2" start="0x2" />
+        <Enum name="B_0x3" description="Event 3" start="0x3" />
+        <Enum name="B_0x4" description="Event 4" start="0x4" />
+        <Enum name="B_0x5" description="Event 5" start="0x5" />
+        <Enum name="B_0x6" description="Event 6" start="0x6" />
+        <Enum name="B_0x7" description="Event 7" start="0x7" />
+        <Enum name="B_0x1F" description="Event 31" start="0x1F" />
+      </BitField>
+      <BitField name="EXTEN" description="External trigger enable and polarity selection for regular channels These bits are set and cleared by software to select the external trigger polarity and enable the trigger of a regular group. Note: The software is allowed to write these bits only when ADSTART=0 (which ensures that no regular conversion is ongoing)." start="10" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Hardware trigger detection disabled (conversions can be launched by software)" start="0x0" />
+        <Enum name="B_0x1" description="Hardware trigger detection on the rising edge" start="0x1" />
+        <Enum name="B_0x2" description="Hardware trigger detection on the falling edge" start="0x2" />
+        <Enum name="B_0x3" description="Hardware trigger detection on both the rising and falling edges" start="0x3" />
+      </BitField>
+      <BitField name="OVRMOD" description="Overrun Mode This bit is set and cleared by software and configure the way data overrun is managed. Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no regular conversion is ongoing)." start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="ADC_DR register is preserved with the old data when an overrun is detected. " start="0x0" />
+        <Enum name="B_0x1" description="ADC_DR register is overwritten with the last conversion result when an overrun is detected." start="0x1" />
+      </BitField>
+      <BitField name="CONT" description="Single / continuous conversion mode for regular conversions This bit is set and cleared by software. If it is set, regular conversion takes place continuously until it is cleared. Note: It is not possible to have both discontinuous mode and continuous mode enabled: it is forbidden to set both DISCEN=1 and CONT=1. The software is allowed to write this bit only when ADSTART=0 (which ensures that no regular conversion is ongoing). When dual mode is enabled (DAMDF bits in ADCx_CCR register are not equal to zero), the bit CONT of the slave ADC is no more writable and its content is equal to the bit CONT of the master ADC." start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Single conversion mode" start="0x0" />
+        <Enum name="B_0x1" description="Continuous conversion mode" start="0x1" />
+      </BitField>
+      <BitField name="AUTDLY" description="Delayed conversion mode This bit is set and cleared by software to enable/disable the Auto Delayed Conversion mode.. Note: The software is allowed to write this bit only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing). When dual mode is enabled (DAMDF bits in ADCx_CCR register are not equal to zero), the bit AUTDLY of the slave ADC is no more writable and its content is equal to the bit AUTDLY of the master ADC." start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Auto-delayed conversion mode off" start="0x0" />
+        <Enum name="B_0x1" description="Auto-delayed conversion mode on" start="0x1" />
+      </BitField>
+      <BitField name="DISCEN" description="Discontinuous mode for regular channels This bit is set and cleared by software to enable/disable Discontinuous mode for regular channels. Note: It is not possible to have both discontinuous mode and continuous mode enabled: it is forbidden to set both DISCEN=1 and CONT=1. It is not possible to use both auto-injected mode and discontinuous mode simultaneously: the bits DISCEN and JDISCEN must be kept cleared by software when JAUTO is set. The software is allowed to write this bit only when ADSTART=0 (which ensures that no regular conversion is ongoing). When dual mode is enabled (DAMDF bits in ADCx_CCR register are not equal to zero), the bit DISCEN of the slave ADC is no more writable and its content is equal to the bit DISCEN of the master ADC." start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Discontinuous mode for regular channels disabled" start="0x0" />
+        <Enum name="B_0x1" description="Discontinuous mode for regular channels enabled" start="0x1" />
+      </BitField>
+      <BitField name="DISCNUM" description="Discontinuous mode channel count These bits are written by software to define the number of regular channels to be converted in discontinuous mode, after receiving an external trigger. ... Note: The software is allowed to write these bits only when ADSTART=0 (which ensures that no regular conversion is ongoing). When dual mode is enabled (DAMDF bits in ADCx_CCR register are not equal to zero), the bits DISCNUM[2:0] of the slave ADC are no more writable and their content is equal to the bits DISCNUM[2:0] of the master ADC." start="17" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="1 channel" start="0x0" />
+        <Enum name="B_0x1" description="2 channels" start="0x1" />
+        <Enum name="B_0x7" description="8 channels" start="0x7" />
+      </BitField>
+      <BitField name="JDISCEN" description="Discontinuous mode on injected channels This bit is set and cleared by software to enable/disable discontinuous mode on the injected channels of a group. Note: The software is allowed to write this bit only when JADSTART=0 (which ensures that no injected conversion is ongoing). It is not possible to use both auto-injected mode and discontinuous mode simultaneously: the bits DISCEN and JDISCEN must be kept cleared by software when JAUTO is set. When dual mode is enabled (bits DAMDF of ADCx_CCR register are not equal to zero), the bit JDISCEN of the slave ADC is no more writable and its content is equal to the bit JDISCEN of the master ADC." start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Discontinuous mode on injected channels disabled" start="0x0" />
+        <Enum name="B_0x1" description="Discontinuous mode on injected channels enabled" start="0x1" />
+      </BitField>
+      <BitField name="JQM" description="JSQR queue mode This bit is set and cleared by software. It defines how an empty Queue is managed. Refer to for more information. Note: The software is allowed to write this bit only when JADSTART=0 (which ensures that no injected conversion is ongoing). When dual mode is enabled (DAMDF bits in ADCx_CCR register are not equal to zero), the bit JQM of the slave ADC is no more writable and its content is equal to the bit JQM of the master ADC." start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="JSQR Mode 0: The Queue is never empty and maintains the last written configuration into JSQR." start="0x0" />
+        <Enum name="B_0x1" description="JSQR Mode 1: The Queue can be empty and when this occurs, the software and hardware triggers of the injected sequence are both internally disabled just after the completion of the last valid injected sequence." start="0x1" />
+      </BitField>
+      <BitField name="AWD1SGL" description="Enable the watchdog 1 on a single channel or on all channels This bit is set and cleared by software to enable the analog watchdog on the channel identified by the AWD1CH[4:0] bits or on all the channels Note: The software is allowed to write this bit only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing)." start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Analog watchdog 1 enabled on all channels" start="0x0" />
+        <Enum name="B_0x1" description="Analog watchdog 1 enabled on a single channel" start="0x1" />
+      </BitField>
+      <BitField name="AWD1EN" description="Analog watchdog 1 enable on regular channels This bit is set and cleared by software Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no regular conversion is ongoing)." start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Analog watchdog 1 disabled on regular channels" start="0x0" />
+        <Enum name="B_0x1" description="Analog watchdog 1 enabled on regular channels" start="0x1" />
+      </BitField>
+      <BitField name="JAWD1EN" description="Analog watchdog 1 enable on injected channels This bit is set and cleared by software Note: The software is allowed to write this bit only when JADSTART=0 (which ensures that no injected conversion is ongoing)." start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Analog watchdog 1 disabled on injected channels" start="0x0" />
+        <Enum name="B_0x1" description="Analog watchdog 1 enabled on injected channels" start="0x1" />
+      </BitField>
+      <BitField name="JAUTO" description="Automatic injected group conversion This bit is set and cleared by software to enable/disable automatic injected group conversion after regular group conversion. Note: The software is allowed to write this bit only when ADSTART=0 and JADSTART=0 (which ensures that no regular nor injected conversion is ongoing). When dual mode is enabled (DAMDF bits in ADCx_CCR register are not equal to zero), the bit JAUTO of the slave ADC is no more writable and its content is equal to the bit JAUTO of the master ADC." start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Automatic injected group conversion disabled" start="0x0" />
+        <Enum name="B_0x1" description="Automatic injected group conversion enabled" start="0x1" />
+      </BitField>
+      <BitField name="AWD1CH" description="Analog watchdog 1 channel selection These bits are set and cleared by software. They select the input channel to be guarded by the analog watchdog. ..... others: Reserved, must not be used Note: The channel selected by AWD1CH must be also selected into the SQRi or JSQRi registers. The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing)." start="26" size="5" access="Read/Write">
+        <Enum name="B_0x0" description="ADC analog input channel-0 monitored by AWD1" start="0x0" />
+        <Enum name="B_0x1" description="ADC analog input channel-1 monitored by AWD1" start="0x1" />
+        <Enum name="B_0x12" description="ADC analog input channel-19 monitored by AWD1" start="0x12" />
+      </BitField>
+      <BitField name="JQDIS" description="Injected Queue disable These bits are set and cleared by software to disable the Injected Queue mechanism: Note: The software is allowed to write this bit only when ADSTART=0 and JADSTART=0 (which ensures that no regular nor injected conversion is ongoing). A set or reset of JQDIS bit causes the injected queue to be flushed and the JSQR register is cleared." start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Injected Queue enabled" start="0x0" />
+        <Enum name="B_0x1" description="Injected Queue disabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="ADC_CFGR2" description="ADC configuration register 2 " start="+0x10" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ROVSE" description="Regular Oversampling Enable This bit is set and cleared by software to enable regular oversampling. Note: The software is allowed to write this bit only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing)" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Regular Oversampling disabled" start="0x0" />
+        <Enum name="B_0x1" description="Regular Oversampling enabled" start="0x1" />
+      </BitField>
+      <BitField name="JOVSE" description="Injected Oversampling Enable This bit is set and cleared by software to enable injected oversampling. Note: The software is allowed to write this bit only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing)" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Injected Oversampling disabled" start="0x0" />
+        <Enum name="B_0x1" description="Injected Oversampling enabled" start="0x1" />
+      </BitField>
+      <BitField name="OVSS" description="Oversampling right shift This bitfield is set and cleared by software to define the right shifting applied to the raw oversampling result. Others: Reserved, must not be used. Note: The software is allowed to write these bits only when ADSTART=0 (which ensures that no conversion is ongoing)." start="5" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No right shift" start="0x0" />
+        <Enum name="B_0x1" description="Shift right 1-bit" start="0x1" />
+        <Enum name="B_0x2" description="Shift right 2-bits" start="0x2" />
+        <Enum name="B_0x3" description="Shift right 3-bits" start="0x3" />
+        <Enum name="B_0x4" description="Shift right 4-bits" start="0x4" />
+        <Enum name="B_0x5" description="Shift right 5-bits" start="0x5" />
+        <Enum name="B_0x6" description="Shift right 6-bits" start="0x6" />
+        <Enum name="B_0x7" description="Shift right 7-bits" start="0x7" />
+        <Enum name="B_0x8" description="Shift right 8-bits" start="0x8" />
+        <Enum name="B_0x9" description="Shift right 9-bits" start="0x9" />
+        <Enum name="B_0xA" description="Shift right 10-bits" start="0xA" />
+        <Enum name="B_0xB" description="Shift right 11-bits" start="0xB" />
+      </BitField>
+      <BitField name="TROVS" description="Triggered Regular Oversampling This bit is set and cleared by software to enable triggered oversampling Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing)." start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="All oversampled conversions for a channel are done consecutively following a trigger" start="0x0" />
+        <Enum name="B_0x1" description="Each oversampled conversion for a channel needs a new trigger" start="0x1" />
+      </BitField>
+      <BitField name="ROVSM" description="Regular Oversampling mode This bit is set and cleared by software to select the regular oversampling mode. Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing)." start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Continued mode: When injected conversions are triggered, the oversampling is temporary stopped and continued after the injection sequence (oversampling buffer is maintained during injected sequence)" start="0x0" />
+        <Enum name="B_0x1" description="Resumed mode: When injected conversions are triggered, the current oversampling is aborted and resumed from start after the injection sequence (oversampling buffer is zeroed by injected sequence start)" start="0x1" />
+      </BitField>
+      <BitField name="RSHIFT1" description="Right-shift data after Offset 1 correction This bitfield is set and cleared by software to right-shift 1-bit data after offset1 correction. This bit can only be used for 8-bit and 16-bit data format (see (ADC_DR, ADC_JDRy, OFFSETy, OFFSETy_CH, OVSS, LSHIFT, RSHIFT, SSATE) for details)." start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Right-shifting disabled" start="0x0" />
+        <Enum name="B_0x1" description="Data is right-shifted 1-bit." start="0x1" />
+      </BitField>
+      <BitField name="RSHIFT2" description="Right-shift data after Offset 2 correction Refer to RSHIFT1 description" start="12" size="1" access="Read/Write" />
+      <BitField name="RSHIFT3" description="Right-shift data after Offset 3 correction Refer to RSHIFT1 description" start="13" size="1" access="Read/Write" />
+      <BitField name="RSHIFT4" description="Right-shift data after Offset 4 correction Refer to RSHIFT1 description." start="14" size="1" access="Read/Write" />
+      <BitField name="OSVR" description="Oversampling ratio This bitfield is set and cleared by software to define the oversampling ratio. 2: 3x ... 1023: 1024x Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing)." start="16" size="10" access="Read/Write">
+        <Enum name="B_0x0" description="1x (no oversampling)" start="0x0" />
+        <Enum name="B_0x1" description="2x" start="0x1" />
+      </BitField>
+      <BitField name="LSHIFT" description="Left shift factor This bitfield is set and cleared by software to define the left shifting applied to the final result with or without oversampling. Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing)." start="28" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No left shift" start="0x0" />
+        <Enum name="B_0x1" description="Shift left 1-bit" start="0x1" />
+        <Enum name="B_0x2" description="Shift left 2-bits" start="0x2" />
+        <Enum name="B_0x3" description="Shift left 3-bits" start="0x3" />
+        <Enum name="B_0x4" description="Shift left 4-bits" start="0x4" />
+        <Enum name="B_0x5" description="Shift left 5-bits" start="0x5" />
+        <Enum name="B_0x6" description="Shift left 6-bits" start="0x6" />
+        <Enum name="B_0x7" description="Shift left 7-bits" start="0x7" />
+        <Enum name="B_0x8" description="Shift left 8-bits" start="0x8" />
+        <Enum name="B_0x9" description="Shift left 9-bits" start="0x9" />
+        <Enum name="B_0xA" description="Shift left 10-bits" start="0xA" />
+        <Enum name="B_0xB" description="Shift left 11-bits" start="0xB" />
+        <Enum name="B_0xC" description="Shift left 12-bits" start="0xC" />
+        <Enum name="B_0xD" description="Shift left 13-bits" start="0xD" />
+        <Enum name="B_0xE" description="Shift left 14-bits" start="0xE" />
+        <Enum name="B_0xF" description="Shift left 15-bits" start="0xF" />
+      </BitField>
+    </Register>
+    <Register name="ADC_SMPR1" description="ADC sample time register 1 " start="+0x14" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SMP0" description="Channel x sampling time selection (x = 0 to 9) These bits are written by software to select the sampling time individually for each channel. During sample cycles, the channel selection bits must remain unchanged. Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing)." start="0" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="1.5 ADC clock cycles" start="0x0" />
+        <Enum name="B_0x1" description="2.5 ADC clock cycles" start="0x1" />
+        <Enum name="B_0x2" description="8.5 ADC clock cycles" start="0x2" />
+        <Enum name="B_0x3" description="16.5 ADC clock cycles" start="0x3" />
+        <Enum name="B_0x4" description="32.5 ADC clock cycles" start="0x4" />
+        <Enum name="B_0x5" description="64.5 ADC clock cycles" start="0x5" />
+        <Enum name="B_0x6" description="387.5 ADC clock cycles" start="0x6" />
+        <Enum name="B_0x7" description="810.5 ADC clock cycles" start="0x7" />
+      </BitField>
+      <BitField name="SMP1" description="Channel x sampling time selection (x = 0 to 9) These bits are written by software to select the sampling time individually for each channel. During sample cycles, the channel selection bits must remain unchanged. Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing)." start="3" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="1.5 ADC clock cycles" start="0x0" />
+        <Enum name="B_0x1" description="2.5 ADC clock cycles" start="0x1" />
+        <Enum name="B_0x2" description="8.5 ADC clock cycles" start="0x2" />
+        <Enum name="B_0x3" description="16.5 ADC clock cycles" start="0x3" />
+        <Enum name="B_0x4" description="32.5 ADC clock cycles" start="0x4" />
+        <Enum name="B_0x5" description="64.5 ADC clock cycles" start="0x5" />
+        <Enum name="B_0x6" description="387.5 ADC clock cycles" start="0x6" />
+        <Enum name="B_0x7" description="810.5 ADC clock cycles" start="0x7" />
+      </BitField>
+      <BitField name="SMP2" description="Channel x sampling time selection (x = 0 to 9) These bits are written by software to select the sampling time individually for each channel. During sample cycles, the channel selection bits must remain unchanged. Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing)." start="6" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="1.5 ADC clock cycles" start="0x0" />
+        <Enum name="B_0x1" description="2.5 ADC clock cycles" start="0x1" />
+        <Enum name="B_0x2" description="8.5 ADC clock cycles" start="0x2" />
+        <Enum name="B_0x3" description="16.5 ADC clock cycles" start="0x3" />
+        <Enum name="B_0x4" description="32.5 ADC clock cycles" start="0x4" />
+        <Enum name="B_0x5" description="64.5 ADC clock cycles" start="0x5" />
+        <Enum name="B_0x6" description="387.5 ADC clock cycles" start="0x6" />
+        <Enum name="B_0x7" description="810.5 ADC clock cycles" start="0x7" />
+      </BitField>
+      <BitField name="SMP3" description="Channel x sampling time selection (x = 0 to 9) These bits are written by software to select the sampling time individually for each channel. During sample cycles, the channel selection bits must remain unchanged. Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing)." start="9" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="1.5 ADC clock cycles" start="0x0" />
+        <Enum name="B_0x1" description="2.5 ADC clock cycles" start="0x1" />
+        <Enum name="B_0x2" description="8.5 ADC clock cycles" start="0x2" />
+        <Enum name="B_0x3" description="16.5 ADC clock cycles" start="0x3" />
+        <Enum name="B_0x4" description="32.5 ADC clock cycles" start="0x4" />
+        <Enum name="B_0x5" description="64.5 ADC clock cycles" start="0x5" />
+        <Enum name="B_0x6" description="387.5 ADC clock cycles" start="0x6" />
+        <Enum name="B_0x7" description="810.5 ADC clock cycles" start="0x7" />
+      </BitField>
+      <BitField name="SMP4" description="Channel x sampling time selection (x = 0 to 9) These bits are written by software to select the sampling time individually for each channel. During sample cycles, the channel selection bits must remain unchanged. Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing)." start="12" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="1.5 ADC clock cycles" start="0x0" />
+        <Enum name="B_0x1" description="2.5 ADC clock cycles" start="0x1" />
+        <Enum name="B_0x2" description="8.5 ADC clock cycles" start="0x2" />
+        <Enum name="B_0x3" description="16.5 ADC clock cycles" start="0x3" />
+        <Enum name="B_0x4" description="32.5 ADC clock cycles" start="0x4" />
+        <Enum name="B_0x5" description="64.5 ADC clock cycles" start="0x5" />
+        <Enum name="B_0x6" description="387.5 ADC clock cycles" start="0x6" />
+        <Enum name="B_0x7" description="810.5 ADC clock cycles" start="0x7" />
+      </BitField>
+      <BitField name="SMP5" description="Channel x sampling time selection (x = 0 to 9) These bits are written by software to select the sampling time individually for each channel. During sample cycles, the channel selection bits must remain unchanged. Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing)." start="15" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="1.5 ADC clock cycles" start="0x0" />
+        <Enum name="B_0x1" description="2.5 ADC clock cycles" start="0x1" />
+        <Enum name="B_0x2" description="8.5 ADC clock cycles" start="0x2" />
+        <Enum name="B_0x3" description="16.5 ADC clock cycles" start="0x3" />
+        <Enum name="B_0x4" description="32.5 ADC clock cycles" start="0x4" />
+        <Enum name="B_0x5" description="64.5 ADC clock cycles" start="0x5" />
+        <Enum name="B_0x6" description="387.5 ADC clock cycles" start="0x6" />
+        <Enum name="B_0x7" description="810.5 ADC clock cycles" start="0x7" />
+      </BitField>
+      <BitField name="SMP6" description="Channel x sampling time selection (x = 0 to 9) These bits are written by software to select the sampling time individually for each channel. During sample cycles, the channel selection bits must remain unchanged. Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing)." start="18" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="1.5 ADC clock cycles" start="0x0" />
+        <Enum name="B_0x1" description="2.5 ADC clock cycles" start="0x1" />
+        <Enum name="B_0x2" description="8.5 ADC clock cycles" start="0x2" />
+        <Enum name="B_0x3" description="16.5 ADC clock cycles" start="0x3" />
+        <Enum name="B_0x4" description="32.5 ADC clock cycles" start="0x4" />
+        <Enum name="B_0x5" description="64.5 ADC clock cycles" start="0x5" />
+        <Enum name="B_0x6" description="387.5 ADC clock cycles" start="0x6" />
+        <Enum name="B_0x7" description="810.5 ADC clock cycles" start="0x7" />
+      </BitField>
+      <BitField name="SMP7" description="Channel x sampling time selection (x = 0 to 9) These bits are written by software to select the sampling time individually for each channel. During sample cycles, the channel selection bits must remain unchanged. Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing)." start="21" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="1.5 ADC clock cycles" start="0x0" />
+        <Enum name="B_0x1" description="2.5 ADC clock cycles" start="0x1" />
+        <Enum name="B_0x2" description="8.5 ADC clock cycles" start="0x2" />
+        <Enum name="B_0x3" description="16.5 ADC clock cycles" start="0x3" />
+        <Enum name="B_0x4" description="32.5 ADC clock cycles" start="0x4" />
+        <Enum name="B_0x5" description="64.5 ADC clock cycles" start="0x5" />
+        <Enum name="B_0x6" description="387.5 ADC clock cycles" start="0x6" />
+        <Enum name="B_0x7" description="810.5 ADC clock cycles" start="0x7" />
+      </BitField>
+      <BitField name="SMP8" description="Channel x sampling time selection (x = 0 to 9) These bits are written by software to select the sampling time individually for each channel. During sample cycles, the channel selection bits must remain unchanged. Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing)." start="24" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="1.5 ADC clock cycles" start="0x0" />
+        <Enum name="B_0x1" description="2.5 ADC clock cycles" start="0x1" />
+        <Enum name="B_0x2" description="8.5 ADC clock cycles" start="0x2" />
+        <Enum name="B_0x3" description="16.5 ADC clock cycles" start="0x3" />
+        <Enum name="B_0x4" description="32.5 ADC clock cycles" start="0x4" />
+        <Enum name="B_0x5" description="64.5 ADC clock cycles" start="0x5" />
+        <Enum name="B_0x6" description="387.5 ADC clock cycles" start="0x6" />
+        <Enum name="B_0x7" description="810.5 ADC clock cycles" start="0x7" />
+      </BitField>
+      <BitField name="SMP9" description="Channel x sampling time selection (x = 0 to 9) These bits are written by software to select the sampling time individually for each channel. During sample cycles, the channel selection bits must remain unchanged. Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing)." start="27" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="1.5 ADC clock cycles" start="0x0" />
+        <Enum name="B_0x1" description="2.5 ADC clock cycles" start="0x1" />
+        <Enum name="B_0x2" description="8.5 ADC clock cycles" start="0x2" />
+        <Enum name="B_0x3" description="16.5 ADC clock cycles" start="0x3" />
+        <Enum name="B_0x4" description="32.5 ADC clock cycles" start="0x4" />
+        <Enum name="B_0x5" description="64.5 ADC clock cycles" start="0x5" />
+        <Enum name="B_0x6" description="387.5 ADC clock cycles" start="0x6" />
+        <Enum name="B_0x7" description="810.5 ADC clock cycles" start="0x7" />
+      </BitField>
+    </Register>
+    <Register name="ADC_SMPR2" description="ADC sample time register 2 " start="+0x18" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SMP10" description="Channel x sampling time selection (x = 10 to 19) These bits are written by software to select the sampling time individually for each channel. During sampling cycles, the channel selection bits must remain unchanged. Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing)." start="0" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="1.5 ADC clock cycles" start="0x0" />
+        <Enum name="B_0x1" description="2.5 ADC clock cycles" start="0x1" />
+        <Enum name="B_0x2" description="8.5 ADC clock cycles" start="0x2" />
+        <Enum name="B_0x3" description="16.5 ADC clock cycles" start="0x3" />
+        <Enum name="B_0x4" description="32.5 ADC clock cycles" start="0x4" />
+        <Enum name="B_0x5" description="64.5 ADC clock cycles" start="0x5" />
+        <Enum name="B_0x6" description="387.5 ADC clock cycles" start="0x6" />
+        <Enum name="B_0x7" description="810.5 ADC clock cycles" start="0x7" />
+      </BitField>
+      <BitField name="SMP11" description="Channel x sampling time selection (x = 10 to 19) These bits are written by software to select the sampling time individually for each channel. During sampling cycles, the channel selection bits must remain unchanged. Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing)." start="3" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="1.5 ADC clock cycles" start="0x0" />
+        <Enum name="B_0x1" description="2.5 ADC clock cycles" start="0x1" />
+        <Enum name="B_0x2" description="8.5 ADC clock cycles" start="0x2" />
+        <Enum name="B_0x3" description="16.5 ADC clock cycles" start="0x3" />
+        <Enum name="B_0x4" description="32.5 ADC clock cycles" start="0x4" />
+        <Enum name="B_0x5" description="64.5 ADC clock cycles" start="0x5" />
+        <Enum name="B_0x6" description="387.5 ADC clock cycles" start="0x6" />
+        <Enum name="B_0x7" description="810.5 ADC clock cycles" start="0x7" />
+      </BitField>
+      <BitField name="SMP12" description="Channel x sampling time selection (x = 10 to 19) These bits are written by software to select the sampling time individually for each channel. During sampling cycles, the channel selection bits must remain unchanged. Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing)." start="6" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="1.5 ADC clock cycles" start="0x0" />
+        <Enum name="B_0x1" description="2.5 ADC clock cycles" start="0x1" />
+        <Enum name="B_0x2" description="8.5 ADC clock cycles" start="0x2" />
+        <Enum name="B_0x3" description="16.5 ADC clock cycles" start="0x3" />
+        <Enum name="B_0x4" description="32.5 ADC clock cycles" start="0x4" />
+        <Enum name="B_0x5" description="64.5 ADC clock cycles" start="0x5" />
+        <Enum name="B_0x6" description="387.5 ADC clock cycles" start="0x6" />
+        <Enum name="B_0x7" description="810.5 ADC clock cycles" start="0x7" />
+      </BitField>
+      <BitField name="SMP13" description="Channel x sampling time selection (x = 10 to 19) These bits are written by software to select the sampling time individually for each channel. During sampling cycles, the channel selection bits must remain unchanged. Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing)." start="9" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="1.5 ADC clock cycles" start="0x0" />
+        <Enum name="B_0x1" description="2.5 ADC clock cycles" start="0x1" />
+        <Enum name="B_0x2" description="8.5 ADC clock cycles" start="0x2" />
+        <Enum name="B_0x3" description="16.5 ADC clock cycles" start="0x3" />
+        <Enum name="B_0x4" description="32.5 ADC clock cycles" start="0x4" />
+        <Enum name="B_0x5" description="64.5 ADC clock cycles" start="0x5" />
+        <Enum name="B_0x6" description="387.5 ADC clock cycles" start="0x6" />
+        <Enum name="B_0x7" description="810.5 ADC clock cycles" start="0x7" />
+      </BitField>
+      <BitField name="SMP14" description="Channel x sampling time selection (x = 10 to 19) These bits are written by software to select the sampling time individually for each channel. During sampling cycles, the channel selection bits must remain unchanged. Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing)." start="12" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="1.5 ADC clock cycles" start="0x0" />
+        <Enum name="B_0x1" description="2.5 ADC clock cycles" start="0x1" />
+        <Enum name="B_0x2" description="8.5 ADC clock cycles" start="0x2" />
+        <Enum name="B_0x3" description="16.5 ADC clock cycles" start="0x3" />
+        <Enum name="B_0x4" description="32.5 ADC clock cycles" start="0x4" />
+        <Enum name="B_0x5" description="64.5 ADC clock cycles" start="0x5" />
+        <Enum name="B_0x6" description="387.5 ADC clock cycles" start="0x6" />
+        <Enum name="B_0x7" description="810.5 ADC clock cycles" start="0x7" />
+      </BitField>
+      <BitField name="SMP15" description="Channel x sampling time selection (x = 10 to 19) These bits are written by software to select the sampling time individually for each channel. During sampling cycles, the channel selection bits must remain unchanged. Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing)." start="15" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="1.5 ADC clock cycles" start="0x0" />
+        <Enum name="B_0x1" description="2.5 ADC clock cycles" start="0x1" />
+        <Enum name="B_0x2" description="8.5 ADC clock cycles" start="0x2" />
+        <Enum name="B_0x3" description="16.5 ADC clock cycles" start="0x3" />
+        <Enum name="B_0x4" description="32.5 ADC clock cycles" start="0x4" />
+        <Enum name="B_0x5" description="64.5 ADC clock cycles" start="0x5" />
+        <Enum name="B_0x6" description="387.5 ADC clock cycles" start="0x6" />
+        <Enum name="B_0x7" description="810.5 ADC clock cycles" start="0x7" />
+      </BitField>
+      <BitField name="SMP16" description="Channel x sampling time selection (x = 10 to 19) These bits are written by software to select the sampling time individually for each channel. During sampling cycles, the channel selection bits must remain unchanged. Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing)." start="18" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="1.5 ADC clock cycles" start="0x0" />
+        <Enum name="B_0x1" description="2.5 ADC clock cycles" start="0x1" />
+        <Enum name="B_0x2" description="8.5 ADC clock cycles" start="0x2" />
+        <Enum name="B_0x3" description="16.5 ADC clock cycles" start="0x3" />
+        <Enum name="B_0x4" description="32.5 ADC clock cycles" start="0x4" />
+        <Enum name="B_0x5" description="64.5 ADC clock cycles" start="0x5" />
+        <Enum name="B_0x6" description="387.5 ADC clock cycles" start="0x6" />
+        <Enum name="B_0x7" description="810.5 ADC clock cycles" start="0x7" />
+      </BitField>
+      <BitField name="SMP17" description="Channel x sampling time selection (x = 10 to 19) These bits are written by software to select the sampling time individually for each channel. During sampling cycles, the channel selection bits must remain unchanged. Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing)." start="21" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="1.5 ADC clock cycles" start="0x0" />
+        <Enum name="B_0x1" description="2.5 ADC clock cycles" start="0x1" />
+        <Enum name="B_0x2" description="8.5 ADC clock cycles" start="0x2" />
+        <Enum name="B_0x3" description="16.5 ADC clock cycles" start="0x3" />
+        <Enum name="B_0x4" description="32.5 ADC clock cycles" start="0x4" />
+        <Enum name="B_0x5" description="64.5 ADC clock cycles" start="0x5" />
+        <Enum name="B_0x6" description="387.5 ADC clock cycles" start="0x6" />
+        <Enum name="B_0x7" description="810.5 ADC clock cycles" start="0x7" />
+      </BitField>
+      <BitField name="SMP18" description="Channel x sampling time selection (x = 10 to 19) These bits are written by software to select the sampling time individually for each channel. During sampling cycles, the channel selection bits must remain unchanged. Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing)." start="24" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="1.5 ADC clock cycles" start="0x0" />
+        <Enum name="B_0x1" description="2.5 ADC clock cycles" start="0x1" />
+        <Enum name="B_0x2" description="8.5 ADC clock cycles" start="0x2" />
+        <Enum name="B_0x3" description="16.5 ADC clock cycles" start="0x3" />
+        <Enum name="B_0x4" description="32.5 ADC clock cycles" start="0x4" />
+        <Enum name="B_0x5" description="64.5 ADC clock cycles" start="0x5" />
+        <Enum name="B_0x6" description="387.5 ADC clock cycles" start="0x6" />
+        <Enum name="B_0x7" description="810.5 ADC clock cycles" start="0x7" />
+      </BitField>
+      <BitField name="SMP19" description="Channel x sampling time selection (x = 10 to 19) These bits are written by software to select the sampling time individually for each channel. During sampling cycles, the channel selection bits must remain unchanged. Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing)." start="27" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="1.5 ADC clock cycles" start="0x0" />
+        <Enum name="B_0x1" description="2.5 ADC clock cycles" start="0x1" />
+        <Enum name="B_0x2" description="8.5 ADC clock cycles" start="0x2" />
+        <Enum name="B_0x3" description="16.5 ADC clock cycles" start="0x3" />
+        <Enum name="B_0x4" description="32.5 ADC clock cycles" start="0x4" />
+        <Enum name="B_0x5" description="64.5 ADC clock cycles" start="0x5" />
+        <Enum name="B_0x6" description="387.5 ADC clock cycles" start="0x6" />
+        <Enum name="B_0x7" description="810.5 ADC clock cycles" start="0x7" />
+      </BitField>
+    </Register>
+    <Register name="ADC_PCSEL" description="ADC channel preselection register " start="+0x1c" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PCSEL0" description=":Channel x (VINP[i]) pre selection (x = 0 to 19) These bits are written by software to pre select the input channel at IO instance to be converted. Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing)." start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Input Channel x (Vinp x) is not pre selected for conversion, the ADC conversion result with this channel shows wrong result." start="0x0" />
+        <Enum name="B_0x1" description="Input Channel x (Vinp x) is pre selected for conversion" start="0x1" />
+      </BitField>
+      <BitField name="PCSEL1" description=":Channel x (VINP[i]) pre selection (x = 0 to 19) These bits are written by software to pre select the input channel at IO instance to be converted. Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing)." start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Input Channel x (Vinp x) is not pre selected for conversion, the ADC conversion result with this channel shows wrong result." start="0x0" />
+        <Enum name="B_0x1" description="Input Channel x (Vinp x) is pre selected for conversion" start="0x1" />
+      </BitField>
+      <BitField name="PCSEL2" description=":Channel x (VINP[i]) pre selection (x = 0 to 19) These bits are written by software to pre select the input channel at IO instance to be converted. Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing)." start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Input Channel x (Vinp x) is not pre selected for conversion, the ADC conversion result with this channel shows wrong result." start="0x0" />
+        <Enum name="B_0x1" description="Input Channel x (Vinp x) is pre selected for conversion" start="0x1" />
+      </BitField>
+      <BitField name="PCSEL3" description=":Channel x (VINP[i]) pre selection (x = 0 to 19) These bits are written by software to pre select the input channel at IO instance to be converted. Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing)." start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Input Channel x (Vinp x) is not pre selected for conversion, the ADC conversion result with this channel shows wrong result." start="0x0" />
+        <Enum name="B_0x1" description="Input Channel x (Vinp x) is pre selected for conversion" start="0x1" />
+      </BitField>
+      <BitField name="PCSEL4" description=":Channel x (VINP[i]) pre selection (x = 0 to 19) These bits are written by software to pre select the input channel at IO instance to be converted. Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing)." start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Input Channel x (Vinp x) is not pre selected for conversion, the ADC conversion result with this channel shows wrong result." start="0x0" />
+        <Enum name="B_0x1" description="Input Channel x (Vinp x) is pre selected for conversion" start="0x1" />
+      </BitField>
+      <BitField name="PCSEL5" description=":Channel x (VINP[i]) pre selection (x = 0 to 19) These bits are written by software to pre select the input channel at IO instance to be converted. Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing)." start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Input Channel x (Vinp x) is not pre selected for conversion, the ADC conversion result with this channel shows wrong result." start="0x0" />
+        <Enum name="B_0x1" description="Input Channel x (Vinp x) is pre selected for conversion" start="0x1" />
+      </BitField>
+      <BitField name="PCSEL6" description=":Channel x (VINP[i]) pre selection (x = 0 to 19) These bits are written by software to pre select the input channel at IO instance to be converted. Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing)." start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Input Channel x (Vinp x) is not pre selected for conversion, the ADC conversion result with this channel shows wrong result." start="0x0" />
+        <Enum name="B_0x1" description="Input Channel x (Vinp x) is pre selected for conversion" start="0x1" />
+      </BitField>
+      <BitField name="PCSEL7" description=":Channel x (VINP[i]) pre selection (x = 0 to 19) These bits are written by software to pre select the input channel at IO instance to be converted. Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing)." start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Input Channel x (Vinp x) is not pre selected for conversion, the ADC conversion result with this channel shows wrong result." start="0x0" />
+        <Enum name="B_0x1" description="Input Channel x (Vinp x) is pre selected for conversion" start="0x1" />
+      </BitField>
+      <BitField name="PCSEL8" description=":Channel x (VINP[i]) pre selection (x = 0 to 19) These bits are written by software to pre select the input channel at IO instance to be converted. Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing)." start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Input Channel x (Vinp x) is not pre selected for conversion, the ADC conversion result with this channel shows wrong result." start="0x0" />
+        <Enum name="B_0x1" description="Input Channel x (Vinp x) is pre selected for conversion" start="0x1" />
+      </BitField>
+      <BitField name="PCSEL9" description=":Channel x (VINP[i]) pre selection (x = 0 to 19) These bits are written by software to pre select the input channel at IO instance to be converted. Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing)." start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Input Channel x (Vinp x) is not pre selected for conversion, the ADC conversion result with this channel shows wrong result." start="0x0" />
+        <Enum name="B_0x1" description="Input Channel x (Vinp x) is pre selected for conversion" start="0x1" />
+      </BitField>
+      <BitField name="PCSEL10" description=":Channel x (VINP[i]) pre selection (x = 0 to 19) These bits are written by software to pre select the input channel at IO instance to be converted. Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing)." start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Input Channel x (Vinp x) is not pre selected for conversion, the ADC conversion result with this channel shows wrong result." start="0x0" />
+        <Enum name="B_0x1" description="Input Channel x (Vinp x) is pre selected for conversion" start="0x1" />
+      </BitField>
+      <BitField name="PCSEL11" description=":Channel x (VINP[i]) pre selection (x = 0 to 19) These bits are written by software to pre select the input channel at IO instance to be converted. Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing)." start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Input Channel x (Vinp x) is not pre selected for conversion, the ADC conversion result with this channel shows wrong result." start="0x0" />
+        <Enum name="B_0x1" description="Input Channel x (Vinp x) is pre selected for conversion" start="0x1" />
+      </BitField>
+      <BitField name="PCSEL12" description=":Channel x (VINP[i]) pre selection (x = 0 to 19) These bits are written by software to pre select the input channel at IO instance to be converted. Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing)." start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Input Channel x (Vinp x) is not pre selected for conversion, the ADC conversion result with this channel shows wrong result." start="0x0" />
+        <Enum name="B_0x1" description="Input Channel x (Vinp x) is pre selected for conversion" start="0x1" />
+      </BitField>
+      <BitField name="PCSEL13" description=":Channel x (VINP[i]) pre selection (x = 0 to 19) These bits are written by software to pre select the input channel at IO instance to be converted. Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing)." start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Input Channel x (Vinp x) is not pre selected for conversion, the ADC conversion result with this channel shows wrong result." start="0x0" />
+        <Enum name="B_0x1" description="Input Channel x (Vinp x) is pre selected for conversion" start="0x1" />
+      </BitField>
+      <BitField name="PCSEL14" description=":Channel x (VINP[i]) pre selection (x = 0 to 19) These bits are written by software to pre select the input channel at IO instance to be converted. Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing)." start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Input Channel x (Vinp x) is not pre selected for conversion, the ADC conversion result with this channel shows wrong result." start="0x0" />
+        <Enum name="B_0x1" description="Input Channel x (Vinp x) is pre selected for conversion" start="0x1" />
+      </BitField>
+      <BitField name="PCSEL15" description=":Channel x (VINP[i]) pre selection (x = 0 to 19) These bits are written by software to pre select the input channel at IO instance to be converted. Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing)." start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Input Channel x (Vinp x) is not pre selected for conversion, the ADC conversion result with this channel shows wrong result." start="0x0" />
+        <Enum name="B_0x1" description="Input Channel x (Vinp x) is pre selected for conversion" start="0x1" />
+      </BitField>
+      <BitField name="PCSEL16" description=":Channel x (VINP[i]) pre selection (x = 0 to 19) These bits are written by software to pre select the input channel at IO instance to be converted. Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing)." start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Input Channel x (Vinp x) is not pre selected for conversion, the ADC conversion result with this channel shows wrong result." start="0x0" />
+        <Enum name="B_0x1" description="Input Channel x (Vinp x) is pre selected for conversion" start="0x1" />
+      </BitField>
+      <BitField name="PCSEL17" description=":Channel x (VINP[i]) pre selection (x = 0 to 19) These bits are written by software to pre select the input channel at IO instance to be converted. Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing)." start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Input Channel x (Vinp x) is not pre selected for conversion, the ADC conversion result with this channel shows wrong result." start="0x0" />
+        <Enum name="B_0x1" description="Input Channel x (Vinp x) is pre selected for conversion" start="0x1" />
+      </BitField>
+      <BitField name="PCSEL18" description=":Channel x (VINP[i]) pre selection (x = 0 to 19) These bits are written by software to pre select the input channel at IO instance to be converted. Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing)." start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Input Channel x (Vinp x) is not pre selected for conversion, the ADC conversion result with this channel shows wrong result." start="0x0" />
+        <Enum name="B_0x1" description="Input Channel x (Vinp x) is pre selected for conversion" start="0x1" />
+      </BitField>
+      <BitField name="PCSEL19" description=":Channel x (VINP[i]) pre selection (x = 0 to 19) These bits are written by software to pre select the input channel at IO instance to be converted. Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing)." start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Input Channel x (Vinp x) is not pre selected for conversion, the ADC conversion result with this channel shows wrong result." start="0x0" />
+        <Enum name="B_0x1" description="Input Channel x (Vinp x) is pre selected for conversion" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="ADC_LTR1" description="ADC watchdog threshold register 1 " start="+0x20" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LTR1" description="Analog watchdog 1 lower threshold These bits are written by software to define the lower threshold for the analog watchdog 1. Refer to AWD2CH, AWD3CH, AWD_HTRy, AWD_LTRy, AWDy) Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing)." start="0" size="26" access="Read/Write" />
+    </Register>
+    <Register name="ADC_HTR1" description="ADC watchdog threshold register 1 " start="+0x24" size="4" reset_value="0x03FFFFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="HTR1" description="Analog watchdog 1 higher threshold These bits are written by software to define the higher threshold for the analog watchdog 1. Refer to AWD2CH, AWD3CH, AWD_HTRy, AWD_LTRy, AWDy) Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing)." start="0" size="26" access="Read/Write" />
+    </Register>
+    <Register name="ADC_SQR1" description="ADC regular sequence register 1 " start="+0x30" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="L" description="Regular channel sequence length These bits are written by software to define the total number of conversions in the regular channel conversion sequence. ... Note: The software is allowed to write these bits only when ADSTART=0 (which ensures that no regular conversion is ongoing)." start="0" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="1 conversion" start="0x0" />
+        <Enum name="B_0x1" description="2 conversions" start="0x1" />
+        <Enum name="B_0xF" description="16 conversions" start="0xF" />
+      </BitField>
+      <BitField name="SQ1" description="1st conversion in regular sequence These bits are written by software with the channel number (0..19) assigned as the 1st in the regular conversion sequence. Note: The software is allowed to write these bits only when ADSTART=0 (which ensures that no regular conversion is ongoing)." start="6" size="5" access="Read/Write" />
+      <BitField name="SQ2" description="2nd conversion in regular sequence These bits are written by software with the channel number (0..19) assigned as the 2nd in the regular conversion sequence. Note: The software is allowed to write these bits only when ADSTART=0 (which ensures that no regular conversion is ongoing)." start="12" size="5" access="Read/Write" />
+      <BitField name="SQ3" description="3rd conversion in regular sequence These bits are written by software with the channel number (0..19) assigned as the 3rd in the regular conversion sequence. Note: The software is allowed to write these bits only when ADSTART=0 (which ensures that no regular conversion is ongoing)." start="18" size="5" access="Read/Write" />
+      <BitField name="SQ4" description="4th conversion in regular sequence These bits are written by software with the channel number (0..19) assigned as the 4th in the regular conversion sequence." start="24" size="5" access="Read/Write" />
+    </Register>
+    <Register name="ADC_SQR2" description="ADC regular sequence register 2 " start="+0x34" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SQ5" description="5th conversion in regular sequence These bits are written by software with the channel number (0..19) assigned as the 5th in the regular conversion sequence. Note: The software is allowed to write these bits only when ADSTART=0 (which ensures that no regular conversion is ongoing)." start="0" size="5" access="Read/Write" />
+      <BitField name="SQ6" description="6th conversion in regular sequence These bits are written by software with the channel number (0..19) assigned as the 6th in the regular conversion sequence. Note: The software is allowed to write these bits only when ADSTART=0 (which ensures that no regular conversion is ongoing)." start="6" size="5" access="Read/Write" />
+      <BitField name="SQ7" description="7th conversion in regular sequence These bits are written by software with the channel number (0..19) assigned as the 7th in the regular conversion sequence. Note: The software is allowed to write these bits only when ADSTART=0 (which ensures that no regular conversion is ongoing)." start="12" size="5" access="Read/Write" />
+      <BitField name="SQ8" description="8th conversion in regular sequence These bits are written by software with the channel number (0..19) assigned as the 8th in the regular conversion sequence Note: The software is allowed to write these bits only when ADSTART=0 (which ensures that no regular conversion is ongoing)." start="18" size="5" access="Read/Write" />
+      <BitField name="SQ9" description="9th conversion in regular sequence These bits are written by software with the channel number (0..19) assigned as the 9th in the regular conversion sequence. Note: The software is allowed to write these bits only when ADSTART=0 (which ensures that no regular conversion is ongoing)." start="24" size="5" access="Read/Write" />
+    </Register>
+    <Register name="ADC_SQR3" description="ADC regular sequence register 3 " start="+0x38" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SQ10" description="10th conversion in regular sequence These bits are written by software with the channel number (0..19) assigned as the 10th in the regular conversion sequence. Note: The software is allowed to write these bits only when ADSTART=0 (which ensures that no regular conversion is ongoing)." start="0" size="5" access="Read/Write" />
+      <BitField name="SQ11" description="11th conversion in regular sequence These bits are written by software with the channel number (0..19) assigned as the 11th in the regular conversion sequence. Note: The software is allowed to write these bits only when ADSTART=0 (which ensures that no regular conversion is ongoing)." start="6" size="5" access="Read/Write" />
+      <BitField name="SQ12" description="12th conversion in regular sequence These bits are written by software with the channel number (0..19) assigned as the 12th in the regular conversion sequence. Note: The software is allowed to write these bits only when ADSTART=0 (which ensures that no regular conversion is ongoing)." start="12" size="5" access="Read/Write" />
+      <BitField name="SQ13" description="13th conversion in regular sequence These bits are written by software with the channel number (0..19) assigned as the 13th in the regular conversion sequence. Note: The software is allowed to write these bits only when ADSTART=0 (which ensures that no regular conversion is ongoing)." start="18" size="5" access="Read/Write" />
+      <BitField name="SQ14" description="14th conversion in regular sequence These bits are written by software with the channel number (0..19) assigned as the 14th in the regular conversion sequence. Note: The software is allowed to write these bits only when ADSTART=0 (which ensures that no regular conversion is ongoing)." start="24" size="5" access="Read/Write" />
+    </Register>
+    <Register name="ADC_SQR4" description="ADC regular sequence register 4 " start="+0x3c" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SQ15" description="15th conversion in regular sequence These bits are written by software with the channel number (0..19) assigned as the 15th in the regular conversion sequence. Note: The software is allowed to write these bits only when ADSTART=0 (which ensures that no regular conversion is ongoing)." start="0" size="5" access="Read/Write" />
+      <BitField name="SQ16" description="16th conversion in regular sequence These bits are written by software with the channel number (0..19) assigned as the 16th in the regular conversion sequence. Note: The software is allowed to write these bits only when ADSTART=0 (which ensures that no regular conversion is ongoing)." start="6" size="5" access="Read/Write" />
+    </Register>
+    <Register name="ADC_DR" description="ADC regular Data Register " start="+0x40" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RDATA" description="Regular Data converted These bits are read-only. They contain the conversion result from the last converted regular channel. The data are left- or right-aligned as described in ." start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="ADC_JSQR" description="ADC injected sequence register " start="+0x4c" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="JL" description="Injected channel sequence length These bits are written by software to define the total number of conversions in the injected channel conversion sequence. Note: The software is allowed to write these bits only when JADSTART is cleared to 0 (no injected conversion is ongoing)." start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="1 conversion" start="0x0" />
+        <Enum name="B_0x1" description="2 conversions" start="0x1" />
+        <Enum name="B_0x2" description="3 conversions" start="0x2" />
+        <Enum name="B_0x3" description="4 conversions" start="0x3" />
+      </BitField>
+      <BitField name="JEXTSEL" description="External trigger selection for injected group These bits select the external event used to trigger the start of conversion of an injected group: ... Note: The software is allowed to write these bits only when JADSTART is cleared to 0 (no injected conversion is ongoing)." start="2" size="5" access="Read/Write">
+        <Enum name="B_0x0" description="Event 0" start="0x0" />
+        <Enum name="B_0x1" description="Event 1" start="0x1" />
+        <Enum name="B_0x2" description="Event 2" start="0x2" />
+        <Enum name="B_0x3" description="Event 3" start="0x3" />
+        <Enum name="B_0x4" description="Event 4" start="0x4" />
+        <Enum name="B_0x5" description="Event 5" start="0x5" />
+        <Enum name="B_0x6" description="Event 6" start="0x6" />
+        <Enum name="B_0x7" description="Event 7" start="0x7" />
+        <Enum name="B_0x1F" description="Event 31:" start="0x1F" />
+      </BitField>
+      <BitField name="JEXTEN" description="External trigger enable and polarity selection for injected channels These bits are set and cleared by software to select the external trigger polarity and enable the trigger of an injected group. If JQDIS=1 (queue disabled), Hardware trigger detection disabled (conversions can be launched by software Note: The software is allowed to write these bits only when JADSTART is cleared to 0 (no injected conversion is ongoing). If JQM=1 and if the Queue of Context becomes empty, the software and hardware triggers of the injected sequence are both internally disabled (refer to Queue of context for injected conversions)" start="7" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="If JQDIS=0 (queue enabled), Hardware and software trigger detection disabled and" start="0x0" />
+        <Enum name="B_0x1" description="Hardware trigger detection on the rising edge" start="0x1" />
+        <Enum name="B_0x2" description="Hardware trigger detection on the falling edge" start="0x2" />
+        <Enum name="B_0x3" description="Hardware trigger detection on both the rising and falling edges" start="0x3" />
+      </BitField>
+      <BitField name="JSQ1" description="1st conversion in the injected sequence These bits are written by software with the channel number (0..19) assigned as the 1st in the injected conversion sequence. Note: The software is allowed to write these bits only when JADSTART is cleared to 0 (no injected conversion is ongoing) unless the context queue is enabled (JQDIS=0 in ADC_CFGR register)." start="9" size="5" access="Read/Write" />
+      <BitField name="JSQ2" description="2nd conversion in the injected sequence These bits are written by software with the channel number (0..19) assigned as the 2nd in the injected conversion sequence. Note: The software is allowed to write these bits only when JADSTART is cleared to 0 (no injected conversion is ongoing) unless the context queue is enabled (JQDIS=0 in ADC_CFGR register)." start="15" size="5" access="Read/Write" />
+      <BitField name="JSQ3" description="3rd conversion in the injected sequence These bits are written by software with the channel number (0..19) assigned as the 3rd in the injected conversion sequence. Note: The software is allowed to write these bits only when JADSTART is cleared to 0 (no injected conversion is ongoing) unless the context queue is enabled (JQDIS=0 in ADC_CFGR register)." start="21" size="5" access="Read/Write" />
+      <BitField name="JSQ4" description="4th conversion in the injected sequence These bits are written by software with the channel number (0..19) assigned as the 4th in the injected conversion sequence. Note: The software is allowed to write these bits only when JADSTART is cleared to 0 (no injected conversion is ongoing) unless the context queue is enabled (JQDIS=0 in ADC_CFGR register)." start="27" size="5" access="Read/Write" />
+    </Register>
+    <Register name="ADC_OFR1" description="ADC injected channel 1 offset register" start="+0x60" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OFFSET1" description="Data offset y for the channel programmed into bits OFFSETy_CH[4:0] These bits are written by software to define the offset y to be subtracted from the raw converted data when converting a channel (can be regular or injected). The channel to which applies the data offset y must be programmed in the bits OFFSETy_CH[4:0]. The conversion result can be read from in the ADC_DR (regular conversion) or from in the ADC_JDRyi registers (injected conversion). When OFFSETy[25:0] bitfield is reset, the offset compensation is disabled. Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing). If several offset (OFFSETy) point to the same channel, only the offset with the lowest x value is considered for the subtraction. Ex: if OFFSET1_CH[4:0]=4 and OFFSET2_CH[4:0]=4, this is OFFSET1[25:0] which is subtracted when converting channel 4." start="0" size="26" access="Read/Write" />
+      <BitField name="OFFSET1_CH" description="Channel selection for the Data offset y These bits are written by software to define the channel to which the offset programmed into bits OFFSETy[25:0] will apply. Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing)." start="26" size="5" access="Read/Write" />
+      <BitField name="SSATE" description="Signed saturation Enable This bit is written by software to enable or disable the Signed saturation feature. This bit can be enabled only for 8-bit and 16-bit data format (see alignment and offset (ADC_DR, ADC_JDRy, OFFSETy, OFFSETy_CH, OVSS, LSHIFT, RSHIFT, SSATE) for details). Note: The software is allowed to write this bit only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing)." start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Offset is subtracted maintaining data integrity and extending result size (9-bit and 17-bit signed format)." start="0x0" />
+        <Enum name="B_0x1" description="Offset is subtracted and result is saturated to maintain result size." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="ADC_OFR2" description="ADC injected channel 2 offset register" start="+0x64" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OFFSET2" description="Data offset y for the channel programmed into bits OFFSETy_CH[4:0] These bits are written by software to define the offset y to be subtracted from the raw converted data when converting a channel (can be regular or injected). The channel to which applies the data offset y must be programmed in the bits OFFSETy_CH[4:0]. The conversion result can be read from in the ADC_DR (regular conversion) or from in the ADC_JDRyi registers (injected conversion). When OFFSETy[25:0] bitfield is reset, the offset compensation is disabled. Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing). If several offset (OFFSETy) point to the same channel, only the offset with the lowest x value is considered for the subtraction. Ex: if OFFSET1_CH[4:0]=4 and OFFSET2_CH[4:0]=4, this is OFFSET1[25:0] which is subtracted when converting channel 4." start="0" size="26" access="Read/Write" />
+      <BitField name="OFFSET2_CH" description="Channel selection for the Data offset y These bits are written by software to define the channel to which the offset programmed into bits OFFSETy[25:0] will apply. Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing)." start="26" size="5" access="Read/Write" />
+      <BitField name="SSATE" description="Signed saturation Enable This bit is written by software to enable or disable the Signed saturation feature. This bit can be enabled only for 8-bit and 16-bit data format (see alignment and offset (ADC_DR, ADC_JDRy, OFFSETy, OFFSETy_CH, OVSS, LSHIFT, RSHIFT, SSATE) for details). Note: The software is allowed to write this bit only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing)." start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Offset is subtracted maintaining data integrity and extending result size (9-bit and 17-bit signed format)." start="0x0" />
+        <Enum name="B_0x1" description="Offset is subtracted and result is saturated to maintain result size." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="ADC_OFR3" description="ADC injected channel 3 offset register" start="+0x68" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OFFSET3" description="Data offset y for the channel programmed into bits OFFSETy_CH[4:0] These bits are written by software to define the offset y to be subtracted from the raw converted data when converting a channel (can be regular or injected). The channel to which applies the data offset y must be programmed in the bits OFFSETy_CH[4:0]. The conversion result can be read from in the ADC_DR (regular conversion) or from in the ADC_JDRyi registers (injected conversion). When OFFSETy[25:0] bitfield is reset, the offset compensation is disabled. Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing). If several offset (OFFSETy) point to the same channel, only the offset with the lowest x value is considered for the subtraction. Ex: if OFFSET1_CH[4:0]=4 and OFFSET2_CH[4:0]=4, this is OFFSET1[25:0] which is subtracted when converting channel 4." start="0" size="26" access="Read/Write" />
+      <BitField name="OFFSET3_CH" description="Channel selection for the Data offset y These bits are written by software to define the channel to which the offset programmed into bits OFFSETy[25:0] will apply. Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing)." start="26" size="5" access="Read/Write" />
+      <BitField name="SSATE" description="Signed saturation Enable This bit is written by software to enable or disable the Signed saturation feature. This bit can be enabled only for 8-bit and 16-bit data format (see alignment and offset (ADC_DR, ADC_JDRy, OFFSETy, OFFSETy_CH, OVSS, LSHIFT, RSHIFT, SSATE) for details). Note: The software is allowed to write this bit only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing)." start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Offset is subtracted maintaining data integrity and extending result size (9-bit and 17-bit signed format)." start="0x0" />
+        <Enum name="B_0x1" description="Offset is subtracted and result is saturated to maintain result size." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="ADC_OFR4" description="ADC injected channel 4 offset register" start="+0x6c" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OFFSET4" description="Data offset y for the channel programmed into bits OFFSETy_CH[4:0] These bits are written by software to define the offset y to be subtracted from the raw converted data when converting a channel (can be regular or injected). The channel to which applies the data offset y must be programmed in the bits OFFSETy_CH[4:0]. The conversion result can be read from in the ADC_DR (regular conversion) or from in the ADC_JDRyi registers (injected conversion). When OFFSETy[25:0] bitfield is reset, the offset compensation is disabled. Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing). If several offset (OFFSETy) point to the same channel, only the offset with the lowest x value is considered for the subtraction. Ex: if OFFSET1_CH[4:0]=4 and OFFSET2_CH[4:0]=4, this is OFFSET1[25:0] which is subtracted when converting channel 4." start="0" size="26" access="Read/Write" />
+      <BitField name="OFFSET4_CH" description="Channel selection for the Data offset y These bits are written by software to define the channel to which the offset programmed into bits OFFSETy[25:0] will apply. Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing)." start="26" size="5" access="Read/Write" />
+      <BitField name="SSATE" description="Signed saturation Enable This bit is written by software to enable or disable the Signed saturation feature. This bit can be enabled only for 8-bit and 16-bit data format (see alignment and offset (ADC_DR, ADC_JDRy, OFFSETy, OFFSETy_CH, OVSS, LSHIFT, RSHIFT, SSATE) for details). Note: The software is allowed to write this bit only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing)." start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Offset is subtracted maintaining data integrity and extending result size (9-bit and 17-bit signed format)." start="0x0" />
+        <Enum name="B_0x1" description="Offset is subtracted and result is saturated to maintain result size." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="ADC_JDR1" description="ADC injected channel 1 data register" start="+0x80" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="JDATA" description="Injected data These bits are read-only. They contain the conversion result from injected channel y. The data are left -or right-aligned as described in ." start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="ADC_JDR2" description="ADC injected channel 2 data register" start="+0x84" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="JDATA" description="Injected data These bits are read-only. They contain the conversion result from injected channel y. The data are left -or right-aligned as described in ." start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="ADC_JDR3" description="ADC injected channel 3 data register" start="+0x88" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="JDATA" description="Injected data These bits are read-only. They contain the conversion result from injected channel y. The data are left -or right-aligned as described in ." start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="ADC_JDR4" description="ADC injected channel 4 data register" start="+0x8c" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="JDATA" description="Injected data These bits are read-only. They contain the conversion result from injected channel y. The data are left -or right-aligned as described in ." start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="ADC_AWD2CR" description="ADC analog watchdog 2 configuration register&#09;" start="+0xa0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AWD2CH" description="Analog watchdog 2 channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by the analog watchdog 2. AWD2CH[i] = 0: ADC analog input channel-i is not monitored by AWD2 AWD2CH[i] = 1: ADC analog input channel-i is monitored by AWD2 When AWD2CH[19:0] = 000..0, the analog Watchdog 2 is disabled Note: The channels selected by AWD2CH must be also selected into the SQRi or JSQRi registers. The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing)." start="0" size="20" access="Read/Write" />
+    </Register>
+    <Register name="ADC_AWD3CR" description="ADC analog watchdog 3 configuration register&#09;" start="+0xa4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AWD3CH" description="Analog watchdog 3 channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by the analog watchdog 3. AWD3CH[i] = 0: ADC analog input channel-i is not monitored by AWD3 AWD3CH[i] = 1: ADC analog input channel-i is monitored by AWD3 When AWD3CH[19:0] = 000..0, the analog Watchdog 3 is disabled Note: The channels selected by AWD3CH must be also selected into the SQRi or JSQRi registers. The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing)." start="0" size="20" access="Read/Write" />
+    </Register>
+    <Register name="ADC_LTR2" description="ADC watchdog lower threshold register 2 " start="+0xb0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LTR2" description="Analog watchdog 2 lower threshold These bits are written by software to define the lower threshold for the analog watchdog 2. Refer to AWD2CH, AWD3CH, AWD_HTRy, AWD_LTRy, AWDy). Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing)." start="0" size="26" access="Read/Write" />
+    </Register>
+    <Register name="ADC_HTR2" description="ADC watchdog higher threshold register 2 " start="+0xb4" size="4" reset_value="0x03FFFFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="HTR2" description="Analog watchdog 2 higher threshold These bits are written by software to define the higher threshold for the analog watchdog 2. Refer to AWD2CH, AWD3CH, AWD_HTRy, AWD_LTRy, AWDy). Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing)." start="0" size="26" access="Read/Write" />
+    </Register>
+    <Register name="ADC_LTR3" description="ADC watchdog lower threshold register 3 " start="+0xb8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LTR3" description="Analog watchdog 3 lower threshold These bits are written by software to define the lower threshold for the analog watchdog 3. Refer to AWD2CH, AWD3CH, AWD_HTRy, AWD_LTRy, AWDy) Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing)." start="0" size="26" access="Read/Write" />
+    </Register>
+    <Register name="ADC_HTR3" description="ADC watchdog higher threshold register 3 " start="+0xbc" size="4" reset_value="0x03FFFFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="HTR3" description="Analog watchdog 3 higher threshold These bits are written by software to define the higher threshold for the analog watchdog 3. Refer to AWD2CH, AWD3CH, AWD_HTRy, AWD_LTRy, AWDy) Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing)." start="0" size="26" access="Read/Write" />
+    </Register>
+    <Register name="ADC_DIFSEL" description="ADC differential mode selection register " start="+0xc0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DIFSEL" description="Differential mode for channels 19 to 0 These bits are set and cleared by software. They allow to select if a channel is configured as single ended or differential mode. DIFSEL[i] = 0: ADC analog input channel-i is configured in single ended mode DIFSEL[i] = 1: ADC analog input channel-i is configured in differential mode Note: The software is allowed to write these bits only when the ADC is disabled (ADCAL=0, JADSTART=0, JADSTP=0, ADSTART=0, ADSTP=0, ADDIS=0 and ADEN=0)." start="0" size="20" access="Read/Write" />
+    </Register>
+    <Register name="ADC_CALFACT" description="ADC calibration factors register " start="+0xc4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CALFACT_S" description="Calibration Factors In Single-Ended mode These bits are written by hardware or by software. Once a single-ended inputs calibration is complete, they are updated by hardware with the calibration factors. Software can write these bits with a new calibration factor. If the new calibration factor is different from the current one stored into the analog ADC, it will then be applied once a new single-ended conversion is launched. Note: The software is allowed to write these bits only when ADEN=1, ADSTART=0 and JADSTART=0 (ADC is enabled and no calibration is ongoing and no conversion is ongoing)." start="0" size="11" access="Read/Write" />
+      <BitField name="CALFACT_D" description="Calibration Factors in differential mode These bits are written by hardware or by software. Once a differential inputs calibration is complete, they are updated by hardware with the calibration factors. Software can write these bits with a new calibration factor. If the new calibration factor is different from the current one stored into the analog ADC, it will then be applied once a new differential conversion is launched. Note: The software is allowed to write these bits only when ADEN=1, ADSTART=0 and JADSTART=0 (ADC is enabled and no calibration is ongoing and no conversion is ongoing)." start="16" size="11" access="Read/Write" />
+    </Register>
+    <Register name="ADC_CALFACT2" description="ADC calibration factor register 2 " start="+0xc8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LINCALFACT" description="Linearity Calibration Factor These bits are written by hardware or by software. They hold 30-bit out of the 160-bit linearity calibration factor. Once a single-ended inputs calibration is complete, they are updated by hardware with the calibration factors. Software can write these bits with a new calibration factor. If the new calibration factor is different from the current one stored into the analog ADC, it will then be applied once a new single-ended calibration is launched. Note: The software is allowed to write these bits only when ADEN=1, ADSTART=0 and JADSTART=0 (ADC is enabled and no calibration is ongoing and no conversion is ongoing)." start="0" size="30" access="Read/Write" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="ADC2" description="Analog to Digital Converter" start="0x40022100">
+    <Register name="ADC_ISR" description="ADC interrupt and status register " start="+0x0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ADRDY" description="ADC ready This bit is set by hardware after the ADC has been enabled (bit ADEN=1) and when the ADC reaches a state where it is ready to accept conversion requests. It is cleared by software writing 1 to it." start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="ADC not yet ready to start conversion (or the flag event was already acknowledged and cleared by software)" start="0x0" />
+        <Enum name="B_0x1" description="ADC is ready to start conversion" start="0x1" />
+      </BitField>
+      <BitField name="EOSMP" description="End of sampling flag This bit is set by hardware during the conversion of any channel (only for regular channels), at the end of the sampling phase." start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="not at the end of the sampling phase (or the flag event was already acknowledged and cleared by software)" start="0x0" />
+        <Enum name="B_0x1" description="End of sampling phase reached" start="0x1" />
+      </BitField>
+      <BitField name="EOC" description="End of conversion flag This bit is set by hardware at the end of each regular conversion of a channel when a new data is available in the ADC_DR register. It is cleared by software writing 1 to it or by reading the ADC_DR register" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Regular channel conversion not complete (or the flag event was already acknowledged and cleared by software)" start="0x0" />
+        <Enum name="B_0x1" description="Regular channel conversion complete" start="0x1" />
+      </BitField>
+      <BitField name="EOS" description="End of regular sequence flag This bit is set by hardware at the end of the conversions of a regular sequence of channels. It is cleared by software writing 1 to it." start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Regular Conversions sequence not complete (or the flag event was already acknowledged and cleared by software)" start="0x0" />
+        <Enum name="B_0x1" description="Regular Conversions sequence complete" start="0x1" />
+      </BitField>
+      <BitField name="OVR" description="ADC overrun This bit is set by hardware when an overrun occurs on a regular channel, meaning that a new conversion has completed while the EOC flag was already set. It is cleared by software writing 1 to it." start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No overrun occurred (or the flag event was already acknowledged and cleared by software)" start="0x0" />
+        <Enum name="B_0x1" description="Overrun has occurred" start="0x1" />
+      </BitField>
+      <BitField name="JEOC" description="Injected channel end of conversion flag This bit is set by hardware at the end of each injected conversion of a channel when a new data is available in the corresponding ADC_JDRy register. It is cleared by software writing 1 to it or by reading the corresponding ADC_JDRy register" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Injected channel conversion not complete (or the flag event was already acknowledged and cleared by software)" start="0x0" />
+        <Enum name="B_0x1" description="Injected channel conversion complete" start="0x1" />
+      </BitField>
+      <BitField name="JEOS" description="Injected channel end of sequence flag This bit is set by hardware at the end of the conversions of all injected channels in the group. It is cleared by software writing 1 to it." start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Injected conversion sequence not complete (or the flag event was already acknowledged and cleared by software)" start="0x0" />
+        <Enum name="B_0x1" description="Injected conversions complete" start="0x1" />
+      </BitField>
+      <BitField name="AWD1" description="Analog watchdog 1 flag This bit is set by hardware when the converted voltage crosses the values programmed in the fields LT1[11:0] and HT1[11:0] of ADC_TR1 register. It is cleared by software. writing 1 to it." start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No analog watchdog 1 event occurred (or the flag event was already acknowledged and cleared by software)" start="0x0" />
+        <Enum name="B_0x1" description="Analog watchdog 1 event occurred" start="0x1" />
+      </BitField>
+      <BitField name="AWD2" description="Analog watchdog 2 flag This bit is set by hardware when the converted voltage crosses the values programmed in the fields LT2[7:0] and HT2[7:0] of ADC_TR2 register. It is cleared by software writing 1 to it." start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No analog watchdog 2 event occurred (or the flag event was already acknowledged and cleared by software)" start="0x0" />
+        <Enum name="B_0x1" description="Analog watchdog 2 event occurred" start="0x1" />
+      </BitField>
+      <BitField name="AWD3" description="Analog watchdog 3 flag This bit is set by hardware when the converted voltage crosses the values programmed in the fields LT3[7:0] and HT3[7:0] of ADC_TR3 register. It is cleared by software writing 1 to it." start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No analog watchdog 3 event occurred (or the flag event was already acknowledged and cleared by software)" start="0x0" />
+        <Enum name="B_0x1" description="Analog watchdog 3 event occurred" start="0x1" />
+      </BitField>
+      <BitField name="JQOVF" description="Injected context queue overflow This bit is set by hardware when an Overflow of the Injected Queue of Context occurs. It is cleared by software writing 1 to it. Refer to for more information." start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No injected context queue overflow occurred (or the flag event was already acknowledged and cleared by software)" start="0x0" />
+        <Enum name="B_0x1" description="Injected context queue overflow has occurred" start="0x1" />
+      </BitField>
+      <BitField name="LDORDY" description="ADC LDO output voltage ready bit This bit is set and cleared by hardware. It indicates that the ADC internal LDO output is ready and that the ADC can be enabled or calibrated. Note: Refer to for the availability of the LDO regulator." start="12" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="ADC LDO voltage regulator disabled" start="0x0" />
+        <Enum name="B_0x1" description="ADC LDO voltage regulator enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="ADC_IER" description="ADC interrupt enable register " start="+0x4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ADRDYIE" description="ADC ready interrupt enable This bit is set and cleared by software to enable/disable the ADC Ready interrupt. Note: The software is allowed to write this bit only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing)." start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="ADRDY interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="ADRDY interrupt enabled. An interrupt is generated when the ADRDY bit is set." start="0x1" />
+      </BitField>
+      <BitField name="EOSMPIE" description="End of sampling flag interrupt enable for regular conversions This bit is set and cleared by software to enable/disable the end of the sampling phase interrupt for regular conversions. Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no regular conversion is ongoing)." start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="EOSMP interrupt disabled." start="0x0" />
+        <Enum name="B_0x1" description="EOSMP interrupt enabled. An interrupt is generated when the EOSMP bit is set." start="0x1" />
+      </BitField>
+      <BitField name="EOCIE" description="End of regular conversion interrupt enable This bit is set and cleared by software to enable/disable the end of a regular conversion interrupt. Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no regular conversion is ongoing)." start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="EOC interrupt disabled." start="0x0" />
+        <Enum name="B_0x1" description="EOC interrupt enabled. An interrupt is generated when the EOC bit is set." start="0x1" />
+      </BitField>
+      <BitField name="EOSIE" description="End of regular sequence of conversions interrupt enable This bit is set and cleared by software to enable/disable the end of regular sequence of conversions interrupt. Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no regular conversion is ongoing)." start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="EOS interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="EOS interrupt enabled. An interrupt is generated when the EOS bit is set." start="0x1" />
+      </BitField>
+      <BitField name="OVRIE" description="Overrun interrupt enable This bit is set and cleared by software to enable/disable the Overrun interrupt of a regular conversion. Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no regular conversion is ongoing)." start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Overrun interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Overrun interrupt enabled. An interrupt is generated when the OVR bit is set." start="0x1" />
+      </BitField>
+      <BitField name="JEOCIE" description="End of injected conversion interrupt enable This bit is set and cleared by software to enable/disable the end of an injected conversion interrupt. Note: The software is allowed to write this bit only when JADSTART is cleared to 0 (no injected conversion is ongoing)." start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="JEOC interrupt disabled." start="0x0" />
+        <Enum name="B_0x1" description="JEOC interrupt enabled. An interrupt is generated when the JEOC bit is set." start="0x1" />
+      </BitField>
+      <BitField name="JEOSIE" description="End of injected sequence of conversions interrupt enable This bit is set and cleared by software to enable/disable the end of injected sequence of conversions interrupt. Note: The software is allowed to write this bit only when JADSTART=0 (which ensures that no injected conversion is ongoing)." start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="JEOS interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="JEOS interrupt enabled. An interrupt is generated when the JEOS bit is set." start="0x1" />
+      </BitField>
+      <BitField name="AWD1IE" description="Analog watchdog 1 interrupt enable This bit is set and cleared by software to enable/disable the analog watchdog 1 interrupt. Note: The software is allowed to write this bit only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing)." start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Analog watchdog 1 interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Analog watchdog 1 interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="AWD2IE" description="Analog watchdog 2 interrupt enable This bit is set and cleared by software to enable/disable the analog watchdog 2 interrupt. Note: The software is allowed to write this bit only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing)." start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Analog watchdog 2 interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Analog watchdog 2 interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="AWD3IE" description="Analog watchdog 3 interrupt enable This bit is set and cleared by software to enable/disable the analog watchdog 2 interrupt. Note: The software is allowed to write this bit only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing)." start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Analog watchdog 3 interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Analog watchdog 3 interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="JQOVFIE" description="Injected context queue overflow interrupt enable This bit is set and cleared by software to enable/disable the Injected Context Queue Overflow interrupt. Note: The software is allowed to write this bit only when JADSTART=0 (which ensures that no injected conversion is ongoing)." start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Injected Context Queue Overflow interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Injected Context Queue Overflow interrupt enabled. An interrupt is generated when the JQOVF bit is set." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="ADC_CR" description="ADC control register " start="+0x8" size="4" reset_value="0x20000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ADEN" description="ADC enable control This bit is set by software to enable the ADC. The ADC will be effectively ready to operate once the flag ADRDY has been set. It is cleared by hardware when the ADC is disabled, after the execution of the ADDIS command. Note: The software is allowed to set ADEN only when all bits of ADC_CR registers are 0 (ADCAL=0, JADSTART=0, ADSTART=0, ADSTP=0, ADDIS=0 and ADEN=0) except for bit ADVREGEN which must be 1 (and the software must have wait for the startup time of the voltage regulator)" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="ADC is disabled (OFF state)" start="0x0" />
+        <Enum name="B_0x1" description="Write 1 to enable the ADC." start="0x1" />
+      </BitField>
+      <BitField name="ADDIS" description="ADC disable command This bit is set by software to disable the ADC (ADDIS command) and put it into power-down state (OFF state). It is cleared by hardware once the ADC is effectively disabled (ADEN is also cleared by hardware at this time). Note: The software is allowed to set ADDIS only when ADEN=1 and both ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing)" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no ADDIS command ongoing" start="0x0" />
+        <Enum name="B_0x1" description="Write 1 to disable the ADC. Read 1 means that an ADDIS command is in progress. " start="0x1" />
+      </BitField>
+      <BitField name="ADSTART" description="ADC start of regular conversion This bit is set by software to start ADC conversion of regular channels. Depending on the configuration bits EXTEN, a conversion will start immediately (software trigger configuration) or once a regular hardware trigger event occurs (hardware trigger configuration). It is cleared by hardware: in single conversion mode (CONT=0, DISCEN=0) when software trigger is selected (EXTEN=0x0): at the assertion of the End of Regular Conversion Sequence (EOS) flag. In discontinuous conversion mode (CONT=0, DISCEN=1), when the software trigger is selected (EXTEN=0x0): at the end of conversion (EOC) flag. in all other cases: after the execution of the ADSTP command, at the same time that ADSTP is cleared by hardware. Note: The software is allowed to set ADSTART only when ADEN=1 and ADDIS=0 (ADC is enabled and there is no pending request to disable the ADC) In auto-injection mode (JAUTO=1), regular and auto-injected conversions are started by setting bit ADSTART (JADSTART must be kept cleared)" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No ADC regular conversion is ongoing." start="0x0" />
+        <Enum name="B_0x1" description="Write 1 to start regular conversions. Read 1 means that the ADC is operating and eventually converting a regular channel." start="0x1" />
+      </BitField>
+      <BitField name="JADSTART" description="ADC start of injected conversion This bit is set by software to start ADC conversion of injected channels. Depending on the configuration bits JEXTEN, a conversion will start immediately (software trigger configuration) or once an injected hardware trigger event occurs (hardware trigger configuration). It is cleared by hardware: in single conversion mode when software trigger is selected (JEXTSEL=0x0): at the assertion of the End of Injected Conversion Sequence (JEOS) flag. in all cases: after the execution of the JADSTP command, at the same time that JADSTP is cleared by hardware. Note: The software is allowed to set JADSTART only when ADEN=1 and ADDIS=0 (ADC is enabled and there is no pending request to disable the ADC). In auto-injection mode (JAUTO=1), regular and auto-injected conversions are started by setting bit ADSTART (JADSTART must be kept cleared)" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No ADC injected conversion is ongoing." start="0x0" />
+        <Enum name="B_0x1" description="Write 1 to start injected conversions. Read 1 means that the ADC is operating and eventually converting an injected channel." start="0x1" />
+      </BitField>
+      <BitField name="ADSTP" description="ADC stop of regular conversion command This bit is set by software to stop and discard an ongoing regular conversion (ADSTP Command). It is cleared by hardware when the conversion is effectively discarded and the ADC regular sequence and triggers can be re-configured. The ADC is then ready to accept a new start of regular conversions (ADSTART command). Note: The software is allowed to set ADSTP only when ADSTART=1 and ADDIS=0 (ADC is enabled and eventually converting a regular conversion and there is no pending request to disable the ADC). In auto-injection mode (JAUTO=1), setting ADSTP bit aborts both regular and injected conversions (do not use JADSTP). In dual ADC regular simultaneous mode and interleaved mode, the bit ADSTP of the master ADC must be used to stop regular conversions. The other ADSTP bit is inactive." start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No ADC stop regular conversion command ongoing" start="0x0" />
+        <Enum name="B_0x1" description="Write 1 to stop regular conversions ongoing. Read 1 means that an ADSTP command is in progress." start="0x1" />
+      </BitField>
+      <BitField name="JADSTP" description="ADC stop of injected conversion command This bit is set by software to stop and discard an ongoing injected conversion (JADSTP Command). It is cleared by hardware when the conversion is effectively discarded and the ADC injected sequence and triggers can be re-configured. The ADC is then ready to accept a new start of injected conversions (JADSTART command). Note: The software is allowed to set JADSTP only when JADSTART=1 and ADDIS=0 (ADC is enabled and eventually converting an injected conversion and there is no pending request to disable the ADC). In auto-injection mode (JAUTO=1), setting ADSTP bit aborts both regular and injected conversions (do not use JADSTP)" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No ADC stop injected conversion command ongoing" start="0x0" />
+        <Enum name="B_0x1" description="Write 1 to stop injected conversions ongoing. Read 1 means that an ADSTP command is in progress." start="0x1" />
+      </BitField>
+      <BitField name="BOOST" description="Boost mode control This bitfield is set and cleared by software to enable/disable the Boost mode. Note: The software is allowed to write this bit only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing). When dual mode is enabled (bits DAMDF of ADCx_CCR register are not equal to zero), the BOOST bitfield of the slave ADC is no more writable and its content must be equal to the master ADC BOOST bitfield." start="8" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="used when ADC clock ≤ 6.25 MHz" start="0x0" />
+        <Enum name="B_0x1" description="used when 6.25 MHz &lt; ADC clock frequency≤ 12.5 MHz" start="0x1" />
+        <Enum name="B_0x2" description="used when 12.5 MHz &lt; ADC clock ≤25.0 MHz" start="0x2" />
+        <Enum name="B_0x3" description="used when 25.0 MHz &lt; ADC clock ≤ 50.0 MHz" start="0x3" />
+      </BitField>
+      <BitField name="ADCALLIN" description="Linearity calibration This bit is set and cleared by software to enable the Linearity calibration. Note: The software is allowed to write this bit only when the ADC is disabled and is not calibrating (ADCAL=0, JADSTART=0, JADSTP=0, ADSTART=0, ADSTP=0, ADDIS=0 and ADEN=0)." start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Writing ADCAL will launch a calibration without the Linearity calibration." start="0x0" />
+        <Enum name="B_0x1" description="Writing ADCAL will launch a calibration with he Linearity calibration." start="0x1" />
+      </BitField>
+      <BitField name="LINCALRDYW1" description="Linearity calibration ready Word 1 Refer to LINCALRDYW6 description. Note: ADC_CALFACT2[29:0] corresponds linearity correction factor bits[29:0]. The software is allowed to toggle this bit only if the LINCALRDYW6, LINCALRDYW5, LINCALRDYW4, LINCALRDYW3 and LINCALRDYW2 bits are left unchanged." start="22" size="1" access="Read/Write" />
+      <BitField name="LINCALRDYW2" description="Linearity calibration ready Word 2 Refer to LINCALRDYW6 description. Note: ADC_CALFACT2[29:0] corresponds linearity correction factor bits[59:30]. The software is allowed to toggle this bit only if the LINCALRDYW6, LINCALRDYW5, LINCALRDYW4, LINCALRDYW3 and LINCALRDYW1 bits are left unchanged." start="23" size="1" access="Read/Write" />
+      <BitField name="LINCALRDYW3" description="Linearity calibration ready Word 3 Refer to LINCALRDYW6 description. Note: ADC_CALFACT2[29:0] corresponds linearity correction factor bits[89:60]. The software is allowed to toggle this bit only if the LINCALRDYW6, LINCALRDYW5, LINCALRDYW4, LINCALRDYW2 and LINCALRDYW1 bits are left unchanged." start="24" size="1" access="Read/Write" />
+      <BitField name="LINCALRDYW4" description="Linearity calibration ready Word 4 Refer to LINCALRDYW6 description. Note: ADC_CALFACT2[29:0] correspond linearity correction factor bits[119:90]. The software is allowed to toggle this bit only if the LINCALRDYW6, LINCALRDYW5, LINCALRDYW3, LINCALRDYW2 and LINCALRDYW1 bits are left unchanged." start="25" size="1" access="Read/Write" />
+      <BitField name="LINCALRDYW5" description="Linearity calibration ready Word 5 Refer to LINCALRDYW6 description. Note: ADC_CALFACT2[29:0] corresponds linearity correction factor bits[149:120]. The software is allowed to toggle this bit only if the LINCALRDYW6, LINCALRDYW5, LINCALRDYW3, LINCALRDYW2 and LINCALRDYW1 bits are left unchanged." start="26" size="1" access="Read/Write" />
+      <BitField name="LINCALRDYW6" description="Linearity calibration ready Word 6 This control / status bit allows to read/write the 6th linearity calibration factor. When the linearity calibration is complete, this bit is set. A bit clear will launch the transfer of the linearity factor 6 into the LINCALFACT[29:0] of the ADC_CALFACT2 register. The bit will be reset by hardware when the ADC_CALFACT2 register can be read (software must poll the bit until it is cleared). When the LINCALRDYW6 bit is reset, a new linearity factor 6 value can be written into the LINCALFACT[29:0] of the ADC_CALFACT2 register. A bit set will launch the linearity factor 6 update and the bit will be effectively set by hardware once the update will be done (software must poll the bit until it is set to indicate the write is effective). Note: ADC_CALFACT2[29:10] contains 0. ADC_CALFACT2[9:0] corresponds linearity correction factor bits[159:150]. The software is allowed to toggle this bit only if the LINCALRDYW5, LINCALRDYW4, LINCALRDYW3, LINCALRDYW2 and LINCALRDYW1 bits are left unchanged, see chapter for details. The software is allowed to update the linearity calibration factor by writing LINCALRDYWx only when ADEN=1 and ADSTART=0 and JADSTART=0 (ADC enabled and no conversion is ongoing)" start="27" size="1" access="Read/Write" />
+      <BitField name="ADVREGEN" description="ADC voltage regulator enable This bits is set by software to enable the ADC voltage regulator. Before performing any operation such as launching a calibration or enabling the ADC, the ADC voltage regulator must first be enabled and the software must wait for the regulator start-up time. For more details about the ADC voltage regulator enable and disable sequences, refer to (ADVREGEN). The software can program this bitfield only when the ADC is disabled (ADCAL=0, JADSTART=0, ADSTART=0, ADSTP=0, ADDIS=0 and ADEN=0)." start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="ADC Voltage regulator disabled" start="0x0" />
+        <Enum name="B_0x1" description="ADC Voltage regulator enabled." start="0x1" />
+      </BitField>
+      <BitField name="DEEPPWD" description="Deep-power-down enable This bit is set and cleared by software to put the ADC in deep-power-down mode. Note: The software is allowed to write this bit only when the ADC is disabled (ADCAL=0, JADSTART=0, JADSTP=0, ADSTART=0, ADSTP=0, ADDIS=0 and ADEN=0)." start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="ADC not in deep-power down" start="0x0" />
+        <Enum name="B_0x1" description="ADC in deep-power-down (default reset state)" start="0x1" />
+      </BitField>
+      <BitField name="ADCALDIF" description="Differential mode for calibration This bit is set and cleared by software to configure the single-ended or differential inputs mode for the calibration. Note: The software is allowed to write this bit only when the ADC is disabled and is not calibrating (ADCAL=0, JADSTART=0, JADSTP=0, ADSTART=0, ADSTP=0, ADDIS=0 and ADEN=0)." start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Writing ADCAL will launch a calibration in Single-ended inputs Mode." start="0x0" />
+        <Enum name="B_0x1" description="Writing ADCAL will launch a calibration in Differential inputs Mode." start="0x1" />
+      </BitField>
+      <BitField name="ADCAL" description="ADC calibration This bit is set by software to start the calibration of the ADC. Program first the bit ADCALDIF to determine if this calibration applies for single-ended or differential inputs mode. It is cleared by hardware after calibration is complete. Note: The software is allowed to launch a calibration by setting ADCAL only when ADEN=0. The software is allowed to update the calibration factor by writing ADC_CALFACT only when ADEN=1 and ADSTART=0 and JADSTART=0 (ADC enabled and no conversion is ongoing)" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Calibration complete" start="0x0" />
+        <Enum name="B_0x1" description="Write 1 to calibrate the ADC. Read at 1 means that a calibration in progress." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="ADC_CFGR" description="ADC configuration register " start="+0xc" size="4" reset_value="0x80000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DMNGT" description="Data Management configuration This bit is set and cleared by software to select how ADC interface output data are managed. Note: The software is allowed to write this bit only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing). In dual-ADC modes, this bit is not relevant and replaced by control bit DAMDF of the ADCx_CCR register." start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Regular conversion data stored in DR only" start="0x0" />
+        <Enum name="B_0x1" description="DMA One Shot Mode selected" start="0x1" />
+        <Enum name="B_0x2" description="DFSDM mode selected" start="0x2" />
+        <Enum name="B_0x3" description="DMA Circular Mode selected" start="0x3" />
+      </BitField>
+      <BitField name="RES" description="Data resolution These bits are written by software to select the resolution of the conversion. Others: Reserved, must not be used. Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing)." start="2" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="16 bits" start="0x0" />
+        <Enum name="B_0x1" description="14 bits in legacy mode (not optimized power consumption)" start="0x1" />
+        <Enum name="B_0x2" description="12 bits in legacy mode (not optimized power consumption)" start="0x2" />
+        <Enum name="B_0x5" description="14 bits" start="0x5" />
+        <Enum name="B_0x6" description="12 bits" start="0x6" />
+        <Enum name="B_0x3" description="10 bits" start="0x3" />
+        <Enum name="B_0x7" description="8 bits" start="0x7" />
+      </BitField>
+      <BitField name="EXTSEL" description="External trigger selection for regular group These bits select the external event used to trigger the start of conversion of a regular group: ... Note: The software is allowed to write these bits only when ADSTART=0 (which ensures that no regular conversion is ongoing)." start="5" size="5" access="Read/Write">
+        <Enum name="B_0x0" description="Event 0" start="0x0" />
+        <Enum name="B_0x1" description="Event 1" start="0x1" />
+        <Enum name="B_0x2" description="Event 2" start="0x2" />
+        <Enum name="B_0x3" description="Event 3" start="0x3" />
+        <Enum name="B_0x4" description="Event 4" start="0x4" />
+        <Enum name="B_0x5" description="Event 5" start="0x5" />
+        <Enum name="B_0x6" description="Event 6" start="0x6" />
+        <Enum name="B_0x7" description="Event 7" start="0x7" />
+        <Enum name="B_0x1F" description="Event 31" start="0x1F" />
+      </BitField>
+      <BitField name="EXTEN" description="External trigger enable and polarity selection for regular channels These bits are set and cleared by software to select the external trigger polarity and enable the trigger of a regular group. Note: The software is allowed to write these bits only when ADSTART=0 (which ensures that no regular conversion is ongoing)." start="10" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Hardware trigger detection disabled (conversions can be launched by software)" start="0x0" />
+        <Enum name="B_0x1" description="Hardware trigger detection on the rising edge" start="0x1" />
+        <Enum name="B_0x2" description="Hardware trigger detection on the falling edge" start="0x2" />
+        <Enum name="B_0x3" description="Hardware trigger detection on both the rising and falling edges" start="0x3" />
+      </BitField>
+      <BitField name="OVRMOD" description="Overrun Mode This bit is set and cleared by software and configure the way data overrun is managed. Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no regular conversion is ongoing)." start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="ADC_DR register is preserved with the old data when an overrun is detected. " start="0x0" />
+        <Enum name="B_0x1" description="ADC_DR register is overwritten with the last conversion result when an overrun is detected." start="0x1" />
+      </BitField>
+      <BitField name="CONT" description="Single / continuous conversion mode for regular conversions This bit is set and cleared by software. If it is set, regular conversion takes place continuously until it is cleared. Note: It is not possible to have both discontinuous mode and continuous mode enabled: it is forbidden to set both DISCEN=1 and CONT=1. The software is allowed to write this bit only when ADSTART=0 (which ensures that no regular conversion is ongoing). When dual mode is enabled (DAMDF bits in ADCx_CCR register are not equal to zero), the bit CONT of the slave ADC is no more writable and its content is equal to the bit CONT of the master ADC." start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Single conversion mode" start="0x0" />
+        <Enum name="B_0x1" description="Continuous conversion mode" start="0x1" />
+      </BitField>
+      <BitField name="AUTDLY" description="Delayed conversion mode This bit is set and cleared by software to enable/disable the Auto Delayed Conversion mode.. Note: The software is allowed to write this bit only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing). When dual mode is enabled (DAMDF bits in ADCx_CCR register are not equal to zero), the bit AUTDLY of the slave ADC is no more writable and its content is equal to the bit AUTDLY of the master ADC." start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Auto-delayed conversion mode off" start="0x0" />
+        <Enum name="B_0x1" description="Auto-delayed conversion mode on" start="0x1" />
+      </BitField>
+      <BitField name="DISCEN" description="Discontinuous mode for regular channels This bit is set and cleared by software to enable/disable Discontinuous mode for regular channels. Note: It is not possible to have both discontinuous mode and continuous mode enabled: it is forbidden to set both DISCEN=1 and CONT=1. It is not possible to use both auto-injected mode and discontinuous mode simultaneously: the bits DISCEN and JDISCEN must be kept cleared by software when JAUTO is set. The software is allowed to write this bit only when ADSTART=0 (which ensures that no regular conversion is ongoing). When dual mode is enabled (DAMDF bits in ADCx_CCR register are not equal to zero), the bit DISCEN of the slave ADC is no more writable and its content is equal to the bit DISCEN of the master ADC." start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Discontinuous mode for regular channels disabled" start="0x0" />
+        <Enum name="B_0x1" description="Discontinuous mode for regular channels enabled" start="0x1" />
+      </BitField>
+      <BitField name="DISCNUM" description="Discontinuous mode channel count These bits are written by software to define the number of regular channels to be converted in discontinuous mode, after receiving an external trigger. ... Note: The software is allowed to write these bits only when ADSTART=0 (which ensures that no regular conversion is ongoing). When dual mode is enabled (DAMDF bits in ADCx_CCR register are not equal to zero), the bits DISCNUM[2:0] of the slave ADC are no more writable and their content is equal to the bits DISCNUM[2:0] of the master ADC." start="17" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="1 channel" start="0x0" />
+        <Enum name="B_0x1" description="2 channels" start="0x1" />
+        <Enum name="B_0x7" description="8 channels" start="0x7" />
+      </BitField>
+      <BitField name="JDISCEN" description="Discontinuous mode on injected channels This bit is set and cleared by software to enable/disable discontinuous mode on the injected channels of a group. Note: The software is allowed to write this bit only when JADSTART=0 (which ensures that no injected conversion is ongoing). It is not possible to use both auto-injected mode and discontinuous mode simultaneously: the bits DISCEN and JDISCEN must be kept cleared by software when JAUTO is set. When dual mode is enabled (bits DAMDF of ADCx_CCR register are not equal to zero), the bit JDISCEN of the slave ADC is no more writable and its content is equal to the bit JDISCEN of the master ADC." start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Discontinuous mode on injected channels disabled" start="0x0" />
+        <Enum name="B_0x1" description="Discontinuous mode on injected channels enabled" start="0x1" />
+      </BitField>
+      <BitField name="JQM" description="JSQR queue mode This bit is set and cleared by software. It defines how an empty Queue is managed. Refer to for more information. Note: The software is allowed to write this bit only when JADSTART=0 (which ensures that no injected conversion is ongoing). When dual mode is enabled (DAMDF bits in ADCx_CCR register are not equal to zero), the bit JQM of the slave ADC is no more writable and its content is equal to the bit JQM of the master ADC." start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="JSQR Mode 0: The Queue is never empty and maintains the last written configuration into JSQR." start="0x0" />
+        <Enum name="B_0x1" description="JSQR Mode 1: The Queue can be empty and when this occurs, the software and hardware triggers of the injected sequence are both internally disabled just after the completion of the last valid injected sequence." start="0x1" />
+      </BitField>
+      <BitField name="AWD1SGL" description="Enable the watchdog 1 on a single channel or on all channels This bit is set and cleared by software to enable the analog watchdog on the channel identified by the AWD1CH[4:0] bits or on all the channels Note: The software is allowed to write this bit only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing)." start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Analog watchdog 1 enabled on all channels" start="0x0" />
+        <Enum name="B_0x1" description="Analog watchdog 1 enabled on a single channel" start="0x1" />
+      </BitField>
+      <BitField name="AWD1EN" description="Analog watchdog 1 enable on regular channels This bit is set and cleared by software Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no regular conversion is ongoing)." start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Analog watchdog 1 disabled on regular channels" start="0x0" />
+        <Enum name="B_0x1" description="Analog watchdog 1 enabled on regular channels" start="0x1" />
+      </BitField>
+      <BitField name="JAWD1EN" description="Analog watchdog 1 enable on injected channels This bit is set and cleared by software Note: The software is allowed to write this bit only when JADSTART=0 (which ensures that no injected conversion is ongoing)." start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Analog watchdog 1 disabled on injected channels" start="0x0" />
+        <Enum name="B_0x1" description="Analog watchdog 1 enabled on injected channels" start="0x1" />
+      </BitField>
+      <BitField name="JAUTO" description="Automatic injected group conversion This bit is set and cleared by software to enable/disable automatic injected group conversion after regular group conversion. Note: The software is allowed to write this bit only when ADSTART=0 and JADSTART=0 (which ensures that no regular nor injected conversion is ongoing). When dual mode is enabled (DAMDF bits in ADCx_CCR register are not equal to zero), the bit JAUTO of the slave ADC is no more writable and its content is equal to the bit JAUTO of the master ADC." start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Automatic injected group conversion disabled" start="0x0" />
+        <Enum name="B_0x1" description="Automatic injected group conversion enabled" start="0x1" />
+      </BitField>
+      <BitField name="AWD1CH" description="Analog watchdog 1 channel selection These bits are set and cleared by software. They select the input channel to be guarded by the analog watchdog. ..... others: Reserved, must not be used Note: The channel selected by AWD1CH must be also selected into the SQRi or JSQRi registers. The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing)." start="26" size="5" access="Read/Write">
+        <Enum name="B_0x0" description="ADC analog input channel-0 monitored by AWD1" start="0x0" />
+        <Enum name="B_0x1" description="ADC analog input channel-1 monitored by AWD1" start="0x1" />
+        <Enum name="B_0x12" description="ADC analog input channel-19 monitored by AWD1" start="0x12" />
+      </BitField>
+      <BitField name="JQDIS" description="Injected Queue disable These bits are set and cleared by software to disable the Injected Queue mechanism: Note: The software is allowed to write this bit only when ADSTART=0 and JADSTART=0 (which ensures that no regular nor injected conversion is ongoing). A set or reset of JQDIS bit causes the injected queue to be flushed and the JSQR register is cleared." start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Injected Queue enabled" start="0x0" />
+        <Enum name="B_0x1" description="Injected Queue disabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="ADC_CFGR2" description="ADC configuration register 2 " start="+0x10" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ROVSE" description="Regular Oversampling Enable This bit is set and cleared by software to enable regular oversampling. Note: The software is allowed to write this bit only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing)" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Regular Oversampling disabled" start="0x0" />
+        <Enum name="B_0x1" description="Regular Oversampling enabled" start="0x1" />
+      </BitField>
+      <BitField name="JOVSE" description="Injected Oversampling Enable This bit is set and cleared by software to enable injected oversampling. Note: The software is allowed to write this bit only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing)" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Injected Oversampling disabled" start="0x0" />
+        <Enum name="B_0x1" description="Injected Oversampling enabled" start="0x1" />
+      </BitField>
+      <BitField name="OVSS" description="Oversampling right shift This bitfield is set and cleared by software to define the right shifting applied to the raw oversampling result. Others: Reserved, must not be used. Note: The software is allowed to write these bits only when ADSTART=0 (which ensures that no conversion is ongoing)." start="5" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No right shift" start="0x0" />
+        <Enum name="B_0x1" description="Shift right 1-bit" start="0x1" />
+        <Enum name="B_0x2" description="Shift right 2-bits" start="0x2" />
+        <Enum name="B_0x3" description="Shift right 3-bits" start="0x3" />
+        <Enum name="B_0x4" description="Shift right 4-bits" start="0x4" />
+        <Enum name="B_0x5" description="Shift right 5-bits" start="0x5" />
+        <Enum name="B_0x6" description="Shift right 6-bits" start="0x6" />
+        <Enum name="B_0x7" description="Shift right 7-bits" start="0x7" />
+        <Enum name="B_0x8" description="Shift right 8-bits" start="0x8" />
+        <Enum name="B_0x9" description="Shift right 9-bits" start="0x9" />
+        <Enum name="B_0xA" description="Shift right 10-bits" start="0xA" />
+        <Enum name="B_0xB" description="Shift right 11-bits" start="0xB" />
+      </BitField>
+      <BitField name="TROVS" description="Triggered Regular Oversampling This bit is set and cleared by software to enable triggered oversampling Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing)." start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="All oversampled conversions for a channel are done consecutively following a trigger" start="0x0" />
+        <Enum name="B_0x1" description="Each oversampled conversion for a channel needs a new trigger" start="0x1" />
+      </BitField>
+      <BitField name="ROVSM" description="Regular Oversampling mode This bit is set and cleared by software to select the regular oversampling mode. Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing)." start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Continued mode: When injected conversions are triggered, the oversampling is temporary stopped and continued after the injection sequence (oversampling buffer is maintained during injected sequence)" start="0x0" />
+        <Enum name="B_0x1" description="Resumed mode: When injected conversions are triggered, the current oversampling is aborted and resumed from start after the injection sequence (oversampling buffer is zeroed by injected sequence start)" start="0x1" />
+      </BitField>
+      <BitField name="RSHIFT1" description="Right-shift data after Offset 1 correction This bitfield is set and cleared by software to right-shift 1-bit data after offset1 correction. This bit can only be used for 8-bit and 16-bit data format (see (ADC_DR, ADC_JDRy, OFFSETy, OFFSETy_CH, OVSS, LSHIFT, RSHIFT, SSATE) for details)." start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Right-shifting disabled" start="0x0" />
+        <Enum name="B_0x1" description="Data is right-shifted 1-bit." start="0x1" />
+      </BitField>
+      <BitField name="RSHIFT2" description="Right-shift data after Offset 2 correction Refer to RSHIFT1 description" start="12" size="1" access="Read/Write" />
+      <BitField name="RSHIFT3" description="Right-shift data after Offset 3 correction Refer to RSHIFT1 description" start="13" size="1" access="Read/Write" />
+      <BitField name="RSHIFT4" description="Right-shift data after Offset 4 correction Refer to RSHIFT1 description." start="14" size="1" access="Read/Write" />
+      <BitField name="OSVR" description="Oversampling ratio This bitfield is set and cleared by software to define the oversampling ratio. 2: 3x ... 1023: 1024x Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing)." start="16" size="10" access="Read/Write">
+        <Enum name="B_0x0" description="1x (no oversampling)" start="0x0" />
+        <Enum name="B_0x1" description="2x" start="0x1" />
+      </BitField>
+      <BitField name="LSHIFT" description="Left shift factor This bitfield is set and cleared by software to define the left shifting applied to the final result with or without oversampling. Note: The software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing)." start="28" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No left shift" start="0x0" />
+        <Enum name="B_0x1" description="Shift left 1-bit" start="0x1" />
+        <Enum name="B_0x2" description="Shift left 2-bits" start="0x2" />
+        <Enum name="B_0x3" description="Shift left 3-bits" start="0x3" />
+        <Enum name="B_0x4" description="Shift left 4-bits" start="0x4" />
+        <Enum name="B_0x5" description="Shift left 5-bits" start="0x5" />
+        <Enum name="B_0x6" description="Shift left 6-bits" start="0x6" />
+        <Enum name="B_0x7" description="Shift left 7-bits" start="0x7" />
+        <Enum name="B_0x8" description="Shift left 8-bits" start="0x8" />
+        <Enum name="B_0x9" description="Shift left 9-bits" start="0x9" />
+        <Enum name="B_0xA" description="Shift left 10-bits" start="0xA" />
+        <Enum name="B_0xB" description="Shift left 11-bits" start="0xB" />
+        <Enum name="B_0xC" description="Shift left 12-bits" start="0xC" />
+        <Enum name="B_0xD" description="Shift left 13-bits" start="0xD" />
+        <Enum name="B_0xE" description="Shift left 14-bits" start="0xE" />
+        <Enum name="B_0xF" description="Shift left 15-bits" start="0xF" />
+      </BitField>
+    </Register>
+    <Register name="ADC_SMPR1" description="ADC sample time register 1 " start="+0x14" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SMP0" description="Channel x sampling time selection (x = 0 to 9) These bits are written by software to select the sampling time individually for each channel. During sample cycles, the channel selection bits must remain unchanged. Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing)." start="0" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="1.5 ADC clock cycles" start="0x0" />
+        <Enum name="B_0x1" description="2.5 ADC clock cycles" start="0x1" />
+        <Enum name="B_0x2" description="8.5 ADC clock cycles" start="0x2" />
+        <Enum name="B_0x3" description="16.5 ADC clock cycles" start="0x3" />
+        <Enum name="B_0x4" description="32.5 ADC clock cycles" start="0x4" />
+        <Enum name="B_0x5" description="64.5 ADC clock cycles" start="0x5" />
+        <Enum name="B_0x6" description="387.5 ADC clock cycles" start="0x6" />
+        <Enum name="B_0x7" description="810.5 ADC clock cycles" start="0x7" />
+      </BitField>
+      <BitField name="SMP1" description="Channel x sampling time selection (x = 0 to 9) These bits are written by software to select the sampling time individually for each channel. During sample cycles, the channel selection bits must remain unchanged. Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing)." start="3" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="1.5 ADC clock cycles" start="0x0" />
+        <Enum name="B_0x1" description="2.5 ADC clock cycles" start="0x1" />
+        <Enum name="B_0x2" description="8.5 ADC clock cycles" start="0x2" />
+        <Enum name="B_0x3" description="16.5 ADC clock cycles" start="0x3" />
+        <Enum name="B_0x4" description="32.5 ADC clock cycles" start="0x4" />
+        <Enum name="B_0x5" description="64.5 ADC clock cycles" start="0x5" />
+        <Enum name="B_0x6" description="387.5 ADC clock cycles" start="0x6" />
+        <Enum name="B_0x7" description="810.5 ADC clock cycles" start="0x7" />
+      </BitField>
+      <BitField name="SMP2" description="Channel x sampling time selection (x = 0 to 9) These bits are written by software to select the sampling time individually for each channel. During sample cycles, the channel selection bits must remain unchanged. Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing)." start="6" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="1.5 ADC clock cycles" start="0x0" />
+        <Enum name="B_0x1" description="2.5 ADC clock cycles" start="0x1" />
+        <Enum name="B_0x2" description="8.5 ADC clock cycles" start="0x2" />
+        <Enum name="B_0x3" description="16.5 ADC clock cycles" start="0x3" />
+        <Enum name="B_0x4" description="32.5 ADC clock cycles" start="0x4" />
+        <Enum name="B_0x5" description="64.5 ADC clock cycles" start="0x5" />
+        <Enum name="B_0x6" description="387.5 ADC clock cycles" start="0x6" />
+        <Enum name="B_0x7" description="810.5 ADC clock cycles" start="0x7" />
+      </BitField>
+      <BitField name="SMP3" description="Channel x sampling time selection (x = 0 to 9) These bits are written by software to select the sampling time individually for each channel. During sample cycles, the channel selection bits must remain unchanged. Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing)." start="9" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="1.5 ADC clock cycles" start="0x0" />
+        <Enum name="B_0x1" description="2.5 ADC clock cycles" start="0x1" />
+        <Enum name="B_0x2" description="8.5 ADC clock cycles" start="0x2" />
+        <Enum name="B_0x3" description="16.5 ADC clock cycles" start="0x3" />
+        <Enum name="B_0x4" description="32.5 ADC clock cycles" start="0x4" />
+        <Enum name="B_0x5" description="64.5 ADC clock cycles" start="0x5" />
+        <Enum name="B_0x6" description="387.5 ADC clock cycles" start="0x6" />
+        <Enum name="B_0x7" description="810.5 ADC clock cycles" start="0x7" />
+      </BitField>
+      <BitField name="SMP4" description="Channel x sampling time selection (x = 0 to 9) These bits are written by software to select the sampling time individually for each channel. During sample cycles, the channel selection bits must remain unchanged. Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing)." start="12" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="1.5 ADC clock cycles" start="0x0" />
+        <Enum name="B_0x1" description="2.5 ADC clock cycles" start="0x1" />
+        <Enum name="B_0x2" description="8.5 ADC clock cycles" start="0x2" />
+        <Enum name="B_0x3" description="16.5 ADC clock cycles" start="0x3" />
+        <Enum name="B_0x4" description="32.5 ADC clock cycles" start="0x4" />
+        <Enum name="B_0x5" description="64.5 ADC clock cycles" start="0x5" />
+        <Enum name="B_0x6" description="387.5 ADC clock cycles" start="0x6" />
+        <Enum name="B_0x7" description="810.5 ADC clock cycles" start="0x7" />
+      </BitField>
+      <BitField name="SMP5" description="Channel x sampling time selection (x = 0 to 9) These bits are written by software to select the sampling time individually for each channel. During sample cycles, the channel selection bits must remain unchanged. Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing)." start="15" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="1.5 ADC clock cycles" start="0x0" />
+        <Enum name="B_0x1" description="2.5 ADC clock cycles" start="0x1" />
+        <Enum name="B_0x2" description="8.5 ADC clock cycles" start="0x2" />
+        <Enum name="B_0x3" description="16.5 ADC clock cycles" start="0x3" />
+        <Enum name="B_0x4" description="32.5 ADC clock cycles" start="0x4" />
+        <Enum name="B_0x5" description="64.5 ADC clock cycles" start="0x5" />
+        <Enum name="B_0x6" description="387.5 ADC clock cycles" start="0x6" />
+        <Enum name="B_0x7" description="810.5 ADC clock cycles" start="0x7" />
+      </BitField>
+      <BitField name="SMP6" description="Channel x sampling time selection (x = 0 to 9) These bits are written by software to select the sampling time individually for each channel. During sample cycles, the channel selection bits must remain unchanged. Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing)." start="18" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="1.5 ADC clock cycles" start="0x0" />
+        <Enum name="B_0x1" description="2.5 ADC clock cycles" start="0x1" />
+        <Enum name="B_0x2" description="8.5 ADC clock cycles" start="0x2" />
+        <Enum name="B_0x3" description="16.5 ADC clock cycles" start="0x3" />
+        <Enum name="B_0x4" description="32.5 ADC clock cycles" start="0x4" />
+        <Enum name="B_0x5" description="64.5 ADC clock cycles" start="0x5" />
+        <Enum name="B_0x6" description="387.5 ADC clock cycles" start="0x6" />
+        <Enum name="B_0x7" description="810.5 ADC clock cycles" start="0x7" />
+      </BitField>
+      <BitField name="SMP7" description="Channel x sampling time selection (x = 0 to 9) These bits are written by software to select the sampling time individually for each channel. During sample cycles, the channel selection bits must remain unchanged. Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing)." start="21" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="1.5 ADC clock cycles" start="0x0" />
+        <Enum name="B_0x1" description="2.5 ADC clock cycles" start="0x1" />
+        <Enum name="B_0x2" description="8.5 ADC clock cycles" start="0x2" />
+        <Enum name="B_0x3" description="16.5 ADC clock cycles" start="0x3" />
+        <Enum name="B_0x4" description="32.5 ADC clock cycles" start="0x4" />
+        <Enum name="B_0x5" description="64.5 ADC clock cycles" start="0x5" />
+        <Enum name="B_0x6" description="387.5 ADC clock cycles" start="0x6" />
+        <Enum name="B_0x7" description="810.5 ADC clock cycles" start="0x7" />
+      </BitField>
+      <BitField name="SMP8" description="Channel x sampling time selection (x = 0 to 9) These bits are written by software to select the sampling time individually for each channel. During sample cycles, the channel selection bits must remain unchanged. Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing)." start="24" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="1.5 ADC clock cycles" start="0x0" />
+        <Enum name="B_0x1" description="2.5 ADC clock cycles" start="0x1" />
+        <Enum name="B_0x2" description="8.5 ADC clock cycles" start="0x2" />
+        <Enum name="B_0x3" description="16.5 ADC clock cycles" start="0x3" />
+        <Enum name="B_0x4" description="32.5 ADC clock cycles" start="0x4" />
+        <Enum name="B_0x5" description="64.5 ADC clock cycles" start="0x5" />
+        <Enum name="B_0x6" description="387.5 ADC clock cycles" start="0x6" />
+        <Enum name="B_0x7" description="810.5 ADC clock cycles" start="0x7" />
+      </BitField>
+      <BitField name="SMP9" description="Channel x sampling time selection (x = 0 to 9) These bits are written by software to select the sampling time individually for each channel. During sample cycles, the channel selection bits must remain unchanged. Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing)." start="27" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="1.5 ADC clock cycles" start="0x0" />
+        <Enum name="B_0x1" description="2.5 ADC clock cycles" start="0x1" />
+        <Enum name="B_0x2" description="8.5 ADC clock cycles" start="0x2" />
+        <Enum name="B_0x3" description="16.5 ADC clock cycles" start="0x3" />
+        <Enum name="B_0x4" description="32.5 ADC clock cycles" start="0x4" />
+        <Enum name="B_0x5" description="64.5 ADC clock cycles" start="0x5" />
+        <Enum name="B_0x6" description="387.5 ADC clock cycles" start="0x6" />
+        <Enum name="B_0x7" description="810.5 ADC clock cycles" start="0x7" />
+      </BitField>
+    </Register>
+    <Register name="ADC_SMPR2" description="ADC sample time register 2 " start="+0x18" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SMP10" description="Channel x sampling time selection (x = 10 to 19) These bits are written by software to select the sampling time individually for each channel. During sampling cycles, the channel selection bits must remain unchanged. Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing)." start="0" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="1.5 ADC clock cycles" start="0x0" />
+        <Enum name="B_0x1" description="2.5 ADC clock cycles" start="0x1" />
+        <Enum name="B_0x2" description="8.5 ADC clock cycles" start="0x2" />
+        <Enum name="B_0x3" description="16.5 ADC clock cycles" start="0x3" />
+        <Enum name="B_0x4" description="32.5 ADC clock cycles" start="0x4" />
+        <Enum name="B_0x5" description="64.5 ADC clock cycles" start="0x5" />
+        <Enum name="B_0x6" description="387.5 ADC clock cycles" start="0x6" />
+        <Enum name="B_0x7" description="810.5 ADC clock cycles" start="0x7" />
+      </BitField>
+      <BitField name="SMP11" description="Channel x sampling time selection (x = 10 to 19) These bits are written by software to select the sampling time individually for each channel. During sampling cycles, the channel selection bits must remain unchanged. Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing)." start="3" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="1.5 ADC clock cycles" start="0x0" />
+        <Enum name="B_0x1" description="2.5 ADC clock cycles" start="0x1" />
+        <Enum name="B_0x2" description="8.5 ADC clock cycles" start="0x2" />
+        <Enum name="B_0x3" description="16.5 ADC clock cycles" start="0x3" />
+        <Enum name="B_0x4" description="32.5 ADC clock cycles" start="0x4" />
+        <Enum name="B_0x5" description="64.5 ADC clock cycles" start="0x5" />
+        <Enum name="B_0x6" description="387.5 ADC clock cycles" start="0x6" />
+        <Enum name="B_0x7" description="810.5 ADC clock cycles" start="0x7" />
+      </BitField>
+      <BitField name="SMP12" description="Channel x sampling time selection (x = 10 to 19) These bits are written by software to select the sampling time individually for each channel. During sampling cycles, the channel selection bits must remain unchanged. Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing)." start="6" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="1.5 ADC clock cycles" start="0x0" />
+        <Enum name="B_0x1" description="2.5 ADC clock cycles" start="0x1" />
+        <Enum name="B_0x2" description="8.5 ADC clock cycles" start="0x2" />
+        <Enum name="B_0x3" description="16.5 ADC clock cycles" start="0x3" />
+        <Enum name="B_0x4" description="32.5 ADC clock cycles" start="0x4" />
+        <Enum name="B_0x5" description="64.5 ADC clock cycles" start="0x5" />
+        <Enum name="B_0x6" description="387.5 ADC clock cycles" start="0x6" />
+        <Enum name="B_0x7" description="810.5 ADC clock cycles" start="0x7" />
+      </BitField>
+      <BitField name="SMP13" description="Channel x sampling time selection (x = 10 to 19) These bits are written by software to select the sampling time individually for each channel. During sampling cycles, the channel selection bits must remain unchanged. Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing)." start="9" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="1.5 ADC clock cycles" start="0x0" />
+        <Enum name="B_0x1" description="2.5 ADC clock cycles" start="0x1" />
+        <Enum name="B_0x2" description="8.5 ADC clock cycles" start="0x2" />
+        <Enum name="B_0x3" description="16.5 ADC clock cycles" start="0x3" />
+        <Enum name="B_0x4" description="32.5 ADC clock cycles" start="0x4" />
+        <Enum name="B_0x5" description="64.5 ADC clock cycles" start="0x5" />
+        <Enum name="B_0x6" description="387.5 ADC clock cycles" start="0x6" />
+        <Enum name="B_0x7" description="810.5 ADC clock cycles" start="0x7" />
+      </BitField>
+      <BitField name="SMP14" description="Channel x sampling time selection (x = 10 to 19) These bits are written by software to select the sampling time individually for each channel. During sampling cycles, the channel selection bits must remain unchanged. Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing)." start="12" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="1.5 ADC clock cycles" start="0x0" />
+        <Enum name="B_0x1" description="2.5 ADC clock cycles" start="0x1" />
+        <Enum name="B_0x2" description="8.5 ADC clock cycles" start="0x2" />
+        <Enum name="B_0x3" description="16.5 ADC clock cycles" start="0x3" />
+        <Enum name="B_0x4" description="32.5 ADC clock cycles" start="0x4" />
+        <Enum name="B_0x5" description="64.5 ADC clock cycles" start="0x5" />
+        <Enum name="B_0x6" description="387.5 ADC clock cycles" start="0x6" />
+        <Enum name="B_0x7" description="810.5 ADC clock cycles" start="0x7" />
+      </BitField>
+      <BitField name="SMP15" description="Channel x sampling time selection (x = 10 to 19) These bits are written by software to select the sampling time individually for each channel. During sampling cycles, the channel selection bits must remain unchanged. Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing)." start="15" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="1.5 ADC clock cycles" start="0x0" />
+        <Enum name="B_0x1" description="2.5 ADC clock cycles" start="0x1" />
+        <Enum name="B_0x2" description="8.5 ADC clock cycles" start="0x2" />
+        <Enum name="B_0x3" description="16.5 ADC clock cycles" start="0x3" />
+        <Enum name="B_0x4" description="32.5 ADC clock cycles" start="0x4" />
+        <Enum name="B_0x5" description="64.5 ADC clock cycles" start="0x5" />
+        <Enum name="B_0x6" description="387.5 ADC clock cycles" start="0x6" />
+        <Enum name="B_0x7" description="810.5 ADC clock cycles" start="0x7" />
+      </BitField>
+      <BitField name="SMP16" description="Channel x sampling time selection (x = 10 to 19) These bits are written by software to select the sampling time individually for each channel. During sampling cycles, the channel selection bits must remain unchanged. Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing)." start="18" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="1.5 ADC clock cycles" start="0x0" />
+        <Enum name="B_0x1" description="2.5 ADC clock cycles" start="0x1" />
+        <Enum name="B_0x2" description="8.5 ADC clock cycles" start="0x2" />
+        <Enum name="B_0x3" description="16.5 ADC clock cycles" start="0x3" />
+        <Enum name="B_0x4" description="32.5 ADC clock cycles" start="0x4" />
+        <Enum name="B_0x5" description="64.5 ADC clock cycles" start="0x5" />
+        <Enum name="B_0x6" description="387.5 ADC clock cycles" start="0x6" />
+        <Enum name="B_0x7" description="810.5 ADC clock cycles" start="0x7" />
+      </BitField>
+      <BitField name="SMP17" description="Channel x sampling time selection (x = 10 to 19) These bits are written by software to select the sampling time individually for each channel. During sampling cycles, the channel selection bits must remain unchanged. Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing)." start="21" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="1.5 ADC clock cycles" start="0x0" />
+        <Enum name="B_0x1" description="2.5 ADC clock cycles" start="0x1" />
+        <Enum name="B_0x2" description="8.5 ADC clock cycles" start="0x2" />
+        <Enum name="B_0x3" description="16.5 ADC clock cycles" start="0x3" />
+        <Enum name="B_0x4" description="32.5 ADC clock cycles" start="0x4" />
+        <Enum name="B_0x5" description="64.5 ADC clock cycles" start="0x5" />
+        <Enum name="B_0x6" description="387.5 ADC clock cycles" start="0x6" />
+        <Enum name="B_0x7" description="810.5 ADC clock cycles" start="0x7" />
+      </BitField>
+      <BitField name="SMP18" description="Channel x sampling time selection (x = 10 to 19) These bits are written by software to select the sampling time individually for each channel. During sampling cycles, the channel selection bits must remain unchanged. Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing)." start="24" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="1.5 ADC clock cycles" start="0x0" />
+        <Enum name="B_0x1" description="2.5 ADC clock cycles" start="0x1" />
+        <Enum name="B_0x2" description="8.5 ADC clock cycles" start="0x2" />
+        <Enum name="B_0x3" description="16.5 ADC clock cycles" start="0x3" />
+        <Enum name="B_0x4" description="32.5 ADC clock cycles" start="0x4" />
+        <Enum name="B_0x5" description="64.5 ADC clock cycles" start="0x5" />
+        <Enum name="B_0x6" description="387.5 ADC clock cycles" start="0x6" />
+        <Enum name="B_0x7" description="810.5 ADC clock cycles" start="0x7" />
+      </BitField>
+      <BitField name="SMP19" description="Channel x sampling time selection (x = 10 to 19) These bits are written by software to select the sampling time individually for each channel. During sampling cycles, the channel selection bits must remain unchanged. Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing)." start="27" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="1.5 ADC clock cycles" start="0x0" />
+        <Enum name="B_0x1" description="2.5 ADC clock cycles" start="0x1" />
+        <Enum name="B_0x2" description="8.5 ADC clock cycles" start="0x2" />
+        <Enum name="B_0x3" description="16.5 ADC clock cycles" start="0x3" />
+        <Enum name="B_0x4" description="32.5 ADC clock cycles" start="0x4" />
+        <Enum name="B_0x5" description="64.5 ADC clock cycles" start="0x5" />
+        <Enum name="B_0x6" description="387.5 ADC clock cycles" start="0x6" />
+        <Enum name="B_0x7" description="810.5 ADC clock cycles" start="0x7" />
+      </BitField>
+    </Register>
+    <Register name="ADC_PCSEL" description="ADC channel preselection register " start="+0x1c" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PCSEL0" description=":Channel x (VINP[i]) pre selection (x = 0 to 19) These bits are written by software to pre select the input channel at IO instance to be converted. Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing)." start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Input Channel x (Vinp x) is not pre selected for conversion, the ADC conversion result with this channel shows wrong result." start="0x0" />
+        <Enum name="B_0x1" description="Input Channel x (Vinp x) is pre selected for conversion" start="0x1" />
+      </BitField>
+      <BitField name="PCSEL1" description=":Channel x (VINP[i]) pre selection (x = 0 to 19) These bits are written by software to pre select the input channel at IO instance to be converted. Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing)." start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Input Channel x (Vinp x) is not pre selected for conversion, the ADC conversion result with this channel shows wrong result." start="0x0" />
+        <Enum name="B_0x1" description="Input Channel x (Vinp x) is pre selected for conversion" start="0x1" />
+      </BitField>
+      <BitField name="PCSEL2" description=":Channel x (VINP[i]) pre selection (x = 0 to 19) These bits are written by software to pre select the input channel at IO instance to be converted. Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing)." start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Input Channel x (Vinp x) is not pre selected for conversion, the ADC conversion result with this channel shows wrong result." start="0x0" />
+        <Enum name="B_0x1" description="Input Channel x (Vinp x) is pre selected for conversion" start="0x1" />
+      </BitField>
+      <BitField name="PCSEL3" description=":Channel x (VINP[i]) pre selection (x = 0 to 19) These bits are written by software to pre select the input channel at IO instance to be converted. Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing)." start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Input Channel x (Vinp x) is not pre selected for conversion, the ADC conversion result with this channel shows wrong result." start="0x0" />
+        <Enum name="B_0x1" description="Input Channel x (Vinp x) is pre selected for conversion" start="0x1" />
+      </BitField>
+      <BitField name="PCSEL4" description=":Channel x (VINP[i]) pre selection (x = 0 to 19) These bits are written by software to pre select the input channel at IO instance to be converted. Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing)." start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Input Channel x (Vinp x) is not pre selected for conversion, the ADC conversion result with this channel shows wrong result." start="0x0" />
+        <Enum name="B_0x1" description="Input Channel x (Vinp x) is pre selected for conversion" start="0x1" />
+      </BitField>
+      <BitField name="PCSEL5" description=":Channel x (VINP[i]) pre selection (x = 0 to 19) These bits are written by software to pre select the input channel at IO instance to be converted. Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing)." start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Input Channel x (Vinp x) is not pre selected for conversion, the ADC conversion result with this channel shows wrong result." start="0x0" />
+        <Enum name="B_0x1" description="Input Channel x (Vinp x) is pre selected for conversion" start="0x1" />
+      </BitField>
+      <BitField name="PCSEL6" description=":Channel x (VINP[i]) pre selection (x = 0 to 19) These bits are written by software to pre select the input channel at IO instance to be converted. Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing)." start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Input Channel x (Vinp x) is not pre selected for conversion, the ADC conversion result with this channel shows wrong result." start="0x0" />
+        <Enum name="B_0x1" description="Input Channel x (Vinp x) is pre selected for conversion" start="0x1" />
+      </BitField>
+      <BitField name="PCSEL7" description=":Channel x (VINP[i]) pre selection (x = 0 to 19) These bits are written by software to pre select the input channel at IO instance to be converted. Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing)." start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Input Channel x (Vinp x) is not pre selected for conversion, the ADC conversion result with this channel shows wrong result." start="0x0" />
+        <Enum name="B_0x1" description="Input Channel x (Vinp x) is pre selected for conversion" start="0x1" />
+      </BitField>
+      <BitField name="PCSEL8" description=":Channel x (VINP[i]) pre selection (x = 0 to 19) These bits are written by software to pre select the input channel at IO instance to be converted. Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing)." start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Input Channel x (Vinp x) is not pre selected for conversion, the ADC conversion result with this channel shows wrong result." start="0x0" />
+        <Enum name="B_0x1" description="Input Channel x (Vinp x) is pre selected for conversion" start="0x1" />
+      </BitField>
+      <BitField name="PCSEL9" description=":Channel x (VINP[i]) pre selection (x = 0 to 19) These bits are written by software to pre select the input channel at IO instance to be converted. Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing)." start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Input Channel x (Vinp x) is not pre selected for conversion, the ADC conversion result with this channel shows wrong result." start="0x0" />
+        <Enum name="B_0x1" description="Input Channel x (Vinp x) is pre selected for conversion" start="0x1" />
+      </BitField>
+      <BitField name="PCSEL10" description=":Channel x (VINP[i]) pre selection (x = 0 to 19) These bits are written by software to pre select the input channel at IO instance to be converted. Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing)." start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Input Channel x (Vinp x) is not pre selected for conversion, the ADC conversion result with this channel shows wrong result." start="0x0" />
+        <Enum name="B_0x1" description="Input Channel x (Vinp x) is pre selected for conversion" start="0x1" />
+      </BitField>
+      <BitField name="PCSEL11" description=":Channel x (VINP[i]) pre selection (x = 0 to 19) These bits are written by software to pre select the input channel at IO instance to be converted. Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing)." start="11" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Input Channel x (Vinp x) is not pre selected for conversion, the ADC conversion result with this channel shows wrong result." start="0x0" />
+        <Enum name="B_0x1" description="Input Channel x (Vinp x) is pre selected for conversion" start="0x1" />
+      </BitField>
+      <BitField name="PCSEL12" description=":Channel x (VINP[i]) pre selection (x = 0 to 19) These bits are written by software to pre select the input channel at IO instance to be converted. Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing)." start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Input Channel x (Vinp x) is not pre selected for conversion, the ADC conversion result with this channel shows wrong result." start="0x0" />
+        <Enum name="B_0x1" description="Input Channel x (Vinp x) is pre selected for conversion" start="0x1" />
+      </BitField>
+      <BitField name="PCSEL13" description=":Channel x (VINP[i]) pre selection (x = 0 to 19) These bits are written by software to pre select the input channel at IO instance to be converted. Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing)." start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Input Channel x (Vinp x) is not pre selected for conversion, the ADC conversion result with this channel shows wrong result." start="0x0" />
+        <Enum name="B_0x1" description="Input Channel x (Vinp x) is pre selected for conversion" start="0x1" />
+      </BitField>
+      <BitField name="PCSEL14" description=":Channel x (VINP[i]) pre selection (x = 0 to 19) These bits are written by software to pre select the input channel at IO instance to be converted. Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing)." start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Input Channel x (Vinp x) is not pre selected for conversion, the ADC conversion result with this channel shows wrong result." start="0x0" />
+        <Enum name="B_0x1" description="Input Channel x (Vinp x) is pre selected for conversion" start="0x1" />
+      </BitField>
+      <BitField name="PCSEL15" description=":Channel x (VINP[i]) pre selection (x = 0 to 19) These bits are written by software to pre select the input channel at IO instance to be converted. Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing)." start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Input Channel x (Vinp x) is not pre selected for conversion, the ADC conversion result with this channel shows wrong result." start="0x0" />
+        <Enum name="B_0x1" description="Input Channel x (Vinp x) is pre selected for conversion" start="0x1" />
+      </BitField>
+      <BitField name="PCSEL16" description=":Channel x (VINP[i]) pre selection (x = 0 to 19) These bits are written by software to pre select the input channel at IO instance to be converted. Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing)." start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Input Channel x (Vinp x) is not pre selected for conversion, the ADC conversion result with this channel shows wrong result." start="0x0" />
+        <Enum name="B_0x1" description="Input Channel x (Vinp x) is pre selected for conversion" start="0x1" />
+      </BitField>
+      <BitField name="PCSEL17" description=":Channel x (VINP[i]) pre selection (x = 0 to 19) These bits are written by software to pre select the input channel at IO instance to be converted. Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing)." start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Input Channel x (Vinp x) is not pre selected for conversion, the ADC conversion result with this channel shows wrong result." start="0x0" />
+        <Enum name="B_0x1" description="Input Channel x (Vinp x) is pre selected for conversion" start="0x1" />
+      </BitField>
+      <BitField name="PCSEL18" description=":Channel x (VINP[i]) pre selection (x = 0 to 19) These bits are written by software to pre select the input channel at IO instance to be converted. Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing)." start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Input Channel x (Vinp x) is not pre selected for conversion, the ADC conversion result with this channel shows wrong result." start="0x0" />
+        <Enum name="B_0x1" description="Input Channel x (Vinp x) is pre selected for conversion" start="0x1" />
+      </BitField>
+      <BitField name="PCSEL19" description=":Channel x (VINP[i]) pre selection (x = 0 to 19) These bits are written by software to pre select the input channel at IO instance to be converted. Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing)." start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Input Channel x (Vinp x) is not pre selected for conversion, the ADC conversion result with this channel shows wrong result." start="0x0" />
+        <Enum name="B_0x1" description="Input Channel x (Vinp x) is pre selected for conversion" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="ADC_LTR1" description="ADC watchdog threshold register 1 " start="+0x20" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LTR1" description="Analog watchdog 1 lower threshold These bits are written by software to define the lower threshold for the analog watchdog 1. Refer to AWD2CH, AWD3CH, AWD_HTRy, AWD_LTRy, AWDy) Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing)." start="0" size="26" access="Read/Write" />
+    </Register>
+    <Register name="ADC_HTR1" description="ADC watchdog threshold register 1 " start="+0x24" size="4" reset_value="0x03FFFFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="HTR1" description="Analog watchdog 1 higher threshold These bits are written by software to define the higher threshold for the analog watchdog 1. Refer to AWD2CH, AWD3CH, AWD_HTRy, AWD_LTRy, AWDy) Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing)." start="0" size="26" access="Read/Write" />
+    </Register>
+    <Register name="ADC_SQR1" description="ADC regular sequence register 1 " start="+0x30" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="L" description="Regular channel sequence length These bits are written by software to define the total number of conversions in the regular channel conversion sequence. ... Note: The software is allowed to write these bits only when ADSTART=0 (which ensures that no regular conversion is ongoing)." start="0" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="1 conversion" start="0x0" />
+        <Enum name="B_0x1" description="2 conversions" start="0x1" />
+        <Enum name="B_0xF" description="16 conversions" start="0xF" />
+      </BitField>
+      <BitField name="SQ1" description="1st conversion in regular sequence These bits are written by software with the channel number (0..19) assigned as the 1st in the regular conversion sequence. Note: The software is allowed to write these bits only when ADSTART=0 (which ensures that no regular conversion is ongoing)." start="6" size="5" access="Read/Write" />
+      <BitField name="SQ2" description="2nd conversion in regular sequence These bits are written by software with the channel number (0..19) assigned as the 2nd in the regular conversion sequence. Note: The software is allowed to write these bits only when ADSTART=0 (which ensures that no regular conversion is ongoing)." start="12" size="5" access="Read/Write" />
+      <BitField name="SQ3" description="3rd conversion in regular sequence These bits are written by software with the channel number (0..19) assigned as the 3rd in the regular conversion sequence. Note: The software is allowed to write these bits only when ADSTART=0 (which ensures that no regular conversion is ongoing)." start="18" size="5" access="Read/Write" />
+      <BitField name="SQ4" description="4th conversion in regular sequence These bits are written by software with the channel number (0..19) assigned as the 4th in the regular conversion sequence." start="24" size="5" access="Read/Write" />
+    </Register>
+    <Register name="ADC_SQR2" description="ADC regular sequence register 2 " start="+0x34" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SQ5" description="5th conversion in regular sequence These bits are written by software with the channel number (0..19) assigned as the 5th in the regular conversion sequence. Note: The software is allowed to write these bits only when ADSTART=0 (which ensures that no regular conversion is ongoing)." start="0" size="5" access="Read/Write" />
+      <BitField name="SQ6" description="6th conversion in regular sequence These bits are written by software with the channel number (0..19) assigned as the 6th in the regular conversion sequence. Note: The software is allowed to write these bits only when ADSTART=0 (which ensures that no regular conversion is ongoing)." start="6" size="5" access="Read/Write" />
+      <BitField name="SQ7" description="7th conversion in regular sequence These bits are written by software with the channel number (0..19) assigned as the 7th in the regular conversion sequence. Note: The software is allowed to write these bits only when ADSTART=0 (which ensures that no regular conversion is ongoing)." start="12" size="5" access="Read/Write" />
+      <BitField name="SQ8" description="8th conversion in regular sequence These bits are written by software with the channel number (0..19) assigned as the 8th in the regular conversion sequence Note: The software is allowed to write these bits only when ADSTART=0 (which ensures that no regular conversion is ongoing)." start="18" size="5" access="Read/Write" />
+      <BitField name="SQ9" description="9th conversion in regular sequence These bits are written by software with the channel number (0..19) assigned as the 9th in the regular conversion sequence. Note: The software is allowed to write these bits only when ADSTART=0 (which ensures that no regular conversion is ongoing)." start="24" size="5" access="Read/Write" />
+    </Register>
+    <Register name="ADC_SQR3" description="ADC regular sequence register 3 " start="+0x38" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SQ10" description="10th conversion in regular sequence These bits are written by software with the channel number (0..19) assigned as the 10th in the regular conversion sequence. Note: The software is allowed to write these bits only when ADSTART=0 (which ensures that no regular conversion is ongoing)." start="0" size="5" access="Read/Write" />
+      <BitField name="SQ11" description="11th conversion in regular sequence These bits are written by software with the channel number (0..19) assigned as the 11th in the regular conversion sequence. Note: The software is allowed to write these bits only when ADSTART=0 (which ensures that no regular conversion is ongoing)." start="6" size="5" access="Read/Write" />
+      <BitField name="SQ12" description="12th conversion in regular sequence These bits are written by software with the channel number (0..19) assigned as the 12th in the regular conversion sequence. Note: The software is allowed to write these bits only when ADSTART=0 (which ensures that no regular conversion is ongoing)." start="12" size="5" access="Read/Write" />
+      <BitField name="SQ13" description="13th conversion in regular sequence These bits are written by software with the channel number (0..19) assigned as the 13th in the regular conversion sequence. Note: The software is allowed to write these bits only when ADSTART=0 (which ensures that no regular conversion is ongoing)." start="18" size="5" access="Read/Write" />
+      <BitField name="SQ14" description="14th conversion in regular sequence These bits are written by software with the channel number (0..19) assigned as the 14th in the regular conversion sequence. Note: The software is allowed to write these bits only when ADSTART=0 (which ensures that no regular conversion is ongoing)." start="24" size="5" access="Read/Write" />
+    </Register>
+    <Register name="ADC_SQR4" description="ADC regular sequence register 4 " start="+0x3c" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SQ15" description="15th conversion in regular sequence These bits are written by software with the channel number (0..19) assigned as the 15th in the regular conversion sequence. Note: The software is allowed to write these bits only when ADSTART=0 (which ensures that no regular conversion is ongoing)." start="0" size="5" access="Read/Write" />
+      <BitField name="SQ16" description="16th conversion in regular sequence These bits are written by software with the channel number (0..19) assigned as the 16th in the regular conversion sequence. Note: The software is allowed to write these bits only when ADSTART=0 (which ensures that no regular conversion is ongoing)." start="6" size="5" access="Read/Write" />
+    </Register>
+    <Register name="ADC_DR" description="ADC regular Data Register " start="+0x40" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RDATA" description="Regular Data converted These bits are read-only. They contain the conversion result from the last converted regular channel. The data are left- or right-aligned as described in ." start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="ADC_JSQR" description="ADC injected sequence register " start="+0x4c" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="JL" description="Injected channel sequence length These bits are written by software to define the total number of conversions in the injected channel conversion sequence. Note: The software is allowed to write these bits only when JADSTART is cleared to 0 (no injected conversion is ongoing)." start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="1 conversion" start="0x0" />
+        <Enum name="B_0x1" description="2 conversions" start="0x1" />
+        <Enum name="B_0x2" description="3 conversions" start="0x2" />
+        <Enum name="B_0x3" description="4 conversions" start="0x3" />
+      </BitField>
+      <BitField name="JEXTSEL" description="External trigger selection for injected group These bits select the external event used to trigger the start of conversion of an injected group: ... Note: The software is allowed to write these bits only when JADSTART is cleared to 0 (no injected conversion is ongoing)." start="2" size="5" access="Read/Write">
+        <Enum name="B_0x0" description="Event 0" start="0x0" />
+        <Enum name="B_0x1" description="Event 1" start="0x1" />
+        <Enum name="B_0x2" description="Event 2" start="0x2" />
+        <Enum name="B_0x3" description="Event 3" start="0x3" />
+        <Enum name="B_0x4" description="Event 4" start="0x4" />
+        <Enum name="B_0x5" description="Event 5" start="0x5" />
+        <Enum name="B_0x6" description="Event 6" start="0x6" />
+        <Enum name="B_0x7" description="Event 7" start="0x7" />
+        <Enum name="B_0x1F" description="Event 31:" start="0x1F" />
+      </BitField>
+      <BitField name="JEXTEN" description="External trigger enable and polarity selection for injected channels These bits are set and cleared by software to select the external trigger polarity and enable the trigger of an injected group. If JQDIS=1 (queue disabled), Hardware trigger detection disabled (conversions can be launched by software Note: The software is allowed to write these bits only when JADSTART is cleared to 0 (no injected conversion is ongoing). If JQM=1 and if the Queue of Context becomes empty, the software and hardware triggers of the injected sequence are both internally disabled (refer to Queue of context for injected conversions)" start="7" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="If JQDIS=0 (queue enabled), Hardware and software trigger detection disabled and" start="0x0" />
+        <Enum name="B_0x1" description="Hardware trigger detection on the rising edge" start="0x1" />
+        <Enum name="B_0x2" description="Hardware trigger detection on the falling edge" start="0x2" />
+        <Enum name="B_0x3" description="Hardware trigger detection on both the rising and falling edges" start="0x3" />
+      </BitField>
+      <BitField name="JSQ1" description="1st conversion in the injected sequence These bits are written by software with the channel number (0..19) assigned as the 1st in the injected conversion sequence. Note: The software is allowed to write these bits only when JADSTART is cleared to 0 (no injected conversion is ongoing) unless the context queue is enabled (JQDIS=0 in ADC_CFGR register)." start="9" size="5" access="Read/Write" />
+      <BitField name="JSQ2" description="2nd conversion in the injected sequence These bits are written by software with the channel number (0..19) assigned as the 2nd in the injected conversion sequence. Note: The software is allowed to write these bits only when JADSTART is cleared to 0 (no injected conversion is ongoing) unless the context queue is enabled (JQDIS=0 in ADC_CFGR register)." start="15" size="5" access="Read/Write" />
+      <BitField name="JSQ3" description="3rd conversion in the injected sequence These bits are written by software with the channel number (0..19) assigned as the 3rd in the injected conversion sequence. Note: The software is allowed to write these bits only when JADSTART is cleared to 0 (no injected conversion is ongoing) unless the context queue is enabled (JQDIS=0 in ADC_CFGR register)." start="21" size="5" access="Read/Write" />
+      <BitField name="JSQ4" description="4th conversion in the injected sequence These bits are written by software with the channel number (0..19) assigned as the 4th in the injected conversion sequence. Note: The software is allowed to write these bits only when JADSTART is cleared to 0 (no injected conversion is ongoing) unless the context queue is enabled (JQDIS=0 in ADC_CFGR register)." start="27" size="5" access="Read/Write" />
+    </Register>
+    <Register name="ADC_OFR1" description="ADC injected channel 1 offset register" start="+0x60" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OFFSET1" description="Data offset y for the channel programmed into bits OFFSETy_CH[4:0] These bits are written by software to define the offset y to be subtracted from the raw converted data when converting a channel (can be regular or injected). The channel to which applies the data offset y must be programmed in the bits OFFSETy_CH[4:0]. The conversion result can be read from in the ADC_DR (regular conversion) or from in the ADC_JDRyi registers (injected conversion). When OFFSETy[25:0] bitfield is reset, the offset compensation is disabled. Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing). If several offset (OFFSETy) point to the same channel, only the offset with the lowest x value is considered for the subtraction. Ex: if OFFSET1_CH[4:0]=4 and OFFSET2_CH[4:0]=4, this is OFFSET1[25:0] which is subtracted when converting channel 4." start="0" size="26" access="Read/Write" />
+      <BitField name="OFFSET1_CH" description="Channel selection for the Data offset y These bits are written by software to define the channel to which the offset programmed into bits OFFSETy[25:0] will apply. Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing)." start="26" size="5" access="Read/Write" />
+      <BitField name="SSATE" description="Signed saturation Enable This bit is written by software to enable or disable the Signed saturation feature. This bit can be enabled only for 8-bit and 16-bit data format (see alignment and offset (ADC_DR, ADC_JDRy, OFFSETy, OFFSETy_CH, OVSS, LSHIFT, RSHIFT, SSATE) for details). Note: The software is allowed to write this bit only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing)." start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Offset is subtracted maintaining data integrity and extending result size (9-bit and 17-bit signed format)." start="0x0" />
+        <Enum name="B_0x1" description="Offset is subtracted and result is saturated to maintain result size." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="ADC_OFR2" description="ADC injected channel 2 offset register" start="+0x64" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OFFSET2" description="Data offset y for the channel programmed into bits OFFSETy_CH[4:0] These bits are written by software to define the offset y to be subtracted from the raw converted data when converting a channel (can be regular or injected). The channel to which applies the data offset y must be programmed in the bits OFFSETy_CH[4:0]. The conversion result can be read from in the ADC_DR (regular conversion) or from in the ADC_JDRyi registers (injected conversion). When OFFSETy[25:0] bitfield is reset, the offset compensation is disabled. Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing). If several offset (OFFSETy) point to the same channel, only the offset with the lowest x value is considered for the subtraction. Ex: if OFFSET1_CH[4:0]=4 and OFFSET2_CH[4:0]=4, this is OFFSET1[25:0] which is subtracted when converting channel 4." start="0" size="26" access="Read/Write" />
+      <BitField name="OFFSET2_CH" description="Channel selection for the Data offset y These bits are written by software to define the channel to which the offset programmed into bits OFFSETy[25:0] will apply. Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing)." start="26" size="5" access="Read/Write" />
+      <BitField name="SSATE" description="Signed saturation Enable This bit is written by software to enable or disable the Signed saturation feature. This bit can be enabled only for 8-bit and 16-bit data format (see alignment and offset (ADC_DR, ADC_JDRy, OFFSETy, OFFSETy_CH, OVSS, LSHIFT, RSHIFT, SSATE) for details). Note: The software is allowed to write this bit only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing)." start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Offset is subtracted maintaining data integrity and extending result size (9-bit and 17-bit signed format)." start="0x0" />
+        <Enum name="B_0x1" description="Offset is subtracted and result is saturated to maintain result size." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="ADC_OFR3" description="ADC injected channel 3 offset register" start="+0x68" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OFFSET3" description="Data offset y for the channel programmed into bits OFFSETy_CH[4:0] These bits are written by software to define the offset y to be subtracted from the raw converted data when converting a channel (can be regular or injected). The channel to which applies the data offset y must be programmed in the bits OFFSETy_CH[4:0]. The conversion result can be read from in the ADC_DR (regular conversion) or from in the ADC_JDRyi registers (injected conversion). When OFFSETy[25:0] bitfield is reset, the offset compensation is disabled. Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing). If several offset (OFFSETy) point to the same channel, only the offset with the lowest x value is considered for the subtraction. Ex: if OFFSET1_CH[4:0]=4 and OFFSET2_CH[4:0]=4, this is OFFSET1[25:0] which is subtracted when converting channel 4." start="0" size="26" access="Read/Write" />
+      <BitField name="OFFSET3_CH" description="Channel selection for the Data offset y These bits are written by software to define the channel to which the offset programmed into bits OFFSETy[25:0] will apply. Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing)." start="26" size="5" access="Read/Write" />
+      <BitField name="SSATE" description="Signed saturation Enable This bit is written by software to enable or disable the Signed saturation feature. This bit can be enabled only for 8-bit and 16-bit data format (see alignment and offset (ADC_DR, ADC_JDRy, OFFSETy, OFFSETy_CH, OVSS, LSHIFT, RSHIFT, SSATE) for details). Note: The software is allowed to write this bit only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing)." start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Offset is subtracted maintaining data integrity and extending result size (9-bit and 17-bit signed format)." start="0x0" />
+        <Enum name="B_0x1" description="Offset is subtracted and result is saturated to maintain result size." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="ADC_OFR4" description="ADC injected channel 4 offset register" start="+0x6c" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OFFSET4" description="Data offset y for the channel programmed into bits OFFSETy_CH[4:0] These bits are written by software to define the offset y to be subtracted from the raw converted data when converting a channel (can be regular or injected). The channel to which applies the data offset y must be programmed in the bits OFFSETy_CH[4:0]. The conversion result can be read from in the ADC_DR (regular conversion) or from in the ADC_JDRyi registers (injected conversion). When OFFSETy[25:0] bitfield is reset, the offset compensation is disabled. Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing). If several offset (OFFSETy) point to the same channel, only the offset with the lowest x value is considered for the subtraction. Ex: if OFFSET1_CH[4:0]=4 and OFFSET2_CH[4:0]=4, this is OFFSET1[25:0] which is subtracted when converting channel 4." start="0" size="26" access="Read/Write" />
+      <BitField name="OFFSET4_CH" description="Channel selection for the Data offset y These bits are written by software to define the channel to which the offset programmed into bits OFFSETy[25:0] will apply. Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing)." start="26" size="5" access="Read/Write" />
+      <BitField name="SSATE" description="Signed saturation Enable This bit is written by software to enable or disable the Signed saturation feature. This bit can be enabled only for 8-bit and 16-bit data format (see alignment and offset (ADC_DR, ADC_JDRy, OFFSETy, OFFSETy_CH, OVSS, LSHIFT, RSHIFT, SSATE) for details). Note: The software is allowed to write this bit only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing)." start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Offset is subtracted maintaining data integrity and extending result size (9-bit and 17-bit signed format)." start="0x0" />
+        <Enum name="B_0x1" description="Offset is subtracted and result is saturated to maintain result size." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="ADC_JDR1" description="ADC injected channel 1 data register" start="+0x80" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="JDATA" description="Injected data These bits are read-only. They contain the conversion result from injected channel y. The data are left -or right-aligned as described in ." start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="ADC_JDR2" description="ADC injected channel 2 data register" start="+0x84" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="JDATA" description="Injected data These bits are read-only. They contain the conversion result from injected channel y. The data are left -or right-aligned as described in ." start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="ADC_JDR3" description="ADC injected channel 3 data register" start="+0x88" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="JDATA" description="Injected data These bits are read-only. They contain the conversion result from injected channel y. The data are left -or right-aligned as described in ." start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="ADC_JDR4" description="ADC injected channel 4 data register" start="+0x8c" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="JDATA" description="Injected data These bits are read-only. They contain the conversion result from injected channel y. The data are left -or right-aligned as described in ." start="0" size="32" access="ReadOnly" />
+    </Register>
+    <Register name="ADC_AWD2CR" description="ADC analog watchdog 2 configuration register&#09;" start="+0xa0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AWD2CH" description="Analog watchdog 2 channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by the analog watchdog 2. AWD2CH[i] = 0: ADC analog input channel-i is not monitored by AWD2 AWD2CH[i] = 1: ADC analog input channel-i is monitored by AWD2 When AWD2CH[19:0] = 000..0, the analog Watchdog 2 is disabled Note: The channels selected by AWD2CH must be also selected into the SQRi or JSQRi registers. The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing)." start="0" size="20" access="Read/Write" />
+    </Register>
+    <Register name="ADC_AWD3CR" description="ADC analog watchdog 3 configuration register&#09;" start="+0xa4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AWD3CH" description="Analog watchdog 3 channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by the analog watchdog 3. AWD3CH[i] = 0: ADC analog input channel-i is not monitored by AWD3 AWD3CH[i] = 1: ADC analog input channel-i is monitored by AWD3 When AWD3CH[19:0] = 000..0, the analog Watchdog 3 is disabled Note: The channels selected by AWD3CH must be also selected into the SQRi or JSQRi registers. The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing)." start="0" size="20" access="Read/Write" />
+    </Register>
+    <Register name="ADC_LTR2" description="ADC watchdog lower threshold register 2 " start="+0xb0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LTR2" description="Analog watchdog 2 lower threshold These bits are written by software to define the lower threshold for the analog watchdog 2. Refer to AWD2CH, AWD3CH, AWD_HTRy, AWD_LTRy, AWDy). Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing)." start="0" size="26" access="Read/Write" />
+    </Register>
+    <Register name="ADC_HTR2" description="ADC watchdog higher threshold register 2 " start="+0xb4" size="4" reset_value="0x03FFFFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="HTR2" description="Analog watchdog 2 higher threshold These bits are written by software to define the higher threshold for the analog watchdog 2. Refer to AWD2CH, AWD3CH, AWD_HTRy, AWD_LTRy, AWDy). Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing)." start="0" size="26" access="Read/Write" />
+    </Register>
+    <Register name="ADC_LTR3" description="ADC watchdog lower threshold register 3 " start="+0xb8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LTR3" description="Analog watchdog 3 lower threshold These bits are written by software to define the lower threshold for the analog watchdog 3. Refer to AWD2CH, AWD3CH, AWD_HTRy, AWD_LTRy, AWDy) Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing)." start="0" size="26" access="Read/Write" />
+    </Register>
+    <Register name="ADC_HTR3" description="ADC watchdog higher threshold register 3 " start="+0xbc" size="4" reset_value="0x03FFFFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="HTR3" description="Analog watchdog 3 higher threshold These bits are written by software to define the higher threshold for the analog watchdog 3. Refer to AWD2CH, AWD3CH, AWD_HTRy, AWD_LTRy, AWDy) Note: The software is allowed to write these bits only when ADSTART=0 and JADSTART=0 (which ensures that no conversion is ongoing)." start="0" size="26" access="Read/Write" />
+    </Register>
+    <Register name="ADC_DIFSEL" description="ADC differential mode selection register " start="+0xc0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DIFSEL" description="Differential mode for channels 19 to 0 These bits are set and cleared by software. They allow to select if a channel is configured as single ended or differential mode. DIFSEL[i] = 0: ADC analog input channel-i is configured in single ended mode DIFSEL[i] = 1: ADC analog input channel-i is configured in differential mode Note: The software is allowed to write these bits only when the ADC is disabled (ADCAL=0, JADSTART=0, JADSTP=0, ADSTART=0, ADSTP=0, ADDIS=0 and ADEN=0)." start="0" size="20" access="Read/Write" />
+    </Register>
+    <Register name="ADC_CALFACT" description="ADC calibration factors register " start="+0xc4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CALFACT_S" description="Calibration Factors In Single-Ended mode These bits are written by hardware or by software. Once a single-ended inputs calibration is complete, they are updated by hardware with the calibration factors. Software can write these bits with a new calibration factor. If the new calibration factor is different from the current one stored into the analog ADC, it will then be applied once a new single-ended conversion is launched. Note: The software is allowed to write these bits only when ADEN=1, ADSTART=0 and JADSTART=0 (ADC is enabled and no calibration is ongoing and no conversion is ongoing)." start="0" size="11" access="Read/Write" />
+      <BitField name="CALFACT_D" description="Calibration Factors in differential mode These bits are written by hardware or by software. Once a differential inputs calibration is complete, they are updated by hardware with the calibration factors. Software can write these bits with a new calibration factor. If the new calibration factor is different from the current one stored into the analog ADC, it will then be applied once a new differential conversion is launched. Note: The software is allowed to write these bits only when ADEN=1, ADSTART=0 and JADSTART=0 (ADC is enabled and no calibration is ongoing and no conversion is ongoing)." start="16" size="11" access="Read/Write" />
+    </Register>
+    <Register name="ADC_CALFACT2" description="ADC calibration factor register 2 " start="+0xc8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LINCALFACT" description="Linearity Calibration Factor These bits are written by hardware or by software. They hold 30-bit out of the 160-bit linearity calibration factor. Once a single-ended inputs calibration is complete, they are updated by hardware with the calibration factors. Software can write these bits with a new calibration factor. If the new calibration factor is different from the current one stored into the analog ADC, it will then be applied once a new single-ended calibration is launched. Note: The software is allowed to write these bits only when ADEN=1, ADSTART=0 and JADSTART=0 (ADC is enabled and no calibration is ongoing and no conversion is ongoing)." start="0" size="30" access="Read/Write" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="ADC12_Common" description="Analog-to-Digital Converter" start="0x40022300">
+    <Register name="CSR" description="ADC Common status register" start="+0x0" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ADRDY_MST" description="Master ADC ready" start="0" size="1" />
+      <BitField name="EOSMP_MST" description="End of Sampling phase flag of the master ADC" start="1" size="1" />
+      <BitField name="EOC_MST" description="End of regular conversion of the master ADC" start="2" size="1" />
+      <BitField name="EOS_MST" description="End of regular sequence flag of the master ADC" start="3" size="1" />
+      <BitField name="OVR_MST" description="Overrun flag of the master ADC" start="4" size="1" />
+      <BitField name="JEOC_MST" description="End of injected conversion flag of the master ADC" start="5" size="1" />
+      <BitField name="JEOS_MST" description="End of injected sequence flag of the master ADC" start="6" size="1" />
+      <BitField name="AWD1_MST" description="Analog watchdog 1 flag of the master ADC" start="7" size="1" />
+      <BitField name="AWD2_MST" description="Analog watchdog 2 flag of the master ADC" start="8" size="1" />
+      <BitField name="AWD3_MST" description="Analog watchdog 3 flag of the master ADC" start="9" size="1" />
+      <BitField name="JQOVF_MST" description="Injected Context Queue Overflow flag of the master ADC" start="10" size="1" />
+      <BitField name="ADRDY_SLV" description="Slave ADC ready" start="16" size="1" />
+      <BitField name="EOSMP_SLV" description="End of Sampling phase flag of the slave ADC" start="17" size="1" />
+      <BitField name="EOC_SLV" description="End of regular conversion of the slave ADC" start="18" size="1" />
+      <BitField name="EOS_SLV" description="End of regular sequence flag of the slave ADC" start="19" size="1" />
+      <BitField name="OVR_SLV" description="Overrun flag of the slave ADC" start="20" size="1" />
+      <BitField name="JEOC_SLV" description="End of injected conversion flag of the slave ADC" start="21" size="1" />
+      <BitField name="JEOS_SLV" description="End of injected sequence flag of the slave ADC" start="22" size="1" />
+      <BitField name="AWD1_SLV" description="Analog watchdog 1 flag of the slave ADC" start="23" size="1" />
+      <BitField name="AWD2_SLV" description="Analog watchdog 2 flag of the slave ADC" start="24" size="1" />
+      <BitField name="AWD3_SLV" description="Analog watchdog 3 flag of the slave ADC" start="25" size="1" />
+      <BitField name="JQOVF_SLV" description="Injected Context Queue Overflow flag of the slave ADC" start="26" size="1" />
+    </Register>
+    <Register name="CCR" description="ADC common control register" start="+0x8" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DUAL" description="Dual ADC mode selection" start="0" size="5" />
+      <BitField name="DELAY" description="Delay between 2 sampling phases" start="8" size="4" />
+      <BitField name="DAMDF" description="Dual ADC Mode Data Format" start="14" size="2" />
+      <BitField name="CKMODE" description="ADC clock mode" start="16" size="2" />
+      <BitField name="PRESC" description="ADC prescaler" start="18" size="4" />
+      <BitField name="VREFEN" description="VREFINT enable" start="22" size="1" />
+      <BitField name="VSENSEEN" description="Temperature sensor enable" start="23" size="1" />
+      <BitField name="VBATEN" description="VBAT enable" start="24" size="1" />
+    </Register>
+    <Register name="CDR" description="ADC common regular data register for dual and triple modes" start="+0xC" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RDATA_SLV" description="Regular data of the slave ADC" start="16" size="16" />
+      <BitField name="RDATA_MST" description="Regular data of the master ADC" start="0" size="16" />
+    </Register>
+    <Register name="CDR2" description="ADC x common regular data register for 32-bit dual mode" start="+0x10" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RDATA_ALT" description="Regular data of the master/slave alternated ADCs" start="0" size="32" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="ADC3" description="Analog-to-Digital Converter" start="0x58026000">
+    <Register name="ADC_ISR" description="ADC interrupt and status register " start="+0x0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ADRDY" description="ADC ready This bit is set by hardware after the ADC has been enabled (ADEN = 1) and when the ADC reaches a state where it is ready to accept conversion requests. It is cleared by software writing 1 to it." start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="ADC not yet ready to start conversion (or the flag event was already acknowledged and cleared by software)" start="0x0" />
+        <Enum name="B_0x1" description="ADC is ready to start conversion" start="0x1" />
+      </BitField>
+      <BitField name="EOSMP" description="End of sampling flag This bit is set by hardware during the conversion of any channel (only for regular channels), at the end of the sampling phase." start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="not at the end of the sampling phase (or the flag event was already acknowledged and cleared by software)" start="0x0" />
+        <Enum name="B_0x1" description="End of sampling phase reached" start="0x1" />
+      </BitField>
+      <BitField name="EOC" description="End of conversion flag This bit is set by hardware at the end of each regular conversion of a channel when a new data is available in the ADC_DR register. It is cleared by software writing 1 to it or by reading the ADC_DR register" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Regular channel conversion not complete (or the flag event was already acknowledged and cleared by software)" start="0x0" />
+        <Enum name="B_0x1" description="Regular channel conversion complete" start="0x1" />
+      </BitField>
+      <BitField name="EOS" description="End of regular sequence flag This bit is set by hardware at the end of the conversions of a regular sequence of channels. It is cleared by software writing 1 to it." start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Regular Conversions sequence not complete (or the flag event was already acknowledged and cleared by software)" start="0x0" />
+        <Enum name="B_0x1" description="Regular Conversions sequence complete" start="0x1" />
+      </BitField>
+      <BitField name="OVR" description="ADC overrun This bit is set by hardware when an overrun occurs on a regular channel, meaning that a new conversion has completed while the EOC flag was already set. It is cleared by software writing 1 to it." start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No overrun occurred (or the flag event was already acknowledged and cleared by software)" start="0x0" />
+        <Enum name="B_0x1" description="Overrun has occurred" start="0x1" />
+      </BitField>
+      <BitField name="JEOC" description="Injected channel end of conversion flag This bit is set by hardware at the end of each injected conversion of a channel when a new data is available in the corresponding ADC_JDRy register. It is cleared by software writing 1 to it or by reading the corresponding ADC_JDRy register" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Injected channel conversion not complete (or the flag event was already acknowledged and cleared by software)" start="0x0" />
+        <Enum name="B_0x1" description="Injected channel conversion complete" start="0x1" />
+      </BitField>
+      <BitField name="JEOS" description="Injected channel end of sequence flag This bit is set by hardware at the end of the conversions of all injected channels in the group. It is cleared by software writing 1 to it." start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Injected conversion sequence not complete (or the flag event was already acknowledged and cleared by software)" start="0x0" />
+        <Enum name="B_0x1" description="Injected conversions complete" start="0x1" />
+      </BitField>
+      <BitField name="AWD1" description="Analog watchdog 1 flag This bit is set by hardware when the converted voltage crosses the values programmed in the fields LT1[11:0] and HT1[11:0] of ADC_TR1 register. It is cleared by software. writing 1 to it." start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No analog watchdog 1 event occurred (or the flag event was already acknowledged and cleared by software)" start="0x0" />
+        <Enum name="B_0x1" description="Analog watchdog 1 event occurred" start="0x1" />
+      </BitField>
+      <BitField name="AWD2" description="Analog watchdog 2 flag This bit is set by hardware when the converted voltage crosses the values programmed in the fields LT2[7:0] and HT2[7:0] of ADC_TR2 register. It is cleared by software writing 1 to it." start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No analog watchdog 2 event occurred (or the flag event was already acknowledged and cleared by software)" start="0x0" />
+        <Enum name="B_0x1" description="Analog watchdog 2 event occurred" start="0x1" />
+      </BitField>
+      <BitField name="AWD3" description="Analog watchdog 3 flag This bit is set by hardware when the converted voltage crosses the values programmed in the fields LT3[7:0] and HT3[7:0] of ADC_TR3 register. It is cleared by software writing 1 to it." start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No analog watchdog 3 event occurred (or the flag event was already acknowledged and cleared by software)" start="0x0" />
+        <Enum name="B_0x1" description="Analog watchdog 3 event occurred" start="0x1" />
+      </BitField>
+      <BitField name="JQOVF" description="Injected context queue overflow This bit is set by hardware when an Overflow of the Injected Queue of Context occurs. It is cleared by software writing 1 to it. Refer to for more information." start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No injected context queue overflow occurred (or the flag event was already acknowledged and cleared by software)" start="0x0" />
+        <Enum name="B_0x1" description="Injected context queue overflow has occurred" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="ADC_IER" description="ADC interrupt enable register " start="+0x4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ADRDYIE" description="ADC ready interrupt enable This bit is set and cleared by software to enable/disable the ADC Ready interrupt. Note: The software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing)." start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="ADRDY interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="ADRDY interrupt enabled. An interrupt is generated when the ADRDY bit is set." start="0x1" />
+      </BitField>
+      <BitField name="EOSMPIE" description="End of sampling flag interrupt enable for regular conversions This bit is set and cleared by software to enable/disable the end of the sampling phase interrupt for regular conversions. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no regular conversion is ongoing)." start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="EOSMP interrupt disabled." start="0x0" />
+        <Enum name="B_0x1" description="EOSMP interrupt enabled. An interrupt is generated when the EOSMP bit is set." start="0x1" />
+      </BitField>
+      <BitField name="EOCIE" description="End of regular conversion interrupt enable This bit is set and cleared by software to enable/disable the end of a regular conversion interrupt. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no regular conversion is ongoing)." start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="EOC interrupt disabled." start="0x0" />
+        <Enum name="B_0x1" description="EOC interrupt enabled. An interrupt is generated when the EOC bit is set." start="0x1" />
+      </BitField>
+      <BitField name="EOSIE" description="End of regular sequence of conversions interrupt enable This bit is set and cleared by software to enable/disable the end of regular sequence of conversions interrupt. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no regular conversion is ongoing)." start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="EOS interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="EOS interrupt enabled. An interrupt is generated when the EOS bit is set." start="0x1" />
+      </BitField>
+      <BitField name="OVRIE" description="Overrun interrupt enable This bit is set and cleared by software to enable/disable the Overrun interrupt of a regular conversion. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no regular conversion is ongoing)." start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Overrun interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Overrun interrupt enabled. An interrupt is generated when the OVR bit is set." start="0x1" />
+      </BitField>
+      <BitField name="JEOCIE" description="End of injected conversion interrupt enable This bit is set and cleared by software to enable/disable the end of an injected conversion interrupt. Note: The software is allowed to write this bit only when JADSTART = 0 (which ensures that no injected conversion is ongoing)." start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="JEOC interrupt disabled." start="0x0" />
+        <Enum name="B_0x1" description="JEOC interrupt enabled. An interrupt is generated when the JEOC bit is set." start="0x1" />
+      </BitField>
+      <BitField name="JEOSIE" description="End of injected sequence of conversions interrupt enable This bit is set and cleared by software to enable/disable the end of injected sequence of conversions interrupt. Note: The software is allowed to write this bit only when JADSTART = 0 (which ensures that no injected conversion is ongoing)." start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="JEOS interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="JEOS interrupt enabled. An interrupt is generated when the JEOS bit is set." start="0x1" />
+      </BitField>
+      <BitField name="AWD1IE" description="Analog watchdog 1 interrupt enable This bit is set and cleared by software to enable/disable the analog watchdog 1 interrupt. Note: The software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing)." start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Analog watchdog 1 interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Analog watchdog 1 interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="AWD2IE" description="Analog watchdog 2 interrupt enable This bit is set and cleared by software to enable/disable the analog watchdog 2 interrupt. Note: The software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing)." start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Analog watchdog 2 interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Analog watchdog 2 interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="AWD3IE" description="Analog watchdog 3 interrupt enable This bit is set and cleared by software to enable/disable the analog watchdog 2 interrupt. Note: The software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing)." start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Analog watchdog 3 interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Analog watchdog 3 interrupt enabled" start="0x1" />
+      </BitField>
+      <BitField name="JQOVFIE" description="Injected context queue overflow interrupt enable This bit is set and cleared by software to enable/disable the Injected Context Queue Overflow interrupt. Note: The software is allowed to write this bit only when JADSTART = 0 (which ensures that no injected conversion is ongoing)." start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Injected Context Queue Overflow interrupt disabled" start="0x0" />
+        <Enum name="B_0x1" description="Injected Context Queue Overflow interrupt enabled. An interrupt is generated when the JQOVF bit is set." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="ADC_CR" description="ADC control register " start="+0x8" size="4" reset_value="0x20000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ADEN" description="ADC enable control This bit is set by software to enable the ADC. The ADC is effectively ready to operate once the flag ADRDY has been set. It is cleared by hardware when the ADC is disabled, after the execution of the ADDIS command. Note: The software is allowed to set ADEN only when all bits of ADC_CR registers are 0 (ADCAL = 0, JADSTART = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0) except for bit ADVREGEN which must be 1 (and the software must have wait for the startup time of the voltage regulator)" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="ADC is disabled (OFF state)" start="0x0" />
+        <Enum name="B_0x1" description="Write 1 to enable the ADC." start="0x1" />
+      </BitField>
+      <BitField name="ADDIS" description="ADC disable command This bit is set by software to disable the ADC (ADDIS command) and put it into power-down state (OFF state). It is cleared by hardware once the ADC is effectively disabled (ADEN is also cleared by hardware at this time). Note: The software is allowed to set ADDIS only when ADEN = 1 and both ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing)" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="no ADDIS command ongoing" start="0x0" />
+        <Enum name="B_0x1" description="Write 1 to disable the ADC. Read 1 means that an ADDIS command is in progress. " start="0x1" />
+      </BitField>
+      <BitField name="ADSTART" description="ADC start of regular conversion This bit is set by software to start ADC conversion of regular channels. Depending on the configuration bits EXTEN, a conversion immediately starts (software trigger configuration) or once a regular hardware trigger event occurs (hardware trigger configuration). It is cleared by hardware: in Single conversion mode when software trigger is selected (EXTSEL = 0x0): at the assertion of the End of Regular Conversion Sequence (EOS) flag. in all cases: after the execution of the ADSTP command, at the same time that ADSTP is cleared by hardware. Note: The software is allowed to set ADSTART only when ADEN = 1 and ADDIS = 0 (ADC is enabled and there is no pending request to disable the ADC) In auto-injection mode (JAUTO = 1), regular and auto-injected conversions are started by setting bit ADSTART (JADSTART must be kept cleared)" start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No ADC regular conversion is ongoing." start="0x0" />
+        <Enum name="B_0x1" description="Write 1 to start regular conversions. Read 1 means that the ADC is operating and eventually converting a regular channel." start="0x1" />
+      </BitField>
+      <BitField name="JADSTART" description="ADC start of injected conversion This bit is set by software to start ADC conversion of injected channels. Depending on the configuration bits JEXTEN, a conversion immediately starts (software trigger configuration) or once an injected hardware trigger event occurs (hardware trigger configuration). It is cleared by hardware: in Single conversion mode when software trigger is selected (JEXTSEL = 0x0): at the assertion of the End of Injected Conversion Sequence (JEOS) flag. in all cases: after the execution of the JADSTP command, at the same time that JADSTP is cleared by hardware. Note: The software is allowed to set JADSTART only when ADEN = 1 and ADDIS = 0 (ADC is enabled and there is no pending request to disable the ADC). In auto-injection mode (JAUTO = 1), regular and auto-injected conversions are started by setting bit ADSTART (JADSTART must be kept cleared)" start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No ADC injected conversion is ongoing." start="0x0" />
+        <Enum name="B_0x1" description="Write 1 to start injected conversions. Read 1 means that the ADC is operating and eventually converting an injected channel." start="0x1" />
+      </BitField>
+      <BitField name="ADSTP" description="ADC stop of regular conversion command This bit is set by software to stop and discard an ongoing regular conversion (ADSTP Command). It is cleared by hardware when the conversion is effectively discarded and the ADC regular sequence and triggers can be re-configured. The ADC is then ready to accept a new start of regular conversions (ADSTART command). Note: The software is allowed to set ADSTP only when ADSTART = 1 and ADDIS = 0 (ADC is enabled and eventually converting a regular conversion and there is no pending request to disable the ADC). In auto-injection mode (JAUTO = 1), setting ADSTP bit aborts both regular and injected conversions (do not use JADSTP)." start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No ADC stop regular conversion command ongoing" start="0x0" />
+        <Enum name="B_0x1" description="Write 1 to stop regular conversions ongoing. Read 1 means that an ADSTP command is in progress." start="0x1" />
+      </BitField>
+      <BitField name="JADSTP" description="ADC stop of injected conversion command This bit is set by software to stop and discard an ongoing injected conversion (JADSTP Command). It is cleared by hardware when the conversion is effectively discarded and the ADC injected sequence and triggers can be re-configured. The ADC is then ready to accept a new start of injected conversions (JADSTART command). Note: The software is allowed to set JADSTP only when JADSTART = 1 and ADDIS = 0 (ADC is enabled and eventually converting an injected conversion and there is no pending request to disable the ADC) In Auto-injection mode (JAUTO = 1), setting ADSTP bit aborts both regular and injected conversions (do not use JADSTP)" start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No ADC stop injected conversion command ongoing" start="0x0" />
+        <Enum name="B_0x1" description="Write 1 to stop injected conversions ongoing. Read 1 means that an ADSTP command is in progress." start="0x1" />
+      </BitField>
+      <BitField name="ADVREGEN" description="ADC voltage regulator enable This bits is set by software to enable the ADC voltage regulator. Before performing any operation such as launching a calibration or enabling the ADC, the ADC voltage regulator must first be enabled and the software must wait for the regulator start-up time. For more details about the ADC voltage regulator enable and disable sequences, refer to (ADVREGEN). The software can program this bit field only when the ADC is disabled (ADCAL = 0, JADSTART = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0)." start="28" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="ADC Voltage regulator disabled" start="0x0" />
+        <Enum name="B_0x1" description="ADC Voltage regulator enabled." start="0x1" />
+      </BitField>
+      <BitField name="DEEPPWD" description="Deep-power-down enable This bit is set and cleared by software to put the ADC in Deep-power-down mode. Note: The software is allowed to write this bit only when the ADC is disabled (ADCAL = 0, JADSTART = 0, JADSTP = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0)." start="29" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="ADC not in Deep-power down" start="0x0" />
+        <Enum name="B_0x1" description="ADC in Deep-power-down (default reset state)" start="0x1" />
+      </BitField>
+      <BitField name="ADCALDIF" description="Differential mode for calibration This bit is set and cleared by software to configure the Single-ended or Differential inputs mode for the calibration. Note: The software is allowed to write this bit only when the ADC is disabled and is not calibrating (ADCAL = 0, JADSTART = 0, JADSTP = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0)." start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Writing ADCAL launches a calibration in Single-ended inputs mode." start="0x0" />
+        <Enum name="B_0x1" description="Writing ADCAL launches a calibration in Differential inputs mode." start="0x1" />
+      </BitField>
+      <BitField name="ADCAL" description="ADC calibration This bit is set by software to start the calibration of the ADC. Program first the bit ADCALDIF to determine if this calibration applies for Single-ended or Differential inputs mode. It is cleared by hardware after calibration is complete. Note: The software is allowed to launch a calibration by setting ADCAL only when ADEN = 0. The software is allowed to update the calibration factor by writing ADC_CALFACT only when ADEN = 1 and ADSTART = 0 and JADSTART = 0 (ADC enabled and no conversion is ongoing)" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Calibration complete" start="0x0" />
+        <Enum name="B_0x1" description="Write 1 to calibrate the ADC. Read at 1 means that a calibration in progress." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="ADC_CFGR" description="ADC configuration register " start="+0xc" size="4" reset_value="0x80000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAEN" description="Direct memory access enable This bit is set and cleared by software to enable the generation of DMA requests. This allows to use the DMA to manage automatically the converted data. For more details, refer to conversions using the DMA. Note: The software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing)." start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DMA disabled" start="0x0" />
+        <Enum name="B_0x1" description="DMA enabled" start="0x1" />
+      </BitField>
+      <BitField name="DMACFG" description="Direct memory access configuration This bit is set and cleared by software to select between two DMA modes of operation and is effective only when DMAEN = 1. For more details, refer to Note: The software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing)." start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DMA One Shot mode selected" start="0x0" />
+        <Enum name="B_0x1" description="DMA Circular mode selected" start="0x1" />
+      </BitField>
+      <BitField name="DFSDMCFG" description="DFSDM mode configuration This bit is set and cleared by software to enable the DFSDM mode. It is effective only when DMAEN = 0. Note: To make sure no conversion is ongoing, the software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0." start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DFSDM mode disabled" start="0x0" />
+        <Enum name="B_0x1" description="DFSDM mode enabled" start="0x1" />
+      </BitField>
+      <BitField name="RES" description="Data resolution These bits are written by software to select the resolution of the conversion. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing)." start="3" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="12-bit" start="0x0" />
+        <Enum name="B_0x1" description="10-bit" start="0x1" />
+        <Enum name="B_0x2" description="8-bit" start="0x2" />
+        <Enum name="B_0x3" description="6-bit" start="0x3" />
+      </BitField>
+      <BitField name="EXTSEL0" description="External trigger selection for regular group These bits select the external event used to trigger the start of conversion of a regular group: ... Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing)." start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="adc_ext_trg0" start="0x0" />
+        <Enum name="B_0x1" description="adc_ext_trg1" start="0x1" />
+        <Enum name="B_0x2" description="adc_ext_trg2" start="0x2" />
+        <Enum name="B_0x3" description="adc_ext_trg3" start="0x3" />
+        <Enum name="B_0x4" description="adc_ext_trg4" start="0x4" />
+        <Enum name="B_0x5" description="adc_ext_trg5" start="0x5" />
+        <Enum name="B_0x6" description="adc_ext_trg6" start="0x6" />
+        <Enum name="B_0x7" description="adc_ext_trg7" start="0x7" />
+        <Enum name="B_0x1F" description="adc_ext_trg31" start="0x1F" />
+      </BitField>
+      <BitField name="EXTSEL1" description="External trigger selection for regular group These bits select the external event used to trigger the start of conversion of a regular group: ... Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing)." start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="adc_ext_trg0" start="0x0" />
+        <Enum name="B_0x1" description="adc_ext_trg1" start="0x1" />
+        <Enum name="B_0x2" description="adc_ext_trg2" start="0x2" />
+        <Enum name="B_0x3" description="adc_ext_trg3" start="0x3" />
+        <Enum name="B_0x4" description="adc_ext_trg4" start="0x4" />
+        <Enum name="B_0x5" description="adc_ext_trg5" start="0x5" />
+        <Enum name="B_0x6" description="adc_ext_trg6" start="0x6" />
+        <Enum name="B_0x7" description="adc_ext_trg7" start="0x7" />
+        <Enum name="B_0x1F" description="adc_ext_trg31" start="0x1F" />
+      </BitField>
+      <BitField name="EXTSEL2" description="External trigger selection for regular group These bits select the external event used to trigger the start of conversion of a regular group: ... Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing)." start="7" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="adc_ext_trg0" start="0x0" />
+        <Enum name="B_0x1" description="adc_ext_trg1" start="0x1" />
+        <Enum name="B_0x2" description="adc_ext_trg2" start="0x2" />
+        <Enum name="B_0x3" description="adc_ext_trg3" start="0x3" />
+        <Enum name="B_0x4" description="adc_ext_trg4" start="0x4" />
+        <Enum name="B_0x5" description="adc_ext_trg5" start="0x5" />
+        <Enum name="B_0x6" description="adc_ext_trg6" start="0x6" />
+        <Enum name="B_0x7" description="adc_ext_trg7" start="0x7" />
+        <Enum name="B_0x1F" description="adc_ext_trg31" start="0x1F" />
+      </BitField>
+      <BitField name="EXTSEL3" description="External trigger selection for regular group These bits select the external event used to trigger the start of conversion of a regular group: ... Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing)." start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="adc_ext_trg0" start="0x0" />
+        <Enum name="B_0x1" description="adc_ext_trg1" start="0x1" />
+        <Enum name="B_0x2" description="adc_ext_trg2" start="0x2" />
+        <Enum name="B_0x3" description="adc_ext_trg3" start="0x3" />
+        <Enum name="B_0x4" description="adc_ext_trg4" start="0x4" />
+        <Enum name="B_0x5" description="adc_ext_trg5" start="0x5" />
+        <Enum name="B_0x6" description="adc_ext_trg6" start="0x6" />
+        <Enum name="B_0x7" description="adc_ext_trg7" start="0x7" />
+        <Enum name="B_0x1F" description="adc_ext_trg31" start="0x1F" />
+      </BitField>
+      <BitField name="EXTSEL4" description="External trigger selection for regular group These bits select the external event used to trigger the start of conversion of a regular group: ... Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing)." start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="adc_ext_trg0" start="0x0" />
+        <Enum name="B_0x1" description="adc_ext_trg1" start="0x1" />
+        <Enum name="B_0x2" description="adc_ext_trg2" start="0x2" />
+        <Enum name="B_0x3" description="adc_ext_trg3" start="0x3" />
+        <Enum name="B_0x4" description="adc_ext_trg4" start="0x4" />
+        <Enum name="B_0x5" description="adc_ext_trg5" start="0x5" />
+        <Enum name="B_0x6" description="adc_ext_trg6" start="0x6" />
+        <Enum name="B_0x7" description="adc_ext_trg7" start="0x7" />
+        <Enum name="B_0x1F" description="adc_ext_trg31" start="0x1F" />
+      </BitField>
+      <BitField name="EXTEN" description="External trigger enable and polarity selection for regular channels These bits are set and cleared by software to select the external trigger polarity and enable the trigger of a regular group. Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing)." start="10" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Hardware trigger detection disabled (conversions can be launched by software)" start="0x0" />
+        <Enum name="B_0x1" description="Hardware trigger detection on the rising edge" start="0x1" />
+        <Enum name="B_0x2" description="Hardware trigger detection on the falling edge" start="0x2" />
+        <Enum name="B_0x3" description="Hardware trigger detection on both the rising and falling edges" start="0x3" />
+      </BitField>
+      <BitField name="OVRMOD" description="Overrun mode This bit is set and cleared by software and configure the way data overrun is managed. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no regular conversion is ongoing)." start="12" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="ADC_DR register is preserved with the old data when an overrun is detected. " start="0x0" />
+        <Enum name="B_0x1" description="ADC_DR register is overwritten with the last conversion result when an overrun is detected." start="0x1" />
+      </BitField>
+      <BitField name="CONT" description="Single / Continuous conversion mode for regular conversions This bit is set and cleared by software. If it is set, regular conversion takes place continuously until it is cleared. Note: It is not possible to have both Discontinuous mode and Continuous mode enabled: it is forbidden to set both DISCEN = 1 and CONT = 1. The software is allowed to write this bit only when ADSTART = 0 (which ensures that no regular conversion is ongoing)." start="13" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Single conversion mode" start="0x0" />
+        <Enum name="B_0x1" description="Continuous conversion mode" start="0x1" />
+      </BitField>
+      <BitField name="AUTDLY" description="Delayed conversion mode This bit is set and cleared by software to enable/disable the Auto Delayed Conversion mode.. Note: The software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing)." start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Auto-delayed conversion mode off" start="0x0" />
+        <Enum name="B_0x1" description="Auto-delayed conversion mode on" start="0x1" />
+      </BitField>
+      <BitField name="ALIGN" description="Data alignment This bit is set and cleared by software to select right or left alignment. Refer to register, data alignment and offset (ADC_DR, OFFSET, OFFSET_CH, ALIGN). Note: The software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing)." start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Right alignment" start="0x0" />
+        <Enum name="B_0x1" description="Left alignment" start="0x1" />
+      </BitField>
+      <BitField name="DISCEN" description="Discontinuous mode for regular channels This bit is set and cleared by software to enable/disable Discontinuous mode for regular channels. Note: It is not possible to have both Discontinuous mode and Continuous mode enabled: it is forbidden to set both DISCEN = 1 and CONT = 1. It is not possible to use both auto-injected mode and Discontinuous mode simultaneously: the bits DISCEN and JDISCEN must be kept cleared by software when JAUTO is set. The software is allowed to write this bit only when ADSTART = 0 (which ensures that no regular conversion is ongoing)." start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Discontinuous mode for regular channels disabled" start="0x0" />
+        <Enum name="B_0x1" description="Discontinuous mode for regular channels enabled" start="0x1" />
+      </BitField>
+      <BitField name="DISCNUM" description="Discontinuous mode channel count These bits are written by software to define the number of regular channels to be converted in Discontinuous mode, after receiving an external trigger. ... Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing)." start="17" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="1 channel" start="0x0" />
+        <Enum name="B_0x1" description="2 channels" start="0x1" />
+        <Enum name="B_0x7" description="8 channels" start="0x7" />
+      </BitField>
+      <BitField name="JDISCEN" description="Discontinuous mode on injected channels This bit is set and cleared by software to enable/disable Discontinuous mode on the injected channels of a group. Note: The software is allowed to write this bit only when JADSTART = 0 (which ensures that no injected conversion is ongoing). It is not possible to use both auto-injected mode and Discontinuous mode simultaneously: the bits DISCEN and JDISCEN must be kept cleared by software when JAUTO is set." start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Discontinuous mode on injected channels disabled" start="0x0" />
+        <Enum name="B_0x1" description="Discontinuous mode on injected channels enabled" start="0x1" />
+      </BitField>
+      <BitField name="JQM" description="JSQR queue mode This bit is set and cleared by software. It defines how an empty Queue is managed. Refer to for more information. Note: The software is allowed to write this bit only when JADSTART = 0 (which ensures that no injected conversion is ongoing)." start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="JSQR mode 0: The Queue is never empty and maintains the last written configuration into JSQR." start="0x0" />
+        <Enum name="B_0x1" description="JSQR mode 1: The Queue can be empty and when this occurs, the software and hardware triggers of the injected sequence are both internally disabled just after the completion of the last valid injected sequence." start="0x1" />
+      </BitField>
+      <BitField name="AWD1SGL" description="Enable the watchdog 1 on a single channel or on all channels This bit is set and cleared by software to enable the analog watchdog on the channel identified by the AWD1CH[4:0] bits or on all the channels Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing)." start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Analog watchdog 1 enabled on all channels" start="0x0" />
+        <Enum name="B_0x1" description="Analog watchdog 1 enabled on a single channel" start="0x1" />
+      </BitField>
+      <BitField name="AWD1EN" description="Analog watchdog 1 enable on regular channels This bit is set and cleared by software Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no regular conversion is ongoing)." start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Analog watchdog 1 disabled on regular channels" start="0x0" />
+        <Enum name="B_0x1" description="Analog watchdog 1 enabled on regular channels" start="0x1" />
+      </BitField>
+      <BitField name="JAWD1EN" description="Analog watchdog 1 enable on injected channels This bit is set and cleared by software Note: The software is allowed to write this bit only when JADSTART = 0 (which ensures that no injected conversion is ongoing)." start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Analog watchdog 1 disabled on injected channels" start="0x0" />
+        <Enum name="B_0x1" description="Analog watchdog 1 enabled on injected channels" start="0x1" />
+      </BitField>
+      <BitField name="JAUTO" description="Automatic injected group conversion This bit is set and cleared by software to enable/disable automatic injected group conversion after regular group conversion. Note: The software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0 (which ensures that no regular nor injected conversion is ongoing)." start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Automatic injected group conversion disabled" start="0x0" />
+        <Enum name="B_0x1" description="Automatic injected group conversion enabled" start="0x1" />
+      </BitField>
+      <BitField name="AWD1CH" description="Analog watchdog 1 channel selection These bits are set and cleared by software. They select the input channel to be guarded by the analog watchdog. ..... others: reserved, must not be used Note: Some channels are not connected physically. Keep the corresponding AWD1CH[4:0] setting to the reset value. The channel selected by AWD1CH must be also selected into the SQRi or JSQRi registers. The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing)." start="26" size="5" access="Read/Write">
+        <Enum name="B_0x0" description="ADC analog input channel 0 monitored by AWD1 " start="0x0" />
+        <Enum name="B_0x1" description="ADC analog input channel 1 monitored by AWD1" start="0x1" />
+        <Enum name="B_0x12" description="ADC analog input channel 18 monitored by AWD1" start="0x12" />
+      </BitField>
+      <BitField name="JQDIS" description="Injected Queue disable These bits are set and cleared by software to disable the Injected Queue mechanism : Note: The software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0 (which ensures that no regular nor injected conversion is ongoing). A set or reset of JQDIS bit causes the injected queue to be flushed and the JSQR register is cleared." start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Injected Queue enabled" start="0x0" />
+        <Enum name="B_0x1" description="Injected Queue disabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="ADC_CFGR2" description="ADC configuration register 2 " start="+0x10" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ROVSE" description="Regular Oversampling Enable This bit is set and cleared by software to enable regular oversampling. Note: The software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing)" start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Regular Oversampling disabled" start="0x0" />
+        <Enum name="B_0x1" description="Regular Oversampling enabled" start="0x1" />
+      </BitField>
+      <BitField name="JOVSE" description="Injected Oversampling Enable This bit is set and cleared by software to enable injected oversampling. Note: The software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing)" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Injected Oversampling disabled" start="0x0" />
+        <Enum name="B_0x1" description="Injected Oversampling enabled" start="0x1" />
+      </BitField>
+      <BitField name="OVSR" description="Oversampling ratio This bitfield is set and cleared by software to define the oversampling ratio. Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no conversion is ongoing)." start="2" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="2x" start="0x0" />
+        <Enum name="B_0x1" description="4x" start="0x1" />
+        <Enum name="B_0x2" description="8x" start="0x2" />
+        <Enum name="B_0x3" description="16x" start="0x3" />
+        <Enum name="B_0x4" description="32x" start="0x4" />
+        <Enum name="B_0x5" description="64x" start="0x5" />
+        <Enum name="B_0x6" description="128x" start="0x6" />
+        <Enum name="B_0x7" description="256x" start="0x7" />
+      </BitField>
+      <BitField name="OVSS" description="Oversampling shift This bitfield is set and cleared by software to define the right shifting applied to the raw oversampling result. Other codes reserved Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no conversion is ongoing)." start="5" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="No shift" start="0x0" />
+        <Enum name="B_0x1" description="Shift 1-bit" start="0x1" />
+        <Enum name="B_0x2" description="Shift 2-bits" start="0x2" />
+        <Enum name="B_0x3" description="Shift 3-bits" start="0x3" />
+        <Enum name="B_0x4" description="Shift 4-bits" start="0x4" />
+        <Enum name="B_0x5" description="Shift 5-bits" start="0x5" />
+        <Enum name="B_0x6" description="Shift 6-bits" start="0x6" />
+        <Enum name="B_0x7" description="Shift 7-bits" start="0x7" />
+        <Enum name="B_0x8" description="Shift 8-bits" start="0x8" />
+      </BitField>
+      <BitField name="TROVS" description="Triggered Regular Oversampling This bit is set and cleared by software to enable triggered oversampling Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing)." start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="All oversampled conversions for a channel are done consecutively following a trigger" start="0x0" />
+        <Enum name="B_0x1" description="Each oversampled conversion for a channel needs a new trigger" start="0x1" />
+      </BitField>
+      <BitField name="ROVSM" description="Regular Oversampling mode This bit is set and cleared by software to select the regular oversampling mode. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing)." start="10" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Continued mode: When injected conversions are triggered, the oversampling is temporary stopped and continued after the injection sequence (oversampling buffer is maintained during injected sequence)" start="0x0" />
+        <Enum name="B_0x1" description="Resumed mode: When injected conversions are triggered, the current oversampling is aborted and resumed from start after the injection sequence (oversampling buffer is zeroed by injected sequence start)" start="0x1" />
+      </BitField>
+      <BitField name="SWTRIG" description="Software trigger bit for sampling time control trigger mode This bit is set and cleared by software to enable the bulb sampling mode. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing)." start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Software trigger starts the conversion for sampling time control trigger mode " start="0x0" />
+        <Enum name="B_0x1" description="Software trigger starts the sampling for sampling time control trigger mode " start="0x1" />
+      </BitField>
+      <BitField name="BULB" description="Bulb sampling mode This bit is set and cleared by software to enable the bulb sampling mode. SAMPTRIG bit must not be set when the BULB bit is set. The very first ADC conversion is performed with the sampling time specified in SMPx bits. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing)." start="26" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Bulb sampling mode disabled " start="0x0" />
+        <Enum name="B_0x1" description="Bulb sampling mode enabled. The sampling period starts just after the previous end of conversion." start="0x1" />
+      </BitField>
+      <BitField name="SMPTRIG" description="Sampling time control trigger mode This bit is set and cleared by software to enable the sampling time control trigger mode. The sampling time starts on the trigger rising edge, and the conversion on the trigger falling edge. EXTEN bit should be set to 01. BULB bit must not be set when the SMPTRIG bit is set. When EXTEN bit is set to 00, set SWTRIG to start the sampling and clear SWTRIG bit to start the conversion. Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing)." start="27" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Sampling time control trigger mode disabled " start="0x0" />
+        <Enum name="B_0x1" description="Sampling time control trigger mode enabled" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="ADC_SMPR1" description="ADC sample time register 1 " start="+0x14" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SMP0" description="Channel x sampling time selection These bits are written by software to select the sampling time individually for each channel. During sample cycles, the channel selection bits must remain unchanged. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). Some channels are not connected physically. Keep the corresponding SMPx[2:0] setting to the reset value." start="0" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="2.5 ADC clock cycles" start="0x0" />
+        <Enum name="B_0x1" description="6.5 ADC clock cycles" start="0x1" />
+        <Enum name="B_0x2" description="12.5 ADC clock cycles" start="0x2" />
+        <Enum name="B_0x3" description="24.5 ADC clock cycles" start="0x3" />
+        <Enum name="B_0x4" description="47.5 ADC clock cycles" start="0x4" />
+        <Enum name="B_0x5" description="92.5 ADC clock cycles" start="0x5" />
+        <Enum name="B_0x6" description="247.5 ADC clock cycles" start="0x6" />
+        <Enum name="B_0x7" description="640.5 ADC clock cycles" start="0x7" />
+      </BitField>
+      <BitField name="SMP1" description="Channel x sampling time selection These bits are written by software to select the sampling time individually for each channel. During sample cycles, the channel selection bits must remain unchanged. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). Some channels are not connected physically. Keep the corresponding SMPx[2:0] setting to the reset value." start="3" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="2.5 ADC clock cycles" start="0x0" />
+        <Enum name="B_0x1" description="6.5 ADC clock cycles" start="0x1" />
+        <Enum name="B_0x2" description="12.5 ADC clock cycles" start="0x2" />
+        <Enum name="B_0x3" description="24.5 ADC clock cycles" start="0x3" />
+        <Enum name="B_0x4" description="47.5 ADC clock cycles" start="0x4" />
+        <Enum name="B_0x5" description="92.5 ADC clock cycles" start="0x5" />
+        <Enum name="B_0x6" description="247.5 ADC clock cycles" start="0x6" />
+        <Enum name="B_0x7" description="640.5 ADC clock cycles" start="0x7" />
+      </BitField>
+      <BitField name="SMP2" description="Channel x sampling time selection These bits are written by software to select the sampling time individually for each channel. During sample cycles, the channel selection bits must remain unchanged. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). Some channels are not connected physically. Keep the corresponding SMPx[2:0] setting to the reset value." start="6" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="2.5 ADC clock cycles" start="0x0" />
+        <Enum name="B_0x1" description="6.5 ADC clock cycles" start="0x1" />
+        <Enum name="B_0x2" description="12.5 ADC clock cycles" start="0x2" />
+        <Enum name="B_0x3" description="24.5 ADC clock cycles" start="0x3" />
+        <Enum name="B_0x4" description="47.5 ADC clock cycles" start="0x4" />
+        <Enum name="B_0x5" description="92.5 ADC clock cycles" start="0x5" />
+        <Enum name="B_0x6" description="247.5 ADC clock cycles" start="0x6" />
+        <Enum name="B_0x7" description="640.5 ADC clock cycles" start="0x7" />
+      </BitField>
+      <BitField name="SMP3" description="Channel x sampling time selection These bits are written by software to select the sampling time individually for each channel. During sample cycles, the channel selection bits must remain unchanged. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). Some channels are not connected physically. Keep the corresponding SMPx[2:0] setting to the reset value." start="9" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="2.5 ADC clock cycles" start="0x0" />
+        <Enum name="B_0x1" description="6.5 ADC clock cycles" start="0x1" />
+        <Enum name="B_0x2" description="12.5 ADC clock cycles" start="0x2" />
+        <Enum name="B_0x3" description="24.5 ADC clock cycles" start="0x3" />
+        <Enum name="B_0x4" description="47.5 ADC clock cycles" start="0x4" />
+        <Enum name="B_0x5" description="92.5 ADC clock cycles" start="0x5" />
+        <Enum name="B_0x6" description="247.5 ADC clock cycles" start="0x6" />
+        <Enum name="B_0x7" description="640.5 ADC clock cycles" start="0x7" />
+      </BitField>
+      <BitField name="SMP4" description="Channel x sampling time selection These bits are written by software to select the sampling time individually for each channel. During sample cycles, the channel selection bits must remain unchanged. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). Some channels are not connected physically. Keep the corresponding SMPx[2:0] setting to the reset value." start="12" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="2.5 ADC clock cycles" start="0x0" />
+        <Enum name="B_0x1" description="6.5 ADC clock cycles" start="0x1" />
+        <Enum name="B_0x2" description="12.5 ADC clock cycles" start="0x2" />
+        <Enum name="B_0x3" description="24.5 ADC clock cycles" start="0x3" />
+        <Enum name="B_0x4" description="47.5 ADC clock cycles" start="0x4" />
+        <Enum name="B_0x5" description="92.5 ADC clock cycles" start="0x5" />
+        <Enum name="B_0x6" description="247.5 ADC clock cycles" start="0x6" />
+        <Enum name="B_0x7" description="640.5 ADC clock cycles" start="0x7" />
+      </BitField>
+      <BitField name="SMP5" description="Channel x sampling time selection These bits are written by software to select the sampling time individually for each channel. During sample cycles, the channel selection bits must remain unchanged. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). Some channels are not connected physically. Keep the corresponding SMPx[2:0] setting to the reset value." start="15" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="2.5 ADC clock cycles" start="0x0" />
+        <Enum name="B_0x1" description="6.5 ADC clock cycles" start="0x1" />
+        <Enum name="B_0x2" description="12.5 ADC clock cycles" start="0x2" />
+        <Enum name="B_0x3" description="24.5 ADC clock cycles" start="0x3" />
+        <Enum name="B_0x4" description="47.5 ADC clock cycles" start="0x4" />
+        <Enum name="B_0x5" description="92.5 ADC clock cycles" start="0x5" />
+        <Enum name="B_0x6" description="247.5 ADC clock cycles" start="0x6" />
+        <Enum name="B_0x7" description="640.5 ADC clock cycles" start="0x7" />
+      </BitField>
+      <BitField name="SMP6" description="Channel x sampling time selection These bits are written by software to select the sampling time individually for each channel. During sample cycles, the channel selection bits must remain unchanged. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). Some channels are not connected physically. Keep the corresponding SMPx[2:0] setting to the reset value." start="18" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="2.5 ADC clock cycles" start="0x0" />
+        <Enum name="B_0x1" description="6.5 ADC clock cycles" start="0x1" />
+        <Enum name="B_0x2" description="12.5 ADC clock cycles" start="0x2" />
+        <Enum name="B_0x3" description="24.5 ADC clock cycles" start="0x3" />
+        <Enum name="B_0x4" description="47.5 ADC clock cycles" start="0x4" />
+        <Enum name="B_0x5" description="92.5 ADC clock cycles" start="0x5" />
+        <Enum name="B_0x6" description="247.5 ADC clock cycles" start="0x6" />
+        <Enum name="B_0x7" description="640.5 ADC clock cycles" start="0x7" />
+      </BitField>
+      <BitField name="SMP7" description="Channel x sampling time selection These bits are written by software to select the sampling time individually for each channel. During sample cycles, the channel selection bits must remain unchanged. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). Some channels are not connected physically. Keep the corresponding SMPx[2:0] setting to the reset value." start="21" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="2.5 ADC clock cycles" start="0x0" />
+        <Enum name="B_0x1" description="6.5 ADC clock cycles" start="0x1" />
+        <Enum name="B_0x2" description="12.5 ADC clock cycles" start="0x2" />
+        <Enum name="B_0x3" description="24.5 ADC clock cycles" start="0x3" />
+        <Enum name="B_0x4" description="47.5 ADC clock cycles" start="0x4" />
+        <Enum name="B_0x5" description="92.5 ADC clock cycles" start="0x5" />
+        <Enum name="B_0x6" description="247.5 ADC clock cycles" start="0x6" />
+        <Enum name="B_0x7" description="640.5 ADC clock cycles" start="0x7" />
+      </BitField>
+      <BitField name="SMP8" description="Channel x sampling time selection These bits are written by software to select the sampling time individually for each channel. During sample cycles, the channel selection bits must remain unchanged. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). Some channels are not connected physically. Keep the corresponding SMPx[2:0] setting to the reset value." start="24" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="2.5 ADC clock cycles" start="0x0" />
+        <Enum name="B_0x1" description="6.5 ADC clock cycles" start="0x1" />
+        <Enum name="B_0x2" description="12.5 ADC clock cycles" start="0x2" />
+        <Enum name="B_0x3" description="24.5 ADC clock cycles" start="0x3" />
+        <Enum name="B_0x4" description="47.5 ADC clock cycles" start="0x4" />
+        <Enum name="B_0x5" description="92.5 ADC clock cycles" start="0x5" />
+        <Enum name="B_0x6" description="247.5 ADC clock cycles" start="0x6" />
+        <Enum name="B_0x7" description="640.5 ADC clock cycles" start="0x7" />
+      </BitField>
+      <BitField name="SMP9" description="Channel x sampling time selection These bits are written by software to select the sampling time individually for each channel. During sample cycles, the channel selection bits must remain unchanged. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). Some channels are not connected physically. Keep the corresponding SMPx[2:0] setting to the reset value." start="27" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="2.5 ADC clock cycles" start="0x0" />
+        <Enum name="B_0x1" description="6.5 ADC clock cycles" start="0x1" />
+        <Enum name="B_0x2" description="12.5 ADC clock cycles" start="0x2" />
+        <Enum name="B_0x3" description="24.5 ADC clock cycles" start="0x3" />
+        <Enum name="B_0x4" description="47.5 ADC clock cycles" start="0x4" />
+        <Enum name="B_0x5" description="92.5 ADC clock cycles" start="0x5" />
+        <Enum name="B_0x6" description="247.5 ADC clock cycles" start="0x6" />
+        <Enum name="B_0x7" description="640.5 ADC clock cycles" start="0x7" />
+      </BitField>
+      <BitField name="SMPPLUS" description="Addition of one clock cycle to the sampling time. To make sure no conversion is ongoing, the software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0." start="31" size="1" access="Read/Write">
+        <Enum name="B_0x1" description="2.5 ADC clock cycle sampling time becomes 3.5 ADC clock cycles for the ADC_SMPR1 and ADC_SMPR2 registers." start="0x1" />
+        <Enum name="B_0x0" description="The sampling time remains set to 2.5 ADC clock cycles remains " start="0x0" />
+      </BitField>
+    </Register>
+    <Register name="ADC_SMPR2" description="ADC sample time register 2 " start="+0x18" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SMP10" description="Channel x sampling time selection These bits are written by software to select the sampling time individually for each channel. During sampling cycles, the channel selection bits must remain unchanged. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). Some channels are not connected physically. Keep the corresponding SMPx[2:0] setting to the reset value." start="0" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="2.5 ADC clock cycles" start="0x0" />
+        <Enum name="B_0x1" description="6.5 ADC clock cycles" start="0x1" />
+        <Enum name="B_0x2" description="12.5 ADC clock cycles" start="0x2" />
+        <Enum name="B_0x3" description="24.5 ADC clock cycles" start="0x3" />
+        <Enum name="B_0x4" description="47.5 ADC clock cycles" start="0x4" />
+        <Enum name="B_0x5" description="92.5 ADC clock cycles" start="0x5" />
+        <Enum name="B_0x6" description="247.5 ADC clock cycles" start="0x6" />
+        <Enum name="B_0x7" description="640.5 ADC clock cycles" start="0x7" />
+      </BitField>
+      <BitField name="SMP11" description="Channel x sampling time selection These bits are written by software to select the sampling time individually for each channel. During sampling cycles, the channel selection bits must remain unchanged. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). Some channels are not connected physically. Keep the corresponding SMPx[2:0] setting to the reset value." start="3" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="2.5 ADC clock cycles" start="0x0" />
+        <Enum name="B_0x1" description="6.5 ADC clock cycles" start="0x1" />
+        <Enum name="B_0x2" description="12.5 ADC clock cycles" start="0x2" />
+        <Enum name="B_0x3" description="24.5 ADC clock cycles" start="0x3" />
+        <Enum name="B_0x4" description="47.5 ADC clock cycles" start="0x4" />
+        <Enum name="B_0x5" description="92.5 ADC clock cycles" start="0x5" />
+        <Enum name="B_0x6" description="247.5 ADC clock cycles" start="0x6" />
+        <Enum name="B_0x7" description="640.5 ADC clock cycles" start="0x7" />
+      </BitField>
+      <BitField name="SMP12" description="Channel x sampling time selection These bits are written by software to select the sampling time individually for each channel. During sampling cycles, the channel selection bits must remain unchanged. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). Some channels are not connected physically. Keep the corresponding SMPx[2:0] setting to the reset value." start="6" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="2.5 ADC clock cycles" start="0x0" />
+        <Enum name="B_0x1" description="6.5 ADC clock cycles" start="0x1" />
+        <Enum name="B_0x2" description="12.5 ADC clock cycles" start="0x2" />
+        <Enum name="B_0x3" description="24.5 ADC clock cycles" start="0x3" />
+        <Enum name="B_0x4" description="47.5 ADC clock cycles" start="0x4" />
+        <Enum name="B_0x5" description="92.5 ADC clock cycles" start="0x5" />
+        <Enum name="B_0x6" description="247.5 ADC clock cycles" start="0x6" />
+        <Enum name="B_0x7" description="640.5 ADC clock cycles" start="0x7" />
+      </BitField>
+      <BitField name="SMP13" description="Channel x sampling time selection These bits are written by software to select the sampling time individually for each channel. During sampling cycles, the channel selection bits must remain unchanged. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). Some channels are not connected physically. Keep the corresponding SMPx[2:0] setting to the reset value." start="9" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="2.5 ADC clock cycles" start="0x0" />
+        <Enum name="B_0x1" description="6.5 ADC clock cycles" start="0x1" />
+        <Enum name="B_0x2" description="12.5 ADC clock cycles" start="0x2" />
+        <Enum name="B_0x3" description="24.5 ADC clock cycles" start="0x3" />
+        <Enum name="B_0x4" description="47.5 ADC clock cycles" start="0x4" />
+        <Enum name="B_0x5" description="92.5 ADC clock cycles" start="0x5" />
+        <Enum name="B_0x6" description="247.5 ADC clock cycles" start="0x6" />
+        <Enum name="B_0x7" description="640.5 ADC clock cycles" start="0x7" />
+      </BitField>
+      <BitField name="SMP14" description="Channel x sampling time selection These bits are written by software to select the sampling time individually for each channel. During sampling cycles, the channel selection bits must remain unchanged. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). Some channels are not connected physically. Keep the corresponding SMPx[2:0] setting to the reset value." start="12" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="2.5 ADC clock cycles" start="0x0" />
+        <Enum name="B_0x1" description="6.5 ADC clock cycles" start="0x1" />
+        <Enum name="B_0x2" description="12.5 ADC clock cycles" start="0x2" />
+        <Enum name="B_0x3" description="24.5 ADC clock cycles" start="0x3" />
+        <Enum name="B_0x4" description="47.5 ADC clock cycles" start="0x4" />
+        <Enum name="B_0x5" description="92.5 ADC clock cycles" start="0x5" />
+        <Enum name="B_0x6" description="247.5 ADC clock cycles" start="0x6" />
+        <Enum name="B_0x7" description="640.5 ADC clock cycles" start="0x7" />
+      </BitField>
+      <BitField name="SMP15" description="Channel x sampling time selection These bits are written by software to select the sampling time individually for each channel. During sampling cycles, the channel selection bits must remain unchanged. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). Some channels are not connected physically. Keep the corresponding SMPx[2:0] setting to the reset value." start="15" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="2.5 ADC clock cycles" start="0x0" />
+        <Enum name="B_0x1" description="6.5 ADC clock cycles" start="0x1" />
+        <Enum name="B_0x2" description="12.5 ADC clock cycles" start="0x2" />
+        <Enum name="B_0x3" description="24.5 ADC clock cycles" start="0x3" />
+        <Enum name="B_0x4" description="47.5 ADC clock cycles" start="0x4" />
+        <Enum name="B_0x5" description="92.5 ADC clock cycles" start="0x5" />
+        <Enum name="B_0x6" description="247.5 ADC clock cycles" start="0x6" />
+        <Enum name="B_0x7" description="640.5 ADC clock cycles" start="0x7" />
+      </BitField>
+      <BitField name="SMP16" description="Channel x sampling time selection These bits are written by software to select the sampling time individually for each channel. During sampling cycles, the channel selection bits must remain unchanged. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). Some channels are not connected physically. Keep the corresponding SMPx[2:0] setting to the reset value." start="18" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="2.5 ADC clock cycles" start="0x0" />
+        <Enum name="B_0x1" description="6.5 ADC clock cycles" start="0x1" />
+        <Enum name="B_0x2" description="12.5 ADC clock cycles" start="0x2" />
+        <Enum name="B_0x3" description="24.5 ADC clock cycles" start="0x3" />
+        <Enum name="B_0x4" description="47.5 ADC clock cycles" start="0x4" />
+        <Enum name="B_0x5" description="92.5 ADC clock cycles" start="0x5" />
+        <Enum name="B_0x6" description="247.5 ADC clock cycles" start="0x6" />
+        <Enum name="B_0x7" description="640.5 ADC clock cycles" start="0x7" />
+      </BitField>
+      <BitField name="SMP17" description="Channel x sampling time selection These bits are written by software to select the sampling time individually for each channel. During sampling cycles, the channel selection bits must remain unchanged. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). Some channels are not connected physically. Keep the corresponding SMPx[2:0] setting to the reset value." start="21" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="2.5 ADC clock cycles" start="0x0" />
+        <Enum name="B_0x1" description="6.5 ADC clock cycles" start="0x1" />
+        <Enum name="B_0x2" description="12.5 ADC clock cycles" start="0x2" />
+        <Enum name="B_0x3" description="24.5 ADC clock cycles" start="0x3" />
+        <Enum name="B_0x4" description="47.5 ADC clock cycles" start="0x4" />
+        <Enum name="B_0x5" description="92.5 ADC clock cycles" start="0x5" />
+        <Enum name="B_0x6" description="247.5 ADC clock cycles" start="0x6" />
+        <Enum name="B_0x7" description="640.5 ADC clock cycles" start="0x7" />
+      </BitField>
+      <BitField name="SMP18" description="Channel x sampling time selection These bits are written by software to select the sampling time individually for each channel. During sampling cycles, the channel selection bits must remain unchanged. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). Some channels are not connected physically. Keep the corresponding SMPx[2:0] setting to the reset value." start="24" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="2.5 ADC clock cycles" start="0x0" />
+        <Enum name="B_0x1" description="6.5 ADC clock cycles" start="0x1" />
+        <Enum name="B_0x2" description="12.5 ADC clock cycles" start="0x2" />
+        <Enum name="B_0x3" description="24.5 ADC clock cycles" start="0x3" />
+        <Enum name="B_0x4" description="47.5 ADC clock cycles" start="0x4" />
+        <Enum name="B_0x5" description="92.5 ADC clock cycles" start="0x5" />
+        <Enum name="B_0x6" description="247.5 ADC clock cycles" start="0x6" />
+        <Enum name="B_0x7" description="640.5 ADC clock cycles" start="0x7" />
+      </BitField>
+    </Register>
+    <Register name="ADC_TR1" description="ADC watchdog threshold register 1 " start="+0x20" size="4" reset_value="0x0FFF0000" reset_mask="0xFFFFFFFF">
+      <BitField name="LT1" description="Analog watchdog 1 lower threshold These bits are written by software to define the lower threshold for the analog watchdog 1. Refer to AWD2CH, AWD3CH, AWD_HTx, AWD_LTx, AWDx) Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing)." start="0" size="12" access="Read/Write" />
+      <BitField name="AWDFILT" description="Analog watchdog filtering parameter This bit is set and cleared by software. ... Note: The software is allowed to write this bit only when ADSTART = 0 (which ensures that no conversion is ongoing)." start="12" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="No filtering " start="0x0" />
+        <Enum name="B_0x1" description="two consecutive detection generates an AWDx flag or an interrupt" start="0x1" />
+        <Enum name="B_0x7" description="Eight consecutive detection generates an AWDx flag or an interrupt" start="0x7" />
+      </BitField>
+      <BitField name="HT1" description="Analog watchdog 1 higher threshold These bits are written by software to define the higher threshold for the analog watchdog 1. Refer to AWD2CH, AWD3CH, AWD_HTx, AWD_LTx, AWDx) Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing)." start="16" size="12" access="Read/Write" />
+    </Register>
+    <Register name="ADC_TR2" description="ADC watchdog threshold register 2 " start="+0x24" size="4" reset_value="0x00FF0000" reset_mask="0xFFFFFFFF">
+      <BitField name="LT2" description="Analog watchdog 2 lower threshold These bits are written by software to define the lower threshold for the analog watchdog 2. Refer to AWD2CH, AWD3CH, AWD_HTx, AWD_LTx, AWDx) Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing)." start="0" size="8" access="Read/Write" />
+      <BitField name="HT2" description="Analog watchdog 2 higher threshold These bits are written by software to define the higher threshold for the analog watchdog 2. Refer to AWD2CH, AWD3CH, AWD_HTx, AWD_LTx, AWDx) Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing)." start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="ADC_TR3" description="ADC watchdog threshold register 3 " start="+0x28" size="4" reset_value="0x00FF0000" reset_mask="0xFFFFFFFF">
+      <BitField name="LT3" description="Analog watchdog 3 lower threshold These bits are written by software to define the lower threshold for the analog watchdog 3. This watchdog compares the 8-bit of LT3 with the 8 MSB of the converted data. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing)." start="0" size="8" access="Read/Write" />
+      <BitField name="HT3" description="Analog watchdog 3 higher threshold These bits are written by software to define the higher threshold for the analog watchdog 3. Refer to AWD2CH, AWD3CH, AWD_HTx, AWD_LTx, AWDx) Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing)." start="16" size="8" access="Read/Write" />
+    </Register>
+    <Register name="ADC_SQR1" description="ADC regular sequence register 1 " start="+0x30" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="L" description="Regular channel sequence length These bits are written by software to define the total number of conversions in the regular channel conversion sequence. ... Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing)." start="0" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="1 conversion" start="0x0" />
+        <Enum name="B_0x1" description="2 conversions" start="0x1" />
+        <Enum name="B_0xF" description="16 conversions" start="0xF" />
+      </BitField>
+      <BitField name="SQ1" description="1st conversion in regular sequence These bits are written by software with the channel number (0 to 18) assigned as the 1st in the regular conversion sequence. Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing)." start="6" size="5" access="Read/Write" />
+      <BitField name="SQ2" description="2nd conversion in regular sequence These bits are written by software with the channel number (0 to 18) assigned as the 2nd in the regular conversion sequence. Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing)." start="12" size="5" access="Read/Write" />
+      <BitField name="SQ3" description="3rd conversion in regular sequence These bits are written by software with the channel number (0 to 18) assigned as the 3rd in the regular conversion sequence. Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing)." start="18" size="5" access="Read/Write" />
+      <BitField name="SQ4" description="4th conversion in regular sequence These bits are written by software with the channel number (0 to 18) assigned as the 4th in the regular conversion sequence. Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing)." start="24" size="5" access="Read/Write" />
+    </Register>
+    <Register name="ADC_SQR2" description="ADC regular sequence register 2 " start="+0x34" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SQ5" description="5th conversion in regular sequence These bits are written by software with the channel number (0 to 18) assigned as the 5th in the regular conversion sequence. Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing)." start="0" size="5" access="Read/Write" />
+      <BitField name="SQ6" description="6th conversion in regular sequence These bits are written by software with the channel number (0 to 18) assigned as the 6th in the regular conversion sequence. Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing)." start="6" size="5" access="Read/Write" />
+      <BitField name="SQ7" description="7th conversion in regular sequence These bits are written by software with the channel number (0 to 18) assigned as the 7th in the regular conversion sequence. Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing)." start="12" size="5" access="Read/Write" />
+      <BitField name="SQ8" description="8th conversion in regular sequence These bits are written by software with the channel number (0 to 18) assigned as the 8th in the regular conversion sequence Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing)." start="18" size="5" access="Read/Write" />
+      <BitField name="SQ9" description="9th conversion in regular sequence These bits are written by software with the channel number (0 to 18) assigned as the 9th in the regular conversion sequence. Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing)." start="24" size="5" access="Read/Write" />
+    </Register>
+    <Register name="ADC_SQR3" description="ADC regular sequence register 3 " start="+0x38" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SQ10" description="10th conversion in regular sequence These bits are written by software with the channel number (0 to 18) assigned as the 10th in the regular conversion sequence. Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing)." start="0" size="5" access="Read/Write" />
+      <BitField name="SQ11" description="11th conversion in regular sequence These bits are written by software with the channel number (0 to 18) assigned as the 11th in the regular conversion sequence. Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing)." start="6" size="5" access="Read/Write" />
+      <BitField name="SQ12" description="12th conversion in regular sequence These bits are written by software with the channel number (0 to 18) assigned as the 12th in the regular conversion sequence. Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing)." start="12" size="5" access="Read/Write" />
+      <BitField name="SQ13" description="13th conversion in regular sequence These bits are written by software with the channel number (0 to 18) assigned as the 13th in the regular conversion sequence. Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing)." start="18" size="5" access="Read/Write" />
+      <BitField name="SQ14" description="14th conversion in regular sequence These bits are written by software with the channel number (0 to 18) assigned as the 14th in the regular conversion sequence. Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing)." start="24" size="5" access="Read/Write" />
+    </Register>
+    <Register name="ADC_SQR4" description="ADC regular sequence register 4 " start="+0x3c" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SQ15" description="15th conversion in regular sequence These bits are written by software with the channel number (0 to 18) assigned as the 15th in the regular conversion sequence. Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing)." start="0" size="5" access="Read/Write" />
+      <BitField name="SQ16" description="16th conversion in regular sequence These bits are written by software with the channel number (0 to 18) assigned as the 16th in the regular conversion sequence. Note: The software is allowed to write these bits only when ADSTART = 0 (which ensures that no regular conversion is ongoing)." start="6" size="5" access="Read/Write" />
+    </Register>
+    <Register name="ADC_DR" description="ADC regular data register " start="+0x40" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RDATA" description="Regular data converted These bits are read-only. They contain the conversion result from the last converted regular channel. The data are left- or right-aligned as described in ." start="0" size="16" access="ReadOnly" />
+    </Register>
+    <Register name="ADC_JSQR" description="ADC injected sequence register " start="+0x4c" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="JL" description="Injected channel sequence length These bits are written by software to define the total number of conversions in the injected channel conversion sequence. Note: The software is allowed to write these bits only when JADSTART = 0 (which ensures that no injected conversion is ongoing)." start="0" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="1 conversion" start="0x0" />
+        <Enum name="B_0x1" description="2 conversions" start="0x1" />
+        <Enum name="B_0x2" description="3 conversions" start="0x2" />
+        <Enum name="B_0x3" description="4 conversions" start="0x3" />
+      </BitField>
+      <BitField name="JEXTSEL" description="External Trigger Selection for injected group These bits select the external event used to trigger the start of conversion of an injected group: ... Note: The software is allowed to write these bits only when JADSTART = 0 (which ensures that no injected conversion is ongoing)." start="2" size="5" access="Read/Write">
+        <Enum name="B_0x0" description="adc_jext_trg0" start="0x0" />
+        <Enum name="B_0x1" description="adc_jext_trg1" start="0x1" />
+        <Enum name="B_0x2" description="adc_jext_trg2" start="0x2" />
+        <Enum name="B_0x3" description="adc_jext_trg3" start="0x3" />
+        <Enum name="B_0x4" description="adc_jext_trg4" start="0x4" />
+        <Enum name="B_0x5" description="adc_jext_trg5" start="0x5" />
+        <Enum name="B_0x6" description="adc_jext_trg6" start="0x6" />
+        <Enum name="B_0x7" description="adc_jext_trg7" start="0x7" />
+        <Enum name="B_0x1F" description="adc_jext_trg31" start="0x1F" />
+      </BitField>
+      <BitField name="JEXTEN" description="External trigger enable and polarity selection for injected channels These bits are set and cleared by software to select the external trigger polarity and enable the trigger of an injected group. Note: The software is allowed to write these bits only when JADSTART = 0 (which ensures that no injected conversion is ongoing). If JQM = 1 and if the Queue of Context becomes empty, the software and hardware triggers of the injected sequence are both internally disabled (refer to Queue of context for injected conversions)" start="7" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="If JQDIS = 0 (queue enabled), hardware and software trigger detection disabled. Otherwise, the queue is disabled as well as hardware trigger detection (conversions can be launched by software)" start="0x0" />
+        <Enum name="B_0x1" description="Hardware trigger detection on the rising edge" start="0x1" />
+        <Enum name="B_0x2" description="Hardware trigger detection on the falling edge" start="0x2" />
+        <Enum name="B_0x3" description="Hardware trigger detection on both the rising and falling edges" start="0x3" />
+      </BitField>
+      <BitField name="JSQ1" description="1st conversion in the injected sequence These bits are written by software with the channel number (0 to 18) assigned as the 1st in the injected conversion sequence. Note: The software is allowed to write these bits only when JADSTART = 0 (which ensures that no injected conversion is ongoing)." start="9" size="5" access="Read/Write" />
+      <BitField name="JSQ2" description="2nd conversion in the injected sequence These bits are written by software with the channel number (0 to 18) assigned as the 2nd in the injected conversion sequence. Note: The software is allowed to write these bits only when JADSTART = 0 (which ensures that no injected conversion is ongoing)." start="15" size="5" access="Read/Write" />
+      <BitField name="JSQ3" description="3rd conversion in the injected sequence These bits are written by software with the channel number (0 to 18) assigned as the 3rd in the injected conversion sequence. Note: The software is allowed to write these bits only when JADSTART = 0 (which ensures that no injected conversion is ongoing)." start="21" size="5" access="Read/Write" />
+      <BitField name="JSQ4" description="4th conversion in the injected sequence These bits are written by software with the channel number (0 to 18) assigned as the 4th in the injected conversion sequence. Note: The software is allowed to write these bits only when JADSTART = 0 (which ensures that no injected conversion is ongoing)." start="27" size="5" access="Read/Write" />
+    </Register>
+    <Register name="ADC_OFR1" description="ADC offset 1 register" start="+0x60" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OFFSET" description="Data offset y for the channel programmed into bits OFFSET_CH[4:0] These bits are written by software to define the offset to be subtracted from the raw converted data when converting a channel (can be regular or injected). The channel to which applies the data offset must be programmed in the bits OFFSET_CH[4:0]. The conversion result can be read from in the ADC_DR (regular conversion) or from in the ADC_JDRyi registers (injected conversion). Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). If several offset (OFFSET) point to the same channel, only the offset with the lowest x value is considered for the subtraction. Ex: if OFFSET1_CH[4:0] = 4 and OFFSET2_CH[4:0] = 4, this is OFFSET1[11:0] which is subtracted when converting channel 4." start="0" size="12" access="Read/Write" />
+      <BitField name="OFFSETPOS" description="Positive offset This bit is set and cleared by software to enable the positive offset. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing)." start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Negative offset " start="0x0" />
+        <Enum name="B_0x1" description="Positive offset " start="0x1" />
+      </BitField>
+      <BitField name="SATEN" description="Saturation enable This bit is set and cleared by software to enable the saturation at 0x000 and 0xFFF for the offset function. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing)." start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No saturation control, offset result can be signed" start="0x0" />
+        <Enum name="B_0x1" description="Saturation enabled, offset result unsigned and saturated at 0x000 and 0xFFF" start="0x1" />
+      </BitField>
+      <BitField name="OFFSET_CH" description="Channel selection for the data offset y These bits are written by software to define the channel to which the offset programmed into bits OFFSET[11:0] applies. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). Some channels are not connected physically and must not be selected for the data offset y. If OFFSET_EN is set, it is not allowed to select the same channel for different ADC_OFRy registers." start="26" size="5" access="Read/Write" />
+      <BitField name="OFFSET_EN" description="Offset y enable This bit is written by software to enable or disable the offset programmed into bits OFFSET[11:0]. Note: The software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing)." start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="ADC_OFR2" description="ADC offset 2 register" start="+0x64" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OFFSET" description="Data offset y for the channel programmed into bits OFFSET_CH[4:0] These bits are written by software to define the offset to be subtracted from the raw converted data when converting a channel (can be regular or injected). The channel to which applies the data offset must be programmed in the bits OFFSET_CH[4:0]. The conversion result can be read from in the ADC_DR (regular conversion) or from in the ADC_JDRyi registers (injected conversion). Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). If several offset (OFFSET) point to the same channel, only the offset with the lowest x value is considered for the subtraction. Ex: if OFFSET1_CH[4:0] = 4 and OFFSET2_CH[4:0] = 4, this is OFFSET1[11:0] which is subtracted when converting channel 4." start="0" size="12" access="Read/Write" />
+      <BitField name="OFFSETPOS" description="Positive offset This bit is set and cleared by software to enable the positive offset. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing)." start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Negative offset " start="0x0" />
+        <Enum name="B_0x1" description="Positive offset " start="0x1" />
+      </BitField>
+      <BitField name="SATEN" description="Saturation enable This bit is set and cleared by software to enable the saturation at 0x000 and 0xFFF for the offset function. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing)." start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No saturation control, offset result can be signed" start="0x0" />
+        <Enum name="B_0x1" description="Saturation enabled, offset result unsigned and saturated at 0x000 and 0xFFF" start="0x1" />
+      </BitField>
+      <BitField name="OFFSET_CH" description="Channel selection for the data offset y These bits are written by software to define the channel to which the offset programmed into bits OFFSET[11:0] applies. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). Some channels are not connected physically and must not be selected for the data offset y. If OFFSET_EN is set, it is not allowed to select the same channel for different ADC_OFRy registers." start="26" size="5" access="Read/Write" />
+      <BitField name="OFFSET_EN" description="Offset y enable This bit is written by software to enable or disable the offset programmed into bits OFFSET[11:0]. Note: The software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing)." start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="ADC_OFR3" description="ADC offset 3 register" start="+0x68" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OFFSET" description="Data offset y for the channel programmed into bits OFFSET_CH[4:0] These bits are written by software to define the offset to be subtracted from the raw converted data when converting a channel (can be regular or injected). The channel to which applies the data offset must be programmed in the bits OFFSET_CH[4:0]. The conversion result can be read from in the ADC_DR (regular conversion) or from in the ADC_JDRyi registers (injected conversion). Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). If several offset (OFFSET) point to the same channel, only the offset with the lowest x value is considered for the subtraction. Ex: if OFFSET1_CH[4:0] = 4 and OFFSET2_CH[4:0] = 4, this is OFFSET1[11:0] which is subtracted when converting channel 4." start="0" size="12" access="Read/Write" />
+      <BitField name="OFFSETPOS" description="Positive offset This bit is set and cleared by software to enable the positive offset. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing)." start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Negative offset " start="0x0" />
+        <Enum name="B_0x1" description="Positive offset " start="0x1" />
+      </BitField>
+      <BitField name="SATEN" description="Saturation enable This bit is set and cleared by software to enable the saturation at 0x000 and 0xFFF for the offset function. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing)." start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No saturation control, offset result can be signed" start="0x0" />
+        <Enum name="B_0x1" description="Saturation enabled, offset result unsigned and saturated at 0x000 and 0xFFF" start="0x1" />
+      </BitField>
+      <BitField name="OFFSET_CH" description="Channel selection for the data offset y These bits are written by software to define the channel to which the offset programmed into bits OFFSET[11:0] applies. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). Some channels are not connected physically and must not be selected for the data offset y. If OFFSET_EN is set, it is not allowed to select the same channel for different ADC_OFRy registers." start="26" size="5" access="Read/Write" />
+      <BitField name="OFFSET_EN" description="Offset y enable This bit is written by software to enable or disable the offset programmed into bits OFFSET[11:0]. Note: The software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing)." start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="ADC_OFR4" description="ADC offset 4 register" start="+0x6c" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OFFSET" description="Data offset y for the channel programmed into bits OFFSET_CH[4:0] These bits are written by software to define the offset to be subtracted from the raw converted data when converting a channel (can be regular or injected). The channel to which applies the data offset must be programmed in the bits OFFSET_CH[4:0]. The conversion result can be read from in the ADC_DR (regular conversion) or from in the ADC_JDRyi registers (injected conversion). Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). If several offset (OFFSET) point to the same channel, only the offset with the lowest x value is considered for the subtraction. Ex: if OFFSET1_CH[4:0] = 4 and OFFSET2_CH[4:0] = 4, this is OFFSET1[11:0] which is subtracted when converting channel 4." start="0" size="12" access="Read/Write" />
+      <BitField name="OFFSETPOS" description="Positive offset This bit is set and cleared by software to enable the positive offset. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing)." start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Negative offset " start="0x0" />
+        <Enum name="B_0x1" description="Positive offset " start="0x1" />
+      </BitField>
+      <BitField name="SATEN" description="Saturation enable This bit is set and cleared by software to enable the saturation at 0x000 and 0xFFF for the offset function. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing)." start="25" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No saturation control, offset result can be signed" start="0x0" />
+        <Enum name="B_0x1" description="Saturation enabled, offset result unsigned and saturated at 0x000 and 0xFFF" start="0x1" />
+      </BitField>
+      <BitField name="OFFSET_CH" description="Channel selection for the data offset y These bits are written by software to define the channel to which the offset programmed into bits OFFSET[11:0] applies. Note: The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). Some channels are not connected physically and must not be selected for the data offset y. If OFFSET_EN is set, it is not allowed to select the same channel for different ADC_OFRy registers." start="26" size="5" access="Read/Write" />
+      <BitField name="OFFSET_EN" description="Offset y enable This bit is written by software to enable or disable the offset programmed into bits OFFSET[11:0]. Note: The software is allowed to write this bit only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing)." start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="ADC_JDR1" description="ADC injected channel 1 data register" start="+0x80" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="JDATA" description="Injected data These bits are read-only. They contain the conversion result from injected channel y. The data are left -or right-aligned as described in ." start="0" size="16" access="ReadOnly" />
+    </Register>
+    <Register name="ADC_JDR2" description="ADC injected channel 2 data register" start="+0x84" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="JDATA" description="Injected data These bits are read-only. They contain the conversion result from injected channel y. The data are left -or right-aligned as described in ." start="0" size="16" access="ReadOnly" />
+    </Register>
+    <Register name="ADC_JDR3" description="ADC injected channel 3 data register" start="+0x88" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="JDATA" description="Injected data These bits are read-only. They contain the conversion result from injected channel y. The data are left -or right-aligned as described in ." start="0" size="16" access="ReadOnly" />
+    </Register>
+    <Register name="ADC_JDR4" description="ADC injected channel 4 data register" start="+0x8c" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="JDATA" description="Injected data These bits are read-only. They contain the conversion result from injected channel y. The data are left -or right-aligned as described in ." start="0" size="16" access="ReadOnly" />
+    </Register>
+    <Register name="ADC_AWD2CR" description="ADC Analog Watchdog 2 Configuration Register " start="+0xa0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AWD2CH" description="Analog watchdog 2 channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by the analog watchdog 2. AWD2CH[i] = 0: ADC analog input channel i is not monitored by AWD2 AWD2CH[i] = 1: ADC analog input channel i is monitored by AWD2 When AWD2CH[18:0] = 000..0, the analog Watchdog 2 is disabled Note: The channels selected by AWD2CH must be also selected into the SQRi or JSQRi registers. The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). Some channels are not connected physically and must not be selected for the analog watchdog." start="0" size="19" access="Read/Write" />
+    </Register>
+    <Register name="ADC_AWD3CR" description="ADC Analog Watchdog 3 Configuration Register " start="+0xa4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AWD3CH" description="Analog watchdog 3 channel selection These bits are set and cleared by software. They enable and select the input channels to be guarded by the analog watchdog 3. AWD3CH[i] = 0: ADC analog input channel i is not monitored by AWD3 AWD3CH[i] = 1: ADC analog input channel i is monitored by AWD3 When AWD3CH[18:0] = 000..0, the analog Watchdog 3 is disabled Note: The channels selected by AWD3CH must be also selected into the SQRi or JSQRi registers. The software is allowed to write these bits only when ADSTART = 0 and JADSTART = 0 (which ensures that no conversion is ongoing). Some channels are not connected physically and must not be selected for the analog watchdog." start="0" size="19" access="Read/Write" />
+    </Register>
+    <Register name="ADC_DIFSEL" description="ADC Differential mode Selection Register " start="+0xb0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DIFSEL" description="Differential mode for channels 18 to 0. These bits are set and cleared by software. They allow to select if a channel is configured as Single-ended or Differential mode. DIFSEL[i] = 0: ADC analog input channel is configured in Single-ended mode DIFSEL[i] = 1: ADC analog input channel i is configured in Differential mode Note: The DIFSEL bits corresponding to channels that are either connected to a single-ended I/O port or to an internal channel must be kept their reset value (Single-ended input mode). The software is allowed to write these bits only when the ADC is disabled (ADCAL = 0, JADSTART = 0, JADSTP = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0)." start="0" size="19" access="Read/Write" />
+    </Register>
+    <Register name="ADC_CALFACT" description="ADC Calibration Factors " start="+0xb4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CALFACT_S" description="Calibration Factors In Single-ended mode These bits are written by hardware or by software. Once a single-ended inputs calibration is complete, they are updated by hardware with the calibration factors. Software can write these bits with a new calibration factor. If the new calibration factor is different from the current one stored into the analog ADC, it is then applied once a new single-ended calibration is launched. Note: The software is allowed to write these bits only when ADEN = 1, ADSTART = 0 and JADSTART = 0 (ADC is enabled and no calibration is ongoing and no conversion is ongoing)." start="0" size="7" access="Read/Write" />
+      <BitField name="CALFACT_D" description="Calibration Factors in differential mode These bits are written by hardware or by software. Once a differential inputs calibration is complete, they are updated by hardware with the calibration factors. Software can write these bits with a new calibration factor. If the new calibration factor is different from the current one stored into the analog ADC, it is then applied once a new differential calibration is launched. Note: The software is allowed to write these bits only when ADEN = 1, ADSTART = 0 and JADSTART = 0 (ADC is enabled and no calibration is ongoing and no conversion is ongoing)." start="16" size="7" access="Read/Write" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="ADC3_Common" description="Analog-to-Digital Converter" start="0x58026300">
+    <Register name="ADC_CSR" description="ADC common status register " start="+0x0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ADRDY_MST" description="Master ADC ready This bit is a copy of the ADRDY bit in the corresponding ADC_ISR register." start="0" size="1" access="ReadOnly" />
+      <BitField name="EOSMP_MST" description="End of Sampling phase flag of the master ADC This bit is a copy of the EOSMP bit in the corresponding ADC_ISR register." start="1" size="1" access="ReadOnly" />
+      <BitField name="EOC_MST" description="End of regular conversion of the master ADC This bit is a copy of the EOC bit in the corresponding ADC_ISR register." start="2" size="1" access="ReadOnly" />
+      <BitField name="EOS_MST" description="End of regular sequence flag of the master ADC This bit is a copy of the EOS bit in the corresponding ADC_ISR register." start="3" size="1" access="ReadOnly" />
+      <BitField name="OVR_MST" description="Overrun flag of the master ADC This bit is a copy of the OVR bit in the corresponding ADC_ISR register." start="4" size="1" access="ReadOnly" />
+      <BitField name="JEOC_MST" description="End of injected conversion flag of the master ADC This bit is a copy of the JEOC bit in the corresponding ADC_ISR register." start="5" size="1" access="ReadOnly" />
+      <BitField name="JEOS_MST" description="End of injected sequence flag of the master ADC This bit is a copy of the JEOS bit in the corresponding ADC_ISR register." start="6" size="1" access="ReadOnly" />
+      <BitField name="AWD1_MST" description="Analog watchdog 1 flag of the master ADC This bit is a copy of the AWD1 bit in the corresponding ADC_ISR register." start="7" size="1" access="ReadOnly" />
+      <BitField name="AWD2_MST" description="Analog watchdog 2 flag of the master ADC This bit is a copy of the AWD2 bit in the corresponding ADC_ISR register." start="8" size="1" access="ReadOnly" />
+      <BitField name="AWD3_MST" description="Analog watchdog 3 flag of the master ADC This bit is a copy of the AWD3 bit in the corresponding ADC_ISR register." start="9" size="1" access="ReadOnly" />
+      <BitField name="JQOVF_MST" description="Injected Context Queue Overflow flag of the master ADC This bit is a copy of the JQOVF bit in the corresponding ADC_ISR register." start="10" size="1" access="ReadOnly" />
+    </Register>
+    <Register name="ADC_CCR" description="ADC common control register " start="+0x8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CKMODE" description="ADC clock mode These bits are set and cleared by software to define the ADC clock scheme (which is common to both master and slave ADCs): In all synchronous clock modes, there is no jitter in the delay from a timer trigger to the start of a conversion. Note: The software is allowed to write these bits only when the ADCs are disabled (ADCAL = 0, JADSTART = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0)." start="16" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="adc_ker_ck (x = 3) (Asynchronous clock mode), generated at product level (refer to Section 6: Reset and clock control (RCC))" start="0x0" />
+        <Enum name="B_0x1" description="adc_hclk/1 (Synchronous clock mode). This configuration must be enabled only if the AHB clock prescaler is set to 1 (HPRE[3:0] = 0XXX in RCC_CFGR register) and if the system clock has a 50% duty cycle." start="0x1" />
+        <Enum name="B_0x2" description="adc_hclk/2 (Synchronous clock mode)" start="0x2" />
+        <Enum name="B_0x3" description="adc_hclk/4 (Synchronous clock mode)" start="0x3" />
+      </BitField>
+      <BitField name="PRESC" description="ADC prescaler These bits are set and cleared by software to select the frequency of the clock to the ADC. The clock is common for all the ADCs. other: reserved Note: The software is allowed to write these bits only when the ADC is disabled (ADCAL = 0, JADSTART = 0, ADSTART = 0, ADSTP = 0, ADDIS = 0 and ADEN = 0). The ADC prescaler value is applied only when CKMODE[1:0] = 0b00." start="18" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="input ADC clock not divided" start="0x0" />
+        <Enum name="B_0x1" description="input ADC clock divided by 2" start="0x1" />
+        <Enum name="B_0x2" description="input ADC clock divided by 4" start="0x2" />
+        <Enum name="B_0x3" description="input ADC clock divided by 6" start="0x3" />
+        <Enum name="B_0x4" description="input ADC clock divided by 8" start="0x4" />
+        <Enum name="B_0x5" description="input ADC clock divided by 10" start="0x5" />
+        <Enum name="B_0x6" description="input ADC clock divided by 12" start="0x6" />
+        <Enum name="B_0x7" description="input ADC clock divided by 16" start="0x7" />
+        <Enum name="B_0x8" description="input ADC clock divided by 32" start="0x8" />
+        <Enum name="B_0x9" description="input ADC clock divided by 64" start="0x9" />
+        <Enum name="B_0xA" description="input ADC clock divided by 128" start="0xA" />
+        <Enum name="B_0xB" description="input ADC clock divided by 256" start="0xB" />
+      </BitField>
+      <BitField name="VREFEN" description="VREFINT enable This bit is set and cleared by software to enable/disable the VREFINT channel." start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="VREFINT channel disabled" start="0x0" />
+        <Enum name="B_0x1" description="VREFINT channel enabled" start="0x1" />
+      </BitField>
+      <BitField name="TSEN" description="VSENSE enable This bit is set and cleared by software to control VSENSE." start="23" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Temperature sensor channel disabled" start="0x0" />
+        <Enum name="B_0x1" description="Temperature sensor channel enabled" start="0x1" />
+      </BitField>
+      <BitField name="VBATEN" description="VBAT enable This bit is set and cleared by software to control." start="24" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="VBAT channel disabled" start="0x0" />
+        <Enum name="B_0x1" description="VBAT channel enabled" start="0x1" />
+      </BitField>
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="AXI" description="AXI interconnect registers" start="0x51000000">
+    <Register name="AXI_PERIPH_ID_4" description="AXI interconnect - peripheral ID4 register" start="+0x1FD0" size="4" access="ReadOnly" reset_value="0x00000004" reset_mask="0xFFFFFFFF">
+      <BitField name="JEP106CON" description="JEP106 continuation code" start="0" size="4" />
+      <BitField name="KCOUNT4" description="Register file size" start="4" size="4" />
+    </Register>
+    <Register name="AXI_PERIPH_ID_0" description="AXI interconnect - peripheral ID0 register" start="+0x1FE0" size="4" access="ReadOnly" reset_value="0x00000004" reset_mask="0xFFFFFFFF">
+      <BitField name="PARTNUM" description="Peripheral part number bits 0 to 7" start="0" size="8" />
+    </Register>
+    <Register name="AXI_PERIPH_ID_1" description="AXI interconnect - peripheral ID1 register" start="+0x1FE4" size="4" access="ReadOnly" reset_value="0x00000004" reset_mask="0xFFFFFFFF">
+      <BitField name="PARTNUM" description="Peripheral part number bits 8 to 11" start="0" size="4" />
+      <BitField name="JEP106I" description="JEP106 identity bits 0 to 3" start="4" size="4" />
+    </Register>
+    <Register name="AXI_PERIPH_ID_2" description="AXI interconnect - peripheral ID2 register" start="+0x1FE8" size="4" access="ReadOnly" reset_value="0x00000004" reset_mask="0xFFFFFFFF">
+      <BitField name="JEP106ID" description="JEP106 Identity bits 4 to 6" start="0" size="3" />
+      <BitField name="JEDEC" description="JEP106 code flag" start="3" size="1" />
+      <BitField name="REVISION" description="Peripheral revision number" start="4" size="4" />
+    </Register>
+    <Register name="AXI_PERIPH_ID_3" description="AXI interconnect - peripheral ID3 register" start="+0x1FEC" size="4" access="ReadOnly" reset_value="0x00000004" reset_mask="0xFFFFFFFF">
+      <BitField name="CUST_MOD_NUM" description="Customer modification" start="0" size="4" />
+      <BitField name="REV_AND" description="Customer version" start="4" size="4" />
+    </Register>
+    <Register name="AXI_COMP_ID_0" description="AXI interconnect - component ID0 register" start="+0x1FF0" size="4" access="ReadOnly" reset_value="0x00000004" reset_mask="0xFFFFFFFF">
+      <BitField name="PREAMBLE" description="Preamble bits 0 to 7" start="0" size="8" />
+    </Register>
+    <Register name="AXI_COMP_ID_1" description="AXI interconnect - component ID1 register" start="+0x1FF4" size="4" access="ReadOnly" reset_value="0x00000004" reset_mask="0xFFFFFFFF">
+      <BitField name="PREAMBLE" description="Preamble bits 8 to 11" start="0" size="4" />
+      <BitField name="CLASS" description="Component class" start="4" size="4" />
+    </Register>
+    <Register name="AXI_COMP_ID_2" description="AXI interconnect - component ID2 register" start="+0x1FF8" size="4" access="ReadOnly" reset_value="0x00000004" reset_mask="0xFFFFFFFF">
+      <BitField name="PREAMBLE" description="Preamble bits 12 to 19" start="0" size="8" />
+    </Register>
+    <Register name="AXI_COMP_ID_3" description="AXI interconnect - component ID3 register" start="+0x1FFC" size="4" access="ReadOnly" reset_value="0x00000004" reset_mask="0xFFFFFFFF">
+      <BitField name="PREAMBLE" description="Preamble bits 20 to 27" start="0" size="8" />
+    </Register>
+    <Register name="AXI_TARG1_FN_MOD_ISS_BM" description="AXI interconnect - TARG x bus matrix issuing functionality register" start="+0x2008" size="4" access="Read/Write" reset_value="0x00000004" reset_mask="0xFFFFFFFF">
+      <BitField name="READ_ISS_OVERRIDE" description="READ_ISS_OVERRIDE" start="0" size="1" />
+      <BitField name="WRITE_ISS_OVERRIDE" description="Switch matrix write issuing override for target" start="1" size="1" />
+    </Register>
+    <Register name="AXI_TARG2_FN_MOD_ISS_BM" description="AXI interconnect - TARG x bus matrix issuing functionality register" start="+0x3008" size="4" access="Read/Write" reset_value="0x00000004" reset_mask="0xFFFFFFFF">
+      <BitField name="READ_ISS_OVERRIDE" description="READ_ISS_OVERRIDE" start="0" size="1" />
+      <BitField name="WRITE_ISS_OVERRIDE" description="Switch matrix write issuing override for target" start="1" size="1" />
+    </Register>
+    <Register name="AXI_TARG3_FN_MOD_ISS_BM" description="AXI interconnect - TARG x bus matrix issuing functionality register" start="+0x4008" size="4" access="Read/Write" reset_value="0x00000004" reset_mask="0xFFFFFFFF">
+      <BitField name="READ_ISS_OVERRIDE" description="READ_ISS_OVERRIDE" start="0" size="1" />
+      <BitField name="WRITE_ISS_OVERRIDE" description="Switch matrix write issuing override for target" start="1" size="1" />
+    </Register>
+    <Register name="AXI_TARG4_FN_MOD_ISS_BM" description="AXI interconnect - TARG x bus matrix issuing functionality register" start="+0x5008" size="4" access="Read/Write" reset_value="0x00000004" reset_mask="0xFFFFFFFF">
+      <BitField name="READ_ISS_OVERRIDE" description="READ_ISS_OVERRIDE" start="0" size="1" />
+      <BitField name="WRITE_ISS_OVERRIDE" description="Switch matrix write issuing override for target" start="1" size="1" />
+    </Register>
+    <Register name="AXI_TARG5_FN_MOD_ISS_BM" description="AXI interconnect - TARG x bus matrix issuing functionality register" start="+0x6008" size="4" access="Read/Write" reset_value="0x00000004" reset_mask="0xFFFFFFFF">
+      <BitField name="READ_ISS_OVERRIDE" description="READ_ISS_OVERRIDE" start="0" size="1" />
+      <BitField name="WRITE_ISS_OVERRIDE" description="Switch matrix write issuing override for target" start="1" size="1" />
+    </Register>
+    <Register name="AXI_TARG6_FN_MOD_ISS_BM" description="AXI interconnect - TARG x bus matrix issuing functionality register" start="+0x7008" size="4" access="Read/Write" reset_value="0x00000004" reset_mask="0xFFFFFFFF">
+      <BitField name="READ_ISS_OVERRIDE" description="READ_ISS_OVERRIDE" start="0" size="1" />
+      <BitField name="WRITE_ISS_OVERRIDE" description="Switch matrix write issuing override for target" start="1" size="1" />
+    </Register>
+    <Register name="AXI_TARG7_FN_MOD_ISS_BM" description="AXI interconnect - TARG x bus matrix issuing functionality register" start="+0x800C" size="4" access="Read/Write" reset_value="0x00000004" reset_mask="0xFFFFFFFF">
+      <BitField name="READ_ISS_OVERRIDE" description="READ_ISS_OVERRIDE" start="0" size="1" />
+      <BitField name="WRITE_ISS_OVERRIDE" description="Switch matrix write issuing override for target" start="1" size="1" />
+    </Register>
+    <Register name="AXI_TARG1_FN_MOD2" description="AXI interconnect - TARG x bus matrix functionality 2 register" start="+0x2024" size="4" access="Read/Write" reset_value="0x00000004" reset_mask="0xFFFFFFFF">
+      <BitField name="BYPASS_MERGE" description="Disable packing of beats to match the output data width" start="0" size="1" />
+    </Register>
+    <Register name="AXI_TARG2_FN_MOD2" description="AXI interconnect - TARG x bus matrix functionality 2 register" start="+0x3024" size="4" access="Read/Write" reset_value="0x00000004" reset_mask="0xFFFFFFFF">
+      <BitField name="BYPASS_MERGE" description="Disable packing of beats to match the output data width" start="0" size="1" />
+    </Register>
+    <Register name="AXI_TARG7_FN_MOD2" description="AXI interconnect - TARG x bus matrix functionality 2 register" start="+0x8024" size="4" access="Read/Write" reset_value="0x00000004" reset_mask="0xFFFFFFFF">
+      <BitField name="BYPASS_MERGE" description="Disable packing of beats to match the output data width" start="0" size="1" />
+    </Register>
+    <Register name="AXI_TARG1_FN_MOD_LB" description="AXI interconnect - TARG x long burst functionality modification" start="+0x202C" size="4" access="Read/Write" reset_value="0x00000004" reset_mask="0xFFFFFFFF">
+      <BitField name="FN_MOD_LB" description="Controls burst breaking of long bursts" start="0" size="1" />
+    </Register>
+    <Register name="AXI_TARG2_FN_MOD_LB" description="AXI interconnect - TARG x long burst functionality modification" start="+0x302C" size="4" access="Read/Write" reset_value="0x00000004" reset_mask="0xFFFFFFFF">
+      <BitField name="FN_MOD_LB" description="Controls burst breaking of long bursts" start="0" size="1" />
+    </Register>
+    <Register name="AXI_TARG1_FN_MOD" description="AXI interconnect - TARG x long burst functionality modification" start="+0x2108" size="4" access="Read/Write" reset_value="0x00000004" reset_mask="0xFFFFFFFF">
+      <BitField name="READ_ISS_OVERRIDE" description="Override AMIB read issuing capability" start="0" size="1" />
+      <BitField name="WRITE_ISS_OVERRIDE" description="Override AMIB write issuing capability" start="1" size="1" />
+    </Register>
+    <Register name="AXI_TARG2_FN_MOD" description="AXI interconnect - TARG x long burst functionality modification" start="+0x3108" size="4" access="Read/Write" reset_value="0x00000004" reset_mask="0xFFFFFFFF">
+      <BitField name="READ_ISS_OVERRIDE" description="Override AMIB read issuing capability" start="0" size="1" />
+      <BitField name="WRITE_ISS_OVERRIDE" description="Override AMIB write issuing capability" start="1" size="1" />
+    </Register>
+    <Register name="AXI_TARG7_FN_MOD" description="AXI interconnect - TARG x long burst functionality modification" start="+0x8108" size="4" access="Read/Write" reset_value="0x00000004" reset_mask="0xFFFFFFFF">
+      <BitField name="READ_ISS_OVERRIDE" description="Override AMIB read issuing capability" start="0" size="1" />
+      <BitField name="WRITE_ISS_OVERRIDE" description="Override AMIB write issuing capability" start="1" size="1" />
+    </Register>
+    <Register name="AXI_INI1_FN_MOD2" description="AXI interconnect - INI x functionality modification 2 register" start="+0x42024" size="4" access="Read/Write" reset_value="0x00000004" reset_mask="0xFFFFFFFF">
+      <BitField name="BYPASS_MERGE" description="Disables alteration of transactions by the up-sizer unless required by the protocol" start="0" size="1" />
+    </Register>
+    <Register name="AXI_INI3_FN_MOD2" description="AXI interconnect - INI x functionality modification 2 register" start="+0x44024" size="4" access="Read/Write" reset_value="0x00000004" reset_mask="0xFFFFFFFF">
+      <BitField name="BYPASS_MERGE" description="Disables alteration of transactions by the up-sizer unless required by the protocol" start="0" size="1" />
+    </Register>
+    <Register name="AXI_INI1_FN_MOD_AHB" description="AXI interconnect - INI x AHB functionality modification register" start="+0x42028" size="4" access="Read/Write" reset_value="0x00000004" reset_mask="0xFFFFFFFF">
+      <BitField name="RD_INC_OVERRIDE" description="Converts all AHB-Lite write transactions to a series of single beat AXI" start="0" size="1" />
+      <BitField name="WR_INC_OVERRIDE" description="Converts all AHB-Lite read transactions to a series of single beat AXI" start="1" size="1" />
+    </Register>
+    <Register name="AXI_INI3_FN_MOD_AHB" description="AXI interconnect - INI x AHB functionality modification register" start="+0x44028" size="4" access="Read/Write" reset_value="0x00000004" reset_mask="0xFFFFFFFF">
+      <BitField name="RD_INC_OVERRIDE" description="Converts all AHB-Lite write transactions to a series of single beat AXI" start="0" size="1" />
+      <BitField name="WR_INC_OVERRIDE" description="Converts all AHB-Lite read transactions to a series of single beat AXI" start="1" size="1" />
+    </Register>
+    <Register name="AXI_INI1_READ_QOS" description="AXI interconnect - INI x read QoS register" start="+0x42100" size="4" access="Read/Write" reset_value="0x00000004" reset_mask="0xFFFFFFFF">
+      <BitField name="AR_QOS" description="Read channel QoS setting" start="0" size="4" />
+    </Register>
+    <Register name="AXI_INI2_READ_QOS" description="AXI interconnect - INI x read QoS register" start="+0x43100" size="4" access="Read/Write" reset_value="0x00000004" reset_mask="0xFFFFFFFF">
+      <BitField name="AR_QOS" description="Read channel QoS setting" start="0" size="4" />
+    </Register>
+    <Register name="AXI_INI3_READ_QOS" description="AXI interconnect - INI x read QoS register" start="+0x44100" size="4" access="Read/Write" reset_value="0x00000004" reset_mask="0xFFFFFFFF">
+      <BitField name="AR_QOS" description="Read channel QoS setting" start="0" size="4" />
+    </Register>
+    <Register name="AXI_INI4_READ_QOS" description="AXI interconnect - INI x read QoS register" start="+0x45100" size="4" access="Read/Write" reset_value="0x00000004" reset_mask="0xFFFFFFFF">
+      <BitField name="AR_QOS" description="Read channel QoS setting" start="0" size="4" />
+    </Register>
+    <Register name="AXI_INI5_READ_QOS" description="AXI interconnect - INI x read QoS register" start="+0x46100" size="4" access="Read/Write" reset_value="0x00000004" reset_mask="0xFFFFFFFF">
+      <BitField name="AR_QOS" description="Read channel QoS setting" start="0" size="4" />
+    </Register>
+    <Register name="AXI_INI6_READ_QOS" description="AXI interconnect - INI x read QoS register" start="+0x47100" size="4" access="Read/Write" reset_value="0x00000004" reset_mask="0xFFFFFFFF">
+      <BitField name="AR_QOS" description="Read channel QoS setting" start="0" size="4" />
+    </Register>
+    <Register name="AXI_INI1_WRITE_QOS" description="AXI interconnect - INI x write QoS register" start="+0x42104" size="4" access="Read/Write" reset_value="0x00000004" reset_mask="0xFFFFFFFF">
+      <BitField name="AW_QOS" description="Write channel QoS setting" start="0" size="4" />
+    </Register>
+    <Register name="AXI_INI2_WRITE_QOS" description="AXI interconnect - INI x write QoS register" start="+0x43104" size="4" access="Read/Write" reset_value="0x00000004" reset_mask="0xFFFFFFFF">
+      <BitField name="AW_QOS" description="Write channel QoS setting" start="0" size="4" />
+    </Register>
+    <Register name="AXI_INI3_WRITE_QOS" description="AXI interconnect - INI x write QoS register" start="+0x44104" size="4" access="Read/Write" reset_value="0x00000004" reset_mask="0xFFFFFFFF">
+      <BitField name="AW_QOS" description="Write channel QoS setting" start="0" size="4" />
+    </Register>
+    <Register name="AXI_INI4_WRITE_QOS" description="AXI interconnect - INI x write QoS register" start="+0x45104" size="4" access="Read/Write" reset_value="0x00000004" reset_mask="0xFFFFFFFF">
+      <BitField name="AW_QOS" description="Write channel QoS setting" start="0" size="4" />
+    </Register>
+    <Register name="AXI_INI5_WRITE_QOS" description="AXI interconnect - INI x write QoS register" start="+0x46104" size="4" access="Read/Write" reset_value="0x00000004" reset_mask="0xFFFFFFFF">
+      <BitField name="AW_QOS" description="Write channel QoS setting" start="0" size="4" />
+    </Register>
+    <Register name="AXI_INI6_WRITE_QOS" description="AXI interconnect - INI x write QoS register" start="+0x47104" size="4" access="Read/Write" reset_value="0x00000004" reset_mask="0xFFFFFFFF">
+      <BitField name="AW_QOS" description="Write channel QoS setting" start="0" size="4" />
+    </Register>
+    <Register name="AXI_INI1_FN_MOD" description="AXI interconnect - INI x issuing functionality modification register" start="+0x42108" size="4" access="Read/Write" reset_value="0x00000004" reset_mask="0xFFFFFFFF">
+      <BitField name="READ_ISS_OVERRIDE" description="Override ASIB read issuing capability" start="0" size="1" />
+      <BitField name="WRITE_ISS_OVERRIDE" description="Override ASIB write issuing capability" start="1" size="1" />
+    </Register>
+    <Register name="AXI_INI2_FN_MOD" description="AXI interconnect - INI x issuing functionality modification register" start="+0x43108" size="4" access="Read/Write" reset_value="0x00000004" reset_mask="0xFFFFFFFF">
+      <BitField name="READ_ISS_OVERRIDE" description="Override ASIB read issuing capability" start="0" size="1" />
+      <BitField name="WRITE_ISS_OVERRIDE" description="Override ASIB write issuing capability" start="1" size="1" />
+    </Register>
+    <Register name="AXI_INI3_FN_MOD" description="AXI interconnect - INI x issuing functionality modification register" start="+0x44108" size="4" access="Read/Write" reset_value="0x00000004" reset_mask="0xFFFFFFFF">
+      <BitField name="READ_ISS_OVERRIDE" description="Override ASIB read issuing capability" start="0" size="1" />
+      <BitField name="WRITE_ISS_OVERRIDE" description="Override ASIB write issuing capability" start="1" size="1" />
+    </Register>
+    <Register name="AXI_INI4_FN_MOD" description="AXI interconnect - INI x issuing functionality modification register" start="+0x45108" size="4" access="Read/Write" reset_value="0x00000004" reset_mask="0xFFFFFFFF">
+      <BitField name="READ_ISS_OVERRIDE" description="Override ASIB read issuing capability" start="0" size="1" />
+      <BitField name="WRITE_ISS_OVERRIDE" description="Override ASIB write issuing capability" start="1" size="1" />
+    </Register>
+    <Register name="AXI_INI5_FN_MOD" description="AXI interconnect - INI x issuing functionality modification register" start="+0x46108" size="4" access="Read/Write" reset_value="0x00000004" reset_mask="0xFFFFFFFF">
+      <BitField name="READ_ISS_OVERRIDE" description="Override ASIB read issuing capability" start="0" size="1" />
+      <BitField name="WRITE_ISS_OVERRIDE" description="Override ASIB write issuing capability" start="1" size="1" />
+    </Register>
+    <Register name="AXI_INI6_FN_MOD" description="AXI interconnect - INI x issuing functionality modification register" start="+0x47108" size="4" access="Read/Write" reset_value="0x00000004" reset_mask="0xFFFFFFFF">
+      <BitField name="READ_ISS_OVERRIDE" description="Override ASIB read issuing capability" start="0" size="1" />
+      <BitField name="WRITE_ISS_OVERRIDE" description="Override ASIB write issuing capability" start="1" size="1" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="CAN_CCU" description="CCU registers" start="0x4000A800">
+    <Register name="CREL" description="Clock Calibration Unit Core Release Register" start="+0x0" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DAY" description="Time Stamp Day" start="0" size="8" />
+      <BitField name="MON" description="Time Stamp Month" start="8" size="8" />
+      <BitField name="YEAR" description="Time Stamp Year" start="16" size="4" />
+      <BitField name="SUBSTEP" description="Sub-step of Core Release" start="20" size="4" />
+      <BitField name="STEP" description="Step of Core Release" start="24" size="4" />
+      <BitField name="REL" description="Core Release" start="28" size="4" />
+    </Register>
+    <Register name="CCFG" description="Calibration Configuration Register" start="+0x4" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TQBT" description="Time Quanta per Bit Time" start="0" size="5" />
+      <BitField name="BCC" description="Bypass Clock Calibration" start="6" size="1" />
+      <BitField name="CFL" description="Calibration Field Length" start="7" size="1" />
+      <BitField name="OCPM" description="Oscillator Clock Periods Minimum" start="8" size="8" />
+      <BitField name="CDIV" description="Clock Divider" start="16" size="4" />
+      <BitField name="SWR" description="Software Reset" start="31" size="1" />
+    </Register>
+    <Register name="CSTAT" description="Calibration Status Register" start="+0x8" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OCPC" description="Oscillator Clock Period Counter" start="0" size="18" />
+      <BitField name="TQC" description="Time Quanta Counter" start="18" size="11" />
+      <BitField name="CALS" description="Calibration State" start="30" size="2" />
+    </Register>
+    <Register name="CWD" description="Calibration Watchdog Register" start="+0xC" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="WDC" description="WDC" start="0" size="16" />
+      <BitField name="WDV" description="WDV" start="16" size="16" />
+    </Register>
+    <Register name="IR" description="Clock Calibration Unit Interrupt Register" start="+0x10" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CWE" description="Calibration Watchdog Event" start="0" size="1" />
+      <BitField name="CSC" description="Calibration State Changed" start="1" size="1" />
+    </Register>
+    <Register name="IE" description="Clock Calibration Unit Interrupt Enable Register" start="+0x14" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CWEE" description="Calibration Watchdog Event Enable" start="0" size="1" />
+      <BitField name="CSCE" description="Calibration State Changed Enable" start="1" size="1" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="CEC" description="CEC" start="0x40006C00">
+    <Register name="CR" description="CEC control register" start="+0x0" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CECEN" description="CEC Enable The CECEN bit is set and cleared by software. CECEN=1 starts message reception and enables the TXSOM control. CECEN=0 disables the CEC peripheral, clears all bits of CEC_CR register and aborts any on-going reception or transmission." start="0" size="1" />
+      <BitField name="TXSOM" description="Tx Start Of Message TXSOM is set by software to command transmission of the first byte of a CEC message. If the CEC message consists of only one byte, TXEOM must be set before of TXSOM. Start-Bit is effectively started on the CEC line after SFT is counted. If TXSOM is set while a message reception is ongoing, transmission will start after the end of reception. TXSOM is cleared by hardware after the last byte of the message is sent with a positive acknowledge (TXEND=1), in case of transmission underrun (TXUDR=1), negative acknowledge (TXACKE=1), and transmission error (TXERR=1). It is also cleared by CECEN=0. It is not cleared and transmission is automatically retried in case of arbitration lost (ARBLST=1). TXSOM can be also used as a status bit informing application whether any transmission request is pending or under execution. The application can abort a transmission request at any time by clearing the CECEN bit. Note: TXSOM must be set when CECEN=1 TXSOM must be set when transmission data is available into TXDR HEADERs first four bits containing own peripheral address are taken from TXDR[7:4], not from CEC_CFGR.OAR which is used only for reception" start="1" size="1" />
+      <BitField name="TXEOM" description="Tx End Of Message The TXEOM bit is set by software to command transmission of the last byte of a CEC message. TXEOM is cleared by hardware at the same time and under the same conditions as for TXSOM. Note: TXEOM must be set when CECEN=1 TXEOM must be set before writing transmission data to TXDR If TXEOM is set when TXSOM=0, transmitted message will consist of 1 byte (HEADER) only (PING message)" start="2" size="1" />
+    </Register>
+    <Register name="CFGR" description="This register is used to configure the HDMI-CEC controller. It is mandatory to write CEC_CFGR only when CECEN=0." start="+0x4" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SFT" description="Signal Free Time SFT bits are set by software. In the SFT=0x0 configuration the number of nominal data bit periods waited before transmission is ruled by hardware according to the transmission history. In all the other configurations the SFT number is determined by software. * 0x0 ** 2.5 Data-Bit periods if CEC is the last bus initiator with unsuccessful transmission (ARBLST=1, TXERR=1, TXUDR=1 or TXACKE= 1) ** 4 Data-Bit periods if CEC is the new bus initiator ** 6 Data-Bit periods if CEC is the last bus initiator with successful transmission (TXEOM=1) * 0x1: 0.5 nominal data bit periods * 0x2: 1.5 nominal data bit periods * 0x3: 2.5 nominal data bit periods * 0x4: 3.5 nominal data bit periods * 0x5: 4.5 nominal data bit periods * 0x6: 5.5 nominal data bit periods * 0x7: 6.5 nominal data bit periods" start="0" size="3" />
+      <BitField name="RXTOL" description="Rx-Tolerance The RXTOL bit is set and cleared by software. ** Start-Bit, +/- 200 s rise, +/- 200 s fall. ** Data-Bit: +/- 200 s rise. +/- 350 s fall. ** Start-Bit: +/- 400 s rise, +/- 400 s fall ** Data-Bit: +/-300 s rise, +/- 500 s fall" start="3" size="1" />
+      <BitField name="BRESTP" description="Rx-Stop on Bit Rising Error The BRESTP bit is set and cleared by software." start="4" size="1" />
+      <BitField name="BREGEN" description="Generate Error-Bit on Bit Rising Error The BREGEN bit is set and cleared by software. Note: If BRDNOGEN=0, an Error-bit is generated upon BRE detection with BRESTP=1 in broadcast even if BREGEN=0" start="5" size="1" />
+      <BitField name="LBPEGEN" description="Generate Error-Bit on Long Bit Period Error The LBPEGEN bit is set and cleared by software. Note: If BRDNOGEN=0, an Error-bit is generated upon LBPE detection in broadcast even if LBPEGEN=0" start="6" size="1" />
+      <BitField name="BRDNOGEN" description="Avoid Error-Bit Generation in Broadcast The BRDNOGEN bit is set and cleared by software." start="7" size="1" />
+      <BitField name="SFTOPT" description="SFT Option Bit The SFTOPT bit is set and cleared by software." start="8" size="1" />
+      <BitField name="OAR" description="Own addresses configuration The OAR bits are set by software to select which destination logical addresses has to be considered in receive mode. Each bit, when set, enables the CEC logical address identified by the given bit position. At the end of HEADER reception, the received destination address is compared with the enabled addresses. In case of matching address, the incoming message is acknowledged and received. In case of non-matching address, the incoming message is received only in listen mode (LSTN=1), but without acknowledge sent. Broadcast messages are always received. Example: OAR = 0b000 0000 0010 0001 means that CEC acknowledges addresses 0x0 and 0x5. Consequently, each message directed to one of these addresses is received." start="16" size="15" />
+      <BitField name="LSTN" description="Listen mode LSTN bit is set and cleared by software." start="31" size="1" />
+    </Register>
+    <Register name="TXDR" description="CEC Tx data register" start="+0x8" size="4" access="WriteOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TXD" description="Tx Data register. TXD is a write-only register containing the data byte to be transmitted. Note: TXD must be written when TXSTART=1" start="0" size="8" />
+    </Register>
+    <Register name="RXDR" description="CEC Rx Data Register" start="+0xC" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RXD" description="Rx Data register. RXD is read-only and contains the last data byte which has been received from the CEC line." start="0" size="8" />
+    </Register>
+    <Register name="ISR" description="CEC Interrupt and Status Register" start="+0x10" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RXBR" description="Rx-Byte Received The RXBR bit is set by hardware to inform application that a new byte has been received from the CEC line and stored into the RXD buffer. RXBR is cleared by software write at 1." start="0" size="1" />
+      <BitField name="RXEND" description="End Of Reception RXEND is set by hardware to inform application that the last byte of a CEC message is received from the CEC line and stored into the RXD buffer. RXEND is set at the same time of RXBR. RXEND is cleared by software write at 1." start="1" size="1" />
+      <BitField name="RXOVR" description="Rx-Overrun RXOVR is set by hardware if RXBR is not yet cleared at the time a new byte is received on the CEC line and stored into RXD. RXOVR assertion stops message reception so that no acknowledge is sent. In case of broadcast, a negative acknowledge is sent. RXOVR is cleared by software write at 1." start="2" size="1" />
+      <BitField name="BRE" description="Rx-Bit Rising Error BRE is set by hardware in case a Data-Bit waveform is detected with Bit Rising Error. BRE is set either at the time the misplaced rising edge occurs, or at the end of the maximum BRE tolerance allowed by RXTOL, in case rising edge is still longing. BRE stops message reception if BRESTP=1. BRE generates an Error-Bit on the CEC line if BREGEN=1. BRE is cleared by software write at 1." start="3" size="1" />
+      <BitField name="SBPE" description="Rx-Short Bit Period Error SBPE is set by hardware in case a Data-Bit waveform is detected with Short Bit Period Error. SBPE is set at the time the anticipated falling edge occurs. SBPE generates an Error-Bit on the CEC line. SBPE is cleared by software write at 1." start="4" size="1" />
+      <BitField name="LBPE" description="Rx-Long Bit Period Error LBPE is set by hardware in case a Data-Bit waveform is detected with Long Bit Period Error. LBPE is set at the end of the maximum bit-extension tolerance allowed by RXTOL, in case falling edge is still longing. LBPE always stops reception of the CEC message. LBPE generates an Error-Bit on the CEC line if LBPEGEN=1. In case of broadcast, Error-Bit is generated even in case of LBPEGEN=0. LBPE is cleared by software write at 1." start="5" size="1" />
+      <BitField name="RXACKE" description="Rx-Missing Acknowledge In receive mode, RXACKE is set by hardware to inform application that no acknowledge was seen on the CEC line. RXACKE applies only for broadcast messages and in listen mode also for not directly addressed messages (destination address not enabled in OAR). RXACKE aborts message reception. RXACKE is cleared by software write at 1." start="6" size="1" />
+      <BitField name="ARBLST" description="Arbitration Lost ARBLST is set by hardware to inform application that CEC device is switching to reception due to arbitration lost event following the TXSOM command. ARBLST can be due either to a contending CEC device starting earlier or starting at the same time but with higher HEADER priority. After ARBLST assertion TXSOM bit keeps pending for next transmission attempt. ARBLST is cleared by software write at 1." start="7" size="1" />
+      <BitField name="TXBR" description="Tx-Byte Request TXBR is set by hardware to inform application that the next transmission data has to be written to TXDR. TXBR is set when the 4th bit of currently transmitted byte is sent. Application must write the next byte to TXDR within 6 nominal data-bit periods before transmission underrun error occurs (TXUDR). TXBR is cleared by software write at 1." start="8" size="1" />
+      <BitField name="TXEND" description="End of Transmission TXEND is set by hardware to inform application that the last byte of the CEC message has been successfully transmitted. TXEND clears the TXSOM and TXEOM control bits. TXEND is cleared by software write at 1." start="9" size="1" />
+      <BitField name="TXUDR" description="Tx-Buffer Underrun In transmission mode, TXUDR is set by hardware if application was not in time to load TXDR before of next byte transmission. TXUDR aborts message transmission and clears TXSOM and TXEOM control bits. TXUDR is cleared by software write at 1" start="10" size="1" />
+      <BitField name="TXERR" description="Tx-Error In transmission mode, TXERR is set by hardware if the CEC initiator detects low impedance on the CEC line while it is released. TXERR aborts message transmission and clears TXSOM and TXEOM controls. TXERR is cleared by software write at 1." start="11" size="1" />
+      <BitField name="TXACKE" description="Tx-Missing Acknowledge Error In transmission mode, TXACKE is set by hardware to inform application that no acknowledge was received. In case of broadcast transmission, TXACKE informs application that a negative acknowledge was received. TXACKE aborts message transmission and clears TXSOM and TXEOM controls. TXACKE is cleared by software write at 1." start="12" size="1" />
+    </Register>
+    <Register name="IER" description="CEC interrupt enable register" start="+0x14" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RXBRIE" description="Rx-Byte Received Interrupt Enable The RXBRIE bit is set and cleared by software." start="0" size="1" />
+      <BitField name="RXENDIE" description="End Of Reception Interrupt Enable The RXENDIE bit is set and cleared by software." start="1" size="1" />
+      <BitField name="RXOVRIE" description="Rx-Buffer Overrun Interrupt Enable The RXOVRIE bit is set and cleared by software." start="2" size="1" />
+      <BitField name="BREIE" description="Bit Rising Error Interrupt Enable The BREIE bit is set and cleared by software." start="3" size="1" />
+      <BitField name="SBPEIE" description="Short Bit Period Error Interrupt Enable The SBPEIE bit is set and cleared by software." start="4" size="1" />
+      <BitField name="LBPEIE" description="Long Bit Period Error Interrupt Enable The LBPEIE bit is set and cleared by software." start="5" size="1" />
+      <BitField name="RXACKIE" description="Rx-Missing Acknowledge Error Interrupt Enable The RXACKIE bit is set and cleared by software." start="6" size="1" />
+      <BitField name="ARBLSTIE" description="Arbitration Lost Interrupt Enable The ARBLSTIE bit is set and cleared by software." start="7" size="1" />
+      <BitField name="TXBRIE" description="Tx-Byte Request Interrupt Enable The TXBRIE bit is set and cleared by software." start="8" size="1" />
+      <BitField name="TXENDIE" description="Tx-End Of Message Interrupt Enable The TXENDIE bit is set and cleared by software." start="9" size="1" />
+      <BitField name="TXUDRIE" description="Tx-Underrun Interrupt Enable The TXUDRIE bit is set and cleared by software." start="10" size="1" />
+      <BitField name="TXERRIE" description="Tx-Error Interrupt Enable The TXERRIE bit is set and cleared by software." start="11" size="1" />
+      <BitField name="TXACKIE" description="Tx-Missing Acknowledge Error Interrupt Enable The TXACKEIE bit is set and cleared by software." start="12" size="1" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="COMP1" description="COMP1" start="0x58003800">
+    <Register name="SR" description="Comparator status register" start="+0x0" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="C1VAL" description="COMP channel 1 output status bit" start="0" size="1" />
+      <BitField name="C2VAL" description="COMP channel 2 output status bit" start="1" size="1" />
+      <BitField name="C1IF" description="COMP channel 1 Interrupt Flag" start="16" size="1" />
+      <BitField name="C2IF" description="COMP channel 2 Interrupt Flag" start="17" size="1" />
+    </Register>
+    <Register name="ICFR" description="Comparator interrupt clear flag register" start="+0x4" size="4" access="WriteOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CC1IF" description="Clear COMP channel 1 Interrupt Flag" start="16" size="1" />
+      <BitField name="CC2IF" description="Clear COMP channel 2 Interrupt Flag" start="17" size="1" />
+    </Register>
+    <Register name="OR" description="Comparator option register" start="+0x8" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AFOP" description="Selection of source for alternate function of output ports" start="0" size="11" />
+      <BitField name="OR" description="Option Register" start="11" size="21" />
+    </Register>
+    <Register name="CFGR1" description="Comparator configuration register 1" start="+0xC" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="COMP channel 1 enable bit" start="0" size="1" />
+      <BitField name="BRGEN" description="Scaler bridge enable" start="1" size="1" />
+      <BitField name="SCALEN" description="Voltage scaler enable bit" start="2" size="1" />
+      <BitField name="POLARITY" description="COMP channel 1 polarity selection bit" start="3" size="1" />
+      <BitField name="ITEN" description="COMP channel 1 interrupt enable" start="6" size="1" />
+      <BitField name="HYST" description="COMP channel 1 hysteresis selection bits" start="8" size="2" />
+      <BitField name="PWRMODE" description="Power Mode of the COMP channel 1" start="12" size="2" />
+      <BitField name="INMSEL" description="COMP channel 1 inverting input selection field" start="16" size="3" />
+      <BitField name="INPSEL" description="COMP channel 1 non-inverting input selection bit" start="20" size="1" />
+      <BitField name="BLANKING" description="COMP channel 1 blanking source selection bits" start="24" size="4" />
+      <BitField name="LOCK" description="Lock bit" start="31" size="1" />
+    </Register>
+    <Register name="CFGR2" description="Comparator configuration register 2" start="+0x10" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="COMP channel 1 enable bit" start="0" size="1" />
+      <BitField name="BRGEN" description="Scaler bridge enable" start="1" size="1" />
+      <BitField name="SCALEN" description="Voltage scaler enable bit" start="2" size="1" />
+      <BitField name="POLARITY" description="COMP channel 1 polarity selection bit" start="3" size="1" />
+      <BitField name="WINMODE" description="Window comparator mode selection bit" start="4" size="1" />
+      <BitField name="ITEN" description="COMP channel 1 interrupt enable" start="6" size="1" />
+      <BitField name="HYST" description="COMP channel 1 hysteresis selection bits" start="8" size="2" />
+      <BitField name="PWRMODE" description="Power Mode of the COMP channel 1" start="12" size="2" />
+      <BitField name="INMSEL" description="COMP channel 1 inverting input selection field" start="16" size="3" />
+      <BitField name="INPSEL" description="COMP channel 1 non-inverting input selection bit" start="20" size="1" />
+      <BitField name="BLANKING" description="COMP channel 1 blanking source selection bits" start="24" size="4" />
+      <BitField name="LOCK" description="Lock bit" start="31" size="1" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="CORDIC" description="CORDIC register block" start="0x48024400">
+    <Register name="CORDIC_CSR" description="CORDIC control/status register " start="+0x0" size="4" reset_value="0x00000050" reset_mask="0xFFFFFFFF">
+      <BitField name="FUNC" description="Function" start="0" size="4" access="Read/Write">
+        <Enum name="B_0x0" description="Cosine" start="0x0" />
+        <Enum name="B_0x1" description="Sine" start="0x1" />
+      </BitField>
+      <BitField name="PRECISION" description="Precision required (number of iterations) To determine the number of iterations needed for a given accuracy refer to . Note that for most functions, the recommended range for this field is 3 to 6." start="4" size="4" access="Read/Write">
+        <Enum name="B_0x1" description="(Number of iterations)/4" start="0x1" />
+        <Enum name="B_0x2" description="(Number of iterations)/4" start="0x2" />
+        <Enum name="B_0x3" description="(Number of iterations)/4" start="0x3" />
+        <Enum name="B_0x4" description="(Number of iterations)/4" start="0x4" />
+        <Enum name="B_0x5" description="(Number of iterations)/4" start="0x5" />
+        <Enum name="B_0x6" description="(Number of iterations)/4" start="0x6" />
+        <Enum name="B_0x7" description="(Number of iterations)/4" start="0x7" />
+        <Enum name="B_0x8" description="(Number of iterations)/4" start="0x8" />
+        <Enum name="B_0x9" description="(Number of iterations)/4" start="0x9" />
+        <Enum name="B_0xa" description="(Number of iterations)/4" start="0xA" />
+        <Enum name="B_0xb" description="(Number of iterations)/4" start="0xB" />
+        <Enum name="B_0xc" description="(Number of iterations)/4" start="0xC" />
+        <Enum name="B_0xd" description="(Number of iterations)/4" start="0xD" />
+        <Enum name="B_0xe" description="(Number of iterations)/4" start="0xE" />
+        <Enum name="B_0xf" description="(Number of iterations)/4" start="0xF" />
+      </BitField>
+      <BitField name="SCALE" description="Scaling factor The value of this field indicates the scaling factor applied to the arguments and/or results. A value n implies that the arguments have been multiplied by a factor 2-n, and/or the results need to be multiplied by 2n. Refer to for the applicability of the scaling factor for each function and the appropriate range." start="8" size="3" access="Read/Write" />
+      <BitField name="IEN" description="Enable interrupt. This bit is set and cleared by software. A read returns the current state of the bit." start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Disabled. No interrupt requests are generated." start="0x0" />
+        <Enum name="B_0x1" description="Enabled. An interrupt request is generated whenever the RRDY flag is set." start="0x1" />
+      </BitField>
+      <BitField name="DMAREN" description="Enable DMA read channel This bit is set and cleared by software. A read returns the current state of the bit." start="17" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Disabled. No DMA read requests are generated." start="0x0" />
+        <Enum name="B_0x1" description="Enabled. Requests are generated on the DMA read channel whenever the RRDY flag is set." start="0x1" />
+      </BitField>
+      <BitField name="DMAWEN" description="Enable DMA write channel This bit is set and cleared by software. A read returns the current state of the bit." start="18" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Disabled. No DMA write requests are generated." start="0x0" />
+        <Enum name="B_0x1" description="Enabled. Requests are generated on the DMA write channel whenever no operation is pending" start="0x1" />
+      </BitField>
+      <BitField name="NRES" description="Number of results in the CORDIC_RDATA register Reads return the current state of the bit." start="19" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Only one 32-bit value (or two 16-bit values if RESSIZE = 1) is transferred to the CORDIC_RDATA register on completion of the next calculation. One read from CORDIC_RDATA resets the RRDY flag." start="0x0" />
+        <Enum name="B_0x1" description="Two 32-bit values are transferred to the CORDIC_RDATA register on completion of the next calculation. Two reads from CORDIC_RDATA are necessary to reset the RRDY flag." start="0x1" />
+      </BitField>
+      <BitField name="NARGS" description="Number of arguments expected by the CORDIC_WDATA register Reads return the current state of the bit." start="20" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Only one 32-bit write (or two 16-bit values if ARGSIZE = 1) is needed for the next calculation." start="0x0" />
+        <Enum name="B_0x1" description="Two 32-bit values must be written to the CORDIC_WDATA register to trigger the next calculation." start="0x1" />
+      </BitField>
+      <BitField name="RESSIZE" description="Width of output data RESSIZE selects the number of bits used to represent output data. If 32-bit data is selected, the CORDIC_RDATA register contains results in q1.31 format. If 16-bit data is selected, the least significant half-word of CORDIC_RDATA contains the primary result (RES1) in q1.15 format, and the most significant half-word contains the secondary result (RES2), also in q1.15 format." start="21" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="32-bit" start="0x0" />
+        <Enum name="B_0x1" description="16-bit" start="0x1" />
+      </BitField>
+      <BitField name="ARGSIZE" description="Width of input data ARGSIZE selects the number of bits used to represent input data. If 32-bit data is selected, the CORDIC_WDATA register expects arguments in q1.31 format. If 16-bit data is selected, the CORDIC_WDATA register expects arguments in q1.15 format. The primary argument (ARG1) is written to the least significant half-word, and the secondary argument (ARG2) to the most significant half-word." start="22" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="32-bit" start="0x0" />
+        <Enum name="B_0x1" description="16-bit" start="0x1" />
+      </BitField>
+      <BitField name="RRDY" description="Result ready flag This bit is set by hardware when a CORDIC operation completes. It is reset by hardware when the CORDIC_RDATA register is read (NRES+1) times. When this bit is set, if the IEN bit is also set, the CORDIC interrupt is asserted. If the DMAREN bit is set, a DMA read channel request is generated. While this bit is set, no new calculation is started." start="31" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No new result in output register" start="0x0" />
+        <Enum name="B_0x1" description="CORDIC_RDATA register contains new data." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="CORDIC_WDATA" description="CORDIC argument register " start="+0x4" size="4" reset_value="0x00000000" reset_mask="0x00000000">
+      <BitField name="ARG" description="Function input arguments This register is programmed with the input arguments for the function selected in the CORDIC_CSR register FUNC field. If 32-bit format is selected (CORDIC_CSR.ARGSIZE = 0) and two input arguments are required (CORDIC_CSR.NARGS = 1), two successive writes are required to this register. The first writes the primary argument (ARG1), the second writes the secondary argument (ARG2). If 32-bit format is selected and only one input argument is required (NARGS = 0), only one write is required to this register, containing the primary argument (ARG1). If 16-bit format is selected (CORDIC_CSR.ARGSIZE = 1), one write to this register contains both arguments. The primary argument (ARG1) is in the lower half, ARG[15:0], and the secondary argument (ARG2) is in the upper half, ARG[31:16]. In this case, NARGS must be set to 0. Refer to for the arguments required by each function, and their permitted range. When the required number of arguments has been written, the CORDIC evaluates the function designated by CORDIC_CSR.FUNC using the supplied input arguments, provided any previous calculation has completed. If a calculation is ongoing, the ARG1 and ARG 2 values are held pending until the calculation is completed and the results read. During this time, a write to the register cancels the pending operation and overwrite the argument data." start="0" size="32" access="WriteOnly" />
+    </Register>
+    <Register name="CORDIC_RDATA" description="CORDIC result register " start="+0x8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RES" description="Function result If 32-bit format is selected (CORDIC_CSR.RESSIZE = 0) and two output values are expected (CORDIC_CSR.NRES = 1), this register must be read twice when the RRDY flag is set. The first read fetches the primary result (RES1). The second read fetches the secondary result (RES2) and resets RRDY. If 32-bit format is selected and only one output value is expected (NRES = 0), only one read of this register is required to fetch the primary result (RES1) and reset the RRDY flag. If 16-bit format is selected (CORDIC_CSR.RESSIZE = 1), this register contains the primary result (RES1) in the lower half, RES[15:0], and the secondary result (RES2) in the upper half, RES[31:16]. In this case, NRES must be set to 0, and only one read performed. A read from this register resets the RRDY flag in the CORDIC_CSR register." start="0" size="32" access="ReadOnly" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="CRC" description="Cryptographic processor" start="0x58024C00">
+    <Register name="DR" description="Data register" start="+0x0" size="4" access="Read/Write" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="DR" description="Data Register" start="0" size="32" />
+    </Register>
+    <Register name="IDR" description="Independent Data register" start="+0x4" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IDR" description="Independent Data register" start="0" size="32" />
+    </Register>
+    <Register name="CR" description="Control register" start="+0x8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RESET" description="RESET bit" start="0" size="1" access="WriteOnly" />
+      <BitField name="POLYSIZE" description="Polynomial size" start="3" size="2" access="Read/Write" />
+      <BitField name="REV_IN" description="Reverse input data" start="5" size="2" access="Read/Write" />
+      <BitField name="REV_OUT" description="Reverse output data" start="7" size="1" access="Read/Write" />
+    </Register>
+    <Register name="INIT" description="Initial CRC value" start="+0x10" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CRC_INIT" description="Programmable initial CRC value" start="0" size="32" />
+    </Register>
+    <Register name="POL" description="CRC polynomial" start="+0x14" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="POL" description="Programmable polynomial" start="0" size="32" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="CRS" description="Clock Recovery System" start="0x40008400">
+    <Register name="CR" description="CRS control register" start="+0x0" size="4" reset_value="0x00002000" reset_mask="0xFFFFFFFF">
+      <BitField name="SYNCOKIE" description="SYNC event OK interrupt enable" start="0" size="1" access="Read/Write" />
+      <BitField name="SYNCWARNIE" description="SYNC warning interrupt enable" start="1" size="1" access="Read/Write" />
+      <BitField name="ERRIE" description="Synchronization or trimming error interrupt enable" start="2" size="1" access="Read/Write" />
+      <BitField name="ESYNCIE" description="Expected SYNC interrupt enable" start="3" size="1" access="Read/Write" />
+      <BitField name="CEN" description="Frequency error counter enable This bit enables the oscillator clock for the frequency error counter. When this bit is set, the CRS_CFGR register is write-protected and cannot be modified." start="5" size="1" access="Read/Write" />
+      <BitField name="AUTOTRIMEN" description="Automatic trimming enable This bit enables the automatic hardware adjustment of TRIM bits according to the measured frequency error between two SYNC events. If this bit is set, the TRIM bits are read-only. The TRIM value can be adjusted by hardware by one or two steps at a time, depending on the measured frequency error value. Refer to Section7.3.4: Frequency error evaluation and automatic trimming for more details." start="6" size="1" access="Read/Write" />
+      <BitField name="SWSYNC" description="Generate software SYNC event This bit is set by software in order to generate a software SYNC event. It is automatically cleared by hardware." start="7" size="1" access="ReadOnly" />
+      <BitField name="TRIM" description="HSI48 oscillator smooth trimming These bits provide a user-programmable trimming value to the HSI48 oscillator. They can be programmed to adjust to variations in voltage and temperature that influence the frequency of the HSI48. The default value is 32, which corresponds to the middle of the trimming interval. The trimming step is around 67 kHz between two consecutive TRIM steps. A higher TRIM value corresponds to a higher output frequency. When the AUTOTRIMEN bit is set, this field is controlled by hardware and is read-only." start="8" size="6" access="Read/Write" />
+    </Register>
+    <Register name="CFGR" description="This register can be written only when the frequency error counter is disabled (CEN bit is cleared in CRS_CR). When the counter is enabled, this register is write-protected." start="+0x4" size="4" access="Read/Write" reset_value="0x2022BB7F" reset_mask="0xFFFFFFFF">
+      <BitField name="RELOAD" description="Counter reload value RELOAD is the value to be loaded in the frequency error counter with each SYNC event. Refer to Section7.3.3: Frequency error measurement for more details about counter behavior." start="0" size="16" />
+      <BitField name="FELIM" description="Frequency error limit FELIM contains the value to be used to evaluate the captured frequency error value latched in the FECAP[15:0] bits of the CRS_ISR register. Refer to Section7.3.4: Frequency error evaluation and automatic trimming for more details about FECAP evaluation." start="16" size="8" />
+      <BitField name="SYNCDIV" description="SYNC divider These bits are set and cleared by software to control the division factor of the SYNC signal." start="24" size="3" />
+      <BitField name="SYNCSRC" description="SYNC signal source selection These bits are set and cleared by software to select the SYNC signal source. Note: When using USB LPM (Link Power Management) and the device is in Sleep mode, the periodic USB SOF will not be generated by the host. No SYNC signal will therefore be provided to the CRS to calibrate the HSI48 on the run. To guarantee the required clock precision after waking up from Sleep mode, the LSE or reference clock on the GPIOs should be used as SYNC signal." start="28" size="2" />
+      <BitField name="SYNCPOL" description="SYNC polarity selection This bit is set and cleared by software to select the input polarity for the SYNC signal source." start="31" size="1" />
+    </Register>
+    <Register name="ISR" description="CRS interrupt and status register" start="+0x8" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SYNCOKF" description="SYNC event OK flag This flag is set by hardware when the measured frequency error is smaller than FELIM * 3. This means that either no adjustment of the TRIM value is needed or that an adjustment by one trimming step is enough to compensate the frequency error. An interrupt is generated if the SYNCOKIE bit is set in the CRS_CR register. It is cleared by software by setting the SYNCOKC bit in the CRS_ICR register." start="0" size="1" />
+      <BitField name="SYNCWARNF" description="SYNC warning flag This flag is set by hardware when the measured frequency error is greater than or equal to FELIM * 3, but smaller than FELIM * 128. This means that to compensate the frequency error, the TRIM value must be adjusted by two steps or more. An interrupt is generated if the SYNCWARNIE bit is set in the CRS_CR register. It is cleared by software by setting the SYNCWARNC bit in the CRS_ICR register." start="1" size="1" />
+      <BitField name="ERRF" description="Error flag This flag is set by hardware in case of any synchronization or trimming error. It is the logical OR of the TRIMOVF, SYNCMISS and SYNCERR bits. An interrupt is generated if the ERRIE bit is set in the CRS_CR register. It is cleared by software in reaction to setting the ERRC bit in the CRS_ICR register, which clears the TRIMOVF, SYNCMISS and SYNCERR bits." start="2" size="1" />
+      <BitField name="ESYNCF" description="Expected SYNC flag This flag is set by hardware when the frequency error counter reached a zero value. An interrupt is generated if the ESYNCIE bit is set in the CRS_CR register. It is cleared by software by setting the ESYNCC bit in the CRS_ICR register." start="3" size="1" />
+      <BitField name="SYNCERR" description="SYNC error This flag is set by hardware when the SYNC pulse arrives before the ESYNC event and the measured frequency error is greater than or equal to FELIM * 128. This means that the frequency error is too big (internal frequency too low) to be compensated by adjusting the TRIM value, and that some other action should be taken. An interrupt is generated if the ERRIE bit is set in the CRS_CR register. It is cleared by software by setting the ERRC bit in the CRS_ICR register." start="8" size="1" />
+      <BitField name="SYNCMISS" description="SYNC missed This flag is set by hardware when the frequency error counter reached value FELIM * 128 and no SYNC was detected, meaning either that a SYNC pulse was missed or that the frequency error is too big (internal frequency too high) to be compensated by adjusting the TRIM value, and that some other action should be taken. At this point, the frequency error counter is stopped (waiting for a next SYNC) and an interrupt is generated if the ERRIE bit is set in the CRS_CR register. It is cleared by software by setting the ERRC bit in the CRS_ICR register." start="9" size="1" />
+      <BitField name="TRIMOVF" description="Trimming overflow or underflow This flag is set by hardware when the automatic trimming tries to over- or under-flow the TRIM value. An interrupt is generated if the ERRIE bit is set in the CRS_CR register. It is cleared by software by setting the ERRC bit in the CRS_ICR register." start="10" size="1" />
+      <BitField name="FEDIR" description="Frequency error direction FEDIR is the counting direction of the frequency error counter latched in the time of the last SYNC event. It shows whether the actual frequency is below or above the target." start="15" size="1" />
+      <BitField name="FECAP" description="Frequency error capture FECAP is the frequency error counter value latched in the time of the last SYNC event. Refer to Section7.3.4: Frequency error evaluation and automatic trimming for more details about FECAP usage." start="16" size="16" />
+    </Register>
+    <Register name="ICR" description="CRS interrupt flag clear register" start="+0xC" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SYNCOKC" description="SYNC event OK clear flag Writing 1 to this bit clears the SYNCOKF flag in the CRS_ISR register." start="0" size="1" />
+      <BitField name="SYNCWARNC" description="SYNC warning clear flag Writing 1 to this bit clears the SYNCWARNF flag in the CRS_ISR register." start="1" size="1" />
+      <BitField name="ERRC" description="Error clear flag Writing 1 to this bit clears TRIMOVF, SYNCMISS and SYNCERR bits and consequently also the ERRF flag in the CRS_ISR register." start="2" size="1" />
+      <BitField name="ESYNCC" description="Expected SYNC clear flag Writing 1 to this bit clears the ESYNCF flag in the CRS_ISR register." start="3" size="1" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="DAC" description="DAC" start="0x40007400">
+    <Register name="CR" description="DAC control register" start="+0x0" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN1" description="DAC channel1 enable This bit is set and cleared by software to enable/disable DAC channel1." start="0" size="1" />
+      <BitField name="TEN1" description="DAC channel1 trigger enable" start="1" size="1" />
+      <BitField name="TSEL1" description="DAC channel1 trigger selection These bits select the external event used to trigger DAC channel1. Note: Only used if bit TEN1 = 1 (DAC channel1 trigger enabled)." start="2" size="3" />
+      <BitField name="WAVE1" description="DAC channel1 noise/triangle wave generation enable These bits are set and cleared by software. Note: Only used if bit TEN1 = 1 (DAC channel1 trigger enabled)." start="6" size="2" />
+      <BitField name="MAMP1" description="DAC channel1 mask/amplitude selector These bits are written by software to select mask in wave generation mode or amplitude in triangle generation mode. = 1011: Unmask bits[11:0] of LFSR/ triangle amplitude equal to 4095" start="8" size="4" />
+      <BitField name="DMAEN1" description="DAC channel1 DMA enable This bit is set and cleared by software." start="12" size="1" />
+      <BitField name="DMAUDRIE1" description="DAC channel1 DMA Underrun Interrupt enable This bit is set and cleared by software." start="13" size="1" />
+      <BitField name="CEN1" description="DAC Channel 1 calibration enable This bit is set and cleared by software to enable/disable DAC channel 1 calibration, it can be written only if bit EN1=0 into DAC_CR (the calibration mode can be entered/exit only when the DAC channel is disabled) Otherwise, the write operation is ignored." start="14" size="1" />
+      <BitField name="EN2" description="DAC channel2 enable This bit is set and cleared by software to enable/disable DAC channel2." start="16" size="1" />
+      <BitField name="TEN2" description="DAC channel2 trigger enable" start="17" size="1" />
+      <BitField name="TSEL2" description="DAC channel2 trigger selection These bits select the external event used to trigger DAC channel2 Note: Only used if bit TEN2 = 1 (DAC channel2 trigger enabled)." start="18" size="3" />
+      <BitField name="WAVE2" description="DAC channel2 noise/triangle wave generation enable These bits are set/reset by software. 1x: Triangle wave generation enabled Note: Only used if bit TEN2 = 1 (DAC channel2 trigger enabled)" start="22" size="2" />
+      <BitField name="MAMP2" description="DAC channel2 mask/amplitude selector These bits are written by software to select mask in wave generation mode or amplitude in triangle generation mode. = 1011: Unmask bits[11:0] of LFSR/ triangle amplitude equal to 4095" start="24" size="4" />
+      <BitField name="DMAEN2" description="DAC channel2 DMA enable This bit is set and cleared by software." start="28" size="1" />
+      <BitField name="DMAUDRIE2" description="DAC channel2 DMA underrun interrupt enable This bit is set and cleared by software." start="29" size="1" />
+      <BitField name="CEN2" description="DAC Channel 2 calibration enable This bit is set and cleared by software to enable/disable DAC channel 2 calibration, it can be written only if bit EN2=0 into DAC_CR (the calibration mode can be entered/exit only when the DAC channel is disabled) Otherwise, the write operation is ignored." start="30" size="1" />
+    </Register>
+    <Register name="SWTRGR" description="DAC software trigger register" start="+0x4" size="4" access="WriteOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWTRIG1" description="DAC channel1 software trigger This bit is set by software to trigger the DAC in software trigger mode. Note: This bit is cleared by hardware (one APB1 clock cycle later) once the DAC_DHR1 register value has been loaded into the DAC_DOR1 register." start="0" size="1" />
+      <BitField name="SWTRIG2" description="DAC channel2 software trigger This bit is set by software to trigger the DAC in software trigger mode. Note: This bit is cleared by hardware (one APB1 clock cycle later) once the DAC_DHR2 register value has been loaded into the DAC_DOR2 register." start="1" size="1" />
+    </Register>
+    <Register name="DHR12R1" description="DAC channel1 12-bit right-aligned data holding register" start="+0x8" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DACC1DHR" description="DAC channel1 12-bit right-aligned data These bits are written by software which specifies 12-bit data for DAC channel1." start="0" size="12" />
+    </Register>
+    <Register name="DHR12L1" description="DAC channel1 12-bit left aligned data holding register" start="+0xC" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DACC1DHR" description="DAC channel1 12-bit left-aligned data These bits are written by software which specifies 12-bit data for DAC channel1." start="4" size="12" />
+    </Register>
+    <Register name="DHR8R1" description="DAC channel1 8-bit right aligned data holding register" start="+0x10" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DACC1DHR" description="DAC channel1 8-bit right-aligned data These bits are written by software which specifies 8-bit data for DAC channel1." start="0" size="8" />
+    </Register>
+    <Register name="DHR12R2" description="DAC channel2 12-bit right aligned data holding register" start="+0x14" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DACC2DHR" description="DAC channel2 12-bit right-aligned data These bits are written by software which specifies 12-bit data for DAC channel2." start="0" size="12" />
+    </Register>
+    <Register name="DHR12L2" description="DAC channel2 12-bit left aligned data holding register" start="+0x18" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DACC2DHR" description="DAC channel2 12-bit left-aligned data These bits are written by software which specify 12-bit data for DAC channel2." start="4" size="12" />
+    </Register>
+    <Register name="DHR8R2" description="DAC channel2 8-bit right-aligned data holding register" start="+0x1C" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DACC2DHR" description="DAC channel2 8-bit right-aligned data These bits are written by software which specifies 8-bit data for DAC channel2." start="0" size="8" />
+    </Register>
+    <Register name="DHR12RD" description="Dual DAC 12-bit right-aligned data holding register" start="+0x20" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DACC1DHR" description="DAC channel1 12-bit right-aligned data These bits are written by software which specifies 12-bit data for DAC channel1." start="0" size="12" />
+      <BitField name="DACC2DHR" description="DAC channel2 12-bit right-aligned data These bits are written by software which specifies 12-bit data for DAC channel2." start="16" size="12" />
+    </Register>
+    <Register name="DHR12LD" description="DUAL DAC 12-bit left aligned data holding register" start="+0x24" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DACC1DHR" description="DAC channel1 12-bit left-aligned data These bits are written by software which specifies 12-bit data for DAC channel1." start="4" size="12" />
+      <BitField name="DACC2DHR" description="DAC channel2 12-bit left-aligned data These bits are written by software which specifies 12-bit data for DAC channel2." start="20" size="12" />
+    </Register>
+    <Register name="DHR8RD" description="DUAL DAC 8-bit right aligned data holding register" start="+0x28" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DACC1DHR" description="DAC channel1 8-bit right-aligned data These bits are written by software which specifies 8-bit data for DAC channel1." start="0" size="8" />
+      <BitField name="DACC2DHR" description="DAC channel2 8-bit right-aligned data These bits are written by software which specifies 8-bit data for DAC channel2." start="8" size="8" />
+    </Register>
+    <Register name="DOR1" description="DAC channel1 data output register" start="+0x2C" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DACC1DOR" description="DAC channel1 data output These bits are read-only, they contain data output for DAC channel1." start="0" size="12" />
+    </Register>
+    <Register name="DOR2" description="DAC channel2 data output register" start="+0x30" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DACC2DOR" description="DAC channel2 data output These bits are read-only, they contain data output for DAC channel2." start="0" size="12" />
+    </Register>
+    <Register name="SR" description="DAC status register" start="+0x34" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAUDR1" description="DAC channel1 DMA underrun flag This bit is set by hardware and cleared by software (by writing it to 1)." start="13" size="1" access="Read/Write" />
+      <BitField name="CAL_FLAG1" description="DAC Channel 1 calibration offset status This bit is set and cleared by hardware" start="14" size="1" access="ReadOnly" />
+      <BitField name="BWST1" description="DAC Channel 1 busy writing sample time flag This bit is systematically set just after Sample &amp; Hold mode enable and is set each time the software writes the register DAC_SHSR1, It is cleared by hardware when the write operation of DAC_SHSR1 is complete. (It takes about 3LSI periods of synchronization)." start="15" size="1" access="ReadOnly" />
+      <BitField name="DMAUDR2" description="DAC channel2 DMA underrun flag This bit is set by hardware and cleared by software (by writing it to 1)." start="29" size="1" access="Read/Write" />
+      <BitField name="CAL_FLAG2" description="DAC Channel 2 calibration offset status This bit is set and cleared by hardware" start="30" size="1" access="ReadOnly" />
+      <BitField name="BWST2" description="DAC Channel 2 busy writing sample time flag This bit is systematically set just after Sample &amp; Hold mode enable and is set each time the software writes the register DAC_SHSR2, It is cleared by hardware when the write operation of DAC_SHSR2 is complete. (It takes about 3 LSI periods of synchronization)." start="31" size="1" access="ReadOnly" />
+    </Register>
+    <Register name="CCR" description="DAC calibration control register" start="+0x38" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OTRIM1" description="DAC Channel 1 offset trimming value" start="0" size="5" />
+      <BitField name="OTRIM2" description="DAC Channel 2 offset trimming value" start="16" size="5" />
+    </Register>
+    <Register name="MCR" description="DAC mode control register" start="+0x3C" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MODE1" description="DAC Channel 1 mode These bits can be written only when the DAC is disabled and not in the calibration mode (when bit EN1=0 and bit CEN1 =0 in the DAC_CR register). If EN1=1 or CEN1 =1 the write operation is ignored. They can be set and cleared by software to select the DAC Channel 1 mode: DAC Channel 1 in normal Mode DAC Channel 1 in sample &amp;amp; hold mode" start="0" size="3" />
+      <BitField name="MODE2" description="DAC Channel 2 mode These bits can be written only when the DAC is disabled and not in the calibration mode (when bit EN2=0 and bit CEN2 =0 in the DAC_CR register). If EN2=1 or CEN2 =1 the write operation is ignored. They can be set and cleared by software to select the DAC Channel 2 mode: DAC Channel 2 in normal Mode DAC Channel 2 in sample &amp;amp; hold mode" start="16" size="3" />
+    </Register>
+    <Register name="SHSR1" description="DAC Sample and Hold sample time register 1" start="+0x40" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TSAMPLE1" description="DAC Channel 1 sample Time (only valid in sample &amp;amp; hold mode) These bits can be written when the DAC channel1 is disabled or also during normal operation. in the latter case, the write can be done only when BWSTx of DAC_SR register is low, If BWSTx=1, the write operation is ignored." start="0" size="10" />
+    </Register>
+    <Register name="SHSR2" description="DAC Sample and Hold sample time register 2" start="+0x44" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TSAMPLE2" description="DAC Channel 2 sample Time (only valid in sample &amp;amp; hold mode) These bits can be written when the DAC channel2 is disabled or also during normal operation. in the latter case, the write can be done only when BWSTx of DAC_SR register is low, if BWSTx=1, the write operation is ignored." start="0" size="10" />
+    </Register>
+    <Register name="SHHR" description="DAC Sample and Hold hold time register" start="+0x48" size="4" access="Read/Write" reset_value="0x00010001" reset_mask="0xFFFFFFFF">
+      <BitField name="THOLD1" description="DAC Channel 1 hold Time (only valid in sample &amp;amp; hold mode) Hold time= (THOLD[9:0]) x T LSI" start="0" size="10" />
+      <BitField name="THOLD2" description="DAC Channel 2 hold time (only valid in sample &amp;amp; hold mode). Hold time= (THOLD[9:0]) x T LSI" start="16" size="10" />
+    </Register>
+    <Register name="SHRR" description="DAC Sample and Hold refresh time register" start="+0x4C" size="4" access="Read/Write" reset_value="0x00010001" reset_mask="0xFFFFFFFF">
+      <BitField name="TREFRESH1" description="DAC Channel 1 refresh Time (only valid in sample &amp;amp; hold mode) Refresh time= (TREFRESH[7:0]) x T LSI" start="0" size="8" />
+      <BitField name="TREFRESH2" description="DAC Channel 2 refresh Time (only valid in sample &amp;amp; hold mode) Refresh time= (TREFRESH[7:0]) x T LSI" start="16" size="8" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="DBGMCU" description="Microcontroller Debug Unit" start="0x5C001000">
+    <Register name="IDC" description="DBGMCU Identity Code Register" start="+0x0" size="4" access="ReadOnly" reset_value="0x10006450" reset_mask="0xFFFFFFFF">
+      <BitField name="DEV_ID" description="Device ID" start="0" size="12" />
+      <BitField name="REV_ID" description="Revision" start="16" size="16" />
+    </Register>
+    <Register name="CR" description="DBGMCU Configuration Register" start="+0x4" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DBGSLPD1" description=" Allow D1 domain debug in Sleep mode" start="0" size="1" />
+      <BitField name="DBGSTPD1" description="Allow D1 domain debug in Stop mode" start="1" size="1" />
+      <BitField name="DBGSTBD1" description="Allow D1 domain debug in Standby mode" start="2" size="1" />
+      <BitField name="DBGSLPD2" description=" Allow D2 domain debug in Sleep mode" start="3" size="1" />
+      <BitField name="DBGSTPD2" description="Allow D2 domain debug in Stop mode" start="4" size="1" />
+      <BitField name="DBGSTBD2" description=" Allow D2 domain debug in Standby mode" start="5" size="1" />
+      <BitField name="DBGSTPD3" description="Allow debug in D3 Stop mode" start="7" size="1" />
+      <BitField name="DBGSTBD3" description="Allow debug in D3 Standby mode" start="8" size="1" />
+      <BitField name="TRACECLKEN" description="Trace port clock enable" start="20" size="1" />
+      <BitField name="D1DBGCKEN" description=" D1 debug clock enable" start="21" size="1" />
+      <BitField name="D3DBGCKEN" description="D3 debug clock enable" start="22" size="1" />
+      <BitField name="TRGOEN" description="External trigger output enable" start="28" size="1" />
+    </Register>
+    <Register name="APB3FZ1" description="DBGMCU APB3 peripheral freeze register CPU1" start="+0x34" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="WWDG1" description="WWDG1 stop in debug" start="6" size="1" />
+    </Register>
+    <Register name="APB3FZ2" description="DBGMCU APB3 peripheral freeze register CPU2" start="+0x38" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="WWDG1" description="WWDG1 stop in debug" start="6" size="1" />
+    </Register>
+    <Register name="APB1LFZ1" description="DBGMCU APB1L peripheral freeze register" start="+0x3C" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DBG_TIM2" description="TIM2 stop in debug" start="0" size="1" />
+      <BitField name="DBG_TIM3" description="TIM3 stop in debug" start="1" size="1" />
+      <BitField name="DBG_TIM4" description="TIM4 stop in debug" start="2" size="1" />
+      <BitField name="DBG_TIM5" description="TIM5 stop in debug" start="3" size="1" />
+      <BitField name="DBG_TIM6" description="TIM6 stop in debug" start="4" size="1" />
+      <BitField name="DBG_TIM7" description="TIM7 stop in debug" start="5" size="1" />
+      <BitField name="DBG_TIM12" description="TIM12 stop in debug" start="6" size="1" />
+      <BitField name="DBG_TIM13" description="TIM13 stop in debug" start="7" size="1" />
+      <BitField name="DBG_TIM14" description="TIM14 stop in debug" start="8" size="1" />
+      <BitField name="DBG_LPTIM1" description=" LPTIM1 stop in debug" start="9" size="1" />
+      <BitField name="DBG_WWDG2" description="WWDG2 stop in debug" start="11" size="1" />
+      <BitField name="DBG_I2C1" description=" I2C1 SMBUS timeout stop in debug " start="21" size="1" />
+      <BitField name="DBG_I2C2" description=" I2C2 SMBUS timeout stop in debug" start="22" size="1" />
+      <BitField name="DBG_I2C3" description=" I2C3 SMBUS timeout stop in debug" start="23" size="1" />
+    </Register>
+    <Register name="APB1LFZ2" description="DBGMCU APB1L peripheral freeze register CPU2" start="+0x40" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DBG_TIM2" description="TIM2 stop in debug" start="0" size="1" />
+      <BitField name="DBG_TIM3" description="TIM3 stop in debug" start="1" size="1" />
+      <BitField name="DBG_TIM4" description="TIM4 stop in debug" start="2" size="1" />
+      <BitField name="DBG_TIM5" description="TIM5 stop in debug" start="3" size="1" />
+      <BitField name="DBG_TIM6" description="TIM6 stop in debug" start="4" size="1" />
+      <BitField name="DBG_TIM7" description="TIM4 stop in debug" start="5" size="1" />
+      <BitField name="DBG_TIM12" description="TIM12 stop in debug" start="6" size="1" />
+      <BitField name="DBG_TIM13" description="TIM13 stop in debug" start="7" size="1" />
+      <BitField name="DBG_TIM14" description=" TIM14 stop in debug" start="8" size="1" />
+      <BitField name="DBG_LPTIM1" description="LPTIM1 stop in debug" start="9" size="1" />
+      <BitField name="DBG_WWDG2" description="WWDG2 stop in debug" start="11" size="1" />
+      <BitField name="DBG_I2C1" description="I2C1 SMBUS timeout stop in debug" start="21" size="1" />
+      <BitField name="DBG_I2C2" description=" I2C2 SMBUS timeout stop in debug" start="22" size="1" />
+      <BitField name="DBG_I2C3" description=" I2C3 SMBUS timeout stop in debug" start="23" size="1" />
+    </Register>
+    <Register name="APB2FZ1" description="DBGMCU APB2 peripheral freeze register" start="+0x4C" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DBG_TIM1" description=" TIM1 stop in debug" start="0" size="1" />
+      <BitField name="DBG_TIM8" description=" TIM8 stop in debug" start="1" size="1" />
+      <BitField name="DBG_TIM15" description="TIM15 stop in debug" start="16" size="1" />
+      <BitField name="DBG_TIM16" description="TIM16 stop in debug" start="17" size="1" />
+      <BitField name="DBG_TIM17" description=" TIM17 stop in debug" start="18" size="1" />
+    </Register>
+    <Register name="APB2FZ2" description="DBGMCU APB2 peripheral freeze register CPU2" start="+0x50" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DBG_TIM1" description="TIM1 stop in debug" start="0" size="1" />
+      <BitField name="DBG_TIM8" description="TIM8 stop in debug" start="1" size="1" />
+      <BitField name="DBG_TIM15" description="TIM15 stop in debug" start="16" size="1" />
+      <BitField name="DBG_TIM16" description=" TIM16 stop in debug" start="17" size="1" />
+      <BitField name="DBG_TIM17" description="TIM17 stop in debug" start="18" size="1" />
+    </Register>
+    <Register name="APB4FZ1" description="DBGMCU APB4 peripheral freeze register" start="+0x54" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DBG_I2C4" description="I2C4 SMBUS timeout stop in debug" start="7" size="1" />
+      <BitField name="DBG_LPTIM2" description=" LPTIM2 stop in debug" start="9" size="1" />
+      <BitField name="DBG_LPTIM3" description=" LPTIM2 stop in debug" start="10" size="1" />
+      <BitField name="DBG_LPTIM4" description="LPTIM4 stop in debug" start="11" size="1" />
+      <BitField name="DBG_LPTIM5" description="LPTIM5 stop in debug" start="12" size="1" />
+      <BitField name="DBG_RTC" description="RTC stop in debug" start="16" size="1" />
+      <BitField name="DBG_WDGLSD1" description="Independent watchdog for D1 stop in debug" start="18" size="1" />
+      <BitField name="DBG_WDGLSD2" description=" Independent watchdog for D2 stop in debug" start="19" size="1" />
+    </Register>
+    <Register name="APB4FZ2" description="DBGMCU APB4 peripheral freeze register CPU2" start="+0x58" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DBG_I2C4" description="I2C4 SMBUS timeout stop in debug" start="7" size="1" />
+      <BitField name="DBG_LPTIM2" description=" LPTIM2 stop in debug" start="9" size="1" />
+      <BitField name="DBG_LPTIM3" description=" LPTIM2 stop in debug" start="10" size="1" />
+      <BitField name="DBG_LPTIM4" description=" LPTIM4 stop in debug" start="11" size="1" />
+      <BitField name="DBG_LPTIM5" description="LPTIM5 stop in debug" start="12" size="1" />
+      <BitField name="DBG_RTC" description=" RTC stop in debug" start="16" size="1" />
+      <BitField name="DBG_WDGLSD1" description="LS watchdog for D1 stop in debug" start="18" size="1" />
+      <BitField name="DBG_WDGLSD2" description=" LS watchdog for D2 stop in debug" start="19" size="1" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="DCMI" description="Digital camera interface" start="0x48020000">
+    <Register name="CR" description="control register 1" start="+0x0" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="OELS" description="Odd/Even Line Select (Line Select Start)" start="20" size="1" />
+      <BitField name="LSM" description="Line Select mode" start="19" size="1" />
+      <BitField name="OEBS" description="Odd/Even Byte Select (Byte Select Start)" start="18" size="1" />
+      <BitField name="BSM" description="Byte Select mode" start="16" size="2" />
+      <BitField name="ENABLE" description="DCMI enable" start="14" size="1" />
+      <BitField name="EDM" description="Extended data mode" start="10" size="2" />
+      <BitField name="FCRC" description="Frame capture rate control" start="8" size="2" />
+      <BitField name="VSPOL" description="Vertical synchronization polarity" start="7" size="1" />
+      <BitField name="HSPOL" description="Horizontal synchronization polarity" start="6" size="1" />
+      <BitField name="PCKPOL" description="Pixel clock polarity" start="5" size="1" />
+      <BitField name="ESS" description="Embedded synchronization select" start="4" size="1" />
+      <BitField name="JPEG" description="JPEG format" start="3" size="1" />
+      <BitField name="CROP" description="Crop feature" start="2" size="1" />
+      <BitField name="CM" description="Capture mode" start="1" size="1" />
+      <BitField name="CAPTURE" description="Capture enable" start="0" size="1" />
+    </Register>
+    <Register name="SR" description="status register" start="+0x4" size="4" access="ReadOnly" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="FNE" description="FIFO not empty" start="2" size="1" />
+      <BitField name="VSYNC" description="VSYNC" start="1" size="1" />
+      <BitField name="HSYNC" description="HSYNC" start="0" size="1" />
+    </Register>
+    <Register name="RIS" description="raw interrupt status register" start="+0x8" size="4" access="ReadOnly" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="LINE_RIS" description="Line raw interrupt status" start="4" size="1" />
+      <BitField name="VSYNC_RIS" description="VSYNC raw interrupt status" start="3" size="1" />
+      <BitField name="ERR_RIS" description="Synchronization error raw interrupt status" start="2" size="1" />
+      <BitField name="OVR_RIS" description="Overrun raw interrupt status" start="1" size="1" />
+      <BitField name="FRAME_RIS" description="Capture complete raw interrupt status" start="0" size="1" />
+    </Register>
+    <Register name="IER" description="interrupt enable register" start="+0xC" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="LINE_IE" description="Line interrupt enable" start="4" size="1" />
+      <BitField name="VSYNC_IE" description="VSYNC interrupt enable" start="3" size="1" />
+      <BitField name="ERR_IE" description="Synchronization error interrupt enable" start="2" size="1" />
+      <BitField name="OVR_IE" description="Overrun interrupt enable" start="1" size="1" />
+      <BitField name="FRAME_IE" description="Capture complete interrupt enable" start="0" size="1" />
+    </Register>
+    <Register name="MIS" description="masked interrupt status register" start="+0x10" size="4" access="ReadOnly" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="LINE_MIS" description="Line masked interrupt status" start="4" size="1" />
+      <BitField name="VSYNC_MIS" description="VSYNC masked interrupt status" start="3" size="1" />
+      <BitField name="ERR_MIS" description="Synchronization error masked interrupt status" start="2" size="1" />
+      <BitField name="OVR_MIS" description="Overrun masked interrupt status" start="1" size="1" />
+      <BitField name="FRAME_MIS" description="Capture complete masked interrupt status" start="0" size="1" />
+    </Register>
+    <Register name="ICR" description="interrupt clear register" start="+0x14" size="4" access="WriteOnly" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="LINE_ISC" description="line interrupt status clear" start="4" size="1" />
+      <BitField name="VSYNC_ISC" description="Vertical synch interrupt status clear" start="3" size="1" />
+      <BitField name="ERR_ISC" description="Synchronization error interrupt status clear" start="2" size="1" />
+      <BitField name="OVR_ISC" description="Overrun interrupt status clear" start="1" size="1" />
+      <BitField name="FRAME_ISC" description="Capture complete interrupt status clear" start="0" size="1" />
+    </Register>
+    <Register name="ESCR" description="embedded synchronization code register" start="+0x18" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="FEC" description="Frame end delimiter code" start="24" size="8" />
+      <BitField name="LEC" description="Line end delimiter code" start="16" size="8" />
+      <BitField name="LSC" description="Line start delimiter code" start="8" size="8" />
+      <BitField name="FSC" description="Frame start delimiter code" start="0" size="8" />
+    </Register>
+    <Register name="ESUR" description="embedded synchronization unmask register" start="+0x1C" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="FEU" description="Frame end delimiter unmask" start="24" size="8" />
+      <BitField name="LEU" description="Line end delimiter unmask" start="16" size="8" />
+      <BitField name="LSU" description="Line start delimiter unmask" start="8" size="8" />
+      <BitField name="FSU" description="Frame start delimiter unmask" start="0" size="8" />
+    </Register>
+    <Register name="CWSTRT" description="crop window start" start="+0x20" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="VST" description="Vertical start line count" start="16" size="13" />
+      <BitField name="HOFFCNT" description="Horizontal offset count" start="0" size="14" />
+    </Register>
+    <Register name="CWSIZE" description="crop window size" start="+0x24" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="VLINE" description="Vertical line count" start="16" size="14" />
+      <BitField name="CAPCNT" description="Capture count" start="0" size="14" />
+    </Register>
+    <Register name="DR" description="data register" start="+0x28" size="4" access="ReadOnly" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="Byte3" description="Data byte 3" start="24" size="8" />
+      <BitField name="Byte2" description="Data byte 2" start="16" size="8" />
+      <BitField name="Byte1" description="Data byte 1" start="8" size="8" />
+      <BitField name="Byte0" description="Data byte 0" start="0" size="8" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="DELAY_Block_SDMMC1" description="DELAY_Block_SDMMC1" start="0x52008000">
+    <Register name="CR" description="DLYB control register" start="+0x0" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DEN" description="Delay block enable bit" start="0" size="1" />
+      <BitField name="SEN" description="Sampler length enable bit" start="1" size="1" />
+    </Register>
+    <Register name="CFGR" description="DLYB configuration register" start="+0x4" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SEL" description="Select the phase for the Output clock" start="0" size="4" />
+      <BitField name="UNIT" description="Delay Defines the delay of a Unit delay cell" start="8" size="7" />
+      <BitField name="LNG" description="Delay line length value" start="16" size="12" />
+      <BitField name="LNGF" description="Length valid flag" start="31" size="1" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="DELAY_Block_SDMMC2" description="DELAY_Block_SDMMC1" start="0x48022800">
+    <Register name="CR" description="DLYB control register" start="+0x0" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DEN" description="Delay block enable bit" start="0" size="1" />
+      <BitField name="SEN" description="Sampler length enable bit" start="1" size="1" />
+    </Register>
+    <Register name="CFGR" description="DLYB configuration register" start="+0x4" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SEL" description="Select the phase for the Output clock" start="0" size="4" />
+      <BitField name="UNIT" description="Delay Defines the delay of a Unit delay cell" start="8" size="7" />
+      <BitField name="LNG" description="Delay line length value" start="16" size="12" />
+      <BitField name="LNGF" description="Length valid flag" start="31" size="1" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="DFSDM" description="Digital filter for sigma delta modulators" start="0x40017800">
+    <Register name="CH0CFGR1" description="channel configuration y register" start="+0x0" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="DFSDMEN" description="DFSDMEN" start="31" size="1" />
+      <BitField name="CKOUTSRC" description="CKOUTSRC" start="30" size="1" />
+      <BitField name="CKOUTDIV" description="CKOUTDIV" start="16" size="8" />
+      <BitField name="DATPACK" description="DATPACK" start="14" size="2" />
+      <BitField name="DATMPX" description="DATMPX" start="12" size="2" />
+      <BitField name="CHINSEL" description="CHINSEL" start="8" size="1" />
+      <BitField name="CHEN" description="CHEN" start="7" size="1" />
+      <BitField name="CKABEN" description="CKABEN" start="6" size="1" />
+      <BitField name="SCDEN" description="SCDEN" start="5" size="1" />
+      <BitField name="SPICKSEL" description="SPICKSEL" start="2" size="2" />
+      <BitField name="SITP" description="SITP" start="0" size="2" />
+    </Register>
+    <Register name="CH0CFGR2" description="channel configuration y register" start="+0x4" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="OFFSET" description="OFFSET" start="8" size="24" />
+      <BitField name="DTRBS" description="DTRBS" start="3" size="5" />
+    </Register>
+    <Register name="CH0AWSCDR" description="analog watchdog and short-circuit detector register" start="+0x8" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="AWFORD" description="AWFORD" start="22" size="2" />
+      <BitField name="AWFOSR" description="AWFOSR" start="16" size="5" />
+      <BitField name="BKSCD" description="BKSCD" start="12" size="4" />
+      <BitField name="SCDT" description="SCDT" start="0" size="8" />
+    </Register>
+    <Register name="CH0WDATR" description="channel watchdog filter data register" start="+0xC" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="WDATA" description="WDATA" start="0" size="16" />
+    </Register>
+    <Register name="CH0DATINR" description="channel data input register" start="+0x10" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="INDAT1" description="INDAT1" start="16" size="16" />
+      <BitField name="INDAT0" description="INDAT0" start="0" size="16" />
+    </Register>
+    <Register name="CH0DLYR" description="channel y delay register" start="+0x14" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="PLSSKP" description="PLSSKP" start="0" size="6" />
+    </Register>
+    <Register name="CH1CFGR1" description="CH1CFGR1" start="+0x20" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="DATPACK" description="DATPACK" start="14" size="2" />
+      <BitField name="DATMPX" description="DATMPX" start="12" size="2" />
+      <BitField name="CHINSEL" description="CHINSEL" start="8" size="1" />
+      <BitField name="CHEN" description="CHEN" start="7" size="1" />
+      <BitField name="CKABEN" description="CKABEN" start="6" size="1" />
+      <BitField name="SCDEN" description="SCDEN" start="5" size="1" />
+      <BitField name="SPICKSEL" description="SPICKSEL" start="2" size="2" />
+      <BitField name="SITP" description="SITP" start="0" size="2" />
+    </Register>
+    <Register name="CH1CFGR2" description="CH1CFGR2" start="+0x24" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="OFFSET" description="OFFSET" start="8" size="24" />
+      <BitField name="DTRBS" description="DTRBS" start="3" size="5" />
+    </Register>
+    <Register name="CH1AWSCDR" description="CH1AWSCDR" start="+0x28" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="AWFORD" description="AWFORD" start="22" size="2" />
+      <BitField name="AWFOSR" description="AWFOSR" start="16" size="5" />
+      <BitField name="BKSCD" description="BKSCD" start="12" size="4" />
+      <BitField name="SCDT" description="SCDT" start="0" size="8" />
+    </Register>
+    <Register name="CH1WDATR" description="CH1WDATR" start="+0x2C" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="WDATA" description="WDATA" start="0" size="16" />
+    </Register>
+    <Register name="CH1DATINR" description="CH1DATINR" start="+0x30" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="INDAT1" description="INDAT1" start="16" size="16" />
+      <BitField name="INDAT0" description="INDAT0" start="0" size="16" />
+    </Register>
+    <Register name="CH1DLYR" description="channel y delay register" start="+0x34" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="PLSSKP" description="PLSSKP" start="0" size="6" />
+    </Register>
+    <Register name="CH2CFGR1" description="CH2CFGR1" start="+0x40" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="DATPACK" description="DATPACK" start="14" size="2" />
+      <BitField name="DATMPX" description="DATMPX" start="12" size="2" />
+      <BitField name="CHINSEL" description="CHINSEL" start="8" size="1" />
+      <BitField name="CHEN" description="CHEN" start="7" size="1" />
+      <BitField name="CKABEN" description="CKABEN" start="6" size="1" />
+      <BitField name="SCDEN" description="SCDEN" start="5" size="1" />
+      <BitField name="SPICKSEL" description="SPICKSEL" start="2" size="2" />
+      <BitField name="SITP" description="SITP" start="0" size="2" />
+    </Register>
+    <Register name="CH2CFGR2" description="CH2CFGR2" start="+0x44" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="OFFSET" description="OFFSET" start="8" size="24" />
+      <BitField name="DTRBS" description="DTRBS" start="3" size="5" />
+    </Register>
+    <Register name="CH2AWSCDR" description="CH2AWSCDR" start="+0x48" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="AWFORD" description="AWFORD" start="22" size="2" />
+      <BitField name="AWFOSR" description="AWFOSR" start="16" size="5" />
+      <BitField name="BKSCD" description="BKSCD" start="12" size="4" />
+      <BitField name="SCDT" description="SCDT" start="0" size="8" />
+    </Register>
+    <Register name="CH2WDATR" description="CH2WDATR" start="+0x4C" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="WDATA" description="WDATA" start="0" size="16" />
+    </Register>
+    <Register name="CH2DATINR" description="CH2DATINR" start="+0x50" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="INDAT1" description="INDAT1" start="16" size="16" />
+      <BitField name="INDAT0" description="INDAT0" start="0" size="16" />
+    </Register>
+    <Register name="CH2DLYR" description="channel y delay register" start="+0x54" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="PLSSKP" description="PLSSKP" start="0" size="6" />
+    </Register>
+    <Register name="CH3CFGR1" description="CH3CFGR1" start="+0x60" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="DATPACK" description="DATPACK" start="14" size="2" />
+      <BitField name="DATMPX" description="DATMPX" start="12" size="2" />
+      <BitField name="CHINSEL" description="CHINSEL" start="8" size="1" />
+      <BitField name="CHEN" description="CHEN" start="7" size="1" />
+      <BitField name="CKABEN" description="CKABEN" start="6" size="1" />
+      <BitField name="SCDEN" description="SCDEN" start="5" size="1" />
+      <BitField name="SPICKSEL" description="SPICKSEL" start="2" size="2" />
+      <BitField name="SITP" description="SITP" start="0" size="2" />
+    </Register>
+    <Register name="CH3CFGR2" description="CH3CFGR2" start="+0x64" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="OFFSET" description="OFFSET" start="8" size="24" />
+      <BitField name="DTRBS" description="DTRBS" start="3" size="5" />
+    </Register>
+    <Register name="CH3AWSCDR" description="CH3AWSCDR" start="+0x68" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="AWFORD" description="AWFORD" start="22" size="2" />
+      <BitField name="AWFOSR" description="AWFOSR" start="16" size="5" />
+      <BitField name="BKSCD" description="BKSCD" start="12" size="4" />
+      <BitField name="SCDT" description="SCDT" start="0" size="8" />
+    </Register>
+    <Register name="CH3WDATR" description="CH3WDATR" start="+0x6C" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="WDATA" description="WDATA" start="0" size="16" />
+    </Register>
+    <Register name="CH3DATINR" description="CH3DATINR" start="+0x70" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="INDAT1" description="INDAT1" start="16" size="16" />
+      <BitField name="INDAT0" description="INDAT0" start="0" size="16" />
+    </Register>
+    <Register name="CH3DLYR" description="channel y delay register" start="+0x74" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="PLSSKP" description="PLSSKP" start="0" size="6" />
+    </Register>
+    <Register name="CH4CFGR1" description="CH4CFGR1" start="+0x80" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="DATPACK" description="DATPACK" start="14" size="2" />
+      <BitField name="DATMPX" description="DATMPX" start="12" size="2" />
+      <BitField name="CHINSEL" description="CHINSEL" start="8" size="1" />
+      <BitField name="CHEN" description="CHEN" start="7" size="1" />
+      <BitField name="CKABEN" description="CKABEN" start="6" size="1" />
+      <BitField name="SCDEN" description="SCDEN" start="5" size="1" />
+      <BitField name="SPICKSEL" description="SPICKSEL" start="2" size="2" />
+      <BitField name="SITP" description="SITP" start="0" size="2" />
+    </Register>
+    <Register name="CH4CFGR2" description="CH4CFGR2" start="+0x84" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="OFFSET" description="OFFSET" start="8" size="24" />
+      <BitField name="DTRBS" description="DTRBS" start="3" size="5" />
+    </Register>
+    <Register name="CH4AWSCDR" description="CH4AWSCDR" start="+0x88" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="AWFORD" description="AWFORD" start="22" size="2" />
+      <BitField name="AWFOSR" description="AWFOSR" start="16" size="5" />
+      <BitField name="BKSCD" description="BKSCD" start="12" size="4" />
+      <BitField name="SCDT" description="SCDT" start="0" size="8" />
+    </Register>
+    <Register name="CH4WDATR" description="CH4WDATR" start="+0x8C" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="WDATA" description="WDATA" start="0" size="16" />
+    </Register>
+    <Register name="CH4DATINR" description="CH4DATINR" start="+0x90" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="INDAT1" description="INDAT1" start="16" size="16" />
+      <BitField name="INDAT0" description="INDAT0" start="0" size="16" />
+    </Register>
+    <Register name="CH4DLYR" description="channel y delay register" start="+0x94" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="PLSSKP" description="PLSSKP" start="0" size="6" />
+    </Register>
+    <Register name="CH5CFGR1" description="CH5CFGR1" start="+0xA0" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="DATPACK" description="DATPACK" start="14" size="2" />
+      <BitField name="DATMPX" description="DATMPX" start="12" size="2" />
+      <BitField name="CHINSEL" description="CHINSEL" start="8" size="1" />
+      <BitField name="CHEN" description="CHEN" start="7" size="1" />
+      <BitField name="CKABEN" description="CKABEN" start="6" size="1" />
+      <BitField name="SCDEN" description="SCDEN" start="5" size="1" />
+      <BitField name="SPICKSEL" description="SPICKSEL" start="2" size="2" />
+      <BitField name="SITP" description="SITP" start="0" size="2" />
+    </Register>
+    <Register name="CH5CFGR2" description="CH5CFGR2" start="+0xA4" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="OFFSET" description="OFFSET" start="8" size="24" />
+      <BitField name="DTRBS" description="DTRBS" start="3" size="5" />
+    </Register>
+    <Register name="CH5AWSCDR" description="CH5AWSCDR" start="+0xA8" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="AWFORD" description="AWFORD" start="22" size="2" />
+      <BitField name="AWFOSR" description="AWFOSR" start="16" size="5" />
+      <BitField name="BKSCD" description="BKSCD" start="12" size="4" />
+      <BitField name="SCDT" description="SCDT" start="0" size="8" />
+    </Register>
+    <Register name="CH5WDATR" description="CH5WDATR" start="+0xAC" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="WDATA" description="WDATA" start="0" size="16" />
+    </Register>
+    <Register name="CH5DATINR" description="CH5DATINR" start="+0xB0" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="INDAT1" description="INDAT1" start="16" size="16" />
+      <BitField name="INDAT0" description="INDAT0" start="0" size="16" />
+    </Register>
+    <Register name="CH5DLYR" description="channel y delay register" start="+0xB4" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="PLSSKP" description="PLSSKP" start="0" size="6" />
+    </Register>
+    <Register name="CH6CFGR1" description="CH6CFGR1" start="+0xC0" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="DATPACK" description="DATPACK" start="14" size="2" />
+      <BitField name="DATMPX" description="DATMPX" start="12" size="2" />
+      <BitField name="CHINSEL" description="CHINSEL" start="8" size="1" />
+      <BitField name="CHEN" description="CHEN" start="7" size="1" />
+      <BitField name="CKABEN" description="CKABEN" start="6" size="1" />
+      <BitField name="SCDEN" description="SCDEN" start="5" size="1" />
+      <BitField name="SPICKSEL" description="SPICKSEL" start="2" size="2" />
+      <BitField name="SITP" description="SITP" start="0" size="2" />
+    </Register>
+    <Register name="CH6CFGR2" description="CH6CFGR2" start="+0xC4" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="OFFSET" description="OFFSET" start="8" size="24" />
+      <BitField name="DTRBS" description="DTRBS" start="3" size="5" />
+    </Register>
+    <Register name="CH6AWSCDR" description="CH6AWSCDR" start="+0xC8" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="AWFORD" description="AWFORD" start="22" size="2" />
+      <BitField name="AWFOSR" description="AWFOSR" start="16" size="5" />
+      <BitField name="BKSCD" description="BKSCD" start="12" size="4" />
+      <BitField name="SCDT" description="SCDT" start="0" size="8" />
+    </Register>
+    <Register name="CH6WDATR" description="CH6WDATR" start="+0xCC" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="WDATA" description="WDATA" start="0" size="16" />
+    </Register>
+    <Register name="CH6DATINR" description="CH6DATINR" start="+0xD0" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="INDAT1" description="INDAT1" start="16" size="16" />
+      <BitField name="INDAT0" description="INDAT0" start="0" size="16" />
+    </Register>
+    <Register name="CH6DLYR" description="channel y delay register" start="+0xD4" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="PLSSKP" description="PLSSKP" start="0" size="6" />
+    </Register>
+    <Register name="CH7CFGR1" description="CH7CFGR1" start="+0xE0" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="DATPACK" description="DATPACK" start="14" size="2" />
+      <BitField name="DATMPX" description="DATMPX" start="12" size="2" />
+      <BitField name="CHINSEL" description="CHINSEL" start="8" size="1" />
+      <BitField name="CHEN" description="CHEN" start="7" size="1" />
+      <BitField name="CKABEN" description="CKABEN" start="6" size="1" />
+      <BitField name="SCDEN" description="SCDEN" start="5" size="1" />
+      <BitField name="SPICKSEL" description="SPICKSEL" start="2" size="2" />
+      <BitField name="SITP" description="SITP" start="0" size="2" />
+    </Register>
+    <Register name="CH7CFGR2" description="CH7CFGR2" start="+0xE4" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="OFFSET" description="OFFSET" start="8" size="24" />
+      <BitField name="DTRBS" description="DTRBS" start="3" size="5" />
+    </Register>
+    <Register name="CH7AWSCDR" description="CH7AWSCDR" start="+0xE8" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="AWFORD" description="AWFORD" start="22" size="2" />
+      <BitField name="AWFOSR" description="AWFOSR" start="16" size="5" />
+      <BitField name="BKSCD" description="BKSCD" start="12" size="4" />
+      <BitField name="SCDT" description="SCDT" start="0" size="8" />
+    </Register>
+    <Register name="CH7WDATR" description="CH7WDATR" start="+0xEC" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="WDATA" description="WDATA" start="0" size="16" />
+    </Register>
+    <Register name="CH7DATINR" description="CH7DATINR" start="+0xF0" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="INDAT1" description="INDAT1" start="16" size="16" />
+      <BitField name="INDAT0" description="INDAT0" start="0" size="16" />
+    </Register>
+    <Register name="CH7DLYR" description="channel y delay register" start="+0xF4" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="PLSSKP" description="PLSSKP" start="0" size="6" />
+    </Register>
+    <Register name="DFSDM_FLT0CR1" description="control register 1" start="+0x100" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AWFSEL" description="Analog watchdog fast mode select" start="30" size="1" />
+      <BitField name="FAST" description="Fast conversion mode selection for regular conversions" start="29" size="1" />
+      <BitField name="RCH" description="Regular channel selection" start="24" size="3" />
+      <BitField name="RDMAEN" description="DMA channel enabled to read data for the regular conversion" start="21" size="1" />
+      <BitField name="RSYNC" description="Launch regular conversion synchronously with DFSDM0" start="19" size="1" />
+      <BitField name="RCONT" description="Continuous mode selection for regular conversions" start="18" size="1" />
+      <BitField name="RSWSTART" description="Software start of a conversion on the regular channel" start="17" size="1" />
+      <BitField name="JEXTEN" description="Trigger enable and trigger edge selection for injected conversions" start="13" size="2" />
+      <BitField name="JEXTSEL" description="Trigger signal selection for launching injected conversions" start="8" size="3" />
+      <BitField name="JDMAEN" description="DMA channel enabled to read data for the injected channel group" start="5" size="1" />
+      <BitField name="JSCAN" description="Scanning conversion mode for injected conversions" start="4" size="1" />
+      <BitField name="JSYNC" description="Launch an injected conversion synchronously with the DFSDM0 JSWSTART trigger" start="3" size="1" />
+      <BitField name="JSWSTART" description="Start a conversion of the injected group of channels" start="1" size="1" />
+      <BitField name="DFEN" description="DFSDM enable" start="0" size="1" />
+    </Register>
+    <Register name="DFSDM_FLT0CR2" description="control register 2" start="+0x104" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AWDCH" description="Analog watchdog channel selection" start="16" size="8" />
+      <BitField name="EXCH" description="Extremes detector channel selection" start="8" size="8" />
+      <BitField name="CKABIE" description="Clock absence interrupt enable" start="6" size="1" />
+      <BitField name="SCDIE" description="Short-circuit detector interrupt enable" start="5" size="1" />
+      <BitField name="AWDIE" description="Analog watchdog interrupt enable" start="4" size="1" />
+      <BitField name="ROVRIE" description="Regular data overrun interrupt enable" start="3" size="1" />
+      <BitField name="JOVRIE" description="Injected data overrun interrupt enable" start="2" size="1" />
+      <BitField name="REOCIE" description="Regular end of conversion interrupt enable" start="1" size="1" />
+      <BitField name="JEOCIE" description="Injected end of conversion interrupt enable" start="0" size="1" />
+    </Register>
+    <Register name="DFSDM_FLT0ISR" description="interrupt and status register" start="+0x108" size="4" access="ReadOnly" reset_value="0x00FF0000" reset_mask="0xFFFFFFFF">
+      <BitField name="SCDF" description="short-circuit detector flag" start="24" size="8" />
+      <BitField name="CKABF" description="Clock absence flag" start="16" size="8" />
+      <BitField name="RCIP" description="Regular conversion in progress status" start="14" size="1" />
+      <BitField name="JCIP" description="Injected conversion in progress status" start="13" size="1" />
+      <BitField name="AWDF" description="Analog watchdog" start="4" size="1" />
+      <BitField name="ROVRF" description="Regular conversion overrun flag" start="3" size="1" />
+      <BitField name="JOVRF" description="Injected conversion overrun flag" start="2" size="1" />
+      <BitField name="REOCF" description="End of regular conversion flag" start="1" size="1" />
+      <BitField name="JEOCF" description="End of injected conversion flag" start="0" size="1" />
+    </Register>
+    <Register name="DFSDM_FLT0ICR" description="interrupt flag clear register" start="+0x10C" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CLRSCDF" description="Clear the short-circuit detector flag" start="24" size="8" />
+      <BitField name="CLRCKABF" description="Clear the clock absence flag" start="16" size="8" />
+      <BitField name="CLRROVRF" description="Clear the regular conversion overrun flag" start="3" size="1" />
+      <BitField name="CLRJOVRF" description="Clear the injected conversion overrun flag" start="2" size="1" />
+    </Register>
+    <Register name="DFSDM_FLT0JCHGR" description="injected channel group selection register" start="+0x110" size="4" access="Read/Write" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField name="JCHG" description="Injected channel group selection" start="0" size="8" />
+    </Register>
+    <Register name="DFSDM_FLT0FCR" description="filter control register" start="+0x114" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FORD" description="Sinc filter order" start="29" size="3" />
+      <BitField name="FOSR" description="Sinc filter oversampling ratio (decimation rate)" start="16" size="10" />
+      <BitField name="IOSR" description="Integrator oversampling ratio (averaging length)" start="0" size="8" />
+    </Register>
+    <Register name="DFSDM_FLT0JDATAR" description="data register for injected group" start="+0x118" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="JDATA" description="Injected group conversion data" start="8" size="24" />
+      <BitField name="JDATACH" description="Injected channel most recently converted" start="0" size="3" />
+    </Register>
+    <Register name="DFSDM_FLT0RDATAR" description="data register for the regular channel" start="+0x11C" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RDATA" description="Regular channel conversion data" start="8" size="24" />
+      <BitField name="RPEND" description="Regular channel pending data" start="4" size="1" />
+      <BitField name="RDATACH" description="Regular channel most recently converted" start="0" size="3" />
+    </Register>
+    <Register name="DFSDM_FLT0AWHTR" description="analog watchdog high threshold register" start="+0x120" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AWHT" description="Analog watchdog high threshold" start="8" size="24" />
+      <BitField name="BKAWH" description="Break signal assignment to analog watchdog high threshold event" start="0" size="4" />
+    </Register>
+    <Register name="DFSDM_FLT0AWLTR" description="analog watchdog low threshold register" start="+0x124" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AWLT" description="Analog watchdog low threshold" start="8" size="24" />
+      <BitField name="BKAWL" description="Break signal assignment to analog watchdog low threshold event" start="0" size="4" />
+    </Register>
+    <Register name="DFSDM_FLT0AWSR" description="analog watchdog status register" start="+0x128" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AWHTF" description="Analog watchdog high threshold flag" start="8" size="8" />
+      <BitField name="AWLTF" description="Analog watchdog low threshold flag" start="0" size="8" />
+    </Register>
+    <Register name="DFSDM_FLT0AWCFR" description="analog watchdog clear flag register" start="+0x12C" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CLRAWHTF" description="Clear the analog watchdog high threshold flag" start="8" size="8" />
+      <BitField name="CLRAWLTF" description="Clear the analog watchdog low threshold flag" start="0" size="8" />
+    </Register>
+    <Register name="DFSDM_FLT0EXMAX" description="Extremes detector maximum register" start="+0x130" size="4" access="ReadOnly" reset_value="0x80000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EXMAX" description="Extremes detector maximum value" start="8" size="24" />
+      <BitField name="EXMAXCH" description="Extremes detector maximum data channel" start="0" size="3" />
+    </Register>
+    <Register name="DFSDM_FLT0EXMIN" description="Extremes detector minimum register" start="+0x134" size="4" access="ReadOnly" reset_value="0x7FFFFF00" reset_mask="0xFFFFFFFF">
+      <BitField name="EXMIN" description="EXMIN" start="8" size="24" />
+      <BitField name="EXMINCH" description="Extremes detector minimum data channel" start="0" size="3" />
+    </Register>
+    <Register name="DFSDM_FLT0CNVTIMR" description="conversion timer register" start="+0x138" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CNVCNT" description="28-bit timer counting conversion time t = CNVCNT[27:0] / fDFSDM_CKIN" start="4" size="28" />
+    </Register>
+    <Register name="DFSDM_FLT1CR1" description="control register 1" start="+0x180" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AWFSEL" description="Analog watchdog fast mode select" start="30" size="1" />
+      <BitField name="FAST" description="Fast conversion mode selection for regular conversions" start="29" size="1" />
+      <BitField name="RCH" description="Regular channel selection" start="24" size="3" />
+      <BitField name="RDMAEN" description="DMA channel enabled to read data for the regular conversion" start="21" size="1" />
+      <BitField name="RSYNC" description="Launch regular conversion synchronously with DFSDM0" start="19" size="1" />
+      <BitField name="RCONT" description="Continuous mode selection for regular conversions" start="18" size="1" />
+      <BitField name="RSWSTART" description="Software start of a conversion on the regular channel" start="17" size="1" />
+      <BitField name="JEXTEN" description="Trigger enable and trigger edge selection for injected conversions" start="13" size="2" />
+      <BitField name="JEXTSEL" description="Trigger signal selection for launching injected conversions" start="8" size="3" />
+      <BitField name="JDMAEN" description="DMA channel enabled to read data for the injected channel group" start="5" size="1" />
+      <BitField name="JSCAN" description="Scanning conversion mode for injected conversions" start="4" size="1" />
+      <BitField name="JSYNC" description="Launch an injected conversion synchronously with the DFSDM0 JSWSTART trigger" start="3" size="1" />
+      <BitField name="JSWSTART" description="Start a conversion of the injected group of channels" start="1" size="1" />
+      <BitField name="DFEN" description="DFSDM enable" start="0" size="1" />
+    </Register>
+    <Register name="DFSDM_FLT1CR2" description="control register 2" start="+0x184" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AWDCH" description="Analog watchdog channel selection" start="16" size="8" />
+      <BitField name="EXCH" description="Extremes detector channel selection" start="8" size="8" />
+      <BitField name="CKABIE" description="Clock absence interrupt enable" start="6" size="1" />
+      <BitField name="SCDIE" description="Short-circuit detector interrupt enable" start="5" size="1" />
+      <BitField name="AWDIE" description="Analog watchdog interrupt enable" start="4" size="1" />
+      <BitField name="ROVRIE" description="Regular data overrun interrupt enable" start="3" size="1" />
+      <BitField name="JOVRIE" description="Injected data overrun interrupt enable" start="2" size="1" />
+      <BitField name="REOCIE" description="Regular end of conversion interrupt enable" start="1" size="1" />
+      <BitField name="JEOCIE" description="Injected end of conversion interrupt enable" start="0" size="1" />
+    </Register>
+    <Register name="DFSDM_FLT1ISR" description="interrupt and status register" start="+0x188" size="4" access="ReadOnly" reset_value="0x00FF0000" reset_mask="0xFFFFFFFF">
+      <BitField name="SCDF" description="short-circuit detector flag" start="24" size="8" />
+      <BitField name="CKABF" description="Clock absence flag" start="16" size="8" />
+      <BitField name="RCIP" description="Regular conversion in progress status" start="14" size="1" />
+      <BitField name="JCIP" description="Injected conversion in progress status" start="13" size="1" />
+      <BitField name="AWDF" description="Analog watchdog" start="4" size="1" />
+      <BitField name="ROVRF" description="Regular conversion overrun flag" start="3" size="1" />
+      <BitField name="JOVRF" description="Injected conversion overrun flag" start="2" size="1" />
+      <BitField name="REOCF" description="End of regular conversion flag" start="1" size="1" />
+      <BitField name="JEOCF" description="End of injected conversion flag" start="0" size="1" />
+    </Register>
+    <Register name="DFSDM_FLT1ICR" description="interrupt flag clear register" start="+0x18C" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CLRSCDF" description="Clear the short-circuit detector flag" start="24" size="8" />
+      <BitField name="CLRCKABF" description="Clear the clock absence flag" start="16" size="8" />
+      <BitField name="CLRROVRF" description="Clear the regular conversion overrun flag" start="3" size="1" />
+      <BitField name="CLRJOVRF" description="Clear the injected conversion overrun flag" start="2" size="1" />
+    </Register>
+    <Register name="DFSDM_FLT1CHGR" description="injected channel group selection register" start="+0x190" size="4" access="Read/Write" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField name="JCHG" description="Injected channel group selection" start="0" size="8" />
+    </Register>
+    <Register name="DFSDM_FLT1FCR" description="filter control register" start="+0x194" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FORD" description="Sinc filter order" start="29" size="3" />
+      <BitField name="FOSR" description="Sinc filter oversampling ratio (decimation rate)" start="16" size="10" />
+      <BitField name="IOSR" description="Integrator oversampling ratio (averaging length)" start="0" size="8" />
+    </Register>
+    <Register name="DFSDM_FLT1JDATAR" description="data register for injected group" start="+0x198" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="JDATA" description="Injected group conversion data" start="8" size="24" />
+      <BitField name="JDATACH" description="Injected channel most recently converted" start="0" size="3" />
+    </Register>
+    <Register name="DFSDM_FLT1RDATAR" description="data register for the regular channel" start="+0x19C" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RDATA" description="Regular channel conversion data" start="8" size="24" />
+      <BitField name="RPEND" description="Regular channel pending data" start="4" size="1" />
+      <BitField name="RDATACH" description="Regular channel most recently converted" start="0" size="3" />
+    </Register>
+    <Register name="DFSDM_FLT1AWHTR" description="analog watchdog high threshold register" start="+0x1A0" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AWHT" description="Analog watchdog high threshold" start="8" size="24" />
+      <BitField name="BKAWH" description="Break signal assignment to analog watchdog high threshold event" start="0" size="4" />
+    </Register>
+    <Register name="DFSDM_FLT1AWLTR" description="analog watchdog low threshold register" start="+0x1A4" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AWLT" description="Analog watchdog low threshold" start="8" size="24" />
+      <BitField name="BKAWL" description="Break signal assignment to analog watchdog low threshold event" start="0" size="4" />
+    </Register>
+    <Register name="DFSDM_FLT1AWSR" description="analog watchdog status register" start="+0x1A8" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AWHTF" description="Analog watchdog high threshold flag" start="8" size="8" />
+      <BitField name="AWLTF" description="Analog watchdog low threshold flag" start="0" size="8" />
+    </Register>
+    <Register name="DFSDM_FLT1AWCFR" description="analog watchdog clear flag register" start="+0x1AC" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CLRAWHTF" description="Clear the analog watchdog high threshold flag" start="8" size="8" />
+      <BitField name="CLRAWLTF" description="Clear the analog watchdog low threshold flag" start="0" size="8" />
+    </Register>
+    <Register name="DFSDM_FLT1EXMAX" description="Extremes detector maximum register" start="+0x1B0" size="4" access="ReadOnly" reset_value="0x80000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EXMAX" description="Extremes detector maximum value" start="8" size="24" />
+      <BitField name="EXMAXCH" description="Extremes detector maximum data channel" start="0" size="3" />
+    </Register>
+    <Register name="DFSDM_FLT1EXMIN" description="Extremes detector minimum register" start="+0x1B4" size="4" access="ReadOnly" reset_value="0x7FFFFF00" reset_mask="0xFFFFFFFF">
+      <BitField name="EXMIN" description="EXMIN" start="8" size="24" />
+      <BitField name="EXMINCH" description="Extremes detector minimum data channel" start="0" size="3" />
+    </Register>
+    <Register name="DFSDM_FLT1CNVTIMR" description="conversion timer register" start="+0x1B8" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CNVCNT" description="28-bit timer counting conversion time t = CNVCNT[27:0] / fDFSDM_CKIN" start="4" size="28" />
+    </Register>
+    <Register name="DFSDM_FLT2CR1" description="control register 1" start="+0x200" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AWFSEL" description="Analog watchdog fast mode select" start="30" size="1" />
+      <BitField name="FAST" description="Fast conversion mode selection for regular conversions" start="29" size="1" />
+      <BitField name="RCH" description="Regular channel selection" start="24" size="3" />
+      <BitField name="RDMAEN" description="DMA channel enabled to read data for the regular conversion" start="21" size="1" />
+      <BitField name="RSYNC" description="Launch regular conversion synchronously with DFSDM0" start="19" size="1" />
+      <BitField name="RCONT" description="Continuous mode selection for regular conversions" start="18" size="1" />
+      <BitField name="RSWSTART" description="Software start of a conversion on the regular channel" start="17" size="1" />
+      <BitField name="JEXTEN" description="Trigger enable and trigger edge selection for injected conversions" start="13" size="2" />
+      <BitField name="JEXTSEL" description="Trigger signal selection for launching injected conversions" start="8" size="3" />
+      <BitField name="JDMAEN" description="DMA channel enabled to read data for the injected channel group" start="5" size="1" />
+      <BitField name="JSCAN" description="Scanning conversion mode for injected conversions" start="4" size="1" />
+      <BitField name="JSYNC" description="Launch an injected conversion synchronously with the DFSDM0 JSWSTART trigger" start="3" size="1" />
+      <BitField name="JSWSTART" description="Start a conversion of the injected group of channels" start="1" size="1" />
+      <BitField name="DFEN" description="DFSDM enable" start="0" size="1" />
+    </Register>
+    <Register name="DFSDM_FLT2CR2" description="control register 2" start="+0x204" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AWDCH" description="Analog watchdog channel selection" start="16" size="8" />
+      <BitField name="EXCH" description="Extremes detector channel selection" start="8" size="8" />
+      <BitField name="CKABIE" description="Clock absence interrupt enable" start="6" size="1" />
+      <BitField name="SCDIE" description="Short-circuit detector interrupt enable" start="5" size="1" />
+      <BitField name="AWDIE" description="Analog watchdog interrupt enable" start="4" size="1" />
+      <BitField name="ROVRIE" description="Regular data overrun interrupt enable" start="3" size="1" />
+      <BitField name="JOVRIE" description="Injected data overrun interrupt enable" start="2" size="1" />
+      <BitField name="REOCIE" description="Regular end of conversion interrupt enable" start="1" size="1" />
+      <BitField name="JEOCIE" description="Injected end of conversion interrupt enable" start="0" size="1" />
+    </Register>
+    <Register name="DFSDM_FLT2ISR" description="interrupt and status register" start="+0x208" size="4" access="ReadOnly" reset_value="0x00FF0000" reset_mask="0xFFFFFFFF">
+      <BitField name="SCDF" description="short-circuit detector flag" start="24" size="8" />
+      <BitField name="CKABF" description="Clock absence flag" start="16" size="8" />
+      <BitField name="RCIP" description="Regular conversion in progress status" start="14" size="1" />
+      <BitField name="JCIP" description="Injected conversion in progress status" start="13" size="1" />
+      <BitField name="AWDF" description="Analog watchdog" start="4" size="1" />
+      <BitField name="ROVRF" description="Regular conversion overrun flag" start="3" size="1" />
+      <BitField name="JOVRF" description="Injected conversion overrun flag" start="2" size="1" />
+      <BitField name="REOCF" description="End of regular conversion flag" start="1" size="1" />
+      <BitField name="JEOCF" description="End of injected conversion flag" start="0" size="1" />
+    </Register>
+    <Register name="DFSDM_FLT2ICR" description="interrupt flag clear register" start="+0x20C" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CLRSCDF" description="Clear the short-circuit detector flag" start="24" size="8" />
+      <BitField name="CLRCKABF" description="Clear the clock absence flag" start="16" size="8" />
+      <BitField name="CLRROVRF" description="Clear the regular conversion overrun flag" start="3" size="1" />
+      <BitField name="CLRJOVRF" description="Clear the injected conversion overrun flag" start="2" size="1" />
+    </Register>
+    <Register name="DFSDM_FLT2JCHGR" description="injected channel group selection register" start="+0x210" size="4" access="Read/Write" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField name="JCHG" description="Injected channel group selection" start="0" size="8" />
+    </Register>
+    <Register name="DFSDM_FLT2FCR" description="filter control register" start="+0x214" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FORD" description="Sinc filter order" start="29" size="3" />
+      <BitField name="FOSR" description="Sinc filter oversampling ratio (decimation rate)" start="16" size="10" />
+      <BitField name="IOSR" description="Integrator oversampling ratio (averaging length)" start="0" size="8" />
+    </Register>
+    <Register name="DFSDM_FLT2JDATAR" description="data register for injected group" start="+0x218" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="JDATA" description="Injected group conversion data" start="8" size="24" />
+      <BitField name="JDATACH" description="Injected channel most recently converted" start="0" size="3" />
+    </Register>
+    <Register name="DFSDM_FLT2RDATAR" description="data register for the regular channel" start="+0x21C" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RDATA" description="Regular channel conversion data" start="8" size="24" />
+      <BitField name="RPEND" description="Regular channel pending data" start="4" size="1" />
+      <BitField name="RDATACH" description="Regular channel most recently converted" start="0" size="3" />
+    </Register>
+    <Register name="DFSDM_FLT2AWHTR" description="analog watchdog high threshold register" start="+0x220" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AWHT" description="Analog watchdog high threshold" start="8" size="24" />
+      <BitField name="BKAWH" description="Break signal assignment to analog watchdog high threshold event" start="0" size="4" />
+    </Register>
+    <Register name="DFSDM_FLT2AWLTR" description="analog watchdog low threshold register" start="+0x224" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AWLT" description="Analog watchdog low threshold" start="8" size="24" />
+      <BitField name="BKAWL" description="Break signal assignment to analog watchdog low threshold event" start="0" size="4" />
+    </Register>
+    <Register name="DFSDM_FLT2AWSR" description="analog watchdog status register" start="+0x228" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AWHTF" description="Analog watchdog high threshold flag" start="8" size="8" />
+      <BitField name="AWLTF" description="Analog watchdog low threshold flag" start="0" size="8" />
+    </Register>
+    <Register name="DFSDM_FLT2AWCFR" description="analog watchdog clear flag register" start="+0x22C" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CLRAWHTF" description="Clear the analog watchdog high threshold flag" start="8" size="8" />
+      <BitField name="CLRAWLTF" description="Clear the analog watchdog low threshold flag" start="0" size="8" />
+    </Register>
+    <Register name="DFSDM_FLT2EXMAX" description="Extremes detector maximum register" start="+0x230" size="4" access="ReadOnly" reset_value="0x80000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EXMAX" description="Extremes detector maximum value" start="8" size="24" />
+      <BitField name="EXMAXCH" description="Extremes detector maximum data channel" start="0" size="3" />
+    </Register>
+    <Register name="DFSDM_FLT2EXMIN" description="Extremes detector minimum register" start="+0x234" size="4" access="ReadOnly" reset_value="0x7FFFFF00" reset_mask="0xFFFFFFFF">
+      <BitField name="EXMIN" description="EXMIN" start="8" size="24" />
+      <BitField name="EXMINCH" description="Extremes detector minimum data channel" start="0" size="3" />
+    </Register>
+    <Register name="DFSDM_FLT2CNVTIMR" description="conversion timer register" start="+0x238" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CNVCNT" description="28-bit timer counting conversion time t = CNVCNT[27:0] / fDFSDM_CKIN" start="4" size="28" />
+    </Register>
+    <Register name="DFSDM_FLT3CR1" description="control register 1" start="+0x280" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AWFSEL" description="Analog watchdog fast mode select" start="30" size="1" />
+      <BitField name="FAST" description="Fast conversion mode selection for regular conversions" start="29" size="1" />
+      <BitField name="RCH" description="Regular channel selection" start="24" size="3" />
+      <BitField name="RDMAEN" description="DMA channel enabled to read data for the regular conversion" start="21" size="1" />
+      <BitField name="RSYNC" description="Launch regular conversion synchronously with DFSDM0" start="19" size="1" />
+      <BitField name="RCONT" description="Continuous mode selection for regular conversions" start="18" size="1" />
+      <BitField name="RSWSTART" description="Software start of a conversion on the regular channel" start="17" size="1" />
+      <BitField name="JEXTEN" description="Trigger enable and trigger edge selection for injected conversions" start="13" size="2" />
+      <BitField name="JEXTSEL" description="Trigger signal selection for launching injected conversions" start="8" size="3" />
+      <BitField name="JDMAEN" description="DMA channel enabled to read data for the injected channel group" start="5" size="1" />
+      <BitField name="JSCAN" description="Scanning conversion mode for injected conversions" start="4" size="1" />
+      <BitField name="JSYNC" description="Launch an injected conversion synchronously with the DFSDM0 JSWSTART trigger" start="3" size="1" />
+      <BitField name="JSWSTART" description="Start a conversion of the injected group of channels" start="1" size="1" />
+      <BitField name="DFEN" description="DFSDM enable" start="0" size="1" />
+    </Register>
+    <Register name="DFSDM_FLT3CR2" description="control register 2" start="+0x284" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AWDCH" description="Analog watchdog channel selection" start="16" size="8" />
+      <BitField name="EXCH" description="Extremes detector channel selection" start="8" size="8" />
+      <BitField name="CKABIE" description="Clock absence interrupt enable" start="6" size="1" />
+      <BitField name="SCDIE" description="Short-circuit detector interrupt enable" start="5" size="1" />
+      <BitField name="AWDIE" description="Analog watchdog interrupt enable" start="4" size="1" />
+      <BitField name="ROVRIE" description="Regular data overrun interrupt enable" start="3" size="1" />
+      <BitField name="JOVRIE" description="Injected data overrun interrupt enable" start="2" size="1" />
+      <BitField name="REOCIE" description="Regular end of conversion interrupt enable" start="1" size="1" />
+      <BitField name="JEOCIE" description="Injected end of conversion interrupt enable" start="0" size="1" />
+    </Register>
+    <Register name="DFSDM_FLT3ISR" description="interrupt and status register" start="+0x288" size="4" access="ReadOnly" reset_value="0x00FF0000" reset_mask="0xFFFFFFFF">
+      <BitField name="SCDF" description="short-circuit detector flag" start="24" size="8" />
+      <BitField name="CKABF" description="Clock absence flag" start="16" size="8" />
+      <BitField name="RCIP" description="Regular conversion in progress status" start="14" size="1" />
+      <BitField name="JCIP" description="Injected conversion in progress status" start="13" size="1" />
+      <BitField name="AWDF" description="Analog watchdog" start="4" size="1" />
+      <BitField name="ROVRF" description="Regular conversion overrun flag" start="3" size="1" />
+      <BitField name="JOVRF" description="Injected conversion overrun flag" start="2" size="1" />
+      <BitField name="REOCF" description="End of regular conversion flag" start="1" size="1" />
+      <BitField name="JEOCF" description="End of injected conversion flag" start="0" size="1" />
+    </Register>
+    <Register name="DFSDM_FLT3ICR" description="interrupt flag clear register" start="+0x28C" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CLRSCDF" description="Clear the short-circuit detector flag" start="24" size="8" />
+      <BitField name="CLRCKABF" description="Clear the clock absence flag" start="16" size="8" />
+      <BitField name="CLRROVRF" description="Clear the regular conversion overrun flag" start="3" size="1" />
+      <BitField name="CLRJOVRF" description="Clear the injected conversion overrun flag" start="2" size="1" />
+    </Register>
+    <Register name="DFSDM_FLT3JCHGR" description="injected channel group selection register" start="+0x290" size="4" access="Read/Write" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField name="JCHG" description="Injected channel group selection" start="0" size="8" />
+    </Register>
+    <Register name="DFSDM_FLT3FCR" description="filter control register" start="+0x294" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FORD" description="Sinc filter order" start="29" size="3" />
+      <BitField name="FOSR" description="Sinc filter oversampling ratio (decimation rate)" start="16" size="10" />
+      <BitField name="IOSR" description="Integrator oversampling ratio (averaging length)" start="0" size="8" />
+    </Register>
+    <Register name="DFSDM_FLT3JDATAR" description="data register for injected group" start="+0x298" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="JDATA" description="Injected group conversion data" start="8" size="24" />
+      <BitField name="JDATACH" description="Injected channel most recently converted" start="0" size="3" />
+    </Register>
+    <Register name="DFSDM_FLT3RDATAR" description="data register for the regular channel" start="+0x29C" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RDATA" description="Regular channel conversion data" start="8" size="24" />
+      <BitField name="RPEND" description="Regular channel pending data" start="4" size="1" />
+      <BitField name="RDATACH" description="Regular channel most recently converted" start="0" size="3" />
+    </Register>
+    <Register name="DFSDM_FLT3AWHTR" description="analog watchdog high threshold register" start="+0x2A0" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AWHT" description="Analog watchdog high threshold" start="8" size="24" />
+      <BitField name="BKAWH" description="Break signal assignment to analog watchdog high threshold event" start="0" size="4" />
+    </Register>
+    <Register name="DFSDM_FLT3AWLTR" description="analog watchdog low threshold register" start="+0x2A4" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AWLT" description="Analog watchdog low threshold" start="8" size="24" />
+      <BitField name="BKAWL" description="Break signal assignment to analog watchdog low threshold event" start="0" size="4" />
+    </Register>
+    <Register name="DFSDM_FLT3AWSR" description="analog watchdog status register" start="+0x2A8" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AWHTF" description="Analog watchdog high threshold flag" start="8" size="8" />
+      <BitField name="AWLTF" description="Analog watchdog low threshold flag" start="0" size="8" />
+    </Register>
+    <Register name="DFSDM_FLT3AWCFR" description="analog watchdog clear flag register" start="+0x2AC" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CLRAWHTF" description="Clear the analog watchdog high threshold flag" start="8" size="8" />
+      <BitField name="CLRAWLTF" description="Clear the analog watchdog low threshold flag" start="0" size="8" />
+    </Register>
+    <Register name="DFSDM_FLT3EXMAX" description="Extremes detector maximum register" start="+0x2B0" size="4" access="ReadOnly" reset_value="0x80000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EXMAX" description="Extremes detector maximum value" start="8" size="24" />
+      <BitField name="EXMAXCH" description="Extremes detector maximum data channel" start="0" size="3" />
+    </Register>
+    <Register name="DFSDM_FLT3EXMIN" description="Extremes detector minimum register" start="+0x2B4" size="4" access="ReadOnly" reset_value="0x7FFFFF00" reset_mask="0xFFFFFFFF">
+      <BitField name="EXMIN" description="EXMIN" start="8" size="24" />
+      <BitField name="EXMINCH" description="Extremes detector minimum data channel" start="0" size="3" />
+    </Register>
+    <Register name="DFSDM_FLT3CNVTIMR" description="conversion timer register" start="+0x2B8" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CNVCNT" description="28-bit timer counting conversion time t = CNVCNT[27:0] / fDFSDM_CKIN" start="4" size="28" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="DMA1" description="DMA controller" start="0x40020000">
+    <Register name="LISR" description="low interrupt status register" start="+0x0" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TCIF3" description="Stream x transfer complete interrupt flag (x = 3..0)" start="27" size="1" />
+      <BitField name="HTIF3" description="Stream x half transfer interrupt flag (x=3..0)" start="26" size="1" />
+      <BitField name="TEIF3" description="Stream x transfer error interrupt flag (x=3..0)" start="25" size="1" />
+      <BitField name="DMEIF3" description="Stream x direct mode error interrupt flag (x=3..0)" start="24" size="1" />
+      <BitField name="FEIF3" description="Stream x FIFO error interrupt flag (x=3..0)" start="22" size="1" />
+      <BitField name="TCIF2" description="Stream x transfer complete interrupt flag (x = 3..0)" start="21" size="1" />
+      <BitField name="HTIF2" description="Stream x half transfer interrupt flag (x=3..0)" start="20" size="1" />
+      <BitField name="TEIF2" description="Stream x transfer error interrupt flag (x=3..0)" start="19" size="1" />
+      <BitField name="DMEIF2" description="Stream x direct mode error interrupt flag (x=3..0)" start="18" size="1" />
+      <BitField name="FEIF2" description="Stream x FIFO error interrupt flag (x=3..0)" start="16" size="1" />
+      <BitField name="TCIF1" description="Stream x transfer complete interrupt flag (x = 3..0)" start="11" size="1" />
+      <BitField name="HTIF1" description="Stream x half transfer interrupt flag (x=3..0)" start="10" size="1" />
+      <BitField name="TEIF1" description="Stream x transfer error interrupt flag (x=3..0)" start="9" size="1" />
+      <BitField name="DMEIF1" description="Stream x direct mode error interrupt flag (x=3..0)" start="8" size="1" />
+      <BitField name="FEIF1" description="Stream x FIFO error interrupt flag (x=3..0)" start="6" size="1" />
+      <BitField name="TCIF0" description="Stream x transfer complete interrupt flag (x = 3..0)" start="5" size="1" />
+      <BitField name="HTIF0" description="Stream x half transfer interrupt flag (x=3..0)" start="4" size="1" />
+      <BitField name="TEIF0" description="Stream x transfer error interrupt flag (x=3..0)" start="3" size="1" />
+      <BitField name="DMEIF0" description="Stream x direct mode error interrupt flag (x=3..0)" start="2" size="1" />
+      <BitField name="FEIF0" description="Stream x FIFO error interrupt flag (x=3..0)" start="0" size="1" />
+    </Register>
+    <Register name="HISR" description="high interrupt status register" start="+0x4" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TCIF7" description="Stream x transfer complete interrupt flag (x=7..4)" start="27" size="1" />
+      <BitField name="HTIF7" description="Stream x half transfer interrupt flag (x=7..4)" start="26" size="1" />
+      <BitField name="TEIF7" description="Stream x transfer error interrupt flag (x=7..4)" start="25" size="1" />
+      <BitField name="DMEIF7" description="Stream x direct mode error interrupt flag (x=7..4)" start="24" size="1" />
+      <BitField name="FEIF7" description="Stream x FIFO error interrupt flag (x=7..4)" start="22" size="1" />
+      <BitField name="TCIF6" description="Stream x transfer complete interrupt flag (x=7..4)" start="21" size="1" />
+      <BitField name="HTIF6" description="Stream x half transfer interrupt flag (x=7..4)" start="20" size="1" />
+      <BitField name="TEIF6" description="Stream x transfer error interrupt flag (x=7..4)" start="19" size="1" />
+      <BitField name="DMEIF6" description="Stream x direct mode error interrupt flag (x=7..4)" start="18" size="1" />
+      <BitField name="FEIF6" description="Stream x FIFO error interrupt flag (x=7..4)" start="16" size="1" />
+      <BitField name="TCIF5" description="Stream x transfer complete interrupt flag (x=7..4)" start="11" size="1" />
+      <BitField name="HTIF5" description="Stream x half transfer interrupt flag (x=7..4)" start="10" size="1" />
+      <BitField name="TEIF5" description="Stream x transfer error interrupt flag (x=7..4)" start="9" size="1" />
+      <BitField name="DMEIF5" description="Stream x direct mode error interrupt flag (x=7..4)" start="8" size="1" />
+      <BitField name="FEIF5" description="Stream x FIFO error interrupt flag (x=7..4)" start="6" size="1" />
+      <BitField name="TCIF4" description="Stream x transfer complete interrupt flag (x=7..4)" start="5" size="1" />
+      <BitField name="HTIF4" description="Stream x half transfer interrupt flag (x=7..4)" start="4" size="1" />
+      <BitField name="TEIF4" description="Stream x transfer error interrupt flag (x=7..4)" start="3" size="1" />
+      <BitField name="DMEIF4" description="Stream x direct mode error interrupt flag (x=7..4)" start="2" size="1" />
+      <BitField name="FEIF4" description="Stream x FIFO error interrupt flag (x=7..4)" start="0" size="1" />
+    </Register>
+    <Register name="LIFCR" description="low interrupt flag clear register" start="+0x8" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CTCIF3" description="Stream x clear transfer complete interrupt flag (x = 3..0)" start="27" size="1" />
+      <BitField name="CHTIF3" description="Stream x clear half transfer interrupt flag (x = 3..0)" start="26" size="1" />
+      <BitField name="CTEIF3" description="Stream x clear transfer error interrupt flag (x = 3..0)" start="25" size="1" />
+      <BitField name="CDMEIF3" description="Stream x clear direct mode error interrupt flag (x = 3..0)" start="24" size="1" />
+      <BitField name="CFEIF3" description="Stream x clear FIFO error interrupt flag (x = 3..0)" start="22" size="1" />
+      <BitField name="CTCIF2" description="Stream x clear transfer complete interrupt flag (x = 3..0)" start="21" size="1" />
+      <BitField name="CHTIF2" description="Stream x clear half transfer interrupt flag (x = 3..0)" start="20" size="1" />
+      <BitField name="CTEIF2" description="Stream x clear transfer error interrupt flag (x = 3..0)" start="19" size="1" />
+      <BitField name="CDMEIF2" description="Stream x clear direct mode error interrupt flag (x = 3..0)" start="18" size="1" />
+      <BitField name="CFEIF2" description="Stream x clear FIFO error interrupt flag (x = 3..0)" start="16" size="1" />
+      <BitField name="CTCIF1" description="Stream x clear transfer complete interrupt flag (x = 3..0)" start="11" size="1" />
+      <BitField name="CHTIF1" description="Stream x clear half transfer interrupt flag (x = 3..0)" start="10" size="1" />
+      <BitField name="CTEIF1" description="Stream x clear transfer error interrupt flag (x = 3..0)" start="9" size="1" />
+      <BitField name="CDMEIF1" description="Stream x clear direct mode error interrupt flag (x = 3..0)" start="8" size="1" />
+      <BitField name="CFEIF1" description="Stream x clear FIFO error interrupt flag (x = 3..0)" start="6" size="1" />
+      <BitField name="CTCIF0" description="Stream x clear transfer complete interrupt flag (x = 3..0)" start="5" size="1" />
+      <BitField name="CHTIF0" description="Stream x clear half transfer interrupt flag (x = 3..0)" start="4" size="1" />
+      <BitField name="CTEIF0" description="Stream x clear transfer error interrupt flag (x = 3..0)" start="3" size="1" />
+      <BitField name="CDMEIF0" description="Stream x clear direct mode error interrupt flag (x = 3..0)" start="2" size="1" />
+      <BitField name="CFEIF0" description="Stream x clear FIFO error interrupt flag (x = 3..0)" start="0" size="1" />
+    </Register>
+    <Register name="HIFCR" description="high interrupt flag clear register" start="+0xC" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CTCIF7" description="Stream x clear transfer complete interrupt flag (x = 7..4)" start="27" size="1" />
+      <BitField name="CHTIF7" description="Stream x clear half transfer interrupt flag (x = 7..4)" start="26" size="1" />
+      <BitField name="CTEIF7" description="Stream x clear transfer error interrupt flag (x = 7..4)" start="25" size="1" />
+      <BitField name="CDMEIF7" description="Stream x clear direct mode error interrupt flag (x = 7..4)" start="24" size="1" />
+      <BitField name="CFEIF7" description="Stream x clear FIFO error interrupt flag (x = 7..4)" start="22" size="1" />
+      <BitField name="CTCIF6" description="Stream x clear transfer complete interrupt flag (x = 7..4)" start="21" size="1" />
+      <BitField name="CHTIF6" description="Stream x clear half transfer interrupt flag (x = 7..4)" start="20" size="1" />
+      <BitField name="CTEIF6" description="Stream x clear transfer error interrupt flag (x = 7..4)" start="19" size="1" />
+      <BitField name="CDMEIF6" description="Stream x clear direct mode error interrupt flag (x = 7..4)" start="18" size="1" />
+      <BitField name="CFEIF6" description="Stream x clear FIFO error interrupt flag (x = 7..4)" start="16" size="1" />
+      <BitField name="CTCIF5" description="Stream x clear transfer complete interrupt flag (x = 7..4)" start="11" size="1" />
+      <BitField name="CHTIF5" description="Stream x clear half transfer interrupt flag (x = 7..4)" start="10" size="1" />
+      <BitField name="CTEIF5" description="Stream x clear transfer error interrupt flag (x = 7..4)" start="9" size="1" />
+      <BitField name="CDMEIF5" description="Stream x clear direct mode error interrupt flag (x = 7..4)" start="8" size="1" />
+      <BitField name="CFEIF5" description="Stream x clear FIFO error interrupt flag (x = 7..4)" start="6" size="1" />
+      <BitField name="CTCIF4" description="Stream x clear transfer complete interrupt flag (x = 7..4)" start="5" size="1" />
+      <BitField name="CHTIF4" description="Stream x clear half transfer interrupt flag (x = 7..4)" start="4" size="1" />
+      <BitField name="CTEIF4" description="Stream x clear transfer error interrupt flag (x = 7..4)" start="3" size="1" />
+      <BitField name="CDMEIF4" description="Stream x clear direct mode error interrupt flag (x = 7..4)" start="2" size="1" />
+      <BitField name="CFEIF4" description="Stream x clear FIFO error interrupt flag (x = 7..4)" start="0" size="1" />
+    </Register>
+    <Register name="S0CR" description="stream x configuration register" start="+0x10" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MBURST" description="Memory burst transfer configuration" start="23" size="2" />
+      <BitField name="PBURST" description="Peripheral burst transfer configuration" start="21" size="2" />
+      <BitField name="CT" description="Current target (only in double buffer mode)" start="19" size="1" />
+      <BitField name="DBM" description="Double buffer mode" start="18" size="1" />
+      <BitField name="PL" description="Priority level" start="16" size="2" />
+      <BitField name="PINCOS" description="Peripheral increment offset size" start="15" size="1" />
+      <BitField name="MSIZE" description="Memory data size" start="13" size="2" />
+      <BitField name="PSIZE" description="Peripheral data size" start="11" size="2" />
+      <BitField name="MINC" description="Memory increment mode" start="10" size="1" />
+      <BitField name="PINC" description="Peripheral increment mode" start="9" size="1" />
+      <BitField name="CIRC" description="Circular mode" start="8" size="1" />
+      <BitField name="DIR" description="Data transfer direction" start="6" size="2" />
+      <BitField name="PFCTRL" description="Peripheral flow controller" start="5" size="1" />
+      <BitField name="TCIE" description="Transfer complete interrupt enable" start="4" size="1" />
+      <BitField name="HTIE" description="Half transfer interrupt enable" start="3" size="1" />
+      <BitField name="TEIE" description="Transfer error interrupt enable" start="2" size="1" />
+      <BitField name="DMEIE" description="Direct mode error interrupt enable" start="1" size="1" />
+      <BitField name="EN" description="Stream enable / flag stream ready when read low" start="0" size="1" />
+    </Register>
+    <Register name="S0NDTR" description="stream x number of data register" start="+0x14" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="NDT" description="Number of data items to transfer" start="0" size="16" />
+    </Register>
+    <Register name="S0PAR" description="stream x peripheral address register" start="+0x18" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PA" description="Peripheral address" start="0" size="32" />
+    </Register>
+    <Register name="S0M0AR" description="stream x memory 0 address register" start="+0x1C" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="M0A" description="Memory 0 address" start="0" size="32" />
+    </Register>
+    <Register name="S0M1AR" description="stream x memory 1 address register" start="+0x20" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="M1A" description="Memory 1 address (used in case of Double buffer mode)" start="0" size="32" />
+    </Register>
+    <Register name="S0FCR" description="stream x FIFO control register" start="+0x24" size="4" reset_value="0x00000021" reset_mask="0xFFFFFFFF">
+      <BitField name="FEIE" description="FIFO error interrupt enable" start="7" size="1" access="Read/Write" />
+      <BitField name="FS" description="FIFO status" start="3" size="3" access="ReadOnly" />
+      <BitField name="DMDIS" description="Direct mode disable" start="2" size="1" access="Read/Write" />
+      <BitField name="FTH" description="FIFO threshold selection" start="0" size="2" access="Read/Write" />
+    </Register>
+    <Register name="S1CR" description="stream x configuration register" start="+0x28" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MBURST" description="Memory burst transfer configuration" start="23" size="2" />
+      <BitField name="PBURST" description="Peripheral burst transfer configuration" start="21" size="2" />
+      <BitField name="ACK" description="ACK" start="20" size="1" />
+      <BitField name="CT" description="Current target (only in double buffer mode)" start="19" size="1" />
+      <BitField name="DBM" description="Double buffer mode" start="18" size="1" />
+      <BitField name="PL" description="Priority level" start="16" size="2" />
+      <BitField name="PINCOS" description="Peripheral increment offset size" start="15" size="1" />
+      <BitField name="MSIZE" description="Memory data size" start="13" size="2" />
+      <BitField name="PSIZE" description="Peripheral data size" start="11" size="2" />
+      <BitField name="MINC" description="Memory increment mode" start="10" size="1" />
+      <BitField name="PINC" description="Peripheral increment mode" start="9" size="1" />
+      <BitField name="CIRC" description="Circular mode" start="8" size="1" />
+      <BitField name="DIR" description="Data transfer direction" start="6" size="2" />
+      <BitField name="PFCTRL" description="Peripheral flow controller" start="5" size="1" />
+      <BitField name="TCIE" description="Transfer complete interrupt enable" start="4" size="1" />
+      <BitField name="HTIE" description="Half transfer interrupt enable" start="3" size="1" />
+      <BitField name="TEIE" description="Transfer error interrupt enable" start="2" size="1" />
+      <BitField name="DMEIE" description="Direct mode error interrupt enable" start="1" size="1" />
+      <BitField name="EN" description="Stream enable / flag stream ready when read low" start="0" size="1" />
+    </Register>
+    <Register name="S1NDTR" description="stream x number of data register" start="+0x2C" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="NDT" description="Number of data items to transfer" start="0" size="16" />
+    </Register>
+    <Register name="S1PAR" description="stream x peripheral address register" start="+0x30" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PA" description="Peripheral address" start="0" size="32" />
+    </Register>
+    <Register name="S1M0AR" description="stream x memory 0 address register" start="+0x34" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="M0A" description="Memory 0 address" start="0" size="32" />
+    </Register>
+    <Register name="S1M1AR" description="stream x memory 1 address register" start="+0x38" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="M1A" description="Memory 1 address (used in case of Double buffer mode)" start="0" size="32" />
+    </Register>
+    <Register name="S1FCR" description="stream x FIFO control register" start="+0x3C" size="4" reset_value="0x00000021" reset_mask="0xFFFFFFFF">
+      <BitField name="FEIE" description="FIFO error interrupt enable" start="7" size="1" access="Read/Write" />
+      <BitField name="FS" description="FIFO status" start="3" size="3" access="ReadOnly" />
+      <BitField name="DMDIS" description="Direct mode disable" start="2" size="1" access="Read/Write" />
+      <BitField name="FTH" description="FIFO threshold selection" start="0" size="2" access="Read/Write" />
+    </Register>
+    <Register name="S2CR" description="stream x configuration register" start="+0x40" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MBURST" description="Memory burst transfer configuration" start="23" size="2" />
+      <BitField name="PBURST" description="Peripheral burst transfer configuration" start="21" size="2" />
+      <BitField name="ACK" description="ACK" start="20" size="1" />
+      <BitField name="CT" description="Current target (only in double buffer mode)" start="19" size="1" />
+      <BitField name="DBM" description="Double buffer mode" start="18" size="1" />
+      <BitField name="PL" description="Priority level" start="16" size="2" />
+      <BitField name="PINCOS" description="Peripheral increment offset size" start="15" size="1" />
+      <BitField name="MSIZE" description="Memory data size" start="13" size="2" />
+      <BitField name="PSIZE" description="Peripheral data size" start="11" size="2" />
+      <BitField name="MINC" description="Memory increment mode" start="10" size="1" />
+      <BitField name="PINC" description="Peripheral increment mode" start="9" size="1" />
+      <BitField name="CIRC" description="Circular mode" start="8" size="1" />
+      <BitField name="DIR" description="Data transfer direction" start="6" size="2" />
+      <BitField name="PFCTRL" description="Peripheral flow controller" start="5" size="1" />
+      <BitField name="TCIE" description="Transfer complete interrupt enable" start="4" size="1" />
+      <BitField name="HTIE" description="Half transfer interrupt enable" start="3" size="1" />
+      <BitField name="TEIE" description="Transfer error interrupt enable" start="2" size="1" />
+      <BitField name="DMEIE" description="Direct mode error interrupt enable" start="1" size="1" />
+      <BitField name="EN" description="Stream enable / flag stream ready when read low" start="0" size="1" />
+    </Register>
+    <Register name="S2NDTR" description="stream x number of data register" start="+0x44" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="NDT" description="Number of data items to transfer" start="0" size="16" />
+    </Register>
+    <Register name="S2PAR" description="stream x peripheral address register" start="+0x48" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PA" description="Peripheral address" start="0" size="32" />
+    </Register>
+    <Register name="S2M0AR" description="stream x memory 0 address register" start="+0x4C" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="M0A" description="Memory 0 address" start="0" size="32" />
+    </Register>
+    <Register name="S2M1AR" description="stream x memory 1 address register" start="+0x50" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="M1A" description="Memory 1 address (used in case of Double buffer mode)" start="0" size="32" />
+    </Register>
+    <Register name="S2FCR" description="stream x FIFO control register" start="+0x54" size="4" reset_value="0x00000021" reset_mask="0xFFFFFFFF">
+      <BitField name="FEIE" description="FIFO error interrupt enable" start="7" size="1" access="Read/Write" />
+      <BitField name="FS" description="FIFO status" start="3" size="3" access="ReadOnly" />
+      <BitField name="DMDIS" description="Direct mode disable" start="2" size="1" access="Read/Write" />
+      <BitField name="FTH" description="FIFO threshold selection" start="0" size="2" access="Read/Write" />
+    </Register>
+    <Register name="S3CR" description="stream x configuration register" start="+0x58" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MBURST" description="Memory burst transfer configuration" start="23" size="2" />
+      <BitField name="PBURST" description="Peripheral burst transfer configuration" start="21" size="2" />
+      <BitField name="ACK" description="ACK" start="20" size="1" />
+      <BitField name="CT" description="Current target (only in double buffer mode)" start="19" size="1" />
+      <BitField name="DBM" description="Double buffer mode" start="18" size="1" />
+      <BitField name="PL" description="Priority level" start="16" size="2" />
+      <BitField name="PINCOS" description="Peripheral increment offset size" start="15" size="1" />
+      <BitField name="MSIZE" description="Memory data size" start="13" size="2" />
+      <BitField name="PSIZE" description="Peripheral data size" start="11" size="2" />
+      <BitField name="MINC" description="Memory increment mode" start="10" size="1" />
+      <BitField name="PINC" description="Peripheral increment mode" start="9" size="1" />
+      <BitField name="CIRC" description="Circular mode" start="8" size="1" />
+      <BitField name="DIR" description="Data transfer direction" start="6" size="2" />
+      <BitField name="PFCTRL" description="Peripheral flow controller" start="5" size="1" />
+      <BitField name="TCIE" description="Transfer complete interrupt enable" start="4" size="1" />
+      <BitField name="HTIE" description="Half transfer interrupt enable" start="3" size="1" />
+      <BitField name="TEIE" description="Transfer error interrupt enable" start="2" size="1" />
+      <BitField name="DMEIE" description="Direct mode error interrupt enable" start="1" size="1" />
+      <BitField name="EN" description="Stream enable / flag stream ready when read low" start="0" size="1" />
+    </Register>
+    <Register name="S3NDTR" description="stream x number of data register" start="+0x5C" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="NDT" description="Number of data items to transfer" start="0" size="16" />
+    </Register>
+    <Register name="S3PAR" description="stream x peripheral address register" start="+0x60" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PA" description="Peripheral address" start="0" size="32" />
+    </Register>
+    <Register name="S3M0AR" description="stream x memory 0 address register" start="+0x64" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="M0A" description="Memory 0 address" start="0" size="32" />
+    </Register>
+    <Register name="S3M1AR" description="stream x memory 1 address register" start="+0x68" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="M1A" description="Memory 1 address (used in case of Double buffer mode)" start="0" size="32" />
+    </Register>
+    <Register name="S3FCR" description="stream x FIFO control register" start="+0x6C" size="4" reset_value="0x00000021" reset_mask="0xFFFFFFFF">
+      <BitField name="FEIE" description="FIFO error interrupt enable" start="7" size="1" access="Read/Write" />
+      <BitField name="FS" description="FIFO status" start="3" size="3" access="ReadOnly" />
+      <BitField name="DMDIS" description="Direct mode disable" start="2" size="1" access="Read/Write" />
+      <BitField name="FTH" description="FIFO threshold selection" start="0" size="2" access="Read/Write" />
+    </Register>
+    <Register name="S4CR" description="stream x configuration register" start="+0x70" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MBURST" description="Memory burst transfer configuration" start="23" size="2" />
+      <BitField name="PBURST" description="Peripheral burst transfer configuration" start="21" size="2" />
+      <BitField name="ACK" description="ACK" start="20" size="1" />
+      <BitField name="CT" description="Current target (only in double buffer mode)" start="19" size="1" />
+      <BitField name="DBM" description="Double buffer mode" start="18" size="1" />
+      <BitField name="PL" description="Priority level" start="16" size="2" />
+      <BitField name="PINCOS" description="Peripheral increment offset size" start="15" size="1" />
+      <BitField name="MSIZE" description="Memory data size" start="13" size="2" />
+      <BitField name="PSIZE" description="Peripheral data size" start="11" size="2" />
+      <BitField name="MINC" description="Memory increment mode" start="10" size="1" />
+      <BitField name="PINC" description="Peripheral increment mode" start="9" size="1" />
+      <BitField name="CIRC" description="Circular mode" start="8" size="1" />
+      <BitField name="DIR" description="Data transfer direction" start="6" size="2" />
+      <BitField name="PFCTRL" description="Peripheral flow controller" start="5" size="1" />
+      <BitField name="TCIE" description="Transfer complete interrupt enable" start="4" size="1" />
+      <BitField name="HTIE" description="Half transfer interrupt enable" start="3" size="1" />
+      <BitField name="TEIE" description="Transfer error interrupt enable" start="2" size="1" />
+      <BitField name="DMEIE" description="Direct mode error interrupt enable" start="1" size="1" />
+      <BitField name="EN" description="Stream enable / flag stream ready when read low" start="0" size="1" />
+    </Register>
+    <Register name="S4NDTR" description="stream x number of data register" start="+0x74" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="NDT" description="Number of data items to transfer" start="0" size="16" />
+    </Register>
+    <Register name="S4PAR" description="stream x peripheral address register" start="+0x78" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PA" description="Peripheral address" start="0" size="32" />
+    </Register>
+    <Register name="S4M0AR" description="stream x memory 0 address register" start="+0x7C" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="M0A" description="Memory 0 address" start="0" size="32" />
+    </Register>
+    <Register name="S4M1AR" description="stream x memory 1 address register" start="+0x80" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="M1A" description="Memory 1 address (used in case of Double buffer mode)" start="0" size="32" />
+    </Register>
+    <Register name="S4FCR" description="stream x FIFO control register" start="+0x84" size="4" reset_value="0x00000021" reset_mask="0xFFFFFFFF">
+      <BitField name="FEIE" description="FIFO error interrupt enable" start="7" size="1" access="Read/Write" />
+      <BitField name="FS" description="FIFO status" start="3" size="3" access="ReadOnly" />
+      <BitField name="DMDIS" description="Direct mode disable" start="2" size="1" access="Read/Write" />
+      <BitField name="FTH" description="FIFO threshold selection" start="0" size="2" access="Read/Write" />
+    </Register>
+    <Register name="S5CR" description="stream x configuration register" start="+0x88" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MBURST" description="Memory burst transfer configuration" start="23" size="2" />
+      <BitField name="PBURST" description="Peripheral burst transfer configuration" start="21" size="2" />
+      <BitField name="ACK" description="ACK" start="20" size="1" />
+      <BitField name="CT" description="Current target (only in double buffer mode)" start="19" size="1" />
+      <BitField name="DBM" description="Double buffer mode" start="18" size="1" />
+      <BitField name="PL" description="Priority level" start="16" size="2" />
+      <BitField name="PINCOS" description="Peripheral increment offset size" start="15" size="1" />
+      <BitField name="MSIZE" description="Memory data size" start="13" size="2" />
+      <BitField name="PSIZE" description="Peripheral data size" start="11" size="2" />
+      <BitField name="MINC" description="Memory increment mode" start="10" size="1" />
+      <BitField name="PINC" description="Peripheral increment mode" start="9" size="1" />
+      <BitField name="CIRC" description="Circular mode" start="8" size="1" />
+      <BitField name="DIR" description="Data transfer direction" start="6" size="2" />
+      <BitField name="PFCTRL" description="Peripheral flow controller" start="5" size="1" />
+      <BitField name="TCIE" description="Transfer complete interrupt enable" start="4" size="1" />
+      <BitField name="HTIE" description="Half transfer interrupt enable" start="3" size="1" />
+      <BitField name="TEIE" description="Transfer error interrupt enable" start="2" size="1" />
+      <BitField name="DMEIE" description="Direct mode error interrupt enable" start="1" size="1" />
+      <BitField name="EN" description="Stream enable / flag stream ready when read low" start="0" size="1" />
+    </Register>
+    <Register name="S5NDTR" description="stream x number of data register" start="+0x8C" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="NDT" description="Number of data items to transfer" start="0" size="16" />
+    </Register>
+    <Register name="S5PAR" description="stream x peripheral address register" start="+0x90" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PA" description="Peripheral address" start="0" size="32" />
+    </Register>
+    <Register name="S5M0AR" description="stream x memory 0 address register" start="+0x94" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="M0A" description="Memory 0 address" start="0" size="32" />
+    </Register>
+    <Register name="S5M1AR" description="stream x memory 1 address register" start="+0x98" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="M1A" description="Memory 1 address (used in case of Double buffer mode)" start="0" size="32" />
+    </Register>
+    <Register name="S5FCR" description="stream x FIFO control register" start="+0x9C" size="4" reset_value="0x00000021" reset_mask="0xFFFFFFFF">
+      <BitField name="FEIE" description="FIFO error interrupt enable" start="7" size="1" access="Read/Write" />
+      <BitField name="FS" description="FIFO status" start="3" size="3" access="ReadOnly" />
+      <BitField name="DMDIS" description="Direct mode disable" start="2" size="1" access="Read/Write" />
+      <BitField name="FTH" description="FIFO threshold selection" start="0" size="2" access="Read/Write" />
+    </Register>
+    <Register name="S6CR" description="stream x configuration register" start="+0xA0" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MBURST" description="Memory burst transfer configuration" start="23" size="2" />
+      <BitField name="PBURST" description="Peripheral burst transfer configuration" start="21" size="2" />
+      <BitField name="ACK" description="ACK" start="20" size="1" />
+      <BitField name="CT" description="Current target (only in double buffer mode)" start="19" size="1" />
+      <BitField name="DBM" description="Double buffer mode" start="18" size="1" />
+      <BitField name="PL" description="Priority level" start="16" size="2" />
+      <BitField name="PINCOS" description="Peripheral increment offset size" start="15" size="1" />
+      <BitField name="MSIZE" description="Memory data size" start="13" size="2" />
+      <BitField name="PSIZE" description="Peripheral data size" start="11" size="2" />
+      <BitField name="MINC" description="Memory increment mode" start="10" size="1" />
+      <BitField name="PINC" description="Peripheral increment mode" start="9" size="1" />
+      <BitField name="CIRC" description="Circular mode" start="8" size="1" />
+      <BitField name="DIR" description="Data transfer direction" start="6" size="2" />
+      <BitField name="PFCTRL" description="Peripheral flow controller" start="5" size="1" />
+      <BitField name="TCIE" description="Transfer complete interrupt enable" start="4" size="1" />
+      <BitField name="HTIE" description="Half transfer interrupt enable" start="3" size="1" />
+      <BitField name="TEIE" description="Transfer error interrupt enable" start="2" size="1" />
+      <BitField name="DMEIE" description="Direct mode error interrupt enable" start="1" size="1" />
+      <BitField name="EN" description="Stream enable / flag stream ready when read low" start="0" size="1" />
+    </Register>
+    <Register name="S6NDTR" description="stream x number of data register" start="+0xA4" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="NDT" description="Number of data items to transfer" start="0" size="16" />
+    </Register>
+    <Register name="S6PAR" description="stream x peripheral address register" start="+0xA8" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PA" description="Peripheral address" start="0" size="32" />
+    </Register>
+    <Register name="S6M0AR" description="stream x memory 0 address register" start="+0xAC" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="M0A" description="Memory 0 address" start="0" size="32" />
+    </Register>
+    <Register name="S6M1AR" description="stream x memory 1 address register" start="+0xB0" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="M1A" description="Memory 1 address (used in case of Double buffer mode)" start="0" size="32" />
+    </Register>
+    <Register name="S6FCR" description="stream x FIFO control register" start="+0xB4" size="4" reset_value="0x00000021" reset_mask="0xFFFFFFFF">
+      <BitField name="FEIE" description="FIFO error interrupt enable" start="7" size="1" access="Read/Write" />
+      <BitField name="FS" description="FIFO status" start="3" size="3" access="ReadOnly" />
+      <BitField name="DMDIS" description="Direct mode disable" start="2" size="1" access="Read/Write" />
+      <BitField name="FTH" description="FIFO threshold selection" start="0" size="2" access="Read/Write" />
+    </Register>
+    <Register name="S7CR" description="stream x configuration register" start="+0xB8" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MBURST" description="Memory burst transfer configuration" start="23" size="2" />
+      <BitField name="PBURST" description="Peripheral burst transfer configuration" start="21" size="2" />
+      <BitField name="ACK" description="ACK" start="20" size="1" />
+      <BitField name="CT" description="Current target (only in double buffer mode)" start="19" size="1" />
+      <BitField name="DBM" description="Double buffer mode" start="18" size="1" />
+      <BitField name="PL" description="Priority level" start="16" size="2" />
+      <BitField name="PINCOS" description="Peripheral increment offset size" start="15" size="1" />
+      <BitField name="MSIZE" description="Memory data size" start="13" size="2" />
+      <BitField name="PSIZE" description="Peripheral data size" start="11" size="2" />
+      <BitField name="MINC" description="Memory increment mode" start="10" size="1" />
+      <BitField name="PINC" description="Peripheral increment mode" start="9" size="1" />
+      <BitField name="CIRC" description="Circular mode" start="8" size="1" />
+      <BitField name="DIR" description="Data transfer direction" start="6" size="2" />
+      <BitField name="PFCTRL" description="Peripheral flow controller" start="5" size="1" />
+      <BitField name="TCIE" description="Transfer complete interrupt enable" start="4" size="1" />
+      <BitField name="HTIE" description="Half transfer interrupt enable" start="3" size="1" />
+      <BitField name="TEIE" description="Transfer error interrupt enable" start="2" size="1" />
+      <BitField name="DMEIE" description="Direct mode error interrupt enable" start="1" size="1" />
+      <BitField name="EN" description="Stream enable / flag stream ready when read low" start="0" size="1" />
+    </Register>
+    <Register name="S7NDTR" description="stream x number of data register" start="+0xBC" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="NDT" description="Number of data items to transfer" start="0" size="16" />
+    </Register>
+    <Register name="S7PAR" description="stream x peripheral address register" start="+0xC0" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PA" description="Peripheral address" start="0" size="32" />
+    </Register>
+    <Register name="S7M0AR" description="stream x memory 0 address register" start="+0xC4" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="M0A" description="Memory 0 address" start="0" size="32" />
+    </Register>
+    <Register name="S7M1AR" description="stream x memory 1 address register" start="+0xC8" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="M1A" description="Memory 1 address (used in case of Double buffer mode)" start="0" size="32" />
+    </Register>
+    <Register name="S7FCR" description="stream x FIFO control register" start="+0xCC" size="4" reset_value="0x00000021" reset_mask="0xFFFFFFFF">
+      <BitField name="FEIE" description="FIFO error interrupt enable" start="7" size="1" access="Read/Write" />
+      <BitField name="FS" description="FIFO status" start="3" size="3" access="ReadOnly" />
+      <BitField name="DMDIS" description="Direct mode disable" start="2" size="1" access="Read/Write" />
+      <BitField name="FTH" description="FIFO threshold selection" start="0" size="2" access="Read/Write" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="DMA2" description="DMA controller" start="0x40020400">
+    <Register name="LISR" description="low interrupt status register" start="+0x0" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TCIF3" description="Stream x transfer complete interrupt flag (x = 3..0)" start="27" size="1" />
+      <BitField name="HTIF3" description="Stream x half transfer interrupt flag (x=3..0)" start="26" size="1" />
+      <BitField name="TEIF3" description="Stream x transfer error interrupt flag (x=3..0)" start="25" size="1" />
+      <BitField name="DMEIF3" description="Stream x direct mode error interrupt flag (x=3..0)" start="24" size="1" />
+      <BitField name="FEIF3" description="Stream x FIFO error interrupt flag (x=3..0)" start="22" size="1" />
+      <BitField name="TCIF2" description="Stream x transfer complete interrupt flag (x = 3..0)" start="21" size="1" />
+      <BitField name="HTIF2" description="Stream x half transfer interrupt flag (x=3..0)" start="20" size="1" />
+      <BitField name="TEIF2" description="Stream x transfer error interrupt flag (x=3..0)" start="19" size="1" />
+      <BitField name="DMEIF2" description="Stream x direct mode error interrupt flag (x=3..0)" start="18" size="1" />
+      <BitField name="FEIF2" description="Stream x FIFO error interrupt flag (x=3..0)" start="16" size="1" />
+      <BitField name="TCIF1" description="Stream x transfer complete interrupt flag (x = 3..0)" start="11" size="1" />
+      <BitField name="HTIF1" description="Stream x half transfer interrupt flag (x=3..0)" start="10" size="1" />
+      <BitField name="TEIF1" description="Stream x transfer error interrupt flag (x=3..0)" start="9" size="1" />
+      <BitField name="DMEIF1" description="Stream x direct mode error interrupt flag (x=3..0)" start="8" size="1" />
+      <BitField name="FEIF1" description="Stream x FIFO error interrupt flag (x=3..0)" start="6" size="1" />
+      <BitField name="TCIF0" description="Stream x transfer complete interrupt flag (x = 3..0)" start="5" size="1" />
+      <BitField name="HTIF0" description="Stream x half transfer interrupt flag (x=3..0)" start="4" size="1" />
+      <BitField name="TEIF0" description="Stream x transfer error interrupt flag (x=3..0)" start="3" size="1" />
+      <BitField name="DMEIF0" description="Stream x direct mode error interrupt flag (x=3..0)" start="2" size="1" />
+      <BitField name="FEIF0" description="Stream x FIFO error interrupt flag (x=3..0)" start="0" size="1" />
+    </Register>
+    <Register name="HISR" description="high interrupt status register" start="+0x4" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TCIF7" description="Stream x transfer complete interrupt flag (x=7..4)" start="27" size="1" />
+      <BitField name="HTIF7" description="Stream x half transfer interrupt flag (x=7..4)" start="26" size="1" />
+      <BitField name="TEIF7" description="Stream x transfer error interrupt flag (x=7..4)" start="25" size="1" />
+      <BitField name="DMEIF7" description="Stream x direct mode error interrupt flag (x=7..4)" start="24" size="1" />
+      <BitField name="FEIF7" description="Stream x FIFO error interrupt flag (x=7..4)" start="22" size="1" />
+      <BitField name="TCIF6" description="Stream x transfer complete interrupt flag (x=7..4)" start="21" size="1" />
+      <BitField name="HTIF6" description="Stream x half transfer interrupt flag (x=7..4)" start="20" size="1" />
+      <BitField name="TEIF6" description="Stream x transfer error interrupt flag (x=7..4)" start="19" size="1" />
+      <BitField name="DMEIF6" description="Stream x direct mode error interrupt flag (x=7..4)" start="18" size="1" />
+      <BitField name="FEIF6" description="Stream x FIFO error interrupt flag (x=7..4)" start="16" size="1" />
+      <BitField name="TCIF5" description="Stream x transfer complete interrupt flag (x=7..4)" start="11" size="1" />
+      <BitField name="HTIF5" description="Stream x half transfer interrupt flag (x=7..4)" start="10" size="1" />
+      <BitField name="TEIF5" description="Stream x transfer error interrupt flag (x=7..4)" start="9" size="1" />
+      <BitField name="DMEIF5" description="Stream x direct mode error interrupt flag (x=7..4)" start="8" size="1" />
+      <BitField name="FEIF5" description="Stream x FIFO error interrupt flag (x=7..4)" start="6" size="1" />
+      <BitField name="TCIF4" description="Stream x transfer complete interrupt flag (x=7..4)" start="5" size="1" />
+      <BitField name="HTIF4" description="Stream x half transfer interrupt flag (x=7..4)" start="4" size="1" />
+      <BitField name="TEIF4" description="Stream x transfer error interrupt flag (x=7..4)" start="3" size="1" />
+      <BitField name="DMEIF4" description="Stream x direct mode error interrupt flag (x=7..4)" start="2" size="1" />
+      <BitField name="FEIF4" description="Stream x FIFO error interrupt flag (x=7..4)" start="0" size="1" />
+    </Register>
+    <Register name="LIFCR" description="low interrupt flag clear register" start="+0x8" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CTCIF3" description="Stream x clear transfer complete interrupt flag (x = 3..0)" start="27" size="1" />
+      <BitField name="CHTIF3" description="Stream x clear half transfer interrupt flag (x = 3..0)" start="26" size="1" />
+      <BitField name="CTEIF3" description="Stream x clear transfer error interrupt flag (x = 3..0)" start="25" size="1" />
+      <BitField name="CDMEIF3" description="Stream x clear direct mode error interrupt flag (x = 3..0)" start="24" size="1" />
+      <BitField name="CFEIF3" description="Stream x clear FIFO error interrupt flag (x = 3..0)" start="22" size="1" />
+      <BitField name="CTCIF2" description="Stream x clear transfer complete interrupt flag (x = 3..0)" start="21" size="1" />
+      <BitField name="CHTIF2" description="Stream x clear half transfer interrupt flag (x = 3..0)" start="20" size="1" />
+      <BitField name="CTEIF2" description="Stream x clear transfer error interrupt flag (x = 3..0)" start="19" size="1" />
+      <BitField name="CDMEIF2" description="Stream x clear direct mode error interrupt flag (x = 3..0)" start="18" size="1" />
+      <BitField name="CFEIF2" description="Stream x clear FIFO error interrupt flag (x = 3..0)" start="16" size="1" />
+      <BitField name="CTCIF1" description="Stream x clear transfer complete interrupt flag (x = 3..0)" start="11" size="1" />
+      <BitField name="CHTIF1" description="Stream x clear half transfer interrupt flag (x = 3..0)" start="10" size="1" />
+      <BitField name="CTEIF1" description="Stream x clear transfer error interrupt flag (x = 3..0)" start="9" size="1" />
+      <BitField name="CDMEIF1" description="Stream x clear direct mode error interrupt flag (x = 3..0)" start="8" size="1" />
+      <BitField name="CFEIF1" description="Stream x clear FIFO error interrupt flag (x = 3..0)" start="6" size="1" />
+      <BitField name="CTCIF0" description="Stream x clear transfer complete interrupt flag (x = 3..0)" start="5" size="1" />
+      <BitField name="CHTIF0" description="Stream x clear half transfer interrupt flag (x = 3..0)" start="4" size="1" />
+      <BitField name="CTEIF0" description="Stream x clear transfer error interrupt flag (x = 3..0)" start="3" size="1" />
+      <BitField name="CDMEIF0" description="Stream x clear direct mode error interrupt flag (x = 3..0)" start="2" size="1" />
+      <BitField name="CFEIF0" description="Stream x clear FIFO error interrupt flag (x = 3..0)" start="0" size="1" />
+    </Register>
+    <Register name="HIFCR" description="high interrupt flag clear register" start="+0xC" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CTCIF7" description="Stream x clear transfer complete interrupt flag (x = 7..4)" start="27" size="1" />
+      <BitField name="CHTIF7" description="Stream x clear half transfer interrupt flag (x = 7..4)" start="26" size="1" />
+      <BitField name="CTEIF7" description="Stream x clear transfer error interrupt flag (x = 7..4)" start="25" size="1" />
+      <BitField name="CDMEIF7" description="Stream x clear direct mode error interrupt flag (x = 7..4)" start="24" size="1" />
+      <BitField name="CFEIF7" description="Stream x clear FIFO error interrupt flag (x = 7..4)" start="22" size="1" />
+      <BitField name="CTCIF6" description="Stream x clear transfer complete interrupt flag (x = 7..4)" start="21" size="1" />
+      <BitField name="CHTIF6" description="Stream x clear half transfer interrupt flag (x = 7..4)" start="20" size="1" />
+      <BitField name="CTEIF6" description="Stream x clear transfer error interrupt flag (x = 7..4)" start="19" size="1" />
+      <BitField name="CDMEIF6" description="Stream x clear direct mode error interrupt flag (x = 7..4)" start="18" size="1" />
+      <BitField name="CFEIF6" description="Stream x clear FIFO error interrupt flag (x = 7..4)" start="16" size="1" />
+      <BitField name="CTCIF5" description="Stream x clear transfer complete interrupt flag (x = 7..4)" start="11" size="1" />
+      <BitField name="CHTIF5" description="Stream x clear half transfer interrupt flag (x = 7..4)" start="10" size="1" />
+      <BitField name="CTEIF5" description="Stream x clear transfer error interrupt flag (x = 7..4)" start="9" size="1" />
+      <BitField name="CDMEIF5" description="Stream x clear direct mode error interrupt flag (x = 7..4)" start="8" size="1" />
+      <BitField name="CFEIF5" description="Stream x clear FIFO error interrupt flag (x = 7..4)" start="6" size="1" />
+      <BitField name="CTCIF4" description="Stream x clear transfer complete interrupt flag (x = 7..4)" start="5" size="1" />
+      <BitField name="CHTIF4" description="Stream x clear half transfer interrupt flag (x = 7..4)" start="4" size="1" />
+      <BitField name="CTEIF4" description="Stream x clear transfer error interrupt flag (x = 7..4)" start="3" size="1" />
+      <BitField name="CDMEIF4" description="Stream x clear direct mode error interrupt flag (x = 7..4)" start="2" size="1" />
+      <BitField name="CFEIF4" description="Stream x clear FIFO error interrupt flag (x = 7..4)" start="0" size="1" />
+    </Register>
+    <Register name="S0CR" description="stream x configuration register" start="+0x10" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MBURST" description="Memory burst transfer configuration" start="23" size="2" />
+      <BitField name="PBURST" description="Peripheral burst transfer configuration" start="21" size="2" />
+      <BitField name="CT" description="Current target (only in double buffer mode)" start="19" size="1" />
+      <BitField name="DBM" description="Double buffer mode" start="18" size="1" />
+      <BitField name="PL" description="Priority level" start="16" size="2" />
+      <BitField name="PINCOS" description="Peripheral increment offset size" start="15" size="1" />
+      <BitField name="MSIZE" description="Memory data size" start="13" size="2" />
+      <BitField name="PSIZE" description="Peripheral data size" start="11" size="2" />
+      <BitField name="MINC" description="Memory increment mode" start="10" size="1" />
+      <BitField name="PINC" description="Peripheral increment mode" start="9" size="1" />
+      <BitField name="CIRC" description="Circular mode" start="8" size="1" />
+      <BitField name="DIR" description="Data transfer direction" start="6" size="2" />
+      <BitField name="PFCTRL" description="Peripheral flow controller" start="5" size="1" />
+      <BitField name="TCIE" description="Transfer complete interrupt enable" start="4" size="1" />
+      <BitField name="HTIE" description="Half transfer interrupt enable" start="3" size="1" />
+      <BitField name="TEIE" description="Transfer error interrupt enable" start="2" size="1" />
+      <BitField name="DMEIE" description="Direct mode error interrupt enable" start="1" size="1" />
+      <BitField name="EN" description="Stream enable / flag stream ready when read low" start="0" size="1" />
+    </Register>
+    <Register name="S0NDTR" description="stream x number of data register" start="+0x14" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="NDT" description="Number of data items to transfer" start="0" size="16" />
+    </Register>
+    <Register name="S0PAR" description="stream x peripheral address register" start="+0x18" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PA" description="Peripheral address" start="0" size="32" />
+    </Register>
+    <Register name="S0M0AR" description="stream x memory 0 address register" start="+0x1C" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="M0A" description="Memory 0 address" start="0" size="32" />
+    </Register>
+    <Register name="S0M1AR" description="stream x memory 1 address register" start="+0x20" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="M1A" description="Memory 1 address (used in case of Double buffer mode)" start="0" size="32" />
+    </Register>
+    <Register name="S0FCR" description="stream x FIFO control register" start="+0x24" size="4" reset_value="0x00000021" reset_mask="0xFFFFFFFF">
+      <BitField name="FEIE" description="FIFO error interrupt enable" start="7" size="1" access="Read/Write" />
+      <BitField name="FS" description="FIFO status" start="3" size="3" access="ReadOnly" />
+      <BitField name="DMDIS" description="Direct mode disable" start="2" size="1" access="Read/Write" />
+      <BitField name="FTH" description="FIFO threshold selection" start="0" size="2" access="Read/Write" />
+    </Register>
+    <Register name="S1CR" description="stream x configuration register" start="+0x28" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MBURST" description="Memory burst transfer configuration" start="23" size="2" />
+      <BitField name="PBURST" description="Peripheral burst transfer configuration" start="21" size="2" />
+      <BitField name="ACK" description="ACK" start="20" size="1" />
+      <BitField name="CT" description="Current target (only in double buffer mode)" start="19" size="1" />
+      <BitField name="DBM" description="Double buffer mode" start="18" size="1" />
+      <BitField name="PL" description="Priority level" start="16" size="2" />
+      <BitField name="PINCOS" description="Peripheral increment offset size" start="15" size="1" />
+      <BitField name="MSIZE" description="Memory data size" start="13" size="2" />
+      <BitField name="PSIZE" description="Peripheral data size" start="11" size="2" />
+      <BitField name="MINC" description="Memory increment mode" start="10" size="1" />
+      <BitField name="PINC" description="Peripheral increment mode" start="9" size="1" />
+      <BitField name="CIRC" description="Circular mode" start="8" size="1" />
+      <BitField name="DIR" description="Data transfer direction" start="6" size="2" />
+      <BitField name="PFCTRL" description="Peripheral flow controller" start="5" size="1" />
+      <BitField name="TCIE" description="Transfer complete interrupt enable" start="4" size="1" />
+      <BitField name="HTIE" description="Half transfer interrupt enable" start="3" size="1" />
+      <BitField name="TEIE" description="Transfer error interrupt enable" start="2" size="1" />
+      <BitField name="DMEIE" description="Direct mode error interrupt enable" start="1" size="1" />
+      <BitField name="EN" description="Stream enable / flag stream ready when read low" start="0" size="1" />
+    </Register>
+    <Register name="S1NDTR" description="stream x number of data register" start="+0x2C" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="NDT" description="Number of data items to transfer" start="0" size="16" />
+    </Register>
+    <Register name="S1PAR" description="stream x peripheral address register" start="+0x30" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PA" description="Peripheral address" start="0" size="32" />
+    </Register>
+    <Register name="S1M0AR" description="stream x memory 0 address register" start="+0x34" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="M0A" description="Memory 0 address" start="0" size="32" />
+    </Register>
+    <Register name="S1M1AR" description="stream x memory 1 address register" start="+0x38" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="M1A" description="Memory 1 address (used in case of Double buffer mode)" start="0" size="32" />
+    </Register>
+    <Register name="S1FCR" description="stream x FIFO control register" start="+0x3C" size="4" reset_value="0x00000021" reset_mask="0xFFFFFFFF">
+      <BitField name="FEIE" description="FIFO error interrupt enable" start="7" size="1" access="Read/Write" />
+      <BitField name="FS" description="FIFO status" start="3" size="3" access="ReadOnly" />
+      <BitField name="DMDIS" description="Direct mode disable" start="2" size="1" access="Read/Write" />
+      <BitField name="FTH" description="FIFO threshold selection" start="0" size="2" access="Read/Write" />
+    </Register>
+    <Register name="S2CR" description="stream x configuration register" start="+0x40" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MBURST" description="Memory burst transfer configuration" start="23" size="2" />
+      <BitField name="PBURST" description="Peripheral burst transfer configuration" start="21" size="2" />
+      <BitField name="ACK" description="ACK" start="20" size="1" />
+      <BitField name="CT" description="Current target (only in double buffer mode)" start="19" size="1" />
+      <BitField name="DBM" description="Double buffer mode" start="18" size="1" />
+      <BitField name="PL" description="Priority level" start="16" size="2" />
+      <BitField name="PINCOS" description="Peripheral increment offset size" start="15" size="1" />
+      <BitField name="MSIZE" description="Memory data size" start="13" size="2" />
+      <BitField name="PSIZE" description="Peripheral data size" start="11" size="2" />
+      <BitField name="MINC" description="Memory increment mode" start="10" size="1" />
+      <BitField name="PINC" description="Peripheral increment mode" start="9" size="1" />
+      <BitField name="CIRC" description="Circular mode" start="8" size="1" />
+      <BitField name="DIR" description="Data transfer direction" start="6" size="2" />
+      <BitField name="PFCTRL" description="Peripheral flow controller" start="5" size="1" />
+      <BitField name="TCIE" description="Transfer complete interrupt enable" start="4" size="1" />
+      <BitField name="HTIE" description="Half transfer interrupt enable" start="3" size="1" />
+      <BitField name="TEIE" description="Transfer error interrupt enable" start="2" size="1" />
+      <BitField name="DMEIE" description="Direct mode error interrupt enable" start="1" size="1" />
+      <BitField name="EN" description="Stream enable / flag stream ready when read low" start="0" size="1" />
+    </Register>
+    <Register name="S2NDTR" description="stream x number of data register" start="+0x44" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="NDT" description="Number of data items to transfer" start="0" size="16" />
+    </Register>
+    <Register name="S2PAR" description="stream x peripheral address register" start="+0x48" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PA" description="Peripheral address" start="0" size="32" />
+    </Register>
+    <Register name="S2M0AR" description="stream x memory 0 address register" start="+0x4C" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="M0A" description="Memory 0 address" start="0" size="32" />
+    </Register>
+    <Register name="S2M1AR" description="stream x memory 1 address register" start="+0x50" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="M1A" description="Memory 1 address (used in case of Double buffer mode)" start="0" size="32" />
+    </Register>
+    <Register name="S2FCR" description="stream x FIFO control register" start="+0x54" size="4" reset_value="0x00000021" reset_mask="0xFFFFFFFF">
+      <BitField name="FEIE" description="FIFO error interrupt enable" start="7" size="1" access="Read/Write" />
+      <BitField name="FS" description="FIFO status" start="3" size="3" access="ReadOnly" />
+      <BitField name="DMDIS" description="Direct mode disable" start="2" size="1" access="Read/Write" />
+      <BitField name="FTH" description="FIFO threshold selection" start="0" size="2" access="Read/Write" />
+    </Register>
+    <Register name="S3CR" description="stream x configuration register" start="+0x58" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MBURST" description="Memory burst transfer configuration" start="23" size="2" />
+      <BitField name="PBURST" description="Peripheral burst transfer configuration" start="21" size="2" />
+      <BitField name="ACK" description="ACK" start="20" size="1" />
+      <BitField name="CT" description="Current target (only in double buffer mode)" start="19" size="1" />
+      <BitField name="DBM" description="Double buffer mode" start="18" size="1" />
+      <BitField name="PL" description="Priority level" start="16" size="2" />
+      <BitField name="PINCOS" description="Peripheral increment offset size" start="15" size="1" />
+      <BitField name="MSIZE" description="Memory data size" start="13" size="2" />
+      <BitField name="PSIZE" description="Peripheral data size" start="11" size="2" />
+      <BitField name="MINC" description="Memory increment mode" start="10" size="1" />
+      <BitField name="PINC" description="Peripheral increment mode" start="9" size="1" />
+      <BitField name="CIRC" description="Circular mode" start="8" size="1" />
+      <BitField name="DIR" description="Data transfer direction" start="6" size="2" />
+      <BitField name="PFCTRL" description="Peripheral flow controller" start="5" size="1" />
+      <BitField name="TCIE" description="Transfer complete interrupt enable" start="4" size="1" />
+      <BitField name="HTIE" description="Half transfer interrupt enable" start="3" size="1" />
+      <BitField name="TEIE" description="Transfer error interrupt enable" start="2" size="1" />
+      <BitField name="DMEIE" description="Direct mode error interrupt enable" start="1" size="1" />
+      <BitField name="EN" description="Stream enable / flag stream ready when read low" start="0" size="1" />
+    </Register>
+    <Register name="S3NDTR" description="stream x number of data register" start="+0x5C" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="NDT" description="Number of data items to transfer" start="0" size="16" />
+    </Register>
+    <Register name="S3PAR" description="stream x peripheral address register" start="+0x60" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PA" description="Peripheral address" start="0" size="32" />
+    </Register>
+    <Register name="S3M0AR" description="stream x memory 0 address register" start="+0x64" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="M0A" description="Memory 0 address" start="0" size="32" />
+    </Register>
+    <Register name="S3M1AR" description="stream x memory 1 address register" start="+0x68" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="M1A" description="Memory 1 address (used in case of Double buffer mode)" start="0" size="32" />
+    </Register>
+    <Register name="S3FCR" description="stream x FIFO control register" start="+0x6C" size="4" reset_value="0x00000021" reset_mask="0xFFFFFFFF">
+      <BitField name="FEIE" description="FIFO error interrupt enable" start="7" size="1" access="Read/Write" />
+      <BitField name="FS" description="FIFO status" start="3" size="3" access="ReadOnly" />
+      <BitField name="DMDIS" description="Direct mode disable" start="2" size="1" access="Read/Write" />
+      <BitField name="FTH" description="FIFO threshold selection" start="0" size="2" access="Read/Write" />
+    </Register>
+    <Register name="S4CR" description="stream x configuration register" start="+0x70" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MBURST" description="Memory burst transfer configuration" start="23" size="2" />
+      <BitField name="PBURST" description="Peripheral burst transfer configuration" start="21" size="2" />
+      <BitField name="ACK" description="ACK" start="20" size="1" />
+      <BitField name="CT" description="Current target (only in double buffer mode)" start="19" size="1" />
+      <BitField name="DBM" description="Double buffer mode" start="18" size="1" />
+      <BitField name="PL" description="Priority level" start="16" size="2" />
+      <BitField name="PINCOS" description="Peripheral increment offset size" start="15" size="1" />
+      <BitField name="MSIZE" description="Memory data size" start="13" size="2" />
+      <BitField name="PSIZE" description="Peripheral data size" start="11" size="2" />
+      <BitField name="MINC" description="Memory increment mode" start="10" size="1" />
+      <BitField name="PINC" description="Peripheral increment mode" start="9" size="1" />
+      <BitField name="CIRC" description="Circular mode" start="8" size="1" />
+      <BitField name="DIR" description="Data transfer direction" start="6" size="2" />
+      <BitField name="PFCTRL" description="Peripheral flow controller" start="5" size="1" />
+      <BitField name="TCIE" description="Transfer complete interrupt enable" start="4" size="1" />
+      <BitField name="HTIE" description="Half transfer interrupt enable" start="3" size="1" />
+      <BitField name="TEIE" description="Transfer error interrupt enable" start="2" size="1" />
+      <BitField name="DMEIE" description="Direct mode error interrupt enable" start="1" size="1" />
+      <BitField name="EN" description="Stream enable / flag stream ready when read low" start="0" size="1" />
+    </Register>
+    <Register name="S4NDTR" description="stream x number of data register" start="+0x74" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="NDT" description="Number of data items to transfer" start="0" size="16" />
+    </Register>
+    <Register name="S4PAR" description="stream x peripheral address register" start="+0x78" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PA" description="Peripheral address" start="0" size="32" />
+    </Register>
+    <Register name="S4M0AR" description="stream x memory 0 address register" start="+0x7C" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="M0A" description="Memory 0 address" start="0" size="32" />
+    </Register>
+    <Register name="S4M1AR" description="stream x memory 1 address register" start="+0x80" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="M1A" description="Memory 1 address (used in case of Double buffer mode)" start="0" size="32" />
+    </Register>
+    <Register name="S4FCR" description="stream x FIFO control register" start="+0x84" size="4" reset_value="0x00000021" reset_mask="0xFFFFFFFF">
+      <BitField name="FEIE" description="FIFO error interrupt enable" start="7" size="1" access="Read/Write" />
+      <BitField name="FS" description="FIFO status" start="3" size="3" access="ReadOnly" />
+      <BitField name="DMDIS" description="Direct mode disable" start="2" size="1" access="Read/Write" />
+      <BitField name="FTH" description="FIFO threshold selection" start="0" size="2" access="Read/Write" />
+    </Register>
+    <Register name="S5CR" description="stream x configuration register" start="+0x88" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MBURST" description="Memory burst transfer configuration" start="23" size="2" />
+      <BitField name="PBURST" description="Peripheral burst transfer configuration" start="21" size="2" />
+      <BitField name="ACK" description="ACK" start="20" size="1" />
+      <BitField name="CT" description="Current target (only in double buffer mode)" start="19" size="1" />
+      <BitField name="DBM" description="Double buffer mode" start="18" size="1" />
+      <BitField name="PL" description="Priority level" start="16" size="2" />
+      <BitField name="PINCOS" description="Peripheral increment offset size" start="15" size="1" />
+      <BitField name="MSIZE" description="Memory data size" start="13" size="2" />
+      <BitField name="PSIZE" description="Peripheral data size" start="11" size="2" />
+      <BitField name="MINC" description="Memory increment mode" start="10" size="1" />
+      <BitField name="PINC" description="Peripheral increment mode" start="9" size="1" />
+      <BitField name="CIRC" description="Circular mode" start="8" size="1" />
+      <BitField name="DIR" description="Data transfer direction" start="6" size="2" />
+      <BitField name="PFCTRL" description="Peripheral flow controller" start="5" size="1" />
+      <BitField name="TCIE" description="Transfer complete interrupt enable" start="4" size="1" />
+      <BitField name="HTIE" description="Half transfer interrupt enable" start="3" size="1" />
+      <BitField name="TEIE" description="Transfer error interrupt enable" start="2" size="1" />
+      <BitField name="DMEIE" description="Direct mode error interrupt enable" start="1" size="1" />
+      <BitField name="EN" description="Stream enable / flag stream ready when read low" start="0" size="1" />
+    </Register>
+    <Register name="S5NDTR" description="stream x number of data register" start="+0x8C" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="NDT" description="Number of data items to transfer" start="0" size="16" />
+    </Register>
+    <Register name="S5PAR" description="stream x peripheral address register" start="+0x90" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PA" description="Peripheral address" start="0" size="32" />
+    </Register>
+    <Register name="S5M0AR" description="stream x memory 0 address register" start="+0x94" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="M0A" description="Memory 0 address" start="0" size="32" />
+    </Register>
+    <Register name="S5M1AR" description="stream x memory 1 address register" start="+0x98" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="M1A" description="Memory 1 address (used in case of Double buffer mode)" start="0" size="32" />
+    </Register>
+    <Register name="S5FCR" description="stream x FIFO control register" start="+0x9C" size="4" reset_value="0x00000021" reset_mask="0xFFFFFFFF">
+      <BitField name="FEIE" description="FIFO error interrupt enable" start="7" size="1" access="Read/Write" />
+      <BitField name="FS" description="FIFO status" start="3" size="3" access="ReadOnly" />
+      <BitField name="DMDIS" description="Direct mode disable" start="2" size="1" access="Read/Write" />
+      <BitField name="FTH" description="FIFO threshold selection" start="0" size="2" access="Read/Write" />
+    </Register>
+    <Register name="S6CR" description="stream x configuration register" start="+0xA0" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MBURST" description="Memory burst transfer configuration" start="23" size="2" />
+      <BitField name="PBURST" description="Peripheral burst transfer configuration" start="21" size="2" />
+      <BitField name="ACK" description="ACK" start="20" size="1" />
+      <BitField name="CT" description="Current target (only in double buffer mode)" start="19" size="1" />
+      <BitField name="DBM" description="Double buffer mode" start="18" size="1" />
+      <BitField name="PL" description="Priority level" start="16" size="2" />
+      <BitField name="PINCOS" description="Peripheral increment offset size" start="15" size="1" />
+      <BitField name="MSIZE" description="Memory data size" start="13" size="2" />
+      <BitField name="PSIZE" description="Peripheral data size" start="11" size="2" />
+      <BitField name="MINC" description="Memory increment mode" start="10" size="1" />
+      <BitField name="PINC" description="Peripheral increment mode" start="9" size="1" />
+      <BitField name="CIRC" description="Circular mode" start="8" size="1" />
+      <BitField name="DIR" description="Data transfer direction" start="6" size="2" />
+      <BitField name="PFCTRL" description="Peripheral flow controller" start="5" size="1" />
+      <BitField name="TCIE" description="Transfer complete interrupt enable" start="4" size="1" />
+      <BitField name="HTIE" description="Half transfer interrupt enable" start="3" size="1" />
+      <BitField name="TEIE" description="Transfer error interrupt enable" start="2" size="1" />
+      <BitField name="DMEIE" description="Direct mode error interrupt enable" start="1" size="1" />
+      <BitField name="EN" description="Stream enable / flag stream ready when read low" start="0" size="1" />
+    </Register>
+    <Register name="S6NDTR" description="stream x number of data register" start="+0xA4" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="NDT" description="Number of data items to transfer" start="0" size="16" />
+    </Register>
+    <Register name="S6PAR" description="stream x peripheral address register" start="+0xA8" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PA" description="Peripheral address" start="0" size="32" />
+    </Register>
+    <Register name="S6M0AR" description="stream x memory 0 address register" start="+0xAC" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="M0A" description="Memory 0 address" start="0" size="32" />
+    </Register>
+    <Register name="S6M1AR" description="stream x memory 1 address register" start="+0xB0" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="M1A" description="Memory 1 address (used in case of Double buffer mode)" start="0" size="32" />
+    </Register>
+    <Register name="S6FCR" description="stream x FIFO control register" start="+0xB4" size="4" reset_value="0x00000021" reset_mask="0xFFFFFFFF">
+      <BitField name="FEIE" description="FIFO error interrupt enable" start="7" size="1" access="Read/Write" />
+      <BitField name="FS" description="FIFO status" start="3" size="3" access="ReadOnly" />
+      <BitField name="DMDIS" description="Direct mode disable" start="2" size="1" access="Read/Write" />
+      <BitField name="FTH" description="FIFO threshold selection" start="0" size="2" access="Read/Write" />
+    </Register>
+    <Register name="S7CR" description="stream x configuration register" start="+0xB8" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MBURST" description="Memory burst transfer configuration" start="23" size="2" />
+      <BitField name="PBURST" description="Peripheral burst transfer configuration" start="21" size="2" />
+      <BitField name="ACK" description="ACK" start="20" size="1" />
+      <BitField name="CT" description="Current target (only in double buffer mode)" start="19" size="1" />
+      <BitField name="DBM" description="Double buffer mode" start="18" size="1" />
+      <BitField name="PL" description="Priority level" start="16" size="2" />
+      <BitField name="PINCOS" description="Peripheral increment offset size" start="15" size="1" />
+      <BitField name="MSIZE" description="Memory data size" start="13" size="2" />
+      <BitField name="PSIZE" description="Peripheral data size" start="11" size="2" />
+      <BitField name="MINC" description="Memory increment mode" start="10" size="1" />
+      <BitField name="PINC" description="Peripheral increment mode" start="9" size="1" />
+      <BitField name="CIRC" description="Circular mode" start="8" size="1" />
+      <BitField name="DIR" description="Data transfer direction" start="6" size="2" />
+      <BitField name="PFCTRL" description="Peripheral flow controller" start="5" size="1" />
+      <BitField name="TCIE" description="Transfer complete interrupt enable" start="4" size="1" />
+      <BitField name="HTIE" description="Half transfer interrupt enable" start="3" size="1" />
+      <BitField name="TEIE" description="Transfer error interrupt enable" start="2" size="1" />
+      <BitField name="DMEIE" description="Direct mode error interrupt enable" start="1" size="1" />
+      <BitField name="EN" description="Stream enable / flag stream ready when read low" start="0" size="1" />
+    </Register>
+    <Register name="S7NDTR" description="stream x number of data register" start="+0xBC" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="NDT" description="Number of data items to transfer" start="0" size="16" />
+    </Register>
+    <Register name="S7PAR" description="stream x peripheral address register" start="+0xC0" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PA" description="Peripheral address" start="0" size="32" />
+    </Register>
+    <Register name="S7M0AR" description="stream x memory 0 address register" start="+0xC4" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="M0A" description="Memory 0 address" start="0" size="32" />
+    </Register>
+    <Register name="S7M1AR" description="stream x memory 1 address register" start="+0xC8" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="M1A" description="Memory 1 address (used in case of Double buffer mode)" start="0" size="32" />
+    </Register>
+    <Register name="S7FCR" description="stream x FIFO control register" start="+0xCC" size="4" reset_value="0x00000021" reset_mask="0xFFFFFFFF">
+      <BitField name="FEIE" description="FIFO error interrupt enable" start="7" size="1" access="Read/Write" />
+      <BitField name="FS" description="FIFO status" start="3" size="3" access="ReadOnly" />
+      <BitField name="DMDIS" description="Direct mode disable" start="2" size="1" access="Read/Write" />
+      <BitField name="FTH" description="FIFO threshold selection" start="0" size="2" access="Read/Write" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="DMA2D" description="DMA2D" start="0x52001000">
+    <Register name="CR" description="DMA2D control register" start="+0x0" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="START" description="Start This bit can be used to launch the DMA2D according to the parameters loaded in the various configuration registers" start="0" size="1" />
+      <BitField name="SUSP" description="Suspend This bit can be used to suspend the current transfer. This bit is set and reset by software. It is automatically reset by hardware when the START bit is reset." start="1" size="1" />
+      <BitField name="ABORT" description="Abort This bit can be used to abort the current transfer. This bit is set by software and is automatically reset by hardware when the START bit is reset." start="2" size="1" />
+      <BitField name="TEIE" description="Transfer error interrupt enable This bit is set and cleared by software." start="8" size="1" />
+      <BitField name="TCIE" description="Transfer complete interrupt enable This bit is set and cleared by software." start="9" size="1" />
+      <BitField name="TWIE" description="Transfer watermark interrupt enable This bit is set and cleared by software." start="10" size="1" />
+      <BitField name="CAEIE" description="CLUT access error interrupt enable This bit is set and cleared by software." start="11" size="1" />
+      <BitField name="CTCIE" description="CLUT transfer complete interrupt enable This bit is set and cleared by software." start="12" size="1" />
+      <BitField name="CEIE" description="Configuration Error Interrupt Enable This bit is set and cleared by software." start="13" size="1" />
+      <BitField name="MODE" description="DMA2D mode This bit is set and cleared by software. It cannot be modified while a transfer is ongoing." start="16" size="2" />
+    </Register>
+    <Register name="ISR" description="DMA2D Interrupt Status Register" start="+0x4" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TEIF" description="Transfer error interrupt flag This bit is set when an error occurs during a DMA transfer (data transfer or automatic CLUT loading)." start="0" size="1" />
+      <BitField name="TCIF" description="Transfer complete interrupt flag This bit is set when a DMA2D transfer operation is complete (data transfer only)." start="1" size="1" />
+      <BitField name="TWIF" description="Transfer watermark interrupt flag This bit is set when the last pixel of the watermarked line has been transferred." start="2" size="1" />
+      <BitField name="CAEIF" description="CLUT access error interrupt flag This bit is set when the CPU accesses the CLUT while the CLUT is being automatically copied from a system memory to the internal DMA2D." start="3" size="1" />
+      <BitField name="CTCIF" description="CLUT transfer complete interrupt flag This bit is set when the CLUT copy from a system memory area to the internal DMA2D memory is complete." start="4" size="1" />
+      <BitField name="CEIF" description="Configuration error interrupt flag This bit is set when the START bit of DMA2D_CR, DMA2DFGPFCCR or DMA2D_BGPFCCR is set and a wrong configuration has been programmed." start="5" size="1" />
+    </Register>
+    <Register name="IFCR" description="DMA2D interrupt flag clear register" start="+0x8" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CTEIF" description="Clear Transfer error interrupt flag Programming this bit to 1 clears the TEIF flag in the DMA2D_ISR register" start="0" size="1" />
+      <BitField name="CTCIF" description="Clear transfer complete interrupt flag Programming this bit to 1 clears the TCIF flag in the DMA2D_ISR register" start="1" size="1" />
+      <BitField name="CTWIF" description="Clear transfer watermark interrupt flag Programming this bit to 1 clears the TWIF flag in the DMA2D_ISR register" start="2" size="1" />
+      <BitField name="CAECIF" description="Clear CLUT access error interrupt flag Programming this bit to 1 clears the CAEIF flag in the DMA2D_ISR register" start="3" size="1" />
+      <BitField name="CCTCIF" description="Clear CLUT transfer complete interrupt flag Programming this bit to 1 clears the CTCIF flag in the DMA2D_ISR register" start="4" size="1" />
+      <BitField name="CCEIF" description="Clear configuration error interrupt flag Programming this bit to 1 clears the CEIF flag in the DMA2D_ISR register" start="5" size="1" />
+    </Register>
+    <Register name="FGMAR" description="DMA2D foreground memory address register" start="+0xC" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MA" description="Memory address Address of the data used for the foreground image. This register can only be written when data transfers are disabled. Once the data transfer has started, this register is read-only. The address alignment must match the image format selected e.g. a 32-bit per pixel format must be 32-bit aligned, a 16-bit per pixel format must be 16-bit aligned and a 4-bit per pixel format must be 8-bit aligned." start="0" size="32" />
+    </Register>
+    <Register name="FGOR" description="DMA2D foreground offset register" start="+0x10" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset Line offset used for the foreground expressed in pixel. This value is used to generate the address. It is added at the end of each line to determine the starting address of the next line. These bits can only be written when data transfers are disabled. Once a data transfer has started, they become read-only. If the image format is 4-bit per pixel, the line offset must be even." start="0" size="14" />
+    </Register>
+    <Register name="BGMAR" description="DMA2D background memory address register" start="+0x14" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MA" description="Memory address Address of the data used for the background image. This register can only be written when data transfers are disabled. Once a data transfer has started, this register is read-only. The address alignment must match the image format selected e.g. a 32-bit per pixel format must be 32-bit aligned, a 16-bit per pixel format must be 16-bit aligned and a 4-bit per pixel format must be 8-bit aligned." start="0" size="32" />
+    </Register>
+    <Register name="BGOR" description="DMA2D background offset register" start="+0x18" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line offset Line offset used for the background image (expressed in pixel). This value is used for the address generation. It is added at the end of each line to determine the starting address of the next line. These bits can only be written when data transfers are disabled. Once data transfer has started, they become read-only. If the image format is 4-bit per pixel, the line offset must be even." start="0" size="14" />
+    </Register>
+    <Register name="FGPFCCR" description="DMA2D foreground PFC control register" start="+0x1C" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CM" description="Color mode These bits defines the color format of the foreground image. They can only be written when data transfers are disabled. Once the transfer has started, they are read-only. others: meaningless" start="0" size="4" />
+      <BitField name="CCM" description="CLUT color mode This bit defines the color format of the CLUT. It can only be written when the transfer is disabled. Once the CLUT transfer has started, this bit is read-only." start="4" size="1" />
+      <BitField name="START" description="Start This bit can be set to start the automatic loading of the CLUT. It is automatically reset: ** at the end of the transfer ** when the transfer is aborted by the user application by setting the ABORT bit in DMA2D_CR ** when a transfer error occurs ** when the transfer has not started due to a configuration error or another transfer operation already ongoing (data transfer or automatic background CLUT transfer)." start="5" size="1" />
+      <BitField name="CS" description="CLUT size These bits define the size of the CLUT used for the foreground image. Once the CLUT transfer has started, this field is read-only. The number of CLUT entries is equal to CS[7:0] + 1." start="8" size="8" />
+      <BitField name="AM" description="Alpha mode These bits select the alpha channel value to be used for the foreground image. They can only be written data the transfer are disabled. Once the transfer has started, they become read-only. other configurations are meaningless" start="16" size="2" />
+      <BitField name="CSS" description="Chroma Sub-Sampling These bits define the chroma sub-sampling mode for YCbCr color mode. Once the transfer has started, these bits are read-only. others: meaningless" start="18" size="2" />
+      <BitField name="AI" description="Alpha Inverted This bit inverts the alpha value. Once the transfer has started, this bit is read-only." start="20" size="1" />
+      <BitField name="RBS" description="Red Blue Swap This bit allows to swap the R &amp;amp; B to support BGR or ABGR color formats. Once the transfer has started, this bit is read-only." start="21" size="1" />
+      <BitField name="ALPHA" description="Alpha value These bits define a fixed alpha channel value which can replace the original alpha value or be multiplied by the original alpha value according to the alpha mode selected through the AM[1:0] bits. These bits can only be written when data transfers are disabled. Once a transfer has started, they become read-only." start="24" size="8" />
+    </Register>
+    <Register name="FGCOLR" description="DMA2D foreground color register" start="+0x20" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BLUE" description="Blue Value These bits defines the blue value for the A4 or A8 mode of the foreground image. They can only be written when data transfers are disabled. Once the transfer has started, They are read-only." start="0" size="8" />
+      <BitField name="GREEN" description="Green Value These bits defines the green value for the A4 or A8 mode of the foreground image. They can only be written when data transfers are disabled. Once the transfer has started, They are read-only." start="8" size="8" />
+      <BitField name="RED" description="Red Value These bits defines the red value for the A4 or A8 mode of the foreground image. They can only be written when data transfers are disabled. Once the transfer has started, they are read-only." start="16" size="8" />
+    </Register>
+    <Register name="BGPFCCR" description="DMA2D background PFC control register" start="+0x24" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CM" description="Color mode These bits define the color format of the foreground image. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only. others: meaningless" start="0" size="4" />
+      <BitField name="CCM" description="CLUT Color mode These bits define the color format of the CLUT. This register can only be written when the transfer is disabled. Once the CLUT transfer has started, this bit is read-only." start="4" size="1" />
+      <BitField name="START" description="Start This bit is set to start the automatic loading of the CLUT. This bit is automatically reset: ** at the end of the transfer ** when the transfer is aborted by the user application by setting the ABORT bit in the DMA2D_CR ** when a transfer error occurs ** when the transfer has not started due to a configuration error or another transfer operation already on going (data transfer or automatic BackGround CLUT transfer)." start="5" size="1" />
+      <BitField name="CS" description="CLUT size These bits define the size of the CLUT used for the BG. Once the CLUT transfer has started, this field is read-only. The number of CLUT entries is equal to CS[7:0] + 1." start="8" size="8" />
+      <BitField name="AM" description="Alpha mode These bits define which alpha channel value to be used for the background image. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only. others: meaningless" start="16" size="2" />
+      <BitField name="AI" description="Alpha Inverted This bit inverts the alpha value. Once the transfer has started, this bit is read-only." start="20" size="1" />
+      <BitField name="RBS" description="Red Blue Swap This bit allows to swap the R &amp;amp; B to support BGR or ABGR color formats. Once the transfer has started, this bit is read-only." start="21" size="1" />
+      <BitField name="ALPHA" description="Alpha value These bits define a fixed alpha channel value which can replace the original alpha value or be multiplied with the original alpha value according to the alpha mode selected with bits AM[1: 0]. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only." start="24" size="8" />
+    </Register>
+    <Register name="BGCOLR" description="DMA2D background color register" start="+0x28" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BLUE" description="Blue Value These bits define the blue value for the A4 or A8 mode of the background. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only." start="0" size="8" />
+      <BitField name="GREEN" description="Green Value These bits define the green value for the A4 or A8 mode of the background. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only." start="8" size="8" />
+      <BitField name="RED" description="Red Value These bits define the red value for the A4 or A8 mode of the background. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only." start="16" size="8" />
+    </Register>
+    <Register name="FGCMAR" description="DMA2D foreground CLUT memory address register" start="+0x2C" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MA" description="Memory Address Address of the data used for the CLUT address dedicated to the foreground image. This register can only be written when no transfer is ongoing. Once the CLUT transfer has started, this register is read-only. If the foreground CLUT format is 32-bit, the address must be 32-bit aligned." start="0" size="32" />
+    </Register>
+    <Register name="BGCMAR" description="DMA2D background CLUT memory address register" start="+0x30" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MA" description="Memory address Address of the data used for the CLUT address dedicated to the background image. This register can only be written when no transfer is on going. Once the CLUT transfer has started, this register is read-only. If the background CLUT format is 32-bit, the address must be 32-bit aligned." start="0" size="32" />
+    </Register>
+    <Register name="OPFCCR" description="DMA2D output PFC control register" start="+0x34" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CM" description="Color mode These bits define the color format of the output image. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only. others: meaningless" start="0" size="3" />
+      <BitField name="AI" description="Alpha Inverted This bit inverts the alpha value. Once the transfer has started, this bit is read-only." start="20" size="1" />
+      <BitField name="RBS" description="Red Blue Swap This bit allows to swap the R &amp;amp; B to support BGR or ABGR color formats. Once the transfer has started, this bit is read-only." start="21" size="1" />
+    </Register>
+    <Register name="OCOLR" description="DMA2D output color register" start="+0x38" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BLUE" description="Blue Value These bits define the blue value of the output image. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only." start="0" size="8" />
+      <BitField name="GREEN" description="Green Value These bits define the green value of the output image. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only." start="8" size="8" />
+      <BitField name="RED" description="Red Value These bits define the red value of the output image. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only." start="16" size="8" />
+      <BitField name="ALPHA" description="Alpha Channel Value These bits define the alpha channel of the output color. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only." start="24" size="8" />
+    </Register>
+    <Register name="OMAR" description="DMA2D output memory address register" start="+0x3C" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MA" description="Memory Address Address of the data used for the output FIFO. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only. The address alignment must match the image format selected e.g. a 32-bit per pixel format must be 32-bit aligned and a 16-bit per pixel format must be 16-bit aligned." start="0" size="32" />
+    </Register>
+    <Register name="OOR" description="DMA2D output offset register" start="+0x40" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LO" description="Line Offset Line offset used for the output (expressed in pixels). This value is used for the address generation. It is added at the end of each line to determine the starting address of the next line. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only." start="0" size="14" />
+    </Register>
+    <Register name="NLR" description="DMA2D number of line register" start="+0x44" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="NL" description="Number of lines Number of lines of the area to be transferred. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only." start="0" size="16" />
+      <BitField name="PL" description="Pixel per lines Number of pixels per lines of the area to be transferred. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only. If any of the input image format is 4-bit per pixel, pixel per lines must be even." start="16" size="14" />
+    </Register>
+    <Register name="LWR" description="DMA2D line watermark register" start="+0x48" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LW" description="Line watermark These bits allow to configure the line watermark for interrupt generation. An interrupt is raised when the last pixel of the watermarked line has been transferred. These bits can only be written when data transfers are disabled. Once the transfer has started, they are read-only." start="0" size="16" />
+    </Register>
+    <Register name="AMTCR" description="DMA2D AXI master timer configuration register" start="+0x4C" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Enable Enables the dead time functionality." start="0" size="1" />
+      <BitField name="DT" description="Dead Time Dead time value in the AXI clock cycle inserted between two consecutive accesses on the AXI master port. These bits represent the minimum guaranteed number of cycles between two consecutive AXI accesses." start="8" size="8" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="DMAMUX1" description="DMAMUX" start="0x40020800">
+    <Register name="C0CR" description="DMAMux - DMA request line multiplexer channel x control register" start="+0x0" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAREQ_ID" description="Input DMA request line selected" start="0" size="8" />
+      <BitField name="SOIE" description="Interrupt enable at synchronization event overrun" start="8" size="1" />
+      <BitField name="EGE" description="Event generation enable/disable" start="9" size="1" />
+      <BitField name="SE" description="Synchronous operating mode enable/disable" start="16" size="1" />
+      <BitField name="SPOL" description="Synchronization event type selector Defines the synchronization event on the selected synchronization input:" start="17" size="2" />
+      <BitField name="NBREQ" description="Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset." start="19" size="5" />
+      <BitField name="SYNC_ID" description="Synchronization input selected" start="24" size="5" />
+    </Register>
+    <Register name="C1CR" description="DMAMux - DMA request line multiplexer channel x control register" start="+0x4" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAREQ_ID" description="Input DMA request line selected" start="0" size="8" />
+      <BitField name="SOIE" description="Interrupt enable at synchronization event overrun" start="8" size="1" />
+      <BitField name="EGE" description="Event generation enable/disable" start="9" size="1" />
+      <BitField name="SE" description="Synchronous operating mode enable/disable" start="16" size="1" />
+      <BitField name="SPOL" description="Synchronization event type selector Defines the synchronization event on the selected synchronization input:" start="17" size="2" />
+      <BitField name="NBREQ" description="Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset." start="19" size="5" />
+      <BitField name="SYNC_ID" description="Synchronization input selected" start="24" size="5" />
+    </Register>
+    <Register name="C2CR" description="DMAMux - DMA request line multiplexer channel x control register" start="+0x8" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAREQ_ID" description="Input DMA request line selected" start="0" size="8" />
+      <BitField name="SOIE" description="Interrupt enable at synchronization event overrun" start="8" size="1" />
+      <BitField name="EGE" description="Event generation enable/disable" start="9" size="1" />
+      <BitField name="SE" description="Synchronous operating mode enable/disable" start="16" size="1" />
+      <BitField name="SPOL" description="Synchronization event type selector Defines the synchronization event on the selected synchronization input:" start="17" size="2" />
+      <BitField name="NBREQ" description="Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset." start="19" size="5" />
+      <BitField name="SYNC_ID" description="Synchronization input selected" start="24" size="5" />
+    </Register>
+    <Register name="C3CR" description="DMAMux - DMA request line multiplexer channel x control register" start="+0xC" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAREQ_ID" description="Input DMA request line selected" start="0" size="8" />
+      <BitField name="SOIE" description="Interrupt enable at synchronization event overrun" start="8" size="1" />
+      <BitField name="EGE" description="Event generation enable/disable" start="9" size="1" />
+      <BitField name="SE" description="Synchronous operating mode enable/disable" start="16" size="1" />
+      <BitField name="SPOL" description="Synchronization event type selector Defines the synchronization event on the selected synchronization input:" start="17" size="2" />
+      <BitField name="NBREQ" description="Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset." start="19" size="5" />
+      <BitField name="SYNC_ID" description="Synchronization input selected" start="24" size="5" />
+    </Register>
+    <Register name="C4CR" description="DMAMux - DMA request line multiplexer channel x control register" start="+0x10" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAREQ_ID" description="Input DMA request line selected" start="0" size="8" />
+      <BitField name="SOIE" description="Interrupt enable at synchronization event overrun" start="8" size="1" />
+      <BitField name="EGE" description="Event generation enable/disable" start="9" size="1" />
+      <BitField name="SE" description="Synchronous operating mode enable/disable" start="16" size="1" />
+      <BitField name="SPOL" description="Synchronization event type selector Defines the synchronization event on the selected synchronization input:" start="17" size="2" />
+      <BitField name="NBREQ" description="Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset." start="19" size="5" />
+      <BitField name="SYNC_ID" description="Synchronization input selected" start="24" size="5" />
+    </Register>
+    <Register name="C5CR" description="DMAMux - DMA request line multiplexer channel x control register" start="+0x14" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAREQ_ID" description="Input DMA request line selected" start="0" size="8" />
+      <BitField name="SOIE" description="Interrupt enable at synchronization event overrun" start="8" size="1" />
+      <BitField name="EGE" description="Event generation enable/disable" start="9" size="1" />
+      <BitField name="SE" description="Synchronous operating mode enable/disable" start="16" size="1" />
+      <BitField name="SPOL" description="Synchronization event type selector Defines the synchronization event on the selected synchronization input:" start="17" size="2" />
+      <BitField name="NBREQ" description="Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset." start="19" size="5" />
+      <BitField name="SYNC_ID" description="Synchronization input selected" start="24" size="5" />
+    </Register>
+    <Register name="C6CR" description="DMAMux - DMA request line multiplexer channel x control register" start="+0x18" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAREQ_ID" description="Input DMA request line selected" start="0" size="8" />
+      <BitField name="SOIE" description="Interrupt enable at synchronization event overrun" start="8" size="1" />
+      <BitField name="EGE" description="Event generation enable/disable" start="9" size="1" />
+      <BitField name="SE" description="Synchronous operating mode enable/disable" start="16" size="1" />
+      <BitField name="SPOL" description="Synchronization event type selector Defines the synchronization event on the selected synchronization input:" start="17" size="2" />
+      <BitField name="NBREQ" description="Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset." start="19" size="5" />
+      <BitField name="SYNC_ID" description="Synchronization input selected" start="24" size="5" />
+    </Register>
+    <Register name="C7CR" description="DMAMux - DMA request line multiplexer channel x control register" start="+0x1C" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAREQ_ID" description="Input DMA request line selected" start="0" size="8" />
+      <BitField name="SOIE" description="Interrupt enable at synchronization event overrun" start="8" size="1" />
+      <BitField name="EGE" description="Event generation enable/disable" start="9" size="1" />
+      <BitField name="SE" description="Synchronous operating mode enable/disable" start="16" size="1" />
+      <BitField name="SPOL" description="Synchronization event type selector Defines the synchronization event on the selected synchronization input:" start="17" size="2" />
+      <BitField name="NBREQ" description="Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset." start="19" size="5" />
+      <BitField name="SYNC_ID" description="Synchronization input selected" start="24" size="5" />
+    </Register>
+    <Register name="C8CR" description="DMAMux - DMA request line multiplexer channel x control register" start="+0x20" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAREQ_ID" description="Input DMA request line selected" start="0" size="8" />
+      <BitField name="SOIE" description="Interrupt enable at synchronization event overrun" start="8" size="1" />
+      <BitField name="EGE" description="Event generation enable/disable" start="9" size="1" />
+      <BitField name="SE" description="Synchronous operating mode enable/disable" start="16" size="1" />
+      <BitField name="SPOL" description="Synchronization event type selector Defines the synchronization event on the selected synchronization input:" start="17" size="2" />
+      <BitField name="NBREQ" description="Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset." start="19" size="5" />
+      <BitField name="SYNC_ID" description="Synchronization input selected" start="24" size="5" />
+    </Register>
+    <Register name="C9CR" description="DMAMux - DMA request line multiplexer channel x control register" start="+0x24" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAREQ_ID" description="Input DMA request line selected" start="0" size="8" />
+      <BitField name="SOIE" description="Interrupt enable at synchronization event overrun" start="8" size="1" />
+      <BitField name="EGE" description="Event generation enable/disable" start="9" size="1" />
+      <BitField name="SE" description="Synchronous operating mode enable/disable" start="16" size="1" />
+      <BitField name="SPOL" description="Synchronization event type selector Defines the synchronization event on the selected synchronization input:" start="17" size="2" />
+      <BitField name="NBREQ" description="Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset." start="19" size="5" />
+      <BitField name="SYNC_ID" description="Synchronization input selected" start="24" size="5" />
+    </Register>
+    <Register name="C10CR" description="DMAMux - DMA request line multiplexer channel x control register" start="+0x28" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAREQ_ID" description="Input DMA request line selected" start="0" size="8" />
+      <BitField name="SOIE" description="Interrupt enable at synchronization event overrun" start="8" size="1" />
+      <BitField name="EGE" description="Event generation enable/disable" start="9" size="1" />
+      <BitField name="SE" description="Synchronous operating mode enable/disable" start="16" size="1" />
+      <BitField name="SPOL" description="Synchronization event type selector Defines the synchronization event on the selected synchronization input:" start="17" size="2" />
+      <BitField name="NBREQ" description="Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset." start="19" size="5" />
+      <BitField name="SYNC_ID" description="Synchronization input selected" start="24" size="5" />
+    </Register>
+    <Register name="C11CR" description="DMAMux - DMA request line multiplexer channel x control register" start="+0x2C" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAREQ_ID" description="Input DMA request line selected" start="0" size="8" />
+      <BitField name="SOIE" description="Interrupt enable at synchronization event overrun" start="8" size="1" />
+      <BitField name="EGE" description="Event generation enable/disable" start="9" size="1" />
+      <BitField name="SE" description="Synchronous operating mode enable/disable" start="16" size="1" />
+      <BitField name="SPOL" description="Synchronization event type selector Defines the synchronization event on the selected synchronization input:" start="17" size="2" />
+      <BitField name="NBREQ" description="Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset." start="19" size="5" />
+      <BitField name="SYNC_ID" description="Synchronization input selected" start="24" size="5" />
+    </Register>
+    <Register name="C12CR" description="DMAMux - DMA request line multiplexer channel x control register" start="+0x30" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAREQ_ID" description="Input DMA request line selected" start="0" size="8" />
+      <BitField name="SOIE" description="Interrupt enable at synchronization event overrun" start="8" size="1" />
+      <BitField name="EGE" description="Event generation enable/disable" start="9" size="1" />
+      <BitField name="SE" description="Synchronous operating mode enable/disable" start="16" size="1" />
+      <BitField name="SPOL" description="Synchronization event type selector Defines the synchronization event on the selected synchronization input:" start="17" size="2" />
+      <BitField name="NBREQ" description="Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset." start="19" size="5" />
+      <BitField name="SYNC_ID" description="Synchronization input selected" start="24" size="5" />
+    </Register>
+    <Register name="C13CR" description="DMAMux - DMA request line multiplexer channel x control register" start="+0x34" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAREQ_ID" description="Input DMA request line selected" start="0" size="8" />
+      <BitField name="SOIE" description="Interrupt enable at synchronization event overrun" start="8" size="1" />
+      <BitField name="EGE" description="Event generation enable/disable" start="9" size="1" />
+      <BitField name="SE" description="Synchronous operating mode enable/disable" start="16" size="1" />
+      <BitField name="SPOL" description="Synchronization event type selector Defines the synchronization event on the selected synchronization input:" start="17" size="2" />
+      <BitField name="NBREQ" description="Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset." start="19" size="5" />
+      <BitField name="SYNC_ID" description="Synchronization input selected" start="24" size="5" />
+    </Register>
+    <Register name="C14CR" description="DMAMux - DMA request line multiplexer channel x control register" start="+0x38" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAREQ_ID" description="Input DMA request line selected" start="0" size="8" />
+      <BitField name="SOIE" description="Interrupt enable at synchronization event overrun" start="8" size="1" />
+      <BitField name="EGE" description="Event generation enable/disable" start="9" size="1" />
+      <BitField name="SE" description="Synchronous operating mode enable/disable" start="16" size="1" />
+      <BitField name="SPOL" description="Synchronization event type selector Defines the synchronization event on the selected synchronization input:" start="17" size="2" />
+      <BitField name="NBREQ" description="Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset." start="19" size="5" />
+      <BitField name="SYNC_ID" description="Synchronization input selected" start="24" size="5" />
+    </Register>
+    <Register name="C15CR" description="DMAMux - DMA request line multiplexer channel x control register" start="+0x3C" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAREQ_ID" description="Input DMA request line selected" start="0" size="8" />
+      <BitField name="SOIE" description="Interrupt enable at synchronization event overrun" start="8" size="1" />
+      <BitField name="EGE" description="Event generation enable/disable" start="9" size="1" />
+      <BitField name="SE" description="Synchronous operating mode enable/disable" start="16" size="1" />
+      <BitField name="SPOL" description="Synchronization event type selector Defines the synchronization event on the selected synchronization input:" start="17" size="2" />
+      <BitField name="NBREQ" description="Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset." start="19" size="5" />
+      <BitField name="SYNC_ID" description="Synchronization input selected" start="24" size="5" />
+    </Register>
+    <Register name="RG0CR" description="DMAMux - DMA request generator channel x control register" start="+0x100" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SIG_ID" description="DMA request trigger input selected" start="0" size="5" />
+      <BitField name="OIE" description="Interrupt enable at trigger event overrun" start="8" size="1" />
+      <BitField name="GE" description="DMA request generator channel enable/disable" start="16" size="1" />
+      <BitField name="GPOL" description="DMA request generator trigger event type selection Defines the trigger event on the selected DMA request trigger input" start="17" size="2" />
+      <BitField name="GNBREQ" description="Number of DMA requests to generate Defines the number of DMA requests generated after a trigger event, then stop generating. The actual number of generated DMA requests is GNBREQ+1. Note: This field can only be written when GE bit is reset." start="19" size="5" />
+    </Register>
+    <Register name="RG1CR" description="DMAMux - DMA request generator channel x control register" start="+0x104" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SIG_ID" description="DMA request trigger input selected" start="0" size="5" />
+      <BitField name="OIE" description="Interrupt enable at trigger event overrun" start="8" size="1" />
+      <BitField name="GE" description="DMA request generator channel enable/disable" start="16" size="1" />
+      <BitField name="GPOL" description="DMA request generator trigger event type selection Defines the trigger event on the selected DMA request trigger input" start="17" size="2" />
+      <BitField name="GNBREQ" description="Number of DMA requests to generate Defines the number of DMA requests generated after a trigger event, then stop generating. The actual number of generated DMA requests is GNBREQ+1. Note: This field can only be written when GE bit is reset." start="19" size="5" />
+    </Register>
+    <Register name="RG2CR" description="DMAMux - DMA request generator channel x control register" start="+0x108" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SIG_ID" description="DMA request trigger input selected" start="0" size="5" />
+      <BitField name="OIE" description="Interrupt enable at trigger event overrun" start="8" size="1" />
+      <BitField name="GE" description="DMA request generator channel enable/disable" start="16" size="1" />
+      <BitField name="GPOL" description="DMA request generator trigger event type selection Defines the trigger event on the selected DMA request trigger input" start="17" size="2" />
+      <BitField name="GNBREQ" description="Number of DMA requests to generate Defines the number of DMA requests generated after a trigger event, then stop generating. The actual number of generated DMA requests is GNBREQ+1. Note: This field can only be written when GE bit is reset." start="19" size="5" />
+    </Register>
+    <Register name="RG3CR" description="DMAMux - DMA request generator channel x control register" start="+0x10C" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SIG_ID" description="DMA request trigger input selected" start="0" size="5" />
+      <BitField name="OIE" description="Interrupt enable at trigger event overrun" start="8" size="1" />
+      <BitField name="GE" description="DMA request generator channel enable/disable" start="16" size="1" />
+      <BitField name="GPOL" description="DMA request generator trigger event type selection Defines the trigger event on the selected DMA request trigger input" start="17" size="2" />
+      <BitField name="GNBREQ" description="Number of DMA requests to generate Defines the number of DMA requests generated after a trigger event, then stop generating. The actual number of generated DMA requests is GNBREQ+1. Note: This field can only be written when GE bit is reset." start="19" size="5" />
+    </Register>
+    <Register name="RG4CR" description="DMAMux - DMA request generator channel x control register" start="+0x110" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SIG_ID" description="DMA request trigger input selected" start="0" size="5" />
+      <BitField name="OIE" description="Interrupt enable at trigger event overrun" start="8" size="1" />
+      <BitField name="GE" description="DMA request generator channel enable/disable" start="16" size="1" />
+      <BitField name="GPOL" description="DMA request generator trigger event type selection Defines the trigger event on the selected DMA request trigger input" start="17" size="2" />
+      <BitField name="GNBREQ" description="Number of DMA requests to generate Defines the number of DMA requests generated after a trigger event, then stop generating. The actual number of generated DMA requests is GNBREQ+1. Note: This field can only be written when GE bit is reset." start="19" size="5" />
+    </Register>
+    <Register name="RG5CR" description="DMAMux - DMA request generator channel x control register" start="+0x114" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SIG_ID" description="DMA request trigger input selected" start="0" size="5" />
+      <BitField name="OIE" description="Interrupt enable at trigger event overrun" start="8" size="1" />
+      <BitField name="GE" description="DMA request generator channel enable/disable" start="16" size="1" />
+      <BitField name="GPOL" description="DMA request generator trigger event type selection Defines the trigger event on the selected DMA request trigger input" start="17" size="2" />
+      <BitField name="GNBREQ" description="Number of DMA requests to generate Defines the number of DMA requests generated after a trigger event, then stop generating. The actual number of generated DMA requests is GNBREQ+1. Note: This field can only be written when GE bit is reset." start="19" size="5" />
+    </Register>
+    <Register name="RG6CR" description="DMAMux - DMA request generator channel x control register" start="+0x118" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SIG_ID" description="DMA request trigger input selected" start="0" size="5" />
+      <BitField name="OIE" description="Interrupt enable at trigger event overrun" start="8" size="1" />
+      <BitField name="GE" description="DMA request generator channel enable/disable" start="16" size="1" />
+      <BitField name="GPOL" description="DMA request generator trigger event type selection Defines the trigger event on the selected DMA request trigger input" start="17" size="2" />
+      <BitField name="GNBREQ" description="Number of DMA requests to generate Defines the number of DMA requests generated after a trigger event, then stop generating. The actual number of generated DMA requests is GNBREQ+1. Note: This field can only be written when GE bit is reset." start="19" size="5" />
+    </Register>
+    <Register name="RG7CR" description="DMAMux - DMA request generator channel x control register" start="+0x11C" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SIG_ID" description="DMA request trigger input selected" start="0" size="5" />
+      <BitField name="OIE" description="Interrupt enable at trigger event overrun" start="8" size="1" />
+      <BitField name="GE" description="DMA request generator channel enable/disable" start="16" size="1" />
+      <BitField name="GPOL" description="DMA request generator trigger event type selection Defines the trigger event on the selected DMA request trigger input" start="17" size="2" />
+      <BitField name="GNBREQ" description="Number of DMA requests to generate Defines the number of DMA requests generated after a trigger event, then stop generating. The actual number of generated DMA requests is GNBREQ+1. Note: This field can only be written when GE bit is reset." start="19" size="5" />
+    </Register>
+    <Register name="RGSR" description="DMAMux - DMA request generator status register" start="+0x140" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OF" description="Trigger event overrun flag The flag is set when a trigger event occurs on DMA request generator channel x, while the DMA request generator counter value is lower than GNBREQ. The flag is cleared by writing 1 to the corresponding COFx bit in DMAMUX_RGCFR register." start="0" size="8" />
+    </Register>
+    <Register name="RGCFR" description="DMAMux - DMA request generator clear flag register" start="+0x144" size="4" access="WriteOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="COF" description="Clear trigger event overrun flag Upon setting, this bit clears the corresponding overrun flag OFx in the DMAMUX_RGCSR register." start="0" size="8" />
+    </Register>
+    <Register name="CSR" description="DMAMUX request line multiplexer interrupt channel status register" start="+0x80" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SOF" description="Synchronization overrun event flag" start="0" size="16" />
+    </Register>
+    <Register name="CFR" description="DMAMUX request line multiplexer interrupt clear flag register" start="+0x84" size="4" access="WriteOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CSOF" description="Clear synchronization overrun event flag" start="0" size="16" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="DMAMUX3" description="DMAMUX3" start="0x58025800">
+    <Register name="C0CR" description="DMAMux - DMA request line multiplexer channel x control register" start="+0x0" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAREQ_ID" description="Input DMA request line selected" start="0" size="8" />
+      <BitField name="SOIE" description="Interrupt enable at synchronization event overrun" start="8" size="1" />
+      <BitField name="EGE" description="Event generation enable/disable" start="9" size="1" />
+      <BitField name="SE" description="Synchronous operating mode enable/disable" start="16" size="1" />
+      <BitField name="SPOL" description="Synchronization event type selector Defines the synchronization event on the selected synchronization input:" start="17" size="2" />
+      <BitField name="NBREQ" description="Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset." start="19" size="5" />
+      <BitField name="SYNC_ID" description="Synchronization input selected" start="24" size="5" />
+    </Register>
+    <Register name="C1CR" description="DMAMux - DMA request line multiplexer channel x control register" start="+0x4" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAREQ_ID" description="Input DMA request line selected" start="0" size="8" />
+      <BitField name="SOIE" description="Interrupt enable at synchronization event overrun" start="8" size="1" />
+      <BitField name="EGE" description="Event generation enable/disable" start="9" size="1" />
+      <BitField name="SE" description="Synchronous operating mode enable/disable" start="16" size="1" />
+      <BitField name="SPOL" description="Synchronization event type selector Defines the synchronization event on the selected synchronization input:" start="17" size="2" />
+      <BitField name="NBREQ" description="Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset." start="19" size="5" />
+      <BitField name="SYNC_ID" description="Synchronization input selected" start="24" size="5" />
+    </Register>
+    <Register name="C2CR" description="DMAMux - DMA request line multiplexer channel x control register" start="+0x8" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAREQ_ID" description="Input DMA request line selected" start="0" size="8" />
+      <BitField name="SOIE" description="Interrupt enable at synchronization event overrun" start="8" size="1" />
+      <BitField name="EGE" description="Event generation enable/disable" start="9" size="1" />
+      <BitField name="SE" description="Synchronous operating mode enable/disable" start="16" size="1" />
+      <BitField name="SPOL" description="Synchronization event type selector Defines the synchronization event on the selected synchronization input:" start="17" size="2" />
+      <BitField name="NBREQ" description="Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset." start="19" size="5" />
+      <BitField name="SYNC_ID" description="Synchronization input selected" start="24" size="5" />
+    </Register>
+    <Register name="C3CR" description="DMAMux - DMA request line multiplexer channel x control register" start="+0xC" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAREQ_ID" description="Input DMA request line selected" start="0" size="8" />
+      <BitField name="SOIE" description="Interrupt enable at synchronization event overrun" start="8" size="1" />
+      <BitField name="EGE" description="Event generation enable/disable" start="9" size="1" />
+      <BitField name="SE" description="Synchronous operating mode enable/disable" start="16" size="1" />
+      <BitField name="SPOL" description="Synchronization event type selector Defines the synchronization event on the selected synchronization input:" start="17" size="2" />
+      <BitField name="NBREQ" description="Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset." start="19" size="5" />
+      <BitField name="SYNC_ID" description="Synchronization input selected" start="24" size="5" />
+    </Register>
+    <Register name="C4CR" description="DMAMux - DMA request line multiplexer channel x control register" start="+0x10" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAREQ_ID" description="Input DMA request line selected" start="0" size="8" />
+      <BitField name="SOIE" description="Interrupt enable at synchronization event overrun" start="8" size="1" />
+      <BitField name="EGE" description="Event generation enable/disable" start="9" size="1" />
+      <BitField name="SE" description="Synchronous operating mode enable/disable" start="16" size="1" />
+      <BitField name="SPOL" description="Synchronization event type selector Defines the synchronization event on the selected synchronization input:" start="17" size="2" />
+      <BitField name="NBREQ" description="Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset." start="19" size="5" />
+      <BitField name="SYNC_ID" description="Synchronization input selected" start="24" size="5" />
+    </Register>
+    <Register name="C5CR" description="DMAMux - DMA request line multiplexer channel x control register" start="+0x14" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAREQ_ID" description="Input DMA request line selected" start="0" size="8" />
+      <BitField name="SOIE" description="Interrupt enable at synchronization event overrun" start="8" size="1" />
+      <BitField name="EGE" description="Event generation enable/disable" start="9" size="1" />
+      <BitField name="SE" description="Synchronous operating mode enable/disable" start="16" size="1" />
+      <BitField name="SPOL" description="Synchronization event type selector Defines the synchronization event on the selected synchronization input:" start="17" size="2" />
+      <BitField name="NBREQ" description="Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset." start="19" size="5" />
+      <BitField name="SYNC_ID" description="Synchronization input selected" start="24" size="5" />
+    </Register>
+    <Register name="C6CR" description="DMAMux - DMA request line multiplexer channel x control register" start="+0x18" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAREQ_ID" description="Input DMA request line selected" start="0" size="8" />
+      <BitField name="SOIE" description="Interrupt enable at synchronization event overrun" start="8" size="1" />
+      <BitField name="EGE" description="Event generation enable/disable" start="9" size="1" />
+      <BitField name="SE" description="Synchronous operating mode enable/disable" start="16" size="1" />
+      <BitField name="SPOL" description="Synchronization event type selector Defines the synchronization event on the selected synchronization input:" start="17" size="2" />
+      <BitField name="NBREQ" description="Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset." start="19" size="5" />
+      <BitField name="SYNC_ID" description="Synchronization input selected" start="24" size="5" />
+    </Register>
+    <Register name="C7CR" description="DMAMux - DMA request line multiplexer channel x control register" start="+0x1C" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAREQ_ID" description="Input DMA request line selected" start="0" size="8" />
+      <BitField name="SOIE" description="Interrupt enable at synchronization event overrun" start="8" size="1" />
+      <BitField name="EGE" description="Event generation enable/disable" start="9" size="1" />
+      <BitField name="SE" description="Synchronous operating mode enable/disable" start="16" size="1" />
+      <BitField name="SPOL" description="Synchronization event type selector Defines the synchronization event on the selected synchronization input:" start="17" size="2" />
+      <BitField name="NBREQ" description="Number of DMA requests to forward Defines the number of DMA requests forwarded before output event is generated. In synchronous mode, it also defines the number of DMA requests to forward after a synchronization event, then stop forwarding. The actual number of DMA requests forwarded is NBREQ+1. Note: This field can only be written when both SE and EGE bits are reset." start="19" size="5" />
+      <BitField name="SYNC_ID" description="Synchronization input selected" start="24" size="5" />
+    </Register>
+    <Register name="RG0CR" description="DMAMux - DMA request generator channel x control register" start="+0x100" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SIG_ID" description="DMA request trigger input selected" start="0" size="5" />
+      <BitField name="OIE" description="Interrupt enable at trigger event overrun" start="8" size="1" />
+      <BitField name="GE" description="DMA request generator channel enable/disable" start="16" size="1" />
+      <BitField name="GPOL" description="DMA request generator trigger event type selection Defines the trigger event on the selected DMA request trigger input" start="17" size="2" />
+      <BitField name="GNBREQ" description="Number of DMA requests to generate Defines the number of DMA requests generated after a trigger event, then stop generating. The actual number of generated DMA requests is GNBREQ+1. Note: This field can only be written when GE bit is reset." start="19" size="5" />
+    </Register>
+    <Register name="RG1CR" description="DMAMux - DMA request generator channel x control register" start="+0x104" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SIG_ID" description="DMA request trigger input selected" start="0" size="5" />
+      <BitField name="OIE" description="Interrupt enable at trigger event overrun" start="8" size="1" />
+      <BitField name="GE" description="DMA request generator channel enable/disable" start="16" size="1" />
+      <BitField name="GPOL" description="DMA request generator trigger event type selection Defines the trigger event on the selected DMA request trigger input" start="17" size="2" />
+      <BitField name="GNBREQ" description="Number of DMA requests to generate Defines the number of DMA requests generated after a trigger event, then stop generating. The actual number of generated DMA requests is GNBREQ+1. Note: This field can only be written when GE bit is reset." start="19" size="5" />
+    </Register>
+    <Register name="RG2CR" description="DMAMux - DMA request generator channel x control register" start="+0x108" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SIG_ID" description="DMA request trigger input selected" start="0" size="5" />
+      <BitField name="OIE" description="Interrupt enable at trigger event overrun" start="8" size="1" />
+      <BitField name="GE" description="DMA request generator channel enable/disable" start="16" size="1" />
+      <BitField name="GPOL" description="DMA request generator trigger event type selection Defines the trigger event on the selected DMA request trigger input" start="17" size="2" />
+      <BitField name="GNBREQ" description="Number of DMA requests to generate Defines the number of DMA requests generated after a trigger event, then stop generating. The actual number of generated DMA requests is GNBREQ+1. Note: This field can only be written when GE bit is reset." start="19" size="5" />
+    </Register>
+    <Register name="RG3CR" description="DMAMux - DMA request generator channel x control register" start="+0x10C" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SIG_ID" description="DMA request trigger input selected" start="0" size="5" />
+      <BitField name="OIE" description="Interrupt enable at trigger event overrun" start="8" size="1" />
+      <BitField name="GE" description="DMA request generator channel enable/disable" start="16" size="1" />
+      <BitField name="GPOL" description="DMA request generator trigger event type selection Defines the trigger event on the selected DMA request trigger input" start="17" size="2" />
+      <BitField name="GNBREQ" description="Number of DMA requests to generate Defines the number of DMA requests generated after a trigger event, then stop generating. The actual number of generated DMA requests is GNBREQ+1. Note: This field can only be written when GE bit is reset." start="19" size="5" />
+    </Register>
+    <Register name="RG4CR" description="DMAMux - DMA request generator channel x control register" start="+0x110" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SIG_ID" description="DMA request trigger input selected" start="0" size="5" />
+      <BitField name="OIE" description="Interrupt enable at trigger event overrun" start="8" size="1" />
+      <BitField name="GE" description="DMA request generator channel enable/disable" start="16" size="1" />
+      <BitField name="GPOL" description="DMA request generator trigger event type selection Defines the trigger event on the selected DMA request trigger input" start="17" size="2" />
+      <BitField name="GNBREQ" description="Number of DMA requests to generate Defines the number of DMA requests generated after a trigger event, then stop generating. The actual number of generated DMA requests is GNBREQ+1. Note: This field can only be written when GE bit is reset." start="19" size="5" />
+    </Register>
+    <Register name="RG5CR" description="DMAMux - DMA request generator channel x control register" start="+0x114" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SIG_ID" description="DMA request trigger input selected" start="0" size="5" />
+      <BitField name="OIE" description="Interrupt enable at trigger event overrun" start="8" size="1" />
+      <BitField name="GE" description="DMA request generator channel enable/disable" start="16" size="1" />
+      <BitField name="GPOL" description="DMA request generator trigger event type selection Defines the trigger event on the selected DMA request trigger input" start="17" size="2" />
+      <BitField name="GNBREQ" description="Number of DMA requests to generate Defines the number of DMA requests generated after a trigger event, then stop generating. The actual number of generated DMA requests is GNBREQ+1. Note: This field can only be written when GE bit is reset." start="19" size="5" />
+    </Register>
+    <Register name="RG6CR" description="DMAMux - DMA request generator channel x control register" start="+0x118" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SIG_ID" description="DMA request trigger input selected" start="0" size="5" />
+      <BitField name="OIE" description="Interrupt enable at trigger event overrun" start="8" size="1" />
+      <BitField name="GE" description="DMA request generator channel enable/disable" start="16" size="1" />
+      <BitField name="GPOL" description="DMA request generator trigger event type selection Defines the trigger event on the selected DMA request trigger input" start="17" size="2" />
+      <BitField name="GNBREQ" description="Number of DMA requests to generate Defines the number of DMA requests generated after a trigger event, then stop generating. The actual number of generated DMA requests is GNBREQ+1. Note: This field can only be written when GE bit is reset." start="19" size="5" />
+    </Register>
+    <Register name="RG7CR" description="DMAMux - DMA request generator channel x control register" start="+0x11C" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SIG_ID" description="DMA request trigger input selected" start="0" size="5" />
+      <BitField name="OIE" description="Interrupt enable at trigger event overrun" start="8" size="1" />
+      <BitField name="GE" description="DMA request generator channel enable/disable" start="16" size="1" />
+      <BitField name="GPOL" description="DMA request generator trigger event type selection Defines the trigger event on the selected DMA request trigger input" start="17" size="2" />
+      <BitField name="GNBREQ" description="Number of DMA requests to generate Defines the number of DMA requests generated after a trigger event, then stop generating. The actual number of generated DMA requests is GNBREQ+1. Note: This field can only be written when GE bit is reset." start="19" size="5" />
+    </Register>
+    <Register name="RGSR" description="DMAMux - DMA request generator status register" start="+0x140" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OF" description="Trigger event overrun flag The flag is set when a trigger event occurs on DMA request generator channel x, while the DMA request generator counter value is lower than GNBREQ. The flag is cleared by writing 1 to the corresponding COFx bit in DMAMUX_RGCFR register." start="0" size="8" />
+    </Register>
+    <Register name="RGCFR" description="DMAMux - DMA request generator clear flag register" start="+0x144" size="4" access="WriteOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="COF" description="Clear trigger event overrun flag Upon setting, this bit clears the corresponding overrun flag OFx in the DMAMUX_RGCSR register." start="0" size="8" />
+    </Register>
+    <Register name="CSR" description="DMAMUX request line multiplexer interrupt channel status register" start="+0x80" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SOF" description="Synchronization overrun event flag" start="0" size="16" />
+    </Register>
+    <Register name="CFR" description="DMAMUX request line multiplexer interrupt clear flag register" start="+0x84" size="4" access="WriteOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CSOF" description="Clear synchronization overrun event flag" start="0" size="16" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="Delay_Block_OCTOSPI1" description="DELAY_Block_SDMMC1" start="0x52006000">
+    <Register name="CR" description="DLYB control register" start="+0x0" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DEN" description="Delay block enable bit" start="0" size="1" />
+      <BitField name="SEN" description="Sampler length enable bit" start="1" size="1" />
+    </Register>
+    <Register name="CFGR" description="DLYB configuration register" start="+0x4" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SEL" description="Select the phase for the Output clock" start="0" size="4" />
+      <BitField name="UNIT" description="Delay Defines the delay of a Unit delay cell" start="8" size="7" />
+      <BitField name="LNG" description="Delay line length value" start="16" size="12" />
+      <BitField name="LNGF" description="Length valid flag" start="31" size="1" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="Delay_Block_OCTOSPI2" description="DELAY_Block_SDMMC1" start="0x5200B000">
+    <Register name="CR" description="DLYB control register" start="+0x0" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DEN" description="Delay block enable bit" start="0" size="1" />
+      <BitField name="SEN" description="Sampler length enable bit" start="1" size="1" />
+    </Register>
+    <Register name="CFGR" description="DLYB configuration register" start="+0x4" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SEL" description="Select the phase for the Output clock" start="0" size="4" />
+      <BitField name="UNIT" description="Delay Defines the delay of a Unit delay cell" start="8" size="7" />
+      <BitField name="LNG" description="Delay line length value" start="16" size="12" />
+      <BitField name="LNGF" description="Length valid flag" start="31" size="1" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="EXTI" description="External interrupt/event controller" start="0x58000000">
+    <Register name="RTSR1" description="EXTI rising trigger selection register" start="+0x0" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TR0" description="Rising trigger event configuration bit of Configurable Event input" start="0" size="1" />
+      <BitField name="TR1" description="Rising trigger event configuration bit of Configurable Event input" start="1" size="1" />
+      <BitField name="TR2" description="Rising trigger event configuration bit of Configurable Event input" start="2" size="1" />
+      <BitField name="TR3" description="Rising trigger event configuration bit of Configurable Event input" start="3" size="1" />
+      <BitField name="TR4" description="Rising trigger event configuration bit of Configurable Event input" start="4" size="1" />
+      <BitField name="TR5" description="Rising trigger event configuration bit of Configurable Event input" start="5" size="1" />
+      <BitField name="TR6" description="Rising trigger event configuration bit of Configurable Event input" start="6" size="1" />
+      <BitField name="TR7" description="Rising trigger event configuration bit of Configurable Event input" start="7" size="1" />
+      <BitField name="TR8" description="Rising trigger event configuration bit of Configurable Event input" start="8" size="1" />
+      <BitField name="TR9" description="Rising trigger event configuration bit of Configurable Event input" start="9" size="1" />
+      <BitField name="TR10" description="Rising trigger event configuration bit of Configurable Event input" start="10" size="1" />
+      <BitField name="TR11" description="Rising trigger event configuration bit of Configurable Event input" start="11" size="1" />
+      <BitField name="TR12" description="Rising trigger event configuration bit of Configurable Event input" start="12" size="1" />
+      <BitField name="TR13" description="Rising trigger event configuration bit of Configurable Event input" start="13" size="1" />
+      <BitField name="TR14" description="Rising trigger event configuration bit of Configurable Event input" start="14" size="1" />
+      <BitField name="TR15" description="Rising trigger event configuration bit of Configurable Event input" start="15" size="1" />
+      <BitField name="TR16" description="Rising trigger event configuration bit of Configurable Event input" start="16" size="1" />
+      <BitField name="TR17" description="Rising trigger event configuration bit of Configurable Event input" start="17" size="1" />
+      <BitField name="TR18" description="Rising trigger event configuration bit of Configurable Event input" start="18" size="1" />
+      <BitField name="TR19" description="Rising trigger event configuration bit of Configurable Event input" start="19" size="1" />
+      <BitField name="TR20" description="Rising trigger event configuration bit of Configurable Event input" start="20" size="1" />
+      <BitField name="TR21" description="Rising trigger event configuration bit of Configurable Event input" start="21" size="1" />
+    </Register>
+    <Register name="FTSR1" description="EXTI falling trigger selection register" start="+0x4" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TR0" description="Rising trigger event configuration bit of Configurable Event input" start="0" size="1" />
+      <BitField name="TR1" description="Rising trigger event configuration bit of Configurable Event input" start="1" size="1" />
+      <BitField name="TR2" description="Rising trigger event configuration bit of Configurable Event input" start="2" size="1" />
+      <BitField name="TR3" description="Rising trigger event configuration bit of Configurable Event input" start="3" size="1" />
+      <BitField name="TR4" description="Rising trigger event configuration bit of Configurable Event input" start="4" size="1" />
+      <BitField name="TR5" description="Rising trigger event configuration bit of Configurable Event input" start="5" size="1" />
+      <BitField name="TR6" description="Rising trigger event configuration bit of Configurable Event input" start="6" size="1" />
+      <BitField name="TR7" description="Rising trigger event configuration bit of Configurable Event input" start="7" size="1" />
+      <BitField name="TR8" description="Rising trigger event configuration bit of Configurable Event input" start="8" size="1" />
+      <BitField name="TR9" description="Rising trigger event configuration bit of Configurable Event input" start="9" size="1" />
+      <BitField name="TR10" description="Rising trigger event configuration bit of Configurable Event input" start="10" size="1" />
+      <BitField name="TR11" description="Rising trigger event configuration bit of Configurable Event input" start="11" size="1" />
+      <BitField name="TR12" description="Rising trigger event configuration bit of Configurable Event input" start="12" size="1" />
+      <BitField name="TR13" description="Rising trigger event configuration bit of Configurable Event input" start="13" size="1" />
+      <BitField name="TR14" description="Rising trigger event configuration bit of Configurable Event input" start="14" size="1" />
+      <BitField name="TR15" description="Rising trigger event configuration bit of Configurable Event input" start="15" size="1" />
+      <BitField name="TR16" description="Rising trigger event configuration bit of Configurable Event input" start="16" size="1" />
+      <BitField name="TR17" description="Rising trigger event configuration bit of Configurable Event input" start="17" size="1" />
+      <BitField name="TR18" description="Rising trigger event configuration bit of Configurable Event input" start="18" size="1" />
+      <BitField name="TR19" description="Rising trigger event configuration bit of Configurable Event input" start="19" size="1" />
+      <BitField name="TR20" description="Rising trigger event configuration bit of Configurable Event input" start="20" size="1" />
+      <BitField name="TR21" description="Rising trigger event configuration bit of Configurable Event input" start="21" size="1" />
+    </Register>
+    <Register name="SWIER1" description="EXTI software interrupt event register" start="+0x8" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWIER0" description="Rising trigger event configuration bit of Configurable Event input" start="0" size="1" />
+      <BitField name="SWIER1" description="Rising trigger event configuration bit of Configurable Event input" start="1" size="1" />
+      <BitField name="SWIER2" description="Rising trigger event configuration bit of Configurable Event input" start="2" size="1" />
+      <BitField name="SWIER3" description="Rising trigger event configuration bit of Configurable Event input" start="3" size="1" />
+      <BitField name="SWIER4" description="Rising trigger event configuration bit of Configurable Event input" start="4" size="1" />
+      <BitField name="SWIER5" description="Rising trigger event configuration bit of Configurable Event input" start="5" size="1" />
+      <BitField name="SWIER6" description="Rising trigger event configuration bit of Configurable Event input" start="6" size="1" />
+      <BitField name="SWIER7" description="Rising trigger event configuration bit of Configurable Event input" start="7" size="1" />
+      <BitField name="SWIER8" description="Rising trigger event configuration bit of Configurable Event input" start="8" size="1" />
+      <BitField name="SWIER9" description="Rising trigger event configuration bit of Configurable Event input" start="9" size="1" />
+      <BitField name="SWIER10" description="Rising trigger event configuration bit of Configurable Event input" start="10" size="1" />
+      <BitField name="SWIER11" description="Rising trigger event configuration bit of Configurable Event input" start="11" size="1" />
+      <BitField name="SWIER12" description="Rising trigger event configuration bit of Configurable Event input" start="12" size="1" />
+      <BitField name="SWIER13" description="Rising trigger event configuration bit of Configurable Event input" start="13" size="1" />
+      <BitField name="SWIER14" description="Rising trigger event configuration bit of Configurable Event input" start="14" size="1" />
+      <BitField name="SWIER15" description="Rising trigger event configuration bit of Configurable Event input" start="15" size="1" />
+      <BitField name="SWIER16" description="Rising trigger event configuration bit of Configurable Event input" start="16" size="1" />
+      <BitField name="SWIER17" description="Rising trigger event configuration bit of Configurable Event input" start="17" size="1" />
+      <BitField name="SWIER18" description="Rising trigger event configuration bit of Configurable Event input" start="18" size="1" />
+      <BitField name="SWIER19" description="Rising trigger event configuration bit of Configurable Event input" start="19" size="1" />
+      <BitField name="SWIER20" description="Rising trigger event configuration bit of Configurable Event input" start="20" size="1" />
+      <BitField name="SWIER21" description="Rising trigger event configuration bit of Configurable Event input" start="21" size="1" />
+    </Register>
+    <Register name="D3PMR1" description="EXTI D3 pending mask register" start="+0xC" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MR0" description="Rising trigger event configuration bit of Configurable Event input" start="0" size="1" />
+      <BitField name="MR1" description="Rising trigger event configuration bit of Configurable Event input" start="1" size="1" />
+      <BitField name="MR2" description="Rising trigger event configuration bit of Configurable Event input" start="2" size="1" />
+      <BitField name="MR3" description="Rising trigger event configuration bit of Configurable Event input" start="3" size="1" />
+      <BitField name="MR4" description="Rising trigger event configuration bit of Configurable Event input" start="4" size="1" />
+      <BitField name="MR5" description="Rising trigger event configuration bit of Configurable Event input" start="5" size="1" />
+      <BitField name="MR6" description="Rising trigger event configuration bit of Configurable Event input" start="6" size="1" />
+      <BitField name="MR7" description="Rising trigger event configuration bit of Configurable Event input" start="7" size="1" />
+      <BitField name="MR8" description="Rising trigger event configuration bit of Configurable Event input" start="8" size="1" />
+      <BitField name="MR9" description="Rising trigger event configuration bit of Configurable Event input" start="9" size="1" />
+      <BitField name="MR10" description="Rising trigger event configuration bit of Configurable Event input" start="10" size="1" />
+      <BitField name="MR11" description="Rising trigger event configuration bit of Configurable Event input" start="11" size="1" />
+      <BitField name="MR12" description="Rising trigger event configuration bit of Configurable Event input" start="12" size="1" />
+      <BitField name="MR13" description="Rising trigger event configuration bit of Configurable Event input" start="13" size="1" />
+      <BitField name="MR14" description="Rising trigger event configuration bit of Configurable Event input" start="14" size="1" />
+      <BitField name="MR15" description="Rising trigger event configuration bit of Configurable Event input" start="15" size="1" />
+      <BitField name="MR19" description="Rising trigger event configuration bit of Configurable Event input" start="19" size="1" />
+      <BitField name="MR20" description="Rising trigger event configuration bit of Configurable Event input" start="20" size="1" />
+      <BitField name="MR21" description="Rising trigger event configuration bit of Configurable Event input" start="21" size="1" />
+      <BitField name="MR25" description="Rising trigger event configuration bit of Configurable Event input" start="25" size="1" />
+    </Register>
+    <Register name="D3PCR1L" description="EXTI D3 pending clear selection register low" start="+0x10" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PCS0" description="D3 Pending request clear input signal selection on Event input x = truncate (n/2)" start="0" size="2" />
+      <BitField name="PCS1" description="D3 Pending request clear input signal selection on Event input x = truncate (n/2)" start="2" size="2" />
+      <BitField name="PCS2" description="D3 Pending request clear input signal selection on Event input x = truncate (n/2)" start="4" size="2" />
+      <BitField name="PCS3" description="D3 Pending request clear input signal selection on Event input x = truncate (n/2)" start="6" size="2" />
+      <BitField name="PCS4" description="D3 Pending request clear input signal selection on Event input x = truncate (n/2)" start="8" size="2" />
+      <BitField name="PCS5" description="D3 Pending request clear input signal selection on Event input x = truncate (n/2)" start="10" size="2" />
+      <BitField name="PCS6" description="D3 Pending request clear input signal selection on Event input x = truncate (n/2)" start="12" size="2" />
+      <BitField name="PCS7" description="D3 Pending request clear input signal selection on Event input x = truncate (n/2)" start="14" size="2" />
+      <BitField name="PCS8" description="D3 Pending request clear input signal selection on Event input x = truncate (n/2)" start="16" size="2" />
+      <BitField name="PCS9" description="D3 Pending request clear input signal selection on Event input x = truncate (n/2)" start="18" size="2" />
+      <BitField name="PCS10" description="D3 Pending request clear input signal selection on Event input x = truncate (n/2)" start="20" size="2" />
+      <BitField name="PCS11" description="D3 Pending request clear input signal selection on Event input x = truncate (n/2)" start="22" size="2" />
+      <BitField name="PCS12" description="D3 Pending request clear input signal selection on Event input x = truncate (n/2)" start="24" size="2" />
+      <BitField name="PCS13" description="D3 Pending request clear input signal selection on Event input x = truncate (n/2)" start="26" size="2" />
+      <BitField name="PCS14" description="D3 Pending request clear input signal selection on Event input x = truncate (n/2)" start="28" size="2" />
+      <BitField name="PCS15" description="D3 Pending request clear input signal selection on Event input x = truncate (n/2)" start="30" size="2" />
+    </Register>
+    <Register name="D3PCR1H" description="EXTI D3 pending clear selection register high" start="+0x14" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PCS19" description="D3 Pending request clear input signal selection on Event input x = truncate ((n+32)/2)" start="6" size="2" />
+      <BitField name="PCS20" description="D3 Pending request clear input signal selection on Event input x = truncate ((n+32)/2)" start="8" size="2" />
+      <BitField name="PCS21" description="D3 Pending request clear input signal selection on Event input x = truncate ((n+32)/2)" start="10" size="2" />
+      <BitField name="PCS25" description="D3 Pending request clear input signal selection on Event input x = truncate ((n+32)/2)" start="18" size="2" />
+    </Register>
+    <Register name="RTSR2" description="EXTI rising trigger selection register" start="+0x20" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TR49" description="Rising trigger event configuration bit of Configurable Event input x+32" start="17" size="1" />
+      <BitField name="TR51" description="Rising trigger event configuration bit of Configurable Event input x+32" start="19" size="1" />
+    </Register>
+    <Register name="FTSR2" description="EXTI falling trigger selection register" start="+0x24" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TR49" description="Falling trigger event configuration bit of Configurable Event input x+32" start="17" size="1" />
+      <BitField name="TR51" description="Falling trigger event configuration bit of Configurable Event input x+32" start="19" size="1" />
+    </Register>
+    <Register name="SWIER2" description="EXTI software interrupt event register" start="+0x28" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWIER49" description="Software interrupt on line x+32" start="17" size="1" />
+      <BitField name="SWIER51" description="Software interrupt on line x+32" start="19" size="1" />
+    </Register>
+    <Register name="D3PMR2" description="EXTI D3 pending mask register" start="+0x2C" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MR34" description="D3 Pending Mask on Event input x+32" start="2" size="1" />
+      <BitField name="MR35" description="D3 Pending Mask on Event input x+32" start="3" size="1" />
+      <BitField name="MR41" description="D3 Pending Mask on Event input x+32" start="9" size="1" />
+      <BitField name="MR48" description="D3 Pending Mask on Event input x+32" start="16" size="1" />
+      <BitField name="MR49" description="D3 Pending Mask on Event input x+32" start="17" size="1" />
+      <BitField name="MR50" description="D3 Pending Mask on Event input x+32" start="18" size="1" />
+      <BitField name="MR51" description="D3 Pending Mask on Event input x+32" start="19" size="1" />
+      <BitField name="MR52" description="D3 Pending Mask on Event input x+32" start="20" size="1" />
+      <BitField name="MR53" description="D3 Pending Mask on Event input x+32" start="21" size="1" />
+    </Register>
+    <Register name="D3PCR2L" description="EXTI D3 pending clear selection register low" start="+0x30" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PCS35" description="D3 Pending request clear input signal selection on Event input x = truncate ((n+64)/2)" start="6" size="2" />
+      <BitField name="PCS34" description="D3 Pending request clear input signal selection on Event input x = truncate ((n+64)/2)" start="4" size="2" />
+      <BitField name="PCS41" description="D3 Pending request clear input signal selection on Event input x = truncate ((n+64)/2)" start="18" size="2" />
+    </Register>
+    <Register name="D3PCR2H" description="EXTI D3 pending clear selection register high" start="+0x34" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PCS48" description="Pending request clear input signal selection on Event input x= truncate ((n+96)/2)" start="0" size="2" />
+      <BitField name="PCS49" description="Pending request clear input signal selection on Event input x= truncate ((n+96)/2)" start="2" size="2" />
+      <BitField name="PCS50" description="Pending request clear input signal selection on Event input x= truncate ((n+96)/2)" start="4" size="2" />
+      <BitField name="PCS51" description="Pending request clear input signal selection on Event input x= truncate ((n+96)/2)" start="6" size="2" />
+      <BitField name="PCS52" description="Pending request clear input signal selection on Event input x= truncate ((n+96)/2)" start="8" size="2" />
+      <BitField name="PCS53" description="Pending request clear input signal selection on Event input x= truncate ((n+96)/2)" start="10" size="2" />
+    </Register>
+    <Register name="RTSR3" description="EXTI rising trigger selection register" start="+0x40" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TR82" description="Rising trigger event configuration bit of Configurable Event input x+64" start="18" size="1" />
+      <BitField name="TR84" description="Rising trigger event configuration bit of Configurable Event input x+64" start="20" size="1" />
+      <BitField name="TR85" description="Rising trigger event configuration bit of Configurable Event input x+64" start="21" size="1" />
+      <BitField name="TR86" description="Rising trigger event configuration bit of Configurable Event input x+64" start="22" size="1" />
+    </Register>
+    <Register name="FTSR3" description="EXTI falling trigger selection register" start="+0x44" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TR82" description="Falling trigger event configuration bit of Configurable Event input x+64" start="18" size="1" />
+      <BitField name="TR84" description="Falling trigger event configuration bit of Configurable Event input x+64" start="20" size="1" />
+      <BitField name="TR85" description="Falling trigger event configuration bit of Configurable Event input x+64" start="21" size="1" />
+      <BitField name="TR86" description="Falling trigger event configuration bit of Configurable Event input x+64" start="22" size="1" />
+    </Register>
+    <Register name="SWIER3" description="EXTI software interrupt event register" start="+0x48" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWIER82" description="Software interrupt on line x+64" start="18" size="1" />
+      <BitField name="SWIER84" description="Software interrupt on line x+64" start="20" size="1" />
+      <BitField name="SWIER85" description="Software interrupt on line x+64" start="21" size="1" />
+      <BitField name="SWIER86" description="Software interrupt on line x+64" start="22" size="1" />
+    </Register>
+    <Register name="D3PMR3" description="EXTI D3 pending mask register" start="+0x4C" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MR88" description="D3 Pending Mask on Event input x+64" start="24" size="1" />
+    </Register>
+    <Register name="D3PCR3H" description="EXTI D3 pending clear selection register high" start="+0x54" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PCS88" description="D3 Pending request clear input signal selection on Event input x= truncate N+160/2" start="18" size="2" />
+    </Register>
+    <Register name="CPUIMR1" description="EXTI interrupt mask register" start="+0x80" size="4" access="Read/Write" reset_value="0xFFC00000" reset_mask="0xFFFFFFFF">
+      <BitField name="MR0" description="Rising trigger event configuration bit of Configurable Event input" start="0" size="1" />
+      <BitField name="MR1" description="Rising trigger event configuration bit of Configurable Event input" start="1" size="1" />
+      <BitField name="MR2" description="Rising trigger event configuration bit of Configurable Event input" start="2" size="1" />
+      <BitField name="MR3" description="Rising trigger event configuration bit of Configurable Event input" start="3" size="1" />
+      <BitField name="MR4" description="Rising trigger event configuration bit of Configurable Event input" start="4" size="1" />
+      <BitField name="MR5" description="Rising trigger event configuration bit of Configurable Event input" start="5" size="1" />
+      <BitField name="MR6" description="Rising trigger event configuration bit of Configurable Event input" start="6" size="1" />
+      <BitField name="MR7" description="Rising trigger event configuration bit of Configurable Event input" start="7" size="1" />
+      <BitField name="MR8" description="Rising trigger event configuration bit of Configurable Event input" start="8" size="1" />
+      <BitField name="MR9" description="Rising trigger event configuration bit of Configurable Event input" start="9" size="1" />
+      <BitField name="MR10" description="Rising trigger event configuration bit of Configurable Event input" start="10" size="1" />
+      <BitField name="MR11" description="Rising trigger event configuration bit of Configurable Event input" start="11" size="1" />
+      <BitField name="MR12" description="Rising trigger event configuration bit of Configurable Event input" start="12" size="1" />
+      <BitField name="MR13" description="Rising trigger event configuration bit of Configurable Event input" start="13" size="1" />
+      <BitField name="MR14" description="Rising trigger event configuration bit of Configurable Event input" start="14" size="1" />
+      <BitField name="MR15" description="Rising trigger event configuration bit of Configurable Event input" start="15" size="1" />
+      <BitField name="MR16" description="Rising trigger event configuration bit of Configurable Event input" start="16" size="1" />
+      <BitField name="MR17" description="Rising trigger event configuration bit of Configurable Event input" start="17" size="1" />
+      <BitField name="MR18" description="Rising trigger event configuration bit of Configurable Event input" start="18" size="1" />
+      <BitField name="MR19" description="Rising trigger event configuration bit of Configurable Event input" start="19" size="1" />
+      <BitField name="MR20" description="Rising trigger event configuration bit of Configurable Event input" start="20" size="1" />
+      <BitField name="MR21" description="Rising trigger event configuration bit of Configurable Event input" start="21" size="1" />
+      <BitField name="MR22" description="Rising trigger event configuration bit of Configurable Event input" start="22" size="1" />
+      <BitField name="MR23" description="Rising trigger event configuration bit of Configurable Event input" start="23" size="1" />
+      <BitField name="MR24" description="Rising trigger event configuration bit of Configurable Event input" start="24" size="1" />
+      <BitField name="MR25" description="Rising trigger event configuration bit of Configurable Event input" start="25" size="1" />
+      <BitField name="MR26" description="Rising trigger event configuration bit of Configurable Event input" start="26" size="1" />
+      <BitField name="MR27" description="Rising trigger event configuration bit of Configurable Event input" start="27" size="1" />
+      <BitField name="MR28" description="Rising trigger event configuration bit of Configurable Event input" start="28" size="1" />
+      <BitField name="MR29" description="Rising trigger event configuration bit of Configurable Event input" start="29" size="1" />
+      <BitField name="MR30" description="Rising trigger event configuration bit of Configurable Event input" start="30" size="1" />
+      <BitField name="MR31" description="Rising trigger event configuration bit of Configurable Event input" start="31" size="1" />
+    </Register>
+    <Register name="CPUEMR1" description="EXTI event mask register" start="+0x84" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MR0" description="CPU Event mask on Event input x" start="0" size="1" />
+      <BitField name="MR1" description="CPU Event mask on Event input x" start="1" size="1" />
+      <BitField name="MR2" description="CPU Event mask on Event input x" start="2" size="1" />
+      <BitField name="MR3" description="CPU Event mask on Event input x" start="3" size="1" />
+      <BitField name="MR4" description="CPU Event mask on Event input x" start="4" size="1" />
+      <BitField name="MR5" description="CPU Event mask on Event input x" start="5" size="1" />
+      <BitField name="MR6" description="CPU Event mask on Event input x" start="6" size="1" />
+      <BitField name="MR7" description="CPU Event mask on Event input x" start="7" size="1" />
+      <BitField name="MR8" description="CPU Event mask on Event input x" start="8" size="1" />
+      <BitField name="MR9" description="CPU Event mask on Event input x" start="9" size="1" />
+      <BitField name="MR10" description="CPU Event mask on Event input x" start="10" size="1" />
+      <BitField name="MR11" description="CPU Event mask on Event input x" start="11" size="1" />
+      <BitField name="MR12" description="CPU Event mask on Event input x" start="12" size="1" />
+      <BitField name="MR13" description="CPU Event mask on Event input x" start="13" size="1" />
+      <BitField name="MR14" description="CPU Event mask on Event input x" start="14" size="1" />
+      <BitField name="MR15" description="CPU Event mask on Event input x" start="15" size="1" />
+      <BitField name="MR16" description="CPU Event mask on Event input x" start="16" size="1" />
+      <BitField name="MR17" description="CPU Event mask on Event input x" start="17" size="1" />
+      <BitField name="MR18" description="CPU Event mask on Event input x" start="18" size="1" />
+      <BitField name="MR19" description="CPU Event mask on Event input x" start="19" size="1" />
+      <BitField name="MR20" description="CPU Event mask on Event input x" start="20" size="1" />
+      <BitField name="MR21" description="CPU Event mask on Event input x" start="21" size="1" />
+      <BitField name="MR22" description="CPU Event mask on Event input x" start="22" size="1" />
+      <BitField name="MR23" description="CPU Event mask on Event input x" start="23" size="1" />
+      <BitField name="MR24" description="CPU Event mask on Event input x" start="24" size="1" />
+      <BitField name="MR25" description="CPU Event mask on Event input x" start="25" size="1" />
+      <BitField name="MR26" description="CPU Event mask on Event input x" start="26" size="1" />
+      <BitField name="MR27" description="CPU Event mask on Event input x" start="27" size="1" />
+      <BitField name="MR28" description="CPU Event mask on Event input x" start="28" size="1" />
+      <BitField name="MR29" description="CPU Event mask on Event input x" start="29" size="1" />
+      <BitField name="MR30" description="CPU Event mask on Event input x" start="30" size="1" />
+      <BitField name="MR31" description="CPU Event mask on Event input x" start="31" size="1" />
+    </Register>
+    <Register name="CPUPR1" description="EXTI pending register" start="+0x88" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PR0" description="CPU Event mask on Event input x" start="0" size="1" />
+      <BitField name="PR1" description="CPU Event mask on Event input x" start="1" size="1" />
+      <BitField name="PR2" description="CPU Event mask on Event input x" start="2" size="1" />
+      <BitField name="PR3" description="CPU Event mask on Event input x" start="3" size="1" />
+      <BitField name="PR4" description="CPU Event mask on Event input x" start="4" size="1" />
+      <BitField name="PR5" description="CPU Event mask on Event input x" start="5" size="1" />
+      <BitField name="PR6" description="CPU Event mask on Event input x" start="6" size="1" />
+      <BitField name="PR7" description="CPU Event mask on Event input x" start="7" size="1" />
+      <BitField name="PR8" description="CPU Event mask on Event input x" start="8" size="1" />
+      <BitField name="PR9" description="CPU Event mask on Event input x" start="9" size="1" />
+      <BitField name="PR10" description="CPU Event mask on Event input x" start="10" size="1" />
+      <BitField name="PR11" description="CPU Event mask on Event input x" start="11" size="1" />
+      <BitField name="PR12" description="CPU Event mask on Event input x" start="12" size="1" />
+      <BitField name="PR13" description="CPU Event mask on Event input x" start="13" size="1" />
+      <BitField name="PR14" description="CPU Event mask on Event input x" start="14" size="1" />
+      <BitField name="PR15" description="CPU Event mask on Event input x" start="15" size="1" />
+      <BitField name="PR16" description="CPU Event mask on Event input x" start="16" size="1" />
+      <BitField name="PR17" description="CPU Event mask on Event input x" start="17" size="1" />
+      <BitField name="PR18" description="CPU Event mask on Event input x" start="18" size="1" />
+      <BitField name="PR19" description="CPU Event mask on Event input x" start="19" size="1" />
+      <BitField name="PR20" description="CPU Event mask on Event input x" start="20" size="1" />
+      <BitField name="PR21" description="CPU Event mask on Event input x" start="21" size="1" />
+    </Register>
+    <Register name="CPUIMR2" description="EXTI interrupt mask register" start="+0x90" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MR0" description="CPU Interrupt Mask on Direct Event input x+32" start="0" size="1" />
+      <BitField name="MR1" description="CPU Interrupt Mask on Direct Event input x+32" start="1" size="1" />
+      <BitField name="MR2" description="CPU Interrupt Mask on Direct Event input x+32" start="2" size="1" />
+      <BitField name="MR3" description="CPU Interrupt Mask on Direct Event input x+32" start="3" size="1" />
+      <BitField name="MR4" description="CPU Interrupt Mask on Direct Event input x+32" start="4" size="1" />
+      <BitField name="MR5" description="CPU Interrupt Mask on Direct Event input x+32" start="5" size="1" />
+      <BitField name="MR6" description="CPU Interrupt Mask on Direct Event input x+32" start="6" size="1" />
+      <BitField name="MR7" description="CPU Interrupt Mask on Direct Event input x+32" start="7" size="1" />
+      <BitField name="MR8" description="CPU Interrupt Mask on Direct Event input x+32" start="8" size="1" />
+      <BitField name="MR9" description="CPU Interrupt Mask on Direct Event input x+32" start="9" size="1" />
+      <BitField name="MR10" description="CPU Interrupt Mask on Direct Event input x+32" start="10" size="1" />
+      <BitField name="MR11" description="CPU Interrupt Mask on Direct Event input x+32" start="11" size="1" />
+      <BitField name="MR12" description="CPU Interrupt Mask on Direct Event input x+32" start="12" size="1" />
+      <BitField name="MR14" description="CPU Interrupt Mask on Direct Event input x+32" start="14" size="1" />
+      <BitField name="MR15" description="CPU Interrupt Mask on Direct Event input x+32" start="15" size="1" />
+      <BitField name="MR16" description="CPU Interrupt Mask on Direct Event input x+32" start="16" size="1" />
+      <BitField name="MR17" description="CPU Interrupt Mask on Direct Event input x+32" start="17" size="1" />
+      <BitField name="MR18" description="CPU Interrupt Mask on Direct Event input x+32" start="18" size="1" />
+      <BitField name="MR19" description="CPU Interrupt Mask on Direct Event input x+32" start="19" size="1" />
+      <BitField name="MR20" description="CPU Interrupt Mask on Direct Event input x+32" start="20" size="1" />
+      <BitField name="MR21" description="CPU Interrupt Mask on Direct Event input x+32" start="21" size="1" />
+      <BitField name="MR22" description="CPU Interrupt Mask on Direct Event input x+32" start="22" size="1" />
+      <BitField name="MR23" description="CPU Interrupt Mask on Direct Event input x+32" start="23" size="1" />
+      <BitField name="MR24" description="CPU Interrupt Mask on Direct Event input x+32" start="24" size="1" />
+      <BitField name="MR25" description="CPU Interrupt Mask on Direct Event input x+32" start="25" size="1" />
+      <BitField name="MR26" description="CPU Interrupt Mask on Direct Event input x+32" start="26" size="1" />
+      <BitField name="MR27" description="CPU Interrupt Mask on Direct Event input x+32" start="27" size="1" />
+      <BitField name="MR28" description="CPU Interrupt Mask on Direct Event input x+32" start="28" size="1" />
+      <BitField name="MR29" description="CPU Interrupt Mask on Direct Event input x+32" start="29" size="1" />
+      <BitField name="MR30" description="CPU Interrupt Mask on Direct Event input x+32" start="30" size="1" />
+      <BitField name="MR31" description="CPU Interrupt Mask on Direct Event input x+32" start="31" size="1" />
+    </Register>
+    <Register name="CPUEMR2" description="EXTI event mask register" start="+0x94" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MR32" description="CPU Interrupt Mask on Direct Event input x+32" start="0" size="1" />
+      <BitField name="MR33" description="CPU Interrupt Mask on Direct Event input x+32" start="1" size="1" />
+      <BitField name="MR34" description="CPU Interrupt Mask on Direct Event input x+32" start="2" size="1" />
+      <BitField name="MR35" description="CPU Interrupt Mask on Direct Event input x+32" start="3" size="1" />
+      <BitField name="MR36" description="CPU Interrupt Mask on Direct Event input x+32" start="4" size="1" />
+      <BitField name="MR37" description="CPU Interrupt Mask on Direct Event input x+32" start="5" size="1" />
+      <BitField name="MR38" description="CPU Interrupt Mask on Direct Event input x+32" start="6" size="1" />
+      <BitField name="MR39" description="CPU Interrupt Mask on Direct Event input x+32" start="7" size="1" />
+      <BitField name="MR40" description="CPU Interrupt Mask on Direct Event input x+32" start="8" size="1" />
+      <BitField name="MR41" description="CPU Interrupt Mask on Direct Event input x+32" start="9" size="1" />
+      <BitField name="MR42" description="CPU Interrupt Mask on Direct Event input x+32" start="10" size="1" />
+      <BitField name="MR43" description="CPU Interrupt Mask on Direct Event input x+32" start="11" size="1" />
+      <BitField name="MR44" description="CPU Interrupt Mask on Direct Event input x+32" start="12" size="1" />
+      <BitField name="MR46" description="CPU Interrupt Mask on Direct Event input x+32" start="14" size="1" />
+      <BitField name="MR47" description="CPU Interrupt Mask on Direct Event input x+32" start="15" size="1" />
+      <BitField name="MR48" description="CPU Interrupt Mask on Direct Event input x+32" start="16" size="1" />
+      <BitField name="MR49" description="CPU Interrupt Mask on Direct Event input x+32" start="17" size="1" />
+      <BitField name="MR50" description="CPU Interrupt Mask on Direct Event input x+32" start="18" size="1" />
+      <BitField name="MR51" description="CPU Interrupt Mask on Direct Event input x+32" start="19" size="1" />
+      <BitField name="MR52" description="CPU Interrupt Mask on Direct Event input x+32" start="20" size="1" />
+      <BitField name="MR53" description="CPU Interrupt Mask on Direct Event input x+32" start="21" size="1" />
+      <BitField name="MR54" description="CPU Interrupt Mask on Direct Event input x+32" start="22" size="1" />
+      <BitField name="MR55" description="CPU Interrupt Mask on Direct Event input x+32" start="23" size="1" />
+      <BitField name="MR56" description="CPU Interrupt Mask on Direct Event input x+32" start="24" size="1" />
+      <BitField name="MR57" description="CPU Interrupt Mask on Direct Event input x+32" start="25" size="1" />
+      <BitField name="MR58" description="CPU Interrupt Mask on Direct Event input x+32" start="26" size="1" />
+      <BitField name="MR59" description="CPU Interrupt Mask on Direct Event input x+32" start="27" size="1" />
+      <BitField name="MR60" description="CPU Interrupt Mask on Direct Event input x+32" start="28" size="1" />
+      <BitField name="MR61" description="CPU Interrupt Mask on Direct Event input x+32" start="29" size="1" />
+      <BitField name="MR62" description="CPU Interrupt Mask on Direct Event input x+32" start="30" size="1" />
+      <BitField name="MR63" description="CPU Interrupt Mask on Direct Event input x+32" start="31" size="1" />
+    </Register>
+    <Register name="CPUPR2" description="EXTI pending register" start="+0x98" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PR49" description="Configurable event inputs x+32 Pending bit" start="17" size="1" />
+      <BitField name="PR51" description="Configurable event inputs x+32 Pending bit" start="19" size="1" />
+    </Register>
+    <Register name="CPUIMR3" description="EXTI interrupt mask register" start="+0xA0" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MR64" description="CPU Interrupt Mask on Direct Event input x+64" start="0" size="1" />
+      <BitField name="MR65" description="CPU Interrupt Mask on Direct Event input x+64" start="1" size="1" />
+      <BitField name="MR66" description="CPU Interrupt Mask on Direct Event input x+64" start="2" size="1" />
+      <BitField name="MR67" description="CPU Interrupt Mask on Direct Event input x+64" start="3" size="1" />
+      <BitField name="MR68" description="CPU Interrupt Mask on Direct Event input x+64" start="4" size="1" />
+      <BitField name="MR69" description="CPU Interrupt Mask on Direct Event input x+64" start="5" size="1" />
+      <BitField name="MR70" description="CPU Interrupt Mask on Direct Event input x+64" start="6" size="1" />
+      <BitField name="MR71" description="CPU Interrupt Mask on Direct Event input x+64" start="7" size="1" />
+      <BitField name="MR72" description="CPU Interrupt Mask on Direct Event input x+64" start="8" size="1" />
+      <BitField name="MR73" description="CPU Interrupt Mask on Direct Event input x+64" start="9" size="1" />
+      <BitField name="MR74" description="CPU Interrupt Mask on Direct Event input x+64" start="10" size="1" />
+      <BitField name="MR75" description="CPU Interrupt Mask on Direct Event input x+64" start="11" size="1" />
+      <BitField name="MR76" description="CPU Interrupt Mask on Direct Event input x+64" start="12" size="1" />
+      <BitField name="MR77" description="CPU Interrupt Mask on Direct Event input x+64" start="13" size="1" />
+      <BitField name="MR78" description="CPU Interrupt Mask on Direct Event input x+64" start="14" size="1" />
+      <BitField name="MR79" description="CPU Interrupt Mask on Direct Event input x+64" start="15" size="1" />
+      <BitField name="MR80" description="CPU Interrupt Mask on Direct Event input x+64" start="16" size="1" />
+      <BitField name="MR82" description="CPU Interrupt Mask on Direct Event input x+64" start="18" size="1" />
+      <BitField name="MR84" description="CPU Interrupt Mask on Direct Event input x+64" start="20" size="1" />
+      <BitField name="MR85" description="CPU Interrupt Mask on Direct Event input x+64" start="21" size="1" />
+      <BitField name="MR86" description="CPU Interrupt Mask on Direct Event input x+64" start="22" size="1" />
+      <BitField name="MR87" description="CPU Interrupt Mask on Direct Event input x+64" start="23" size="1" />
+      <BitField name="MR88" description="CPU Interrupt Mask on Direct Event input x+64" start="24" size="1" />
+    </Register>
+    <Register name="CPUEMR3" description="EXTI event mask register" start="+0xA4" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MR64" description="CPU Event mask on Event input x+64" start="0" size="1" />
+      <BitField name="MR65" description="CPU Event mask on Event input x+64" start="1" size="1" />
+      <BitField name="MR66" description="CPU Event mask on Event input x+64" start="2" size="1" />
+      <BitField name="MR67" description="CPU Event mask on Event input x+64" start="3" size="1" />
+      <BitField name="MR68" description="CPU Event mask on Event input x+64" start="4" size="1" />
+      <BitField name="MR69" description="CPU Event mask on Event input x+64" start="5" size="1" />
+      <BitField name="MR70" description="CPU Event mask on Event input x+64" start="6" size="1" />
+      <BitField name="MR71" description="CPU Event mask on Event input x+64" start="7" size="1" />
+      <BitField name="MR72" description="CPU Event mask on Event input x+64" start="8" size="1" />
+      <BitField name="MR73" description="CPU Event mask on Event input x+64" start="9" size="1" />
+      <BitField name="MR74" description="CPU Event mask on Event input x+64" start="10" size="1" />
+      <BitField name="MR75" description="CPU Event mask on Event input x+64" start="11" size="1" />
+      <BitField name="MR76" description="CPU Event mask on Event input x+64" start="12" size="1" />
+      <BitField name="MR77" description="CPU Event mask on Event input x+64" start="13" size="1" />
+      <BitField name="MR78" description="CPU Event mask on Event input x+64" start="14" size="1" />
+      <BitField name="MR79" description="CPU Event mask on Event input x+64" start="15" size="1" />
+      <BitField name="MR80" description="CPU Event mask on Event input x+64" start="16" size="1" />
+      <BitField name="MR82" description="CPU Event mask on Event input x+64" start="18" size="1" />
+      <BitField name="MR84" description="CPU Event mask on Event input x+64" start="20" size="1" />
+      <BitField name="MR85" description="CPU Event mask on Event input x+64" start="21" size="1" />
+      <BitField name="MR86" description="CPU Event mask on Event input x+64" start="22" size="1" />
+      <BitField name="MR87" description="CPU Event mask on Event input x+64" start="23" size="1" />
+      <BitField name="MR88" description="CPU Event mask on Event input x+64" start="24" size="1" />
+    </Register>
+    <Register name="CPUPR3" description="EXTI pending register" start="+0xA8" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PR82" description="Configurable event inputs x+64 Pending bit" start="18" size="1" />
+      <BitField name="PR84" description="Configurable event inputs x+64 Pending bit" start="20" size="1" />
+      <BitField name="PR85" description="Configurable event inputs x+64 Pending bit" start="21" size="1" />
+      <BitField name="PR86" description="Configurable event inputs x+64 Pending bit" start="22" size="1" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="Ethernet_MAC" description="Ethernet: media access control (MAC)" start="0x40028000">
+    <Register name="DMAMR" description="DMA mode register" start="+0x1000" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWR" description="Software Reset" start="0" size="1" access="Read/Write" />
+      <BitField name="DA" description="DMA Tx or Rx Arbitration Scheme" start="1" size="1" access="ReadOnly" />
+      <BitField name="TXPR" description="Transmit priority" start="11" size="1" access="ReadOnly" />
+      <BitField name="PR" description="Priority ratio" start="12" size="3" access="ReadOnly" />
+      <BitField name="INTM" description="Interrupt Mode" start="16" size="1" access="Read/Write" />
+    </Register>
+    <Register name="DMASBMR" description="System bus mode register" start="+0x1004" size="4" reset_value="0x01010000" reset_mask="0xFFFFFFFF">
+      <BitField name="FB" description="Fixed Burst Length" start="0" size="1" access="Read/Write" />
+      <BitField name="AAL" description="Address-Aligned Beats" start="12" size="1" access="Read/Write" />
+      <BitField name="MB" description="Mixed Burst" start="14" size="1" access="ReadOnly" />
+      <BitField name="RB" description="Rebuild INCRx Burst" start="15" size="1" access="ReadOnly" />
+    </Register>
+    <Register name="DMAISR" description="Interrupt status register" start="+0x1008" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DC0IS" description="DMA Channel Interrupt Status" start="0" size="1" />
+      <BitField name="MTLIS" description="MTL Interrupt Status" start="16" size="1" />
+      <BitField name="MACIS" description="MAC Interrupt Status" start="17" size="1" />
+    </Register>
+    <Register name="DMADSR" description="Debug status register" start="+0x100C" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AXWHSTS" description="AHB Master Write Channel" start="0" size="1" />
+      <BitField name="RPS0" description="DMA Channel Receive Process State" start="8" size="4" />
+      <BitField name="TPS0" description="DMA Channel Transmit Process State" start="12" size="4" />
+    </Register>
+    <Register name="DMACCR" description="Channel control register" start="+0x1100" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MSS" description="Maximum Segment Size" start="0" size="14" />
+      <BitField name="PBLX8" description="8xPBL mode" start="16" size="1" />
+      <BitField name="DSL" description="Descriptor Skip Length" start="18" size="3" />
+    </Register>
+    <Register name="DMACTxCR" description="Channel transmit control register" start="+0x1104" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ST" description="Start or Stop Transmission Command" start="0" size="1" />
+      <BitField name="OSF" description="Operate on Second Packet" start="4" size="1" />
+      <BitField name="TSE" description="TCP Segmentation Enabled" start="12" size="1" />
+      <BitField name="TXPBL" description="Transmit Programmable Burst Length" start="16" size="6" />
+    </Register>
+    <Register name="DMACRxCR" description="Channel receive control register" start="+0x1108" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SR" description="Start or Stop Receive Command" start="0" size="1" />
+      <BitField name="RBSZ" description="Receive Buffer size" start="1" size="14" />
+      <BitField name="RXPBL" description="RXPBL" start="16" size="6" />
+      <BitField name="RPF" description="DMA Rx Channel Packet Flush" start="31" size="1" />
+    </Register>
+    <Register name="DMACTxDLAR" description="Channel Tx descriptor list address register" start="+0x1114" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TDESLA" description="Start of Transmit List" start="2" size="30" />
+    </Register>
+    <Register name="DMACRxDLAR" description="Channel Rx descriptor list address register" start="+0x111C" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RDESLA" description="Start of Receive List" start="2" size="30" />
+    </Register>
+    <Register name="DMACTxDTPR" description="Channel Tx descriptor tail pointer register" start="+0x1120" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TDT" description="Transmit Descriptor Tail Pointer" start="2" size="30" />
+    </Register>
+    <Register name="DMACRxDTPR" description="Channel Rx descriptor tail pointer register" start="+0x1128" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RDT" description="Receive Descriptor Tail Pointer" start="2" size="30" />
+    </Register>
+    <Register name="DMACTxRLR" description="Channel Tx descriptor ring length register" start="+0x112C" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TDRL" description="Transmit Descriptor Ring Length" start="0" size="10" />
+    </Register>
+    <Register name="DMACRxRLR" description="Channel Rx descriptor ring length register" start="+0x1130" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RDRL" description="Receive Descriptor Ring Length" start="0" size="10" />
+    </Register>
+    <Register name="DMACIER" description="Channel interrupt enable register" start="+0x1134" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TIE" description="Transmit Interrupt Enable" start="0" size="1" />
+      <BitField name="TXSE" description="Transmit Stopped Enable" start="1" size="1" />
+      <BitField name="TBUE" description="Transmit Buffer Unavailable Enable" start="2" size="1" />
+      <BitField name="RIE" description="Receive Interrupt Enable" start="6" size="1" />
+      <BitField name="RBUE" description="Receive Buffer Unavailable Enable" start="7" size="1" />
+      <BitField name="RSE" description="Receive Stopped Enable" start="8" size="1" />
+      <BitField name="RWTE" description="Receive Watchdog Timeout Enable" start="9" size="1" />
+      <BitField name="ETIE" description="Early Transmit Interrupt Enable" start="10" size="1" />
+      <BitField name="ERIE" description="Early Receive Interrupt Enable" start="11" size="1" />
+      <BitField name="FBEE" description="Fatal Bus Error Enable" start="12" size="1" />
+      <BitField name="CDEE" description="Context Descriptor Error Enable" start="13" size="1" />
+      <BitField name="AIE" description="Abnormal Interrupt Summary Enable" start="14" size="1" />
+      <BitField name="NIE" description="Normal Interrupt Summary Enable" start="15" size="1" />
+    </Register>
+    <Register name="DMACRxIWTR" description="Channel Rx interrupt watchdog timer register" start="+0x1138" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RWT" description="Receive Interrupt Watchdog Timer Count" start="0" size="8" />
+    </Register>
+    <Register name="DMACCATxDR" description="Channel current application transmit descriptor register" start="+0x1144" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CURTDESAPTR" description="Application Transmit Descriptor Address Pointer" start="0" size="32" />
+    </Register>
+    <Register name="DMACCARxDR" description="Channel current application receive descriptor register" start="+0x114C" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CURRDESAPTR" description="Application Receive Descriptor Address Pointer" start="0" size="32" />
+    </Register>
+    <Register name="DMACCATxBR" description="Channel current application transmit buffer register" start="+0x1154" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CURTBUFAPTR" description="Application Transmit Buffer Address Pointer" start="0" size="32" />
+    </Register>
+    <Register name="DMACCARxBR" description="Channel current application receive buffer register" start="+0x115C" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CURRBUFAPTR" description="Application Receive Buffer Address Pointer" start="0" size="32" />
+    </Register>
+    <Register name="DMACSR" description="Channel status register" start="+0x1160" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TI" description="Transmit Interrupt" start="0" size="1" access="Read/Write" />
+      <BitField name="TPS" description="Transmit Process Stopped" start="1" size="1" access="Read/Write" />
+      <BitField name="TBU" description="Transmit Buffer Unavailable" start="2" size="1" access="Read/Write" />
+      <BitField name="RI" description="Receive Interrupt" start="6" size="1" access="Read/Write" />
+      <BitField name="RBU" description="Receive Buffer Unavailable" start="7" size="1" access="Read/Write" />
+      <BitField name="RPS" description="Receive Process Stopped" start="8" size="1" access="Read/Write" />
+      <BitField name="RWT" description="Receive Watchdog Timeout" start="9" size="1" access="Read/Write" />
+      <BitField name="ET" description="Early Transmit Interrupt" start="10" size="1" access="Read/Write" />
+      <BitField name="ER" description="Early Receive Interrupt" start="11" size="1" access="Read/Write" />
+      <BitField name="FBE" description="Fatal Bus Error" start="12" size="1" access="Read/Write" />
+      <BitField name="CDE" description="Context Descriptor Error" start="13" size="1" access="Read/Write" />
+      <BitField name="AIS" description="Abnormal Interrupt Summary" start="14" size="1" access="Read/Write" />
+      <BitField name="NIS" description="Normal Interrupt Summary" start="15" size="1" access="Read/Write" />
+      <BitField name="TEB" description="Tx DMA Error Bits" start="16" size="3" access="ReadOnly" />
+      <BitField name="REB" description="Rx DMA Error Bits" start="19" size="3" access="ReadOnly" />
+    </Register>
+    <Register name="DMACMFCR" description="Channel missed frame count register" start="+0x116C" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MFC" description="Dropped Packet Counters" start="0" size="11" />
+      <BitField name="MFCO" description="Overflow status of the MFC Counter" start="15" size="1" />
+    </Register>
+    <Register name="MTLOMR" description="Operating mode Register" start="+0xC00" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DTXSTS" description="DTXSTS" start="1" size="1" />
+      <BitField name="CNTPRST" description="CNTPRST" start="8" size="1" />
+      <BitField name="CNTCLR" description="CNTCLR" start="9" size="1" />
+    </Register>
+    <Register name="MTLISR" description="Interrupt status Register" start="+0xC20" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="Q0IS" description="Queue interrupt status" start="0" size="1" />
+    </Register>
+    <Register name="MTLTxQOMR" description="Tx queue operating mode Register" start="+0xD00" size="4" reset_value="0x00070008" reset_mask="0xFFFFFFFF">
+      <BitField name="FTQ" description="Flush Transmit Queue" start="0" size="1" access="Read/Write" />
+      <BitField name="TSF" description="Transmit Store and Forward" start="1" size="1" access="Read/Write" />
+      <BitField name="TXQEN" description="Transmit Queue Enable" start="2" size="2" access="ReadOnly" />
+      <BitField name="TTC" description="Transmit Threshold Control" start="4" size="3" access="Read/Write" />
+      <BitField name="TQS" description="Transmit Queue Size" start="16" size="9" access="Read/Write" />
+    </Register>
+    <Register name="MTLTxQUR" description="Tx queue underflow register" start="+0xD04" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="UFFRMCNT" description="Underflow Packet Counter" start="0" size="11" />
+      <BitField name="UFCNTOVF" description="UFCNTOVF" start="11" size="1" />
+    </Register>
+    <Register name="MTLTxQDR" description="Tx queue debug Register" start="+0xD08" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TXQPAUSED" description="TXQPAUSED" start="0" size="1" />
+      <BitField name="TRCSTS" description="TRCSTS" start="1" size="2" />
+      <BitField name="TWCSTS" description="TWCSTS" start="3" size="1" />
+      <BitField name="TXQSTS" description="TXQSTS" start="4" size="1" />
+      <BitField name="TXSTSFSTS" description="TXSTSFSTS" start="5" size="1" />
+      <BitField name="PTXQ" description="PTXQ" start="16" size="3" />
+      <BitField name="STXSTSF" description="STXSTSF" start="20" size="3" />
+    </Register>
+    <Register name="MTLQICSR" description="Queue interrupt control status Register" start="+0xD2C" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TXUNFIS" description="TXUNFIS" start="0" size="1" />
+      <BitField name="TXUIE" description="TXUIE" start="8" size="1" />
+      <BitField name="RXOVFIS" description="RXOVFIS" start="16" size="1" />
+      <BitField name="RXOIE" description="RXOIE" start="24" size="1" />
+    </Register>
+    <Register name="MTLRxQOMR" description="Rx queue operating mode register" start="+0xD30" size="4" reset_value="0x00700000" reset_mask="0xFFFFFFFF">
+      <BitField name="RTC" description="RTC" start="0" size="2" access="Read/Write" />
+      <BitField name="FUP" description="FUP" start="3" size="1" access="Read/Write" />
+      <BitField name="FEP" description="FEP" start="4" size="1" access="Read/Write" />
+      <BitField name="RSF" description="RSF" start="5" size="1" access="Read/Write" />
+      <BitField name="DIS_TCP_EF" description="DIS_TCP_EF" start="6" size="1" access="Read/Write" />
+      <BitField name="EHFC" description="EHFC" start="7" size="1" access="Read/Write" />
+      <BitField name="RFA" description="RFA" start="8" size="3" access="Read/Write" />
+      <BitField name="RFD" description="RFD" start="14" size="3" access="Read/Write" />
+      <BitField name="RQS" description="RQS" start="20" size="3" access="ReadOnly" />
+    </Register>
+    <Register name="MTLRxQMPOCR" description="Rx queue missed packet and overflow counter register" start="+0xD34" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OVFPKTCNT" description="OVFPKTCNT" start="0" size="11" />
+      <BitField name="OVFCNTOVF" description="OVFCNTOVF" start="11" size="1" />
+      <BitField name="MISPKTCNT" description="MISPKTCNT" start="16" size="11" />
+      <BitField name="MISCNTOVF" description="MISCNTOVF" start="27" size="1" />
+    </Register>
+    <Register name="MTLRxQDR" description="Rx queue debug register" start="+0xD38" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RWCSTS" description="RWCSTS" start="0" size="1" />
+      <BitField name="RRCSTS" description="RRCSTS" start="1" size="2" />
+      <BitField name="RXQSTS" description="RXQSTS" start="4" size="2" />
+      <BitField name="PRXQ" description="PRXQ" start="16" size="14" />
+    </Register>
+    <Register name="MACCR" description="Operating mode configuration register" start="+0x0" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RE" description="Receiver Enable" start="0" size="1" />
+      <BitField name="TE" description="TE" start="1" size="1" />
+      <BitField name="PRELEN" description="PRELEN" start="2" size="2" />
+      <BitField name="DC" description="DC" start="4" size="1" />
+      <BitField name="BL" description="BL" start="5" size="2" />
+      <BitField name="DR" description="DR" start="8" size="1" />
+      <BitField name="DCRS" description="DCRS" start="9" size="1" />
+      <BitField name="DO" description="DO" start="10" size="1" />
+      <BitField name="ECRSFD" description="ECRSFD" start="11" size="1" />
+      <BitField name="LM" description="LM" start="12" size="1" />
+      <BitField name="DM" description="DM" start="13" size="1" />
+      <BitField name="FES" description="FES" start="14" size="1" />
+      <BitField name="JE" description="JE" start="16" size="1" />
+      <BitField name="JD" description="JD" start="17" size="1" />
+      <BitField name="WD" description="WD" start="19" size="1" />
+      <BitField name="ACS" description="ACS" start="20" size="1" />
+      <BitField name="CST" description="CST" start="21" size="1" />
+      <BitField name="S2KP" description="S2KP" start="22" size="1" />
+      <BitField name="GPSLCE" description="GPSLCE" start="23" size="1" />
+      <BitField name="IPG" description="IPG" start="24" size="3" />
+      <BitField name="IPC" description="IPC" start="27" size="1" />
+      <BitField name="SARC" description="SARC" start="28" size="3" />
+      <BitField name="ARPEN" description="ARPEN" start="31" size="1" />
+    </Register>
+    <Register name="MACECR" description="Extended operating mode configuration register" start="+0x4" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="GPSL" description="GPSL" start="0" size="14" />
+      <BitField name="DCRCC" description="DCRCC" start="16" size="1" />
+      <BitField name="SPEN" description="SPEN" start="17" size="1" />
+      <BitField name="USP" description="USP" start="18" size="1" />
+      <BitField name="EIPGEN" description="EIPGEN" start="24" size="1" />
+      <BitField name="EIPG" description="EIPG" start="25" size="5" />
+    </Register>
+    <Register name="MACPFR" description="Packet filtering control register" start="+0x8" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PR" description="PR" start="0" size="1" />
+      <BitField name="HUC" description="HUC" start="1" size="1" />
+      <BitField name="HMC" description="HMC" start="2" size="1" />
+      <BitField name="DAIF" description="DAIF" start="3" size="1" />
+      <BitField name="PM" description="PM" start="4" size="1" />
+      <BitField name="DBF" description="DBF" start="5" size="1" />
+      <BitField name="PCF" description="PCF" start="6" size="2" />
+      <BitField name="SAIF" description="SAIF" start="8" size="1" />
+      <BitField name="SAF" description="SAF" start="9" size="1" />
+      <BitField name="HPF" description="HPF" start="10" size="1" />
+      <BitField name="VTFE" description="VTFE" start="16" size="1" />
+      <BitField name="IPFE" description="IPFE" start="20" size="1" />
+      <BitField name="DNTU" description="DNTU" start="21" size="1" />
+      <BitField name="RA" description="RA" start="31" size="1" />
+    </Register>
+    <Register name="MACWTR" description="Watchdog timeout register" start="+0xC" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="WTO" description="WTO" start="0" size="4" />
+      <BitField name="PWE" description="PWE" start="8" size="1" />
+    </Register>
+    <Register name="MACHT0R" description="Hash Table 0 register" start="+0x10" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HT31T0" description="HT31T0" start="0" size="32" />
+    </Register>
+    <Register name="MACHT1R" description="Hash Table 1 register" start="+0x14" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HT63T32" description="HT63T32" start="0" size="32" />
+    </Register>
+    <Register name="MACVTR" description="VLAN tag register" start="+0x50" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="VL" description="VL" start="0" size="16" />
+      <BitField name="ETV" description="ETV" start="16" size="1" />
+      <BitField name="VTIM" description="VTIM" start="17" size="1" />
+      <BitField name="ESVL" description="ESVL" start="18" size="1" />
+      <BitField name="ERSVLM" description="ERSVLM" start="19" size="1" />
+      <BitField name="DOVLTC" description="DOVLTC" start="20" size="1" />
+      <BitField name="EVLS" description="EVLS" start="21" size="2" />
+      <BitField name="EVLRXS" description="EVLRXS" start="24" size="1" />
+      <BitField name="VTHM" description="VTHM" start="25" size="1" />
+      <BitField name="EDVLP" description="EDVLP" start="26" size="1" />
+      <BitField name="ERIVLT" description="ERIVLT" start="27" size="1" />
+      <BitField name="EIVLS" description="EIVLS" start="28" size="2" />
+      <BitField name="EIVLRXS" description="EIVLRXS" start="31" size="1" />
+    </Register>
+    <Register name="MACVHTR" description="VLAN Hash table register" start="+0x58" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="VLHT" description="VLHT" start="0" size="16" />
+    </Register>
+    <Register name="MACVIR" description="VLAN inclusion register" start="+0x60" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="VLT" description="VLT" start="0" size="16" />
+      <BitField name="VLC" description="VLC" start="16" size="2" />
+      <BitField name="VLP" description="VLP" start="18" size="1" />
+      <BitField name="CSVL" description="CSVL" start="19" size="1" />
+      <BitField name="VLTI" description="VLTI" start="20" size="1" />
+    </Register>
+    <Register name="MACIVIR" description="Inner VLAN inclusion register" start="+0x64" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="VLT" description="VLT" start="0" size="16" />
+      <BitField name="VLC" description="VLC" start="16" size="2" />
+      <BitField name="VLP" description="VLP" start="18" size="1" />
+      <BitField name="CSVL" description="CSVL" start="19" size="1" />
+      <BitField name="VLTI" description="VLTI" start="20" size="1" />
+    </Register>
+    <Register name="MACQTxFCR" description="Tx Queue flow control register" start="+0x70" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FCB_BPA" description="FCB_BPA" start="0" size="1" />
+      <BitField name="TFE" description="TFE" start="1" size="1" />
+      <BitField name="PLT" description="PLT" start="4" size="3" />
+      <BitField name="DZPQ" description="DZPQ" start="7" size="1" />
+      <BitField name="PT" description="PT" start="16" size="16" />
+    </Register>
+    <Register name="MACRxFCR" description="Rx flow control register" start="+0x90" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RFE" description="RFE" start="0" size="1" />
+      <BitField name="UP" description="UP" start="1" size="1" />
+    </Register>
+    <Register name="MACISR" description="Interrupt status register" start="+0xB0" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PHYIS" description="PHYIS" start="3" size="1" />
+      <BitField name="PMTIS" description="PMTIS" start="4" size="1" />
+      <BitField name="LPIIS" description="LPIIS" start="5" size="1" />
+      <BitField name="MMCIS" description="MMCIS" start="8" size="1" />
+      <BitField name="MMCRXIS" description="MMCRXIS" start="9" size="1" />
+      <BitField name="MMCTXIS" description="MMCTXIS" start="10" size="1" />
+      <BitField name="TSIS" description="TSIS" start="12" size="1" />
+      <BitField name="TXSTSIS" description="TXSTSIS" start="13" size="1" />
+      <BitField name="RXSTSIS" description="RXSTSIS" start="14" size="1" />
+    </Register>
+    <Register name="MACIER" description="Interrupt enable register" start="+0xB4" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PHYIE" description="PHYIE" start="3" size="1" />
+      <BitField name="PMTIE" description="PMTIE" start="4" size="1" />
+      <BitField name="LPIIE" description="LPIIE" start="5" size="1" />
+      <BitField name="TSIE" description="TSIE" start="12" size="1" />
+      <BitField name="TXSTSIE" description="TXSTSIE" start="13" size="1" />
+      <BitField name="RXSTSIE" description="RXSTSIE" start="14" size="1" />
+    </Register>
+    <Register name="MACRxTxSR" description="Rx Tx status register" start="+0xB8" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TJT" description="TJT" start="0" size="1" />
+      <BitField name="NCARR" description="NCARR" start="1" size="1" />
+      <BitField name="LCARR" description="LCARR" start="2" size="1" />
+      <BitField name="EXDEF" description="EXDEF" start="3" size="1" />
+      <BitField name="LCOL" description="LCOL" start="4" size="1" />
+      <BitField name="EXCOL" description="LCOL" start="5" size="1" />
+      <BitField name="RWT" description="RWT" start="8" size="1" />
+    </Register>
+    <Register name="MACPCSR" description="PMT control status register" start="+0xC0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PWRDWN" description="PWRDWN" start="0" size="1" access="Read/Write" />
+      <BitField name="MGKPKTEN" description="MGKPKTEN" start="1" size="1" access="Read/Write" />
+      <BitField name="RWKPKTEN" description="RWKPKTEN" start="2" size="1" access="Read/Write" />
+      <BitField name="MGKPRCVD" description="MGKPRCVD" start="5" size="1" access="ReadOnly" />
+      <BitField name="RWKPRCVD" description="RWKPRCVD" start="6" size="1" access="ReadOnly" />
+      <BitField name="GLBLUCAST" description="GLBLUCAST" start="9" size="1" access="Read/Write" />
+      <BitField name="RWKPFE" description="RWKPFE" start="10" size="1" access="Read/Write" />
+      <BitField name="RWKPTR" description="RWKPTR" start="24" size="5" access="Read/Write" />
+      <BitField name="RWKFILTRST" description="RWKFILTRST" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="MACRWKPFR" description="Remove wakeup packet filter register" start="+0xC4" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="WKUPFRMFTR" description="WKUPFRMFTR" start="0" size="32" />
+    </Register>
+    <Register name="MACLCSR" description="LPI control status register" start="+0xD0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TLPIEN" description="TLPIEN" start="0" size="1" access="ReadOnly" />
+      <BitField name="TLPIEX" description="TLPIEX" start="1" size="1" access="ReadOnly" />
+      <BitField name="RLPIEN" description="RLPIEN" start="2" size="1" access="ReadOnly" />
+      <BitField name="RLPIEX" description="RLPIEX" start="3" size="1" access="ReadOnly" />
+      <BitField name="TLPIST" description="TLPIST" start="8" size="1" access="ReadOnly" />
+      <BitField name="RLPIST" description="RLPIST" start="9" size="1" access="ReadOnly" />
+      <BitField name="LPIEN" description="LPIEN" start="16" size="1" access="Read/Write" />
+      <BitField name="PLS" description="PLS" start="17" size="1" access="Read/Write" />
+      <BitField name="PLSEN" description="PLSEN" start="18" size="1" access="Read/Write" />
+      <BitField name="LPITXA" description="LPITXA" start="19" size="1" access="Read/Write" />
+      <BitField name="LPITE" description="LPITE" start="20" size="1" access="Read/Write" />
+      <BitField name="LPITCSE" description="LPITCSE" start="21" size="1" access="Read/Write" />
+    </Register>
+    <Register name="MACLTCR" description="LPI timers control register" start="+0xD4" size="4" access="Read/Write" reset_value="0x03E80000" reset_mask="0xFFFFFFFF">
+      <BitField name="TWT" description="TWT" start="0" size="16" />
+      <BitField name="LST" description="LST" start="16" size="10" />
+    </Register>
+    <Register name="MACLETR" description="LPI entry timer register" start="+0xD8" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LPIET" description="LPIET" start="0" size="17" />
+    </Register>
+    <Register name="MAC1USTCR" description="1-microsecond-tick counter register" start="+0xDC" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TIC_1US_CNTR" description="TIC_1US_CNTR" start="0" size="12" />
+    </Register>
+    <Register name="MACVR" description="Version register" start="+0x110" size="4" access="ReadOnly" reset_value="0x00003041" reset_mask="0xFFFFFFFF">
+      <BitField name="SNPSVER" description="SNPSVER" start="0" size="8" />
+      <BitField name="USERVER" description="USERVER" start="8" size="8" />
+    </Register>
+    <Register name="MACHWF1R" description="HW feature 1 register" start="+0x120" size="4" access="ReadOnly" reset_value="0x11841904" reset_mask="0xFFFFFFFF">
+      <BitField name="RXFIFOSIZE" description="RXFIFOSIZE" start="0" size="5" />
+      <BitField name="TXFIFOSIZE" description="TXFIFOSIZE" start="6" size="5" />
+      <BitField name="OSTEN" description="OSTEN" start="11" size="1" />
+      <BitField name="PTOEN" description="PTOEN" start="12" size="1" />
+      <BitField name="ADVTHWORD" description="ADVTHWORD" start="13" size="1" />
+      <BitField name="DCBEN" description="DCBEN" start="16" size="1" />
+      <BitField name="SPHEN" description="SPHEN" start="17" size="1" />
+      <BitField name="TSOEN" description="TSOEN" start="18" size="1" />
+      <BitField name="DBGMEMA" description="DBGMEMA" start="19" size="1" />
+      <BitField name="AVSEL" description="AVSEL" start="20" size="1" />
+      <BitField name="HASHTBLSZ" description="HASHTBLSZ" start="24" size="2" />
+      <BitField name="L3L4FNUM" description="L3L4FNUM" start="27" size="4" />
+    </Register>
+    <Register name="MACHWF2R" description="HW feature 2 register" start="+0x124" size="4" access="ReadOnly" reset_value="0x41000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RXQCNT" description="RXQCNT" start="0" size="4" />
+      <BitField name="TXQCNT" description="TXQCNT" start="6" size="4" />
+      <BitField name="RXCHCNT" description="RXCHCNT" start="12" size="4" />
+      <BitField name="TXCHCNT" description="TXCHCNT" start="18" size="4" />
+      <BitField name="PPSOUTNUM" description="PPSOUTNUM" start="24" size="3" />
+      <BitField name="AUXSNAPNUM" description="AUXSNAPNUM" start="28" size="3" />
+    </Register>
+    <Register name="MACMDIOAR" description="MDIO address register" start="+0x200" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MB" description="MB" start="0" size="1" />
+      <BitField name="C45E" description="C45E" start="1" size="1" />
+      <BitField name="GOC" description="GOC" start="2" size="2" />
+      <BitField name="SKAP" description="SKAP" start="4" size="1" />
+      <BitField name="CR" description="CR" start="8" size="4" />
+      <BitField name="NTC" description="NTC" start="12" size="3" />
+      <BitField name="RDA" description="RDA" start="16" size="5" />
+      <BitField name="PA" description="PA" start="21" size="5" />
+      <BitField name="BTB" description="BTB" start="26" size="1" />
+      <BitField name="PSE" description="PSE" start="27" size="1" />
+    </Register>
+    <Register name="MACMDIODR" description="MDIO data register" start="+0x204" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MD" description="MD" start="0" size="16" />
+      <BitField name="RA" description="RA" start="16" size="16" />
+    </Register>
+    <Register name="MACARPAR" description="ARP address register" start="+0xAE0" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ARPPA" description="ARPPA" start="0" size="32" />
+    </Register>
+    <Register name="MACA0HR" description="Address 0 high register" start="+0x300" size="4" reset_value="0x8000FFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="ADDRHI" description="ADDRHI" start="0" size="16" access="Read/Write" />
+      <BitField name="AE" description="AE" start="31" size="1" access="ReadOnly" />
+    </Register>
+    <Register name="MACA0LR" description="Address 0 low register" start="+0x304" size="4" access="Read/Write" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="ADDRLO" description="ADDRLO" start="0" size="32" />
+    </Register>
+    <Register name="MACA1LR" description="Address 1 low register" start="+0x30C" size="4" access="Read/Write" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="ADDRLO" description="ADDRLO" start="0" size="32" />
+    </Register>
+    <Register name="MACA2LR" description="Address 2 low register" start="+0x314" size="4" access="Read/Write" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="ADDRLO" description="ADDRLO" start="0" size="32" />
+    </Register>
+    <Register name="MACA3LR" description="Address 3 low register" start="+0x31C" size="4" access="Read/Write" reset_value="0xFFFFFFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="ADDRLO" description="ADDRLO" start="0" size="32" />
+    </Register>
+    <Register name="MACA1HR" description="Address 1 high register" start="+0x308" size="4" access="Read/Write" reset_value="0x0000FFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="ADDRHI" description="ADDRHI" start="0" size="16" />
+      <BitField name="MBC" description="MBC" start="24" size="6" />
+      <BitField name="SA" description="SA" start="30" size="1" />
+      <BitField name="AE" description="AE" start="31" size="1" />
+    </Register>
+    <Register name="MACA2HR" description="Address 2 high register" start="+0x310" size="4" access="Read/Write" reset_value="0x0000FFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="ADDRHI" description="ADDRHI" start="0" size="16" />
+      <BitField name="MBC" description="MBC" start="24" size="6" />
+      <BitField name="SA" description="SA" start="30" size="1" />
+      <BitField name="AE" description="AE" start="31" size="1" />
+    </Register>
+    <Register name="MACA3HR" description="Address 3 high register" start="+0x318" size="4" access="Read/Write" reset_value="0x0000FFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="ADDRHI" description="ADDRHI" start="0" size="16" />
+      <BitField name="MBC" description="MBC" start="24" size="6" />
+      <BitField name="SA" description="SA" start="30" size="1" />
+      <BitField name="AE" description="AE" start="31" size="1" />
+    </Register>
+    <Register name="MMC_CONTROL" description="MMC control register" start="+0x700" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CNTRST" description="CNTRST" start="0" size="1" />
+      <BitField name="CNTSTOPRO" description="CNTSTOPRO" start="1" size="1" />
+      <BitField name="RSTONRD" description="RSTONRD" start="2" size="1" />
+      <BitField name="CNTFREEZ" description="CNTFREEZ" start="3" size="1" />
+      <BitField name="CNTPRST" description="CNTPRST" start="4" size="1" />
+      <BitField name="CNTPRSTLVL" description="CNTPRSTLVL" start="5" size="1" />
+      <BitField name="UCDBC" description="UCDBC" start="8" size="1" />
+    </Register>
+    <Register name="MMC_RX_INTERRUPT" description="MMC Rx interrupt register" start="+0x704" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RXCRCERPIS" description="RXCRCERPIS" start="5" size="1" />
+      <BitField name="RXALGNERPIS" description="RXALGNERPIS" start="6" size="1" />
+      <BitField name="RXUCGPIS" description="RXUCGPIS" start="17" size="1" />
+      <BitField name="RXLPIUSCIS" description="RXLPIUSCIS" start="26" size="1" />
+      <BitField name="RXLPITRCIS" description="RXLPITRCIS" start="27" size="1" />
+    </Register>
+    <Register name="MMC_TX_INTERRUPT" description="MMC Tx interrupt register" start="+0x708" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TXSCOLGPIS" description="TXSCOLGPIS" start="14" size="1" />
+      <BitField name="TXMCOLGPIS" description="TXMCOLGPIS" start="15" size="1" />
+      <BitField name="TXGPKTIS" description="TXGPKTIS" start="21" size="1" />
+      <BitField name="TXLPIUSCIS" description="TXLPIUSCIS" start="26" size="1" />
+      <BitField name="TXLPITRCIS" description="TXLPITRCIS" start="27" size="1" />
+    </Register>
+    <Register name="MMC_RX_INTERRUPT_MASK" description="MMC Rx interrupt mask register" start="+0x70C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RXCRCERPIM" description="RXCRCERPIM" start="5" size="1" access="Read/Write" />
+      <BitField name="RXALGNERPIM" description="RXALGNERPIM" start="6" size="1" access="Read/Write" />
+      <BitField name="RXUCGPIM" description="RXUCGPIM" start="17" size="1" access="Read/Write" />
+      <BitField name="RXLPIUSCIM" description="RXLPIUSCIM" start="26" size="1" access="Read/Write" />
+      <BitField name="RXLPITRCIM" description="RXLPITRCIM" start="27" size="1" access="ReadOnly" />
+    </Register>
+    <Register name="MMC_TX_INTERRUPT_MASK" description="MMC Tx interrupt mask register" start="+0x710" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TXSCOLGPIM" description="TXSCOLGPIM" start="14" size="1" access="Read/Write" />
+      <BitField name="TXMCOLGPIM" description="TXMCOLGPIM" start="15" size="1" access="Read/Write" />
+      <BitField name="TXGPKTIM" description="TXGPKTIM" start="21" size="1" access="Read/Write" />
+      <BitField name="TXLPIUSCIM" description="TXLPIUSCIM" start="26" size="1" access="Read/Write" />
+      <BitField name="TXLPITRCIM" description="TXLPITRCIM" start="27" size="1" access="ReadOnly" />
+    </Register>
+    <Register name="TX_SINGLE_COLLISION_GOOD_PACKETS" description="Tx single collision good packets register" start="+0x74C" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TXSNGLCOLG" description="TXSNGLCOLG" start="0" size="32" />
+    </Register>
+    <Register name="TX_MULTIPLE_COLLISION_GOOD_PACKETS" description="Tx multiple collision good packets register" start="+0x750" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TXMULTCOLG" description="TXMULTCOLG" start="0" size="32" />
+    </Register>
+    <Register name="TX_PACKET_COUNT_GOOD" description="Tx packet count good register" start="+0x768" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TXPKTG" description="TXPKTG" start="0" size="32" />
+    </Register>
+    <Register name="RX_CRC_ERROR_PACKETS" description="Rx CRC error packets register" start="+0x794" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RXCRCERR" description="RXCRCERR" start="0" size="32" />
+    </Register>
+    <Register name="RX_ALIGNMENT_ERROR_PACKETS" description="Rx alignment error packets register" start="+0x798" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RXALGNERR" description="RXALGNERR" start="0" size="32" />
+    </Register>
+    <Register name="RX_UNICAST_PACKETS_GOOD" description="Rx unicast packets good register" start="+0x7C4" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RXUCASTG" description="RXUCASTG" start="0" size="32" />
+    </Register>
+    <Register name="TX_LPI_USEC_CNTR" description="Tx LPI microsecond timer register" start="+0x7EC" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TXLPIUSC" description="TXLPIUSC" start="0" size="32" />
+    </Register>
+    <Register name="TX_LPI_TRAN_CNTR" description="Tx LPI transition counter register" start="+0x7F0" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TXLPITRC" description="TXLPITRC" start="0" size="32" />
+    </Register>
+    <Register name="RX_LPI_USEC_CNTR" description="Rx LPI microsecond counter register" start="+0x7F4" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RXLPIUSC" description="RXLPIUSC" start="0" size="32" />
+    </Register>
+    <Register name="RX_LPI_TRAN_CNTR" description="Rx LPI transition counter register" start="+0x7F8" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RXLPITRC" description="RXLPITRC" start="0" size="32" />
+    </Register>
+    <Register name="MACL3L4C0R" description="L3 and L4 control 0 register" start="+0x900" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="L3PEN0" description="L3PEN0" start="0" size="1" />
+      <BitField name="L3SAM0" description="L3SAM0" start="2" size="1" />
+      <BitField name="L3SAIM0" description="L3SAIM0" start="3" size="1" />
+      <BitField name="L3DAM0" description="L3DAM0" start="4" size="1" />
+      <BitField name="L3DAIM0" description="L3DAIM0" start="5" size="1" />
+      <BitField name="L3HSBM0" description="L3HSBM0" start="6" size="5" />
+      <BitField name="L3HDBM0" description="L3HDBM0" start="11" size="5" />
+      <BitField name="L4PEN0" description="L4PEN0" start="16" size="1" />
+      <BitField name="L4SPM0" description="L4SPM0" start="18" size="1" />
+      <BitField name="L4SPIM0" description="L4SPIM0" start="19" size="1" />
+      <BitField name="L4DPM0" description="L4DPM0" start="20" size="1" />
+      <BitField name="L4DPIM0" description="L4DPIM0" start="21" size="1" />
+    </Register>
+    <Register name="MACL4A0R" description="Layer4 address filter 0 register" start="+0x904" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="L4SP0" description="L4SP0" start="0" size="16" />
+      <BitField name="L4DP0" description="L4DP0" start="16" size="16" />
+    </Register>
+    <Register name="MACDR" description="Debug register" start="+0x114" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RPESTS" description="RPESTS" start="0" size="1" />
+      <BitField name="RFCFCSTS" description="RFCFCSTS" start="1" size="2" />
+      <BitField name="TPESTS" description="TPESTS" start="16" size="1" />
+      <BitField name="TFCSTS" description="TFCSTS" start="17" size="2" />
+    </Register>
+    <Register name="MACL3A00R" description="MACL3A00R" start="+0x910" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="L3A00" description="L3A00" start="0" size="32" />
+    </Register>
+    <Register name="MACL3A10R" description="Layer3 address 1 filter 0 register" start="+0x914" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="L3A10" description="L3A10" start="0" size="32" />
+    </Register>
+    <Register name="MACL3A20" description="Layer3 Address 2 filter 0 register" start="+0x918" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="L3A20" description="L3A20" start="0" size="32" />
+    </Register>
+    <Register name="MACL3A30" description="Layer3 Address 3 filter 0 register" start="+0x91C" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="L3A30" description="L3A30" start="0" size="32" />
+    </Register>
+    <Register name="MACL3L4C1R" description="L3 and L4 control 1 register" start="+0x930" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="L3PEN1" description="L3PEN1" start="0" size="1" />
+      <BitField name="L3SAM1" description="L3SAM1" start="2" size="1" />
+      <BitField name="L3SAIM1" description="L3SAIM1" start="3" size="1" />
+      <BitField name="L3DAM1" description="L3DAM1" start="4" size="1" />
+      <BitField name="L3DAIM1" description="L3DAIM1" start="5" size="1" />
+      <BitField name="L3HSBM1" description="L3HSBM1" start="6" size="5" />
+      <BitField name="L3HDBM1" description="L3HDBM1" start="11" size="5" />
+      <BitField name="L4PEN1" description="L4PEN1" start="16" size="1" />
+      <BitField name="L4SPM1" description="L4SPM1" start="18" size="1" />
+      <BitField name="L4SPIM1" description="L4SPIM1" start="19" size="1" />
+      <BitField name="L4DPM1" description="L4DPM1" start="20" size="1" />
+      <BitField name="L4DPIM1" description="L4DPIM1" start="21" size="1" />
+    </Register>
+    <Register name="MACL4A1R" description="Layer 4 address filter 1 register" start="+0x934" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="L4SP1" description="L4SP1" start="0" size="16" />
+      <BitField name="L4DP1" description="L4DP1" start="16" size="16" />
+    </Register>
+    <Register name="MACL3A01R" description="Layer3 address 0 filter 1 Register" start="+0x940" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="L3A01" description="L3A01" start="0" size="32" />
+    </Register>
+    <Register name="MACL3A11R" description="Layer3 address 1 filter 1 register" start="+0x944" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="L3A11" description="L3A11" start="0" size="32" />
+    </Register>
+    <Register name="MACL3A21R" description="Layer3 address 2 filter 1 Register" start="+0x948" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="L3A21" description="L3A21" start="0" size="32" />
+    </Register>
+    <Register name="MACL3A31R" description="Layer3 address 3 filter 1 register" start="+0x94C" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="L3A31" description="L3A31" start="0" size="32" />
+    </Register>
+    <Register name="MACTSCR" description="Timestamp control Register" start="+0xB00" size="4" reset_value="0x00000200" reset_mask="0xFFFFFFFF">
+      <BitField name="TSENA" description="TSENA" start="0" size="1" access="Read/Write" />
+      <BitField name="TSCFUPDT" description="TSCFUPDT" start="1" size="1" access="Read/Write" />
+      <BitField name="TSINIT" description="TSINIT" start="2" size="1" access="Read/Write" />
+      <BitField name="TSUPDT" description="TSUPDT" start="3" size="1" access="Read/Write" />
+      <BitField name="TSADDREG" description="TSADDREG" start="5" size="1" access="Read/Write" />
+      <BitField name="TSENALL" description="TSENALL" start="8" size="1" access="Read/Write" />
+      <BitField name="TSCTRLSSR" description="TSCTRLSSR" start="9" size="1" access="Read/Write" />
+      <BitField name="TSVER2ENA" description="TSVER2ENA" start="10" size="1" access="Read/Write" />
+      <BitField name="TSIPENA" description="TSIPENA" start="11" size="1" access="Read/Write" />
+      <BitField name="TSIPV6ENA" description="TSIPV6ENA" start="12" size="1" access="Read/Write" />
+      <BitField name="TSIPV4ENA" description="TSIPV4ENA" start="13" size="1" access="Read/Write" />
+      <BitField name="TSEVNTENA" description="TSEVNTENA" start="14" size="1" access="Read/Write" />
+      <BitField name="TSMSTRENA" description="TSMSTRENA" start="15" size="1" access="Read/Write" />
+      <BitField name="SNAPTYPSEL" description="SNAPTYPSEL" start="16" size="2" access="Read/Write" />
+      <BitField name="TSENMACADDR" description="TSENMACADDR" start="18" size="1" access="Read/Write" />
+      <BitField name="CSC" description="CSC" start="19" size="1" access="ReadOnly" />
+      <BitField name="TXTSSTSM" description="TXTSSTSM" start="24" size="1" access="Read/Write" />
+    </Register>
+    <Register name="MACSSIR" description="Sub-second increment register" start="+0xB04" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SNSINC" description="SNSINC" start="8" size="8" />
+      <BitField name="SSINC" description="SSINC" start="16" size="8" />
+    </Register>
+    <Register name="MACSTSR" description="System time seconds register" start="+0xB08" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TSS" description="TSS" start="0" size="32" />
+    </Register>
+    <Register name="MACSTNR" description="System time nanoseconds register" start="+0xB0C" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TSSS" description="TSSS" start="0" size="31" />
+    </Register>
+    <Register name="MACSTSUR" description="System time seconds update register" start="+0xB10" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TSS" description="TSS" start="0" size="32" />
+    </Register>
+    <Register name="MACSTNUR" description="System time nanoseconds update register" start="+0xB14" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TSSS" description="TSSS" start="0" size="31" />
+      <BitField name="ADDSUB" description="ADDSUB" start="31" size="1" />
+    </Register>
+    <Register name="MACTSAR" description="Timestamp addend register" start="+0xB18" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TSAR" description="TSAR" start="0" size="32" />
+    </Register>
+    <Register name="MACTSSR" description="Timestamp status register" start="+0xB20" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TSSOVF" description="TSSOVF" start="0" size="1" />
+      <BitField name="TSTARGT0" description="TSTARGT0" start="1" size="1" />
+      <BitField name="AUXTSTRIG" description="AUXTSTRIG" start="2" size="1" />
+      <BitField name="TSTRGTERR0" description="TSTRGTERR0" start="3" size="1" />
+      <BitField name="TXTSSIS" description="TXTSSIS" start="15" size="1" />
+      <BitField name="ATSSTN" description="ATSSTN" start="16" size="4" />
+      <BitField name="ATSSTM" description="ATSSTM" start="24" size="1" />
+      <BitField name="ATSNS" description="ATSNS" start="25" size="5" />
+    </Register>
+    <Register name="MACTxTSSNR" description="Tx timestamp status nanoseconds register" start="+0xB30" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TXTSSLO" description="TXTSSLO" start="0" size="31" />
+      <BitField name="TXTSSMIS" description="TXTSSMIS" start="31" size="1" />
+    </Register>
+    <Register name="MACTxTSSSR" description="Tx timestamp status seconds register" start="+0xB34" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TXTSSHI" description="TXTSSHI" start="0" size="32" />
+    </Register>
+    <Register name="MACACR" description="Auxiliary control register" start="+0xB40" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ATSFC" description="ATSFC" start="0" size="1" />
+      <BitField name="ATSEN0" description="ATSEN0" start="4" size="1" />
+      <BitField name="ATSEN1" description="ATSEN1" start="5" size="1" />
+      <BitField name="ATSEN2" description="ATSEN2" start="6" size="1" />
+      <BitField name="ATSEN3" description="ATSEN3" start="7" size="1" />
+    </Register>
+    <Register name="MACATSNR" description="Auxiliary timestamp nanoseconds register" start="+0xB48" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AUXTSLO" description="AUXTSLO" start="0" size="31" />
+    </Register>
+    <Register name="MACATSSR" description="Auxiliary timestamp seconds register" start="+0xB4C" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AUXTSHI" description="AUXTSHI" start="0" size="32" />
+    </Register>
+    <Register name="MACTSIACR" description="Timestamp Ingress asymmetric correction register" start="+0xB50" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OSTIAC" description="OSTIAC" start="0" size="32" />
+    </Register>
+    <Register name="MACTSEACR" description="Timestamp Egress asymmetric correction register" start="+0xB54" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OSTEAC" description="OSTEAC" start="0" size="32" />
+    </Register>
+    <Register name="MACTSICNR" description="Timestamp Ingress correction nanosecond register" start="+0xB58" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TSIC" description="TSIC" start="0" size="32" />
+    </Register>
+    <Register name="MACTSECNR" description="Timestamp Egress correction nanosecond register" start="+0xB5C" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TSEC" description="TSEC" start="0" size="32" />
+    </Register>
+    <Register name="MACPPSCR" description="PPS control register" start="+0xB70" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PPSCTRL" description="PPSCTRL" start="0" size="4" />
+      <BitField name="PPSEN0" description="PPSEN0" start="4" size="1" />
+      <BitField name="TRGTMODSEL0" description="TRGTMODSEL0" start="5" size="2" />
+    </Register>
+    <Register name="MACPPSTTSR" description="PPS target time seconds register" start="+0xB80" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TSTRH0" description="TSTRH0" start="0" size="31" />
+    </Register>
+    <Register name="MACPPSTTNR" description="PPS target time nanoseconds register" start="+0xB84" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TTSL0" description="TTSL0" start="0" size="31" />
+      <BitField name="TRGTBUSY0" description="TRGTBUSY0" start="31" size="1" />
+    </Register>
+    <Register name="MACPPSIR" description="PPS interval register" start="+0xB88" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PPSINT0" description="PPSINT0" start="0" size="32" />
+    </Register>
+    <Register name="MACPPSWR" description="PPS width register" start="+0xB8C" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PPSWIDTH0" description="PPSWIDTH0" start="0" size="32" />
+    </Register>
+    <Register name="MACPOCR" description="PTP Offload control register" start="+0xBC0" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PTOEN" description="PTOEN" start="0" size="1" />
+      <BitField name="ASYNCEN" description="ASYNCEN" start="1" size="1" />
+      <BitField name="APDREQEN" description="APDREQEN" start="2" size="1" />
+      <BitField name="ASYNCTRIG" description="ASYNCTRIG" start="4" size="1" />
+      <BitField name="APDREQTRIG" description="APDREQTRIG" start="5" size="1" />
+      <BitField name="DRRDIS" description="DRRDIS" start="6" size="1" />
+      <BitField name="DN" description="DN" start="8" size="8" />
+    </Register>
+    <Register name="MACSPI0R" description="PTP Source Port Identity 0 Register" start="+0xBC4" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SPI0" description="SPI0" start="0" size="32" />
+    </Register>
+    <Register name="MACSPI1R" description="PTP Source port identity 1 register" start="+0xBC8" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SPI1" description="SPI1" start="0" size="32" />
+    </Register>
+    <Register name="MACSPI2R" description="PTP Source port identity 2 register" start="+0xBCC" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SPI2" description="SPI2" start="0" size="16" />
+    </Register>
+    <Register name="MACLMIR" description="Log message interval register" start="+0xBD0" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LSI" description="LSI" start="0" size="8" />
+      <BitField name="DRSYNCR" description="DRSYNCR" start="8" size="3" />
+      <BitField name="LMPDRI" description="LMPDRI" start="24" size="8" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="FDCAN1" description="FDCAN1" start="0x4000A000">
+    <Register name="FDCAN_CREL" description="FDCAN Core Release Register" start="+0x0" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="REL" description="Core release" start="28" size="4" />
+      <BitField name="STEP" description="Step of Core release" start="24" size="4" />
+      <BitField name="SUBSTEP" description="Sub-step of Core release" start="20" size="4" />
+      <BitField name="YEAR" description="Timestamp Year" start="16" size="4" />
+      <BitField name="MON" description="Timestamp Month" start="8" size="8" />
+      <BitField name="DAY" description="Timestamp Day" start="0" size="8" />
+    </Register>
+    <Register name="FDCAN_ENDN" description="FDCAN Core Release Register" start="+0x4" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ETV" description="Endiannes Test Value" start="0" size="32" />
+    </Register>
+    <Register name="FDCAN_DBTP" description="FDCAN Data Bit Timing and Prescaler Register" start="+0xC" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DSJW" description="Synchronization Jump Width" start="0" size="4" />
+      <BitField name="DTSEG2" description="Data time segment after sample point" start="4" size="4" />
+      <BitField name="DTSEG1" description="Data time segment after sample point" start="8" size="5" />
+      <BitField name="DBRP" description="Data BIt Rate Prescaler" start="16" size="5" />
+      <BitField name="TDC" description="Transceiver Delay Compensation" start="23" size="1" />
+    </Register>
+    <Register name="FDCAN_TEST" description="FDCAN Test Register" start="+0x10" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LBCK" description="Loop Back mode" start="4" size="1" />
+      <BitField name="TX" description="Loop Back mode" start="5" size="2" />
+      <BitField name="RX" description="Control of Transmit Pin" start="7" size="1" />
+    </Register>
+    <Register name="FDCAN_RWD" description="FDCAN RAM Watchdog Register" start="+0x14" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="WDV" description="Watchdog value" start="8" size="8" />
+      <BitField name="WDC" description="Watchdog configuration" start="0" size="8" />
+    </Register>
+    <Register name="FDCAN_CCCR" description="FDCAN CC Control Register" start="+0x18" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="INIT" description="Initialization" start="0" size="1" />
+      <BitField name="CCE" description="Configuration Change Enable" start="1" size="1" />
+      <BitField name="ASM" description="ASM Restricted Operation Mode" start="2" size="1" />
+      <BitField name="CSA" description="Clock Stop Acknowledge" start="3" size="1" />
+      <BitField name="CSR" description="Clock Stop Request" start="4" size="1" />
+      <BitField name="MON" description="Bus Monitoring Mode" start="5" size="1" />
+      <BitField name="DAR" description="Disable Automatic Retransmission" start="6" size="1" />
+      <BitField name="TEST" description="Test Mode Enable" start="7" size="1" />
+      <BitField name="FDOE" description="FD Operation Enable" start="8" size="1" />
+      <BitField name="BSE" description="FDCAN Bit Rate Switching" start="9" size="1" />
+      <BitField name="PXHD" description="Protocol Exception Handling Disable" start="12" size="1" />
+      <BitField name="EFBI" description="Edge Filtering during Bus Integration" start="13" size="1" />
+      <BitField name="TXP" description="TXP" start="14" size="1" />
+      <BitField name="NISO" description="Non ISO Operation" start="15" size="1" />
+    </Register>
+    <Register name="FDCAN_NBTP" description="FDCAN Nominal Bit Timing and Prescaler Register" start="+0x1C" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="NSJW" description="NSJW: Nominal (Re)Synchronization Jump Width" start="25" size="7" />
+      <BitField name="NBRP" description="Bit Rate Prescaler" start="16" size="9" />
+      <BitField name="NTSEG1" description="Nominal Time segment before sample point" start="8" size="8" />
+      <BitField name="TSEG2" description="Nominal Time segment after sample point" start="0" size="7" />
+    </Register>
+    <Register name="FDCAN_TSCC" description="FDCAN Timestamp Counter Configuration Register" start="+0x20" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TCP" description="Timestamp Counter Prescaler" start="16" size="4" />
+      <BitField name="TSS" description="Timestamp Select" start="0" size="2" />
+    </Register>
+    <Register name="FDCAN_TSCV" description="FDCAN Timestamp Counter Value Register" start="+0x24" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TSC" description="Timestamp Counter" start="0" size="16" />
+    </Register>
+    <Register name="FDCAN_TOCC" description="FDCAN Timeout Counter Configuration Register" start="+0x28" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ETOC" description="Enable Timeout Counter" start="0" size="1" />
+      <BitField name="TOS" description="Timeout Select" start="1" size="2" />
+      <BitField name="TOP" description="Timeout Period" start="16" size="16" />
+    </Register>
+    <Register name="FDCAN_TOCV" description="FDCAN Timeout Counter Value Register" start="+0x2C" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TOC" description="Timeout Counter" start="0" size="16" />
+    </Register>
+    <Register name="FDCAN_ECR" description="FDCAN Error Counter Register" start="+0x40" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CEL" description="AN Error Logging" start="16" size="8" />
+      <BitField name="RP" description="Receive Error Passive" start="15" size="1" />
+      <BitField name="TREC" description="Receive Error Counter" start="8" size="7" />
+      <BitField name="TEC" description="Transmit Error Counter" start="0" size="8" />
+    </Register>
+    <Register name="FDCAN_PSR" description="FDCAN Protocol Status Register" start="+0x44" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LEC" description="Last Error Code" start="0" size="3" />
+      <BitField name="ACT" description="Activity" start="3" size="2" />
+      <BitField name="EP" description="Error Passive" start="5" size="1" />
+      <BitField name="EW" description="Warning Status" start="6" size="1" />
+      <BitField name="BO" description="Bus_Off Status" start="7" size="1" />
+      <BitField name="DLEC" description="Data Last Error Code" start="8" size="3" />
+      <BitField name="RESI" description="ESI flag of last received FDCAN Message" start="11" size="1" />
+      <BitField name="RBRS" description="BRS flag of last received FDCAN Message" start="12" size="1" />
+      <BitField name="REDL" description="Received FDCAN Message" start="13" size="1" />
+      <BitField name="PXE" description="Protocol Exception Event" start="14" size="1" />
+      <BitField name="TDCV" description="Transmitter Delay Compensation Value" start="16" size="7" />
+    </Register>
+    <Register name="FDCAN_TDCR" description="FDCAN Transmitter Delay Compensation Register" start="+0x48" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TDCF" description="Transmitter Delay Compensation Filter Window Length" start="0" size="7" />
+      <BitField name="TDCO" description="Transmitter Delay Compensation Offset" start="8" size="7" />
+    </Register>
+    <Register name="FDCAN_IR" description="FDCAN Interrupt Register" start="+0x50" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RF0N" description="Rx FIFO 0 New Message" start="0" size="1" />
+      <BitField name="RF0W" description="Rx FIFO 0 Full" start="1" size="1" />
+      <BitField name="RF0F" description="Rx FIFO 0 Full" start="2" size="1" />
+      <BitField name="RF0L" description="Rx FIFO 0 Message Lost" start="3" size="1" />
+      <BitField name="RF1N" description="Rx FIFO 1 New Message" start="4" size="1" />
+      <BitField name="RF1W" description="Rx FIFO 1 Watermark Reached" start="5" size="1" />
+      <BitField name="RF1F" description="Rx FIFO 1 Watermark Reached" start="6" size="1" />
+      <BitField name="RF1L" description="Rx FIFO 1 Message Lost" start="7" size="1" />
+      <BitField name="HPM" description="High Priority Message" start="8" size="1" />
+      <BitField name="TC" description="Transmission Completed" start="9" size="1" />
+      <BitField name="TCF" description="Transmission Cancellation Finished" start="10" size="1" />
+      <BitField name="TEF" description="Tx FIFO Empty" start="11" size="1" />
+      <BitField name="TEFN" description="Tx Event FIFO New Entry" start="12" size="1" />
+      <BitField name="TEFW" description="Tx Event FIFO Watermark Reached" start="13" size="1" />
+      <BitField name="TEFF" description="Tx Event FIFO Full" start="14" size="1" />
+      <BitField name="TEFL" description="Tx Event FIFO Element Lost" start="15" size="1" />
+      <BitField name="TSW" description="Timestamp Wraparound" start="16" size="1" />
+      <BitField name="MRAF" description="Message RAM Access Failure" start="17" size="1" />
+      <BitField name="TOO" description="Timeout Occurred" start="18" size="1" />
+      <BitField name="DRX" description="Message stored to Dedicated Rx Buffer" start="19" size="1" />
+      <BitField name="ELO" description="Error Logging Overflow" start="22" size="1" />
+      <BitField name="EP" description="Error Passive" start="23" size="1" />
+      <BitField name="EW" description="Warning Status" start="24" size="1" />
+      <BitField name="BO" description="Bus_Off Status" start="25" size="1" />
+      <BitField name="WDI" description="Watchdog Interrupt" start="26" size="1" />
+      <BitField name="PEA" description="Protocol Error in Arbitration Phase (Nominal Bit Time is used)" start="27" size="1" />
+      <BitField name="PED" description="Protocol Error in Data Phase (Data Bit Time is used)" start="28" size="1" />
+      <BitField name="ARA" description="Access to Reserved Address" start="29" size="1" />
+    </Register>
+    <Register name="FDCAN_IE" description="FDCAN Interrupt Enable Register" start="+0x54" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RF0NE" description="Rx FIFO 0 New Message Enable" start="0" size="1" />
+      <BitField name="RF0WE" description="Rx FIFO 0 Full Enable" start="1" size="1" />
+      <BitField name="RF0FE" description="Rx FIFO 0 Full Enable" start="2" size="1" />
+      <BitField name="RF0LE" description="Rx FIFO 0 Message Lost Enable" start="3" size="1" />
+      <BitField name="RF1NE" description="Rx FIFO 1 New Message Enable" start="4" size="1" />
+      <BitField name="RF1WE" description="Rx FIFO 1 Watermark Reached Enable" start="5" size="1" />
+      <BitField name="RF1FE" description="Rx FIFO 1 Watermark Reached Enable" start="6" size="1" />
+      <BitField name="RF1LE" description="Rx FIFO 1 Message Lost Enable" start="7" size="1" />
+      <BitField name="HPME" description="High Priority Message Enable" start="8" size="1" />
+      <BitField name="TCE" description="Transmission Completed Enable" start="9" size="1" />
+      <BitField name="TCFE" description="Transmission Cancellation Finished Enable" start="10" size="1" />
+      <BitField name="TEFE" description="Tx FIFO Empty Enable" start="11" size="1" />
+      <BitField name="TEFNE" description="Tx Event FIFO New Entry Enable" start="12" size="1" />
+      <BitField name="TEFWE" description="Tx Event FIFO Watermark Reached Enable" start="13" size="1" />
+      <BitField name="TEFFE" description="Tx Event FIFO Full Enable" start="14" size="1" />
+      <BitField name="TEFLE" description="Tx Event FIFO Element Lost Enable" start="15" size="1" />
+      <BitField name="TSWE" description="Timestamp Wraparound Enable" start="16" size="1" />
+      <BitField name="MRAFE" description="Message RAM Access Failure Enable" start="17" size="1" />
+      <BitField name="TOOE" description="Timeout Occurred Enable" start="18" size="1" />
+      <BitField name="DRXE" description="Message stored to Dedicated Rx Buffer Enable" start="19" size="1" />
+      <BitField name="BECE" description="Bit Error Corrected Interrupt Enable" start="20" size="1" />
+      <BitField name="BEUE" description="Bit Error Uncorrected Interrupt Enable" start="21" size="1" />
+      <BitField name="ELOE" description="Error Logging Overflow Enable" start="22" size="1" />
+      <BitField name="EPE" description="Error Passive Enable" start="23" size="1" />
+      <BitField name="EWE" description="Warning Status Enable" start="24" size="1" />
+      <BitField name="BOE" description="Bus_Off Status Enable" start="25" size="1" />
+      <BitField name="WDIE" description="Watchdog Interrupt Enable" start="26" size="1" />
+      <BitField name="PEAE" description="Protocol Error in Arbitration Phase Enable" start="27" size="1" />
+      <BitField name="PEDE" description="Protocol Error in Data Phase Enable" start="28" size="1" />
+      <BitField name="ARAE" description="Access to Reserved Address Enable" start="29" size="1" />
+    </Register>
+    <Register name="FDCAN_ILS" description="FDCAN Interrupt Line Select Register" start="+0x58" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RF0NL" description="Rx FIFO 0 New Message Interrupt Line" start="0" size="1" />
+      <BitField name="RF0WL" description="Rx FIFO 0 Watermark Reached Interrupt Line" start="1" size="1" />
+      <BitField name="RF0FL" description="Rx FIFO 0 Full Interrupt Line" start="2" size="1" />
+      <BitField name="RF0LL" description="Rx FIFO 0 Message Lost Interrupt Line" start="3" size="1" />
+      <BitField name="RF1NL" description="Rx FIFO 1 New Message Interrupt Line" start="4" size="1" />
+      <BitField name="RF1WL" description="Rx FIFO 1 Watermark Reached Interrupt Line" start="5" size="1" />
+      <BitField name="RF1FL" description="Rx FIFO 1 Full Interrupt Line" start="6" size="1" />
+      <BitField name="RF1LL" description="Rx FIFO 1 Message Lost Interrupt Line" start="7" size="1" />
+      <BitField name="HPML" description="High Priority Message Interrupt Line" start="8" size="1" />
+      <BitField name="TCL" description="Transmission Completed Interrupt Line" start="9" size="1" />
+      <BitField name="TCFL" description="Transmission Cancellation Finished Interrupt Line" start="10" size="1" />
+      <BitField name="TEFL" description="Tx FIFO Empty Interrupt Line" start="11" size="1" />
+      <BitField name="TEFNL" description="Tx Event FIFO New Entry Interrupt Line" start="12" size="1" />
+      <BitField name="TEFWL" description="Tx Event FIFO Watermark Reached Interrupt Line" start="13" size="1" />
+      <BitField name="TEFFL" description="Tx Event FIFO Full Interrupt Line" start="14" size="1" />
+      <BitField name="TEFLL" description="Tx Event FIFO Element Lost Interrupt Line" start="15" size="1" />
+      <BitField name="TSWL" description="Timestamp Wraparound Interrupt Line" start="16" size="1" />
+      <BitField name="MRAFL" description="Message RAM Access Failure Interrupt Line" start="17" size="1" />
+      <BitField name="TOOL" description="Timeout Occurred Interrupt Line" start="18" size="1" />
+      <BitField name="DRXL" description="Message stored to Dedicated Rx Buffer Interrupt Line" start="19" size="1" />
+      <BitField name="BECL" description="Bit Error Corrected Interrupt Line" start="20" size="1" />
+      <BitField name="BEUL" description="Bit Error Uncorrected Interrupt Line" start="21" size="1" />
+      <BitField name="ELOL" description="Error Logging Overflow Interrupt Line" start="22" size="1" />
+      <BitField name="EPL" description="Error Passive Interrupt Line" start="23" size="1" />
+      <BitField name="EWL" description="Warning Status Interrupt Line" start="24" size="1" />
+      <BitField name="BOL" description="Bus_Off Status" start="25" size="1" />
+      <BitField name="WDIL" description="Watchdog Interrupt Line" start="26" size="1" />
+      <BitField name="PEAL" description="Protocol Error in Arbitration Phase Line" start="27" size="1" />
+      <BitField name="PEDL" description="Protocol Error in Data Phase Line" start="28" size="1" />
+      <BitField name="ARAL" description="Access to Reserved Address Line" start="29" size="1" />
+    </Register>
+    <Register name="FDCAN_ILE" description="FDCAN Interrupt Line Enable Register" start="+0x5C" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EINT0" description="Enable Interrupt Line 0" start="0" size="1" />
+      <BitField name="EINT1" description="Enable Interrupt Line 1" start="1" size="1" />
+    </Register>
+    <Register name="FDCAN_GFC" description="FDCAN Global Filter Configuration Register" start="+0x80" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RRFE" description="Reject Remote Frames Extended" start="0" size="1" />
+      <BitField name="RRFS" description="Reject Remote Frames Standard" start="1" size="1" />
+      <BitField name="ANFE" description="Accept Non-matching Frames Extended" start="2" size="2" />
+      <BitField name="ANFS" description="Accept Non-matching Frames Standard" start="4" size="2" />
+    </Register>
+    <Register name="FDCAN_SIDFC" description="FDCAN Standard ID Filter Configuration Register" start="+0x84" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FLSSA" description="Filter List Standard Start Address" start="2" size="14" />
+      <BitField name="LSS" description="List Size Standard" start="16" size="8" />
+    </Register>
+    <Register name="FDCAN_XIDFC" description="FDCAN Extended ID Filter Configuration Register" start="+0x88" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FLESA" description="Filter List Standard Start Address" start="2" size="14" />
+      <BitField name="LSE" description="List Size Extended" start="16" size="8" />
+    </Register>
+    <Register name="FDCAN_XIDAM" description="FDCAN Extended ID and Mask Register" start="+0x90" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EIDM" description="Extended ID Mask" start="0" size="29" />
+    </Register>
+    <Register name="FDCAN_HPMS" description="FDCAN High Priority Message Status Register" start="+0x94" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BIDX" description="Buffer Index" start="0" size="6" />
+      <BitField name="MSI" description="Message Storage Indicator" start="6" size="2" />
+      <BitField name="FIDX" description="Filter Index" start="8" size="7" />
+      <BitField name="FLST" description="Filter List" start="15" size="1" />
+    </Register>
+    <Register name="FDCAN_NDAT1" description="FDCAN New Data 1 Register" start="+0x98" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ND0" description="New data" start="0" size="1" />
+      <BitField name="ND1" description="New data" start="1" size="1" />
+      <BitField name="ND2" description="New data" start="2" size="1" />
+      <BitField name="ND3" description="New data" start="3" size="1" />
+      <BitField name="ND4" description="New data" start="4" size="1" />
+      <BitField name="ND5" description="New data" start="5" size="1" />
+      <BitField name="ND6" description="New data" start="6" size="1" />
+      <BitField name="ND7" description="New data" start="7" size="1" />
+      <BitField name="ND8" description="New data" start="8" size="1" />
+      <BitField name="ND9" description="New data" start="9" size="1" />
+      <BitField name="ND10" description="New data" start="10" size="1" />
+      <BitField name="ND11" description="New data" start="11" size="1" />
+      <BitField name="ND12" description="New data" start="12" size="1" />
+      <BitField name="ND13" description="New data" start="13" size="1" />
+      <BitField name="ND14" description="New data" start="14" size="1" />
+      <BitField name="ND15" description="New data" start="15" size="1" />
+      <BitField name="ND16" description="New data" start="16" size="1" />
+      <BitField name="ND17" description="New data" start="17" size="1" />
+      <BitField name="ND18" description="New data" start="18" size="1" />
+      <BitField name="ND19" description="New data" start="19" size="1" />
+      <BitField name="ND20" description="New data" start="20" size="1" />
+      <BitField name="ND21" description="New data" start="21" size="1" />
+      <BitField name="ND22" description="New data" start="22" size="1" />
+      <BitField name="ND23" description="New data" start="23" size="1" />
+      <BitField name="ND24" description="New data" start="24" size="1" />
+      <BitField name="ND25" description="New data" start="25" size="1" />
+      <BitField name="ND26" description="New data" start="26" size="1" />
+      <BitField name="ND27" description="New data" start="27" size="1" />
+      <BitField name="ND28" description="New data" start="28" size="1" />
+      <BitField name="ND29" description="New data" start="29" size="1" />
+      <BitField name="ND30" description="New data" start="30" size="1" />
+      <BitField name="ND31" description="New data" start="31" size="1" />
+    </Register>
+    <Register name="FDCAN_NDAT2" description="FDCAN New Data 2 Register" start="+0x9C" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ND32" description="New data" start="0" size="1" />
+      <BitField name="ND33" description="New data" start="1" size="1" />
+      <BitField name="ND34" description="New data" start="2" size="1" />
+      <BitField name="ND35" description="New data" start="3" size="1" />
+      <BitField name="ND36" description="New data" start="4" size="1" />
+      <BitField name="ND37" description="New data" start="5" size="1" />
+      <BitField name="ND38" description="New data" start="6" size="1" />
+      <BitField name="ND39" description="New data" start="7" size="1" />
+      <BitField name="ND40" description="New data" start="8" size="1" />
+      <BitField name="ND41" description="New data" start="9" size="1" />
+      <BitField name="ND42" description="New data" start="10" size="1" />
+      <BitField name="ND43" description="New data" start="11" size="1" />
+      <BitField name="ND44" description="New data" start="12" size="1" />
+      <BitField name="ND45" description="New data" start="13" size="1" />
+      <BitField name="ND46" description="New data" start="14" size="1" />
+      <BitField name="ND47" description="New data" start="15" size="1" />
+      <BitField name="ND48" description="New data" start="16" size="1" />
+      <BitField name="ND49" description="New data" start="17" size="1" />
+      <BitField name="ND50" description="New data" start="18" size="1" />
+      <BitField name="ND51" description="New data" start="19" size="1" />
+      <BitField name="ND52" description="New data" start="20" size="1" />
+      <BitField name="ND53" description="New data" start="21" size="1" />
+      <BitField name="ND54" description="New data" start="22" size="1" />
+      <BitField name="ND55" description="New data" start="23" size="1" />
+      <BitField name="ND56" description="New data" start="24" size="1" />
+      <BitField name="ND57" description="New data" start="25" size="1" />
+      <BitField name="ND58" description="New data" start="26" size="1" />
+      <BitField name="ND59" description="New data" start="27" size="1" />
+      <BitField name="ND60" description="New data" start="28" size="1" />
+      <BitField name="ND61" description="New data" start="29" size="1" />
+      <BitField name="ND62" description="New data" start="30" size="1" />
+      <BitField name="ND63" description="New data" start="31" size="1" />
+    </Register>
+    <Register name="FDCAN_RXF0C" description="FDCAN Rx FIFO 0 Configuration Register" start="+0xA0" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="F0SA" description="Rx FIFO 0 Start Address" start="2" size="14" />
+      <BitField name="F0S" description="Rx FIFO 0 Size" start="16" size="8" />
+      <BitField name="F0WM" description="FIFO 0 Watermark" start="24" size="8" />
+    </Register>
+    <Register name="FDCAN_RXF0S" description="FDCAN Rx FIFO 0 Status Register" start="+0xA4" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="F0FL" description="Rx FIFO 0 Fill Level" start="0" size="7" />
+      <BitField name="F0G" description="Rx FIFO 0 Get Index" start="8" size="6" />
+      <BitField name="F0P" description="Rx FIFO 0 Put Index" start="16" size="6" />
+      <BitField name="F0F" description="Rx FIFO 0 Full" start="24" size="1" />
+      <BitField name="RF0L" description="Rx FIFO 0 Message Lost" start="25" size="1" />
+    </Register>
+    <Register name="FDCAN_RXF0A" description="CAN Rx FIFO 0 Acknowledge Register" start="+0xA8" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FA01" description="Rx FIFO 0 Acknowledge Index" start="0" size="6" />
+    </Register>
+    <Register name="FDCAN_RXBC" description="FDCAN Rx Buffer Configuration Register" start="+0xAC" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RBSA" description="Rx Buffer Start Address" start="2" size="14" />
+    </Register>
+    <Register name="FDCAN_RXF1C" description="FDCAN Rx FIFO 1 Configuration Register" start="+0xB0" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="F1SA" description="Rx FIFO 1 Start Address" start="2" size="14" />
+      <BitField name="F1S" description="Rx FIFO 1 Size" start="16" size="7" />
+      <BitField name="F1WM" description="Rx FIFO 1 Watermark" start="24" size="7" />
+    </Register>
+    <Register name="FDCAN_RXF1S" description="FDCAN Rx FIFO 1 Status Register" start="+0xB4" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="F1FL" description="Rx FIFO 1 Fill Level" start="0" size="7" />
+      <BitField name="F1GI" description="Rx FIFO 1 Get Index" start="8" size="7" />
+      <BitField name="F1PI" description="Rx FIFO 1 Put Index" start="16" size="7" />
+      <BitField name="F1F" description="Rx FIFO 1 Full" start="24" size="1" />
+      <BitField name="RF1L" description="Rx FIFO 1 Message Lost" start="25" size="1" />
+      <BitField name="DMS" description="Debug Message Status" start="30" size="2" />
+    </Register>
+    <Register name="FDCAN_RXF1A" description="FDCAN Rx FIFO 1 Acknowledge Register" start="+0xB8" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="F1AI" description="Rx FIFO 1 Acknowledge Index" start="0" size="6" />
+    </Register>
+    <Register name="FDCAN_RXESC" description="FDCAN Rx Buffer Element Size Configuration Register" start="+0xBC" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="F0DS" description="Rx FIFO 1 Data Field Size:" start="0" size="3" />
+      <BitField name="F1DS" description="Rx FIFO 0 Data Field Size:" start="4" size="3" />
+      <BitField name="RBDS" description="Rx Buffer Data Field Size:" start="8" size="3" />
+    </Register>
+    <Register name="FDCAN_TXBC" description="FDCAN Tx Buffer Configuration Register" start="+0xC0" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TBSA" description="Tx Buffers Start Address" start="2" size="14" />
+      <BitField name="NDTB" description="Number of Dedicated Transmit Buffers" start="16" size="6" />
+      <BitField name="TFQS" description="Transmit FIFO/Queue Size" start="24" size="6" />
+      <BitField name="TFQM" description="Tx FIFO/Queue Mode" start="30" size="1" />
+    </Register>
+    <Register name="FDCAN_TXFQS" description="FDCAN Tx FIFO/Queue Status Register" start="+0xC4" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TFFL" description="Tx FIFO Free Level" start="0" size="6" />
+      <BitField name="TFGI" description="TFGI" start="8" size="5" />
+      <BitField name="TFQPI" description="Tx FIFO/Queue Put Index" start="16" size="5" />
+      <BitField name="TFQF" description="Tx FIFO/Queue Full" start="21" size="1" />
+    </Register>
+    <Register name="FDCAN_TXESC" description="FDCAN Tx Buffer Element Size Configuration Register" start="+0xC8" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TBDS" description="Tx Buffer Data Field Size:" start="0" size="3" />
+    </Register>
+    <Register name="FDCAN_TXBRP" description="FDCAN Tx Buffer Request Pending Register" start="+0xCC" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TRP" description="Transmission Request Pending" start="0" size="32" />
+    </Register>
+    <Register name="FDCAN_TXBAR" description="FDCAN Tx Buffer Add Request Register" start="+0xD0" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AR" description="Add Request" start="0" size="32" />
+    </Register>
+    <Register name="FDCAN_TXBCR" description="FDCAN Tx Buffer Cancellation Request Register" start="+0xD4" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CR" description="Cancellation Request" start="0" size="32" />
+    </Register>
+    <Register name="FDCAN_TXBTO" description="FDCAN Tx Buffer Transmission Occurred Register" start="+0xD8" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TO" description="Transmission Occurred." start="0" size="32" />
+    </Register>
+    <Register name="FDCAN_TXBCF" description="FDCAN Tx Buffer Cancellation Finished Register" start="+0xDC" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CF" description="Cancellation Finished" start="0" size="32" />
+    </Register>
+    <Register name="FDCAN_TXBTIE" description="FDCAN Tx Buffer Transmission Interrupt Enable Register" start="+0xE0" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TIE" description="Transmission Interrupt Enable" start="0" size="32" />
+    </Register>
+    <Register name="FDCAN_TXBCIE" description="FDCAN Tx Buffer Cancellation Finished Interrupt Enable Register" start="+0xE4" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CF" description="Cancellation Finished Interrupt Enable" start="0" size="32" />
+    </Register>
+    <Register name="FDCAN_TXEFC" description="FDCAN Tx Event FIFO Configuration Register" start="+0xF0" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EFSA" description="Event FIFO Start Address" start="2" size="14" />
+      <BitField name="EFS" description="Event FIFO Size" start="16" size="6" />
+      <BitField name="EFWM" description="Event FIFO Watermark" start="24" size="6" />
+    </Register>
+    <Register name="FDCAN_TXEFS" description="FDCAN Tx Event FIFO Status Register" start="+0xF4" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EFFL" description="Event FIFO Fill Level" start="0" size="6" />
+      <BitField name="EFGI" description="Event FIFO Get Index." start="8" size="5" />
+      <BitField name="EFF" description="Event FIFO Full." start="24" size="1" />
+      <BitField name="TEFL" description="Tx Event FIFO Element Lost." start="25" size="1" />
+    </Register>
+    <Register name="FDCAN_TXEFA" description="FDCAN Tx Event FIFO Acknowledge Register" start="+0xF8" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EFAI" description="Event FIFO Acknowledge Index" start="0" size="5" />
+    </Register>
+    <Register name="FDCAN_TTTMC" description="FDCAN TT Trigger Memory Configuration Register" start="+0x100" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TMSA" description="Trigger Memory Start Address" start="2" size="14" />
+      <BitField name="TME" description="Trigger Memory Elements" start="16" size="7" />
+    </Register>
+    <Register name="FDCAN_TTRMC" description="FDCAN TT Reference Message Configuration Register" start="+0x104" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RID" description="Reference Identifier." start="0" size="29" />
+      <BitField name="XTD" description="Extended Identifier" start="30" size="1" />
+      <BitField name="RMPS" description="Reference Message Payload Select" start="31" size="1" />
+    </Register>
+    <Register name="FDCAN_TTOCF" description="FDCAN TT Operation Configuration Register" start="+0x108" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OM" description="Operation Mode" start="0" size="2" />
+      <BitField name="GEN" description="Gap Enable" start="3" size="1" />
+      <BitField name="TM" description="Time Master" start="4" size="1" />
+      <BitField name="LDSDL" description="LD of Synchronization Deviation Limit" start="5" size="3" />
+      <BitField name="IRTO" description="Initial Reference Trigger Offset" start="8" size="7" />
+      <BitField name="EECS" description="Enable External Clock Synchronization" start="15" size="1" />
+      <BitField name="AWL" description="Application Watchdog Limit" start="16" size="8" />
+      <BitField name="EGTF" description="Enable Global Time Filtering" start="24" size="1" />
+      <BitField name="ECC" description="Enable Clock Calibration" start="25" size="1" />
+      <BitField name="EVTP" description="Event Trigger Polarity" start="26" size="1" />
+    </Register>
+    <Register name="FDCAN_TTMLM" description="FDCAN TT Matrix Limits Register" start="+0x10C" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCM" description="Cycle Count Max" start="0" size="6" />
+      <BitField name="CSS" description="Cycle Start Synchronization" start="6" size="2" />
+      <BitField name="TXEW" description="Tx Enable Window" start="8" size="4" />
+      <BitField name="ENTT" description="Expected Number of Tx Triggers" start="16" size="12" />
+    </Register>
+    <Register name="FDCAN_TURCF" description="FDCAN TUR Configuration Register" start="+0x110" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="NCL" description="Numerator Configuration Low." start="0" size="16" />
+      <BitField name="DC" description="Denominator Configuration." start="16" size="14" />
+      <BitField name="ELT" description="Enable Local Time" start="31" size="1" />
+    </Register>
+    <Register name="FDCAN_TTOCN" description="FDCAN TT Operation Control Register" start="+0x114" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SGT" description="Set Global time" start="0" size="1" />
+      <BitField name="ECS" description="External Clock Synchronization" start="1" size="1" />
+      <BitField name="SWP" description="Stop Watch Polarity" start="2" size="1" />
+      <BitField name="SWS" description="Stop Watch Source." start="3" size="2" />
+      <BitField name="RTIE" description="Register Time Mark Interrupt Pulse Enable" start="5" size="1" />
+      <BitField name="TMC" description="Register Time Mark Compare" start="6" size="2" />
+      <BitField name="TTIE" description="Trigger Time Mark Interrupt Pulse Enable" start="8" size="1" />
+      <BitField name="GCS" description="Gap Control Select" start="9" size="1" />
+      <BitField name="FGP" description="Finish Gap." start="10" size="1" />
+      <BitField name="TMG" description="Time Mark Gap" start="11" size="1" />
+      <BitField name="NIG" description="Next is Gap" start="12" size="1" />
+      <BitField name="ESCN" description="External Synchronization Control" start="13" size="1" />
+      <BitField name="LCKC" description="TT Operation Control Register Locked" start="15" size="1" />
+    </Register>
+    <Register name="CAN_TTGTP" description="FDCAN TT Global Time Preset Register" start="+0x118" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="NCL" description="Time Preset" start="0" size="16" />
+      <BitField name="CTP" description="Cycle Time Target Phase" start="16" size="16" />
+    </Register>
+    <Register name="FDCAN_TTTMK" description="FDCAN TT Time Mark Register" start="+0x11C" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TM" description="Time Mark" start="0" size="16" />
+      <BitField name="TICC" description="Time Mark Cycle Code" start="16" size="7" />
+      <BitField name="LCKM" description="TT Time Mark Register Locked" start="31" size="1" />
+    </Register>
+    <Register name="FDCAN_TTIR" description="FDCAN TT Interrupt Register" start="+0x120" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SBC" description="Start of Basic Cycle" start="0" size="1" />
+      <BitField name="SMC" description="Start of Matrix Cycle" start="1" size="1" />
+      <BitField name="CSM" description="Change of Synchronization Mode" start="2" size="1" />
+      <BitField name="SOG" description="Start of Gap" start="3" size="1" />
+      <BitField name="RTMI" description="Register Time Mark Interrupt." start="4" size="1" />
+      <BitField name="TTMI" description="Trigger Time Mark Event Internal" start="5" size="1" />
+      <BitField name="SWE" description="Stop Watch Event" start="6" size="1" />
+      <BitField name="GTW" description="Global Time Wrap" start="7" size="1" />
+      <BitField name="GTD" description="Global Time Discontinuity" start="8" size="1" />
+      <BitField name="GTE" description="Global Time Error" start="9" size="1" />
+      <BitField name="TXU" description="Tx Count Underflow" start="10" size="1" />
+      <BitField name="TXO" description="Tx Count Overflow" start="11" size="1" />
+      <BitField name="SE1" description="Scheduling Error 1" start="12" size="1" />
+      <BitField name="SE2" description="Scheduling Error 2" start="13" size="1" />
+      <BitField name="ELC" description="Error Level Changed." start="14" size="1" />
+      <BitField name="IWTG" description="Initialization Watch Trigger" start="15" size="1" />
+      <BitField name="WT" description="Watch Trigger" start="16" size="1" />
+      <BitField name="AW" description="Application Watchdog" start="17" size="1" />
+      <BitField name="CER" description="Configuration Error" start="18" size="1" />
+    </Register>
+    <Register name="FDCAN_TTIE" description="FDCAN TT Interrupt Enable Register" start="+0x124" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SBCE" description="Start of Basic Cycle Interrupt Enable" start="0" size="1" />
+      <BitField name="SMCE" description="Start of Matrix Cycle Interrupt Enable" start="1" size="1" />
+      <BitField name="CSME" description="Change of Synchronization Mode Interrupt Enable" start="2" size="1" />
+      <BitField name="SOGE" description="Start of Gap Interrupt Enable" start="3" size="1" />
+      <BitField name="RTMIE" description="Register Time Mark Interrupt Enable" start="4" size="1" />
+      <BitField name="TTMIE" description="Trigger Time Mark Event Internal Interrupt Enable" start="5" size="1" />
+      <BitField name="SWEE" description="Stop Watch Event Interrupt Enable" start="6" size="1" />
+      <BitField name="GTWE" description="Global Time Wrap Interrupt Enable" start="7" size="1" />
+      <BitField name="GTDE" description="Global Time Discontinuity Interrupt Enable" start="8" size="1" />
+      <BitField name="GTEE" description="Global Time Error Interrupt Enable" start="9" size="1" />
+      <BitField name="TXUE" description="Tx Count Underflow Interrupt Enable" start="10" size="1" />
+      <BitField name="TXOE" description="Tx Count Overflow Interrupt Enable" start="11" size="1" />
+      <BitField name="SE1E" description="Scheduling Error 1 Interrupt Enable" start="12" size="1" />
+      <BitField name="SE2E" description="Scheduling Error 2 Interrupt Enable" start="13" size="1" />
+      <BitField name="ELCE" description="Change Error Level Interrupt Enable" start="14" size="1" />
+      <BitField name="IWTGE" description="Initialization Watch Trigger Interrupt Enable" start="15" size="1" />
+      <BitField name="WTE" description="Watch Trigger Interrupt Enable" start="16" size="1" />
+      <BitField name="AWE" description="Application Watchdog Interrupt Enable" start="17" size="1" />
+      <BitField name="CERE" description="Configuration Error Interrupt Enable" start="18" size="1" />
+    </Register>
+    <Register name="FDCAN_TTILS" description="FDCAN TT Interrupt Line Select Register" start="+0x128" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SBCL" description="Start of Basic Cycle Interrupt Line" start="0" size="1" />
+      <BitField name="SMCL" description="Start of Matrix Cycle Interrupt Line" start="1" size="1" />
+      <BitField name="CSML" description="Change of Synchronization Mode Interrupt Line" start="2" size="1" />
+      <BitField name="SOGL" description="Start of Gap Interrupt Line" start="3" size="1" />
+      <BitField name="RTMIL" description="Register Time Mark Interrupt Line" start="4" size="1" />
+      <BitField name="TTMIL" description="Trigger Time Mark Event Internal Interrupt Line" start="5" size="1" />
+      <BitField name="SWEL" description="Stop Watch Event Interrupt Line" start="6" size="1" />
+      <BitField name="GTWL" description="Global Time Wrap Interrupt Line" start="7" size="1" />
+      <BitField name="GTDL" description="Global Time Discontinuity Interrupt Line" start="8" size="1" />
+      <BitField name="GTEL" description="Global Time Error Interrupt Line" start="9" size="1" />
+      <BitField name="TXUL" description="Tx Count Underflow Interrupt Line" start="10" size="1" />
+      <BitField name="TXOL" description="Tx Count Overflow Interrupt Line" start="11" size="1" />
+      <BitField name="SE1L" description="Scheduling Error 1 Interrupt Line" start="12" size="1" />
+      <BitField name="SE2L" description="Scheduling Error 2 Interrupt Line" start="13" size="1" />
+      <BitField name="ELCL" description="Change Error Level Interrupt Line" start="14" size="1" />
+      <BitField name="IWTGL" description="Initialization Watch Trigger Interrupt Line" start="15" size="1" />
+      <BitField name="WTL" description="Watch Trigger Interrupt Line" start="16" size="1" />
+      <BitField name="AWL" description="Application Watchdog Interrupt Line" start="17" size="1" />
+      <BitField name="CERL" description="Configuration Error Interrupt Line" start="18" size="1" />
+    </Register>
+    <Register name="FDCAN_TTOST" description="FDCAN TT Operation Status Register" start="+0x12C" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EL" description="Error Level" start="0" size="2" />
+      <BitField name="MS" description="Master State." start="2" size="2" />
+      <BitField name="SYS" description="Synchronization State" start="4" size="2" />
+      <BitField name="GTP" description="Quality of Global Time Phase" start="6" size="1" />
+      <BitField name="QCS" description="Quality of Clock Speed" start="7" size="1" />
+      <BitField name="RTO" description="Reference Trigger Offset" start="8" size="8" />
+      <BitField name="WGTD" description="Wait for Global Time Discontinuity" start="22" size="1" />
+      <BitField name="GFI" description="Gap Finished Indicator." start="23" size="1" />
+      <BitField name="TMP" description="Time Master Priority" start="24" size="3" />
+      <BitField name="GSI" description="Gap Started Indicator." start="27" size="1" />
+      <BitField name="WFE" description="Wait for Event" start="28" size="1" />
+      <BitField name="AWE" description="Application Watchdog Event" start="29" size="1" />
+      <BitField name="WECS" description="Wait for External Clock Synchronization" start="30" size="1" />
+      <BitField name="SPL" description="Schedule Phase Lock" start="31" size="1" />
+    </Register>
+    <Register name="FDCAN_TURNA" description="FDCAN TUR Numerator Actual Register" start="+0x130" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="NAV" description="Numerator Actual Value" start="0" size="18" />
+    </Register>
+    <Register name="FDCAN_TTLGT" description="FDCAN TT Local and Global Time Register" start="+0x134" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LT" description="Local Time" start="0" size="16" />
+      <BitField name="GT" description="Global Time" start="16" size="16" />
+    </Register>
+    <Register name="FDCAN_TTCTC" description="FDCAN TT Cycle Time and Count Register" start="+0x138" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CT" description="Cycle Time" start="0" size="16" />
+      <BitField name="CC" description="Cycle Count" start="16" size="6" />
+    </Register>
+    <Register name="FDCAN_TTCPT" description="FDCAN TT Capture Time Register" start="+0x13C" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CT" description="Cycle Count Value" start="0" size="6" />
+      <BitField name="SWV" description="Stop Watch Value" start="16" size="16" />
+    </Register>
+    <Register name="FDCAN_TTCSM" description="FDCAN TT Cycle Sync Mark Register" start="+0x140" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CSM" description="Cycle Sync Mark" start="0" size="16" />
+    </Register>
+    <Register name="FDCAN_TTTS" description="FDCAN TT Trigger Select Register" start="+0x300" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWTDEL" description="Stop watch trigger input selection" start="0" size="2" />
+      <BitField name="EVTSEL" description="Event trigger input selection" start="4" size="2" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="FDCAN2" description="FDCAN1" start="0x4000A400">
+    <Register name="FDCAN_CREL" description="FDCAN Core Release Register" start="+0x0" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="REL" description="Core release" start="28" size="4" />
+      <BitField name="STEP" description="Step of Core release" start="24" size="4" />
+      <BitField name="SUBSTEP" description="Sub-step of Core release" start="20" size="4" />
+      <BitField name="YEAR" description="Timestamp Year" start="16" size="4" />
+      <BitField name="MON" description="Timestamp Month" start="8" size="8" />
+      <BitField name="DAY" description="Timestamp Day" start="0" size="8" />
+    </Register>
+    <Register name="FDCAN_ENDN" description="FDCAN Core Release Register" start="+0x4" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ETV" description="Endiannes Test Value" start="0" size="32" />
+    </Register>
+    <Register name="FDCAN_DBTP" description="FDCAN Data Bit Timing and Prescaler Register" start="+0xC" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DSJW" description="Synchronization Jump Width" start="0" size="4" />
+      <BitField name="DTSEG2" description="Data time segment after sample point" start="4" size="4" />
+      <BitField name="DTSEG1" description="Data time segment after sample point" start="8" size="5" />
+      <BitField name="DBRP" description="Data BIt Rate Prescaler" start="16" size="5" />
+      <BitField name="TDC" description="Transceiver Delay Compensation" start="23" size="1" />
+    </Register>
+    <Register name="FDCAN_TEST" description="FDCAN Test Register" start="+0x10" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LBCK" description="Loop Back mode" start="4" size="1" />
+      <BitField name="TX" description="Loop Back mode" start="5" size="2" />
+      <BitField name="RX" description="Control of Transmit Pin" start="7" size="1" />
+    </Register>
+    <Register name="FDCAN_RWD" description="FDCAN RAM Watchdog Register" start="+0x14" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="WDV" description="Watchdog value" start="8" size="8" />
+      <BitField name="WDC" description="Watchdog configuration" start="0" size="8" />
+    </Register>
+    <Register name="FDCAN_CCCR" description="FDCAN CC Control Register" start="+0x18" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="INIT" description="Initialization" start="0" size="1" />
+      <BitField name="CCE" description="Configuration Change Enable" start="1" size="1" />
+      <BitField name="ASM" description="ASM Restricted Operation Mode" start="2" size="1" />
+      <BitField name="CSA" description="Clock Stop Acknowledge" start="3" size="1" />
+      <BitField name="CSR" description="Clock Stop Request" start="4" size="1" />
+      <BitField name="MON" description="Bus Monitoring Mode" start="5" size="1" />
+      <BitField name="DAR" description="Disable Automatic Retransmission" start="6" size="1" />
+      <BitField name="TEST" description="Test Mode Enable" start="7" size="1" />
+      <BitField name="FDOE" description="FD Operation Enable" start="8" size="1" />
+      <BitField name="BSE" description="FDCAN Bit Rate Switching" start="9" size="1" />
+      <BitField name="PXHD" description="Protocol Exception Handling Disable" start="12" size="1" />
+      <BitField name="EFBI" description="Edge Filtering during Bus Integration" start="13" size="1" />
+      <BitField name="TXP" description="TXP" start="14" size="1" />
+      <BitField name="NISO" description="Non ISO Operation" start="15" size="1" />
+    </Register>
+    <Register name="FDCAN_NBTP" description="FDCAN Nominal Bit Timing and Prescaler Register" start="+0x1C" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="NSJW" description="NSJW: Nominal (Re)Synchronization Jump Width" start="25" size="7" />
+      <BitField name="NBRP" description="Bit Rate Prescaler" start="16" size="9" />
+      <BitField name="NTSEG1" description="Nominal Time segment before sample point" start="8" size="8" />
+      <BitField name="TSEG2" description="Nominal Time segment after sample point" start="0" size="7" />
+    </Register>
+    <Register name="FDCAN_TSCC" description="FDCAN Timestamp Counter Configuration Register" start="+0x20" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TCP" description="Timestamp Counter Prescaler" start="16" size="4" />
+      <BitField name="TSS" description="Timestamp Select" start="0" size="2" />
+    </Register>
+    <Register name="FDCAN_TSCV" description="FDCAN Timestamp Counter Value Register" start="+0x24" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TSC" description="Timestamp Counter" start="0" size="16" />
+    </Register>
+    <Register name="FDCAN_TOCC" description="FDCAN Timeout Counter Configuration Register" start="+0x28" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ETOC" description="Enable Timeout Counter" start="0" size="1" />
+      <BitField name="TOS" description="Timeout Select" start="1" size="2" />
+      <BitField name="TOP" description="Timeout Period" start="16" size="16" />
+    </Register>
+    <Register name="FDCAN_TOCV" description="FDCAN Timeout Counter Value Register" start="+0x2C" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TOC" description="Timeout Counter" start="0" size="16" />
+    </Register>
+    <Register name="FDCAN_ECR" description="FDCAN Error Counter Register" start="+0x40" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CEL" description="AN Error Logging" start="16" size="8" />
+      <BitField name="RP" description="Receive Error Passive" start="15" size="1" />
+      <BitField name="TREC" description="Receive Error Counter" start="8" size="7" />
+      <BitField name="TEC" description="Transmit Error Counter" start="0" size="8" />
+    </Register>
+    <Register name="FDCAN_PSR" description="FDCAN Protocol Status Register" start="+0x44" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LEC" description="Last Error Code" start="0" size="3" />
+      <BitField name="ACT" description="Activity" start="3" size="2" />
+      <BitField name="EP" description="Error Passive" start="5" size="1" />
+      <BitField name="EW" description="Warning Status" start="6" size="1" />
+      <BitField name="BO" description="Bus_Off Status" start="7" size="1" />
+      <BitField name="DLEC" description="Data Last Error Code" start="8" size="3" />
+      <BitField name="RESI" description="ESI flag of last received FDCAN Message" start="11" size="1" />
+      <BitField name="RBRS" description="BRS flag of last received FDCAN Message" start="12" size="1" />
+      <BitField name="REDL" description="Received FDCAN Message" start="13" size="1" />
+      <BitField name="PXE" description="Protocol Exception Event" start="14" size="1" />
+      <BitField name="TDCV" description="Transmitter Delay Compensation Value" start="16" size="7" />
+    </Register>
+    <Register name="FDCAN_TDCR" description="FDCAN Transmitter Delay Compensation Register" start="+0x48" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TDCF" description="Transmitter Delay Compensation Filter Window Length" start="0" size="7" />
+      <BitField name="TDCO" description="Transmitter Delay Compensation Offset" start="8" size="7" />
+    </Register>
+    <Register name="FDCAN_IR" description="FDCAN Interrupt Register" start="+0x50" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RF0N" description="Rx FIFO 0 New Message" start="0" size="1" />
+      <BitField name="RF0W" description="Rx FIFO 0 Full" start="1" size="1" />
+      <BitField name="RF0F" description="Rx FIFO 0 Full" start="2" size="1" />
+      <BitField name="RF0L" description="Rx FIFO 0 Message Lost" start="3" size="1" />
+      <BitField name="RF1N" description="Rx FIFO 1 New Message" start="4" size="1" />
+      <BitField name="RF1W" description="Rx FIFO 1 Watermark Reached" start="5" size="1" />
+      <BitField name="RF1F" description="Rx FIFO 1 Watermark Reached" start="6" size="1" />
+      <BitField name="RF1L" description="Rx FIFO 1 Message Lost" start="7" size="1" />
+      <BitField name="HPM" description="High Priority Message" start="8" size="1" />
+      <BitField name="TC" description="Transmission Completed" start="9" size="1" />
+      <BitField name="TCF" description="Transmission Cancellation Finished" start="10" size="1" />
+      <BitField name="TEF" description="Tx FIFO Empty" start="11" size="1" />
+      <BitField name="TEFN" description="Tx Event FIFO New Entry" start="12" size="1" />
+      <BitField name="TEFW" description="Tx Event FIFO Watermark Reached" start="13" size="1" />
+      <BitField name="TEFF" description="Tx Event FIFO Full" start="14" size="1" />
+      <BitField name="TEFL" description="Tx Event FIFO Element Lost" start="15" size="1" />
+      <BitField name="TSW" description="Timestamp Wraparound" start="16" size="1" />
+      <BitField name="MRAF" description="Message RAM Access Failure" start="17" size="1" />
+      <BitField name="TOO" description="Timeout Occurred" start="18" size="1" />
+      <BitField name="DRX" description="Message stored to Dedicated Rx Buffer" start="19" size="1" />
+      <BitField name="ELO" description="Error Logging Overflow" start="22" size="1" />
+      <BitField name="EP" description="Error Passive" start="23" size="1" />
+      <BitField name="EW" description="Warning Status" start="24" size="1" />
+      <BitField name="BO" description="Bus_Off Status" start="25" size="1" />
+      <BitField name="WDI" description="Watchdog Interrupt" start="26" size="1" />
+      <BitField name="PEA" description="Protocol Error in Arbitration Phase (Nominal Bit Time is used)" start="27" size="1" />
+      <BitField name="PED" description="Protocol Error in Data Phase (Data Bit Time is used)" start="28" size="1" />
+      <BitField name="ARA" description="Access to Reserved Address" start="29" size="1" />
+    </Register>
+    <Register name="FDCAN_IE" description="FDCAN Interrupt Enable Register" start="+0x54" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RF0NE" description="Rx FIFO 0 New Message Enable" start="0" size="1" />
+      <BitField name="RF0WE" description="Rx FIFO 0 Full Enable" start="1" size="1" />
+      <BitField name="RF0FE" description="Rx FIFO 0 Full Enable" start="2" size="1" />
+      <BitField name="RF0LE" description="Rx FIFO 0 Message Lost Enable" start="3" size="1" />
+      <BitField name="RF1NE" description="Rx FIFO 1 New Message Enable" start="4" size="1" />
+      <BitField name="RF1WE" description="Rx FIFO 1 Watermark Reached Enable" start="5" size="1" />
+      <BitField name="RF1FE" description="Rx FIFO 1 Watermark Reached Enable" start="6" size="1" />
+      <BitField name="RF1LE" description="Rx FIFO 1 Message Lost Enable" start="7" size="1" />
+      <BitField name="HPME" description="High Priority Message Enable" start="8" size="1" />
+      <BitField name="TCE" description="Transmission Completed Enable" start="9" size="1" />
+      <BitField name="TCFE" description="Transmission Cancellation Finished Enable" start="10" size="1" />
+      <BitField name="TEFE" description="Tx FIFO Empty Enable" start="11" size="1" />
+      <BitField name="TEFNE" description="Tx Event FIFO New Entry Enable" start="12" size="1" />
+      <BitField name="TEFWE" description="Tx Event FIFO Watermark Reached Enable" start="13" size="1" />
+      <BitField name="TEFFE" description="Tx Event FIFO Full Enable" start="14" size="1" />
+      <BitField name="TEFLE" description="Tx Event FIFO Element Lost Enable" start="15" size="1" />
+      <BitField name="TSWE" description="Timestamp Wraparound Enable" start="16" size="1" />
+      <BitField name="MRAFE" description="Message RAM Access Failure Enable" start="17" size="1" />
+      <BitField name="TOOE" description="Timeout Occurred Enable" start="18" size="1" />
+      <BitField name="DRXE" description="Message stored to Dedicated Rx Buffer Enable" start="19" size="1" />
+      <BitField name="BECE" description="Bit Error Corrected Interrupt Enable" start="20" size="1" />
+      <BitField name="BEUE" description="Bit Error Uncorrected Interrupt Enable" start="21" size="1" />
+      <BitField name="ELOE" description="Error Logging Overflow Enable" start="22" size="1" />
+      <BitField name="EPE" description="Error Passive Enable" start="23" size="1" />
+      <BitField name="EWE" description="Warning Status Enable" start="24" size="1" />
+      <BitField name="BOE" description="Bus_Off Status Enable" start="25" size="1" />
+      <BitField name="WDIE" description="Watchdog Interrupt Enable" start="26" size="1" />
+      <BitField name="PEAE" description="Protocol Error in Arbitration Phase Enable" start="27" size="1" />
+      <BitField name="PEDE" description="Protocol Error in Data Phase Enable" start="28" size="1" />
+      <BitField name="ARAE" description="Access to Reserved Address Enable" start="29" size="1" />
+    </Register>
+    <Register name="FDCAN_ILS" description="FDCAN Interrupt Line Select Register" start="+0x58" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RF0NL" description="Rx FIFO 0 New Message Interrupt Line" start="0" size="1" />
+      <BitField name="RF0WL" description="Rx FIFO 0 Watermark Reached Interrupt Line" start="1" size="1" />
+      <BitField name="RF0FL" description="Rx FIFO 0 Full Interrupt Line" start="2" size="1" />
+      <BitField name="RF0LL" description="Rx FIFO 0 Message Lost Interrupt Line" start="3" size="1" />
+      <BitField name="RF1NL" description="Rx FIFO 1 New Message Interrupt Line" start="4" size="1" />
+      <BitField name="RF1WL" description="Rx FIFO 1 Watermark Reached Interrupt Line" start="5" size="1" />
+      <BitField name="RF1FL" description="Rx FIFO 1 Full Interrupt Line" start="6" size="1" />
+      <BitField name="RF1LL" description="Rx FIFO 1 Message Lost Interrupt Line" start="7" size="1" />
+      <BitField name="HPML" description="High Priority Message Interrupt Line" start="8" size="1" />
+      <BitField name="TCL" description="Transmission Completed Interrupt Line" start="9" size="1" />
+      <BitField name="TCFL" description="Transmission Cancellation Finished Interrupt Line" start="10" size="1" />
+      <BitField name="TEFL" description="Tx FIFO Empty Interrupt Line" start="11" size="1" />
+      <BitField name="TEFNL" description="Tx Event FIFO New Entry Interrupt Line" start="12" size="1" />
+      <BitField name="TEFWL" description="Tx Event FIFO Watermark Reached Interrupt Line" start="13" size="1" />
+      <BitField name="TEFFL" description="Tx Event FIFO Full Interrupt Line" start="14" size="1" />
+      <BitField name="TEFLL" description="Tx Event FIFO Element Lost Interrupt Line" start="15" size="1" />
+      <BitField name="TSWL" description="Timestamp Wraparound Interrupt Line" start="16" size="1" />
+      <BitField name="MRAFL" description="Message RAM Access Failure Interrupt Line" start="17" size="1" />
+      <BitField name="TOOL" description="Timeout Occurred Interrupt Line" start="18" size="1" />
+      <BitField name="DRXL" description="Message stored to Dedicated Rx Buffer Interrupt Line" start="19" size="1" />
+      <BitField name="BECL" description="Bit Error Corrected Interrupt Line" start="20" size="1" />
+      <BitField name="BEUL" description="Bit Error Uncorrected Interrupt Line" start="21" size="1" />
+      <BitField name="ELOL" description="Error Logging Overflow Interrupt Line" start="22" size="1" />
+      <BitField name="EPL" description="Error Passive Interrupt Line" start="23" size="1" />
+      <BitField name="EWL" description="Warning Status Interrupt Line" start="24" size="1" />
+      <BitField name="BOL" description="Bus_Off Status" start="25" size="1" />
+      <BitField name="WDIL" description="Watchdog Interrupt Line" start="26" size="1" />
+      <BitField name="PEAL" description="Protocol Error in Arbitration Phase Line" start="27" size="1" />
+      <BitField name="PEDL" description="Protocol Error in Data Phase Line" start="28" size="1" />
+      <BitField name="ARAL" description="Access to Reserved Address Line" start="29" size="1" />
+    </Register>
+    <Register name="FDCAN_ILE" description="FDCAN Interrupt Line Enable Register" start="+0x5C" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EINT0" description="Enable Interrupt Line 0" start="0" size="1" />
+      <BitField name="EINT1" description="Enable Interrupt Line 1" start="1" size="1" />
+    </Register>
+    <Register name="FDCAN_GFC" description="FDCAN Global Filter Configuration Register" start="+0x80" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RRFE" description="Reject Remote Frames Extended" start="0" size="1" />
+      <BitField name="RRFS" description="Reject Remote Frames Standard" start="1" size="1" />
+      <BitField name="ANFE" description="Accept Non-matching Frames Extended" start="2" size="2" />
+      <BitField name="ANFS" description="Accept Non-matching Frames Standard" start="4" size="2" />
+    </Register>
+    <Register name="FDCAN_SIDFC" description="FDCAN Standard ID Filter Configuration Register" start="+0x84" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FLSSA" description="Filter List Standard Start Address" start="2" size="14" />
+      <BitField name="LSS" description="List Size Standard" start="16" size="8" />
+    </Register>
+    <Register name="FDCAN_XIDFC" description="FDCAN Extended ID Filter Configuration Register" start="+0x88" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FLESA" description="Filter List Standard Start Address" start="2" size="14" />
+      <BitField name="LSE" description="List Size Extended" start="16" size="8" />
+    </Register>
+    <Register name="FDCAN_XIDAM" description="FDCAN Extended ID and Mask Register" start="+0x90" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EIDM" description="Extended ID Mask" start="0" size="29" />
+    </Register>
+    <Register name="FDCAN_HPMS" description="FDCAN High Priority Message Status Register" start="+0x94" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BIDX" description="Buffer Index" start="0" size="6" />
+      <BitField name="MSI" description="Message Storage Indicator" start="6" size="2" />
+      <BitField name="FIDX" description="Filter Index" start="8" size="7" />
+      <BitField name="FLST" description="Filter List" start="15" size="1" />
+    </Register>
+    <Register name="FDCAN_NDAT1" description="FDCAN New Data 1 Register" start="+0x98" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ND0" description="New data" start="0" size="1" />
+      <BitField name="ND1" description="New data" start="1" size="1" />
+      <BitField name="ND2" description="New data" start="2" size="1" />
+      <BitField name="ND3" description="New data" start="3" size="1" />
+      <BitField name="ND4" description="New data" start="4" size="1" />
+      <BitField name="ND5" description="New data" start="5" size="1" />
+      <BitField name="ND6" description="New data" start="6" size="1" />
+      <BitField name="ND7" description="New data" start="7" size="1" />
+      <BitField name="ND8" description="New data" start="8" size="1" />
+      <BitField name="ND9" description="New data" start="9" size="1" />
+      <BitField name="ND10" description="New data" start="10" size="1" />
+      <BitField name="ND11" description="New data" start="11" size="1" />
+      <BitField name="ND12" description="New data" start="12" size="1" />
+      <BitField name="ND13" description="New data" start="13" size="1" />
+      <BitField name="ND14" description="New data" start="14" size="1" />
+      <BitField name="ND15" description="New data" start="15" size="1" />
+      <BitField name="ND16" description="New data" start="16" size="1" />
+      <BitField name="ND17" description="New data" start="17" size="1" />
+      <BitField name="ND18" description="New data" start="18" size="1" />
+      <BitField name="ND19" description="New data" start="19" size="1" />
+      <BitField name="ND20" description="New data" start="20" size="1" />
+      <BitField name="ND21" description="New data" start="21" size="1" />
+      <BitField name="ND22" description="New data" start="22" size="1" />
+      <BitField name="ND23" description="New data" start="23" size="1" />
+      <BitField name="ND24" description="New data" start="24" size="1" />
+      <BitField name="ND25" description="New data" start="25" size="1" />
+      <BitField name="ND26" description="New data" start="26" size="1" />
+      <BitField name="ND27" description="New data" start="27" size="1" />
+      <BitField name="ND28" description="New data" start="28" size="1" />
+      <BitField name="ND29" description="New data" start="29" size="1" />
+      <BitField name="ND30" description="New data" start="30" size="1" />
+      <BitField name="ND31" description="New data" start="31" size="1" />
+    </Register>
+    <Register name="FDCAN_NDAT2" description="FDCAN New Data 2 Register" start="+0x9C" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ND32" description="New data" start="0" size="1" />
+      <BitField name="ND33" description="New data" start="1" size="1" />
+      <BitField name="ND34" description="New data" start="2" size="1" />
+      <BitField name="ND35" description="New data" start="3" size="1" />
+      <BitField name="ND36" description="New data" start="4" size="1" />
+      <BitField name="ND37" description="New data" start="5" size="1" />
+      <BitField name="ND38" description="New data" start="6" size="1" />
+      <BitField name="ND39" description="New data" start="7" size="1" />
+      <BitField name="ND40" description="New data" start="8" size="1" />
+      <BitField name="ND41" description="New data" start="9" size="1" />
+      <BitField name="ND42" description="New data" start="10" size="1" />
+      <BitField name="ND43" description="New data" start="11" size="1" />
+      <BitField name="ND44" description="New data" start="12" size="1" />
+      <BitField name="ND45" description="New data" start="13" size="1" />
+      <BitField name="ND46" description="New data" start="14" size="1" />
+      <BitField name="ND47" description="New data" start="15" size="1" />
+      <BitField name="ND48" description="New data" start="16" size="1" />
+      <BitField name="ND49" description="New data" start="17" size="1" />
+      <BitField name="ND50" description="New data" start="18" size="1" />
+      <BitField name="ND51" description="New data" start="19" size="1" />
+      <BitField name="ND52" description="New data" start="20" size="1" />
+      <BitField name="ND53" description="New data" start="21" size="1" />
+      <BitField name="ND54" description="New data" start="22" size="1" />
+      <BitField name="ND55" description="New data" start="23" size="1" />
+      <BitField name="ND56" description="New data" start="24" size="1" />
+      <BitField name="ND57" description="New data" start="25" size="1" />
+      <BitField name="ND58" description="New data" start="26" size="1" />
+      <BitField name="ND59" description="New data" start="27" size="1" />
+      <BitField name="ND60" description="New data" start="28" size="1" />
+      <BitField name="ND61" description="New data" start="29" size="1" />
+      <BitField name="ND62" description="New data" start="30" size="1" />
+      <BitField name="ND63" description="New data" start="31" size="1" />
+    </Register>
+    <Register name="FDCAN_RXF0C" description="FDCAN Rx FIFO 0 Configuration Register" start="+0xA0" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="F0SA" description="Rx FIFO 0 Start Address" start="2" size="14" />
+      <BitField name="F0S" description="Rx FIFO 0 Size" start="16" size="8" />
+      <BitField name="F0WM" description="FIFO 0 Watermark" start="24" size="8" />
+    </Register>
+    <Register name="FDCAN_RXF0S" description="FDCAN Rx FIFO 0 Status Register" start="+0xA4" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="F0FL" description="Rx FIFO 0 Fill Level" start="0" size="7" />
+      <BitField name="F0G" description="Rx FIFO 0 Get Index" start="8" size="6" />
+      <BitField name="F0P" description="Rx FIFO 0 Put Index" start="16" size="6" />
+      <BitField name="F0F" description="Rx FIFO 0 Full" start="24" size="1" />
+      <BitField name="RF0L" description="Rx FIFO 0 Message Lost" start="25" size="1" />
+    </Register>
+    <Register name="FDCAN_RXF0A" description="CAN Rx FIFO 0 Acknowledge Register" start="+0xA8" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FA01" description="Rx FIFO 0 Acknowledge Index" start="0" size="6" />
+    </Register>
+    <Register name="FDCAN_RXBC" description="FDCAN Rx Buffer Configuration Register" start="+0xAC" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RBSA" description="Rx Buffer Start Address" start="2" size="14" />
+    </Register>
+    <Register name="FDCAN_RXF1C" description="FDCAN Rx FIFO 1 Configuration Register" start="+0xB0" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="F1SA" description="Rx FIFO 1 Start Address" start="2" size="14" />
+      <BitField name="F1S" description="Rx FIFO 1 Size" start="16" size="7" />
+      <BitField name="F1WM" description="Rx FIFO 1 Watermark" start="24" size="7" />
+    </Register>
+    <Register name="FDCAN_RXF1S" description="FDCAN Rx FIFO 1 Status Register" start="+0xB4" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="F1FL" description="Rx FIFO 1 Fill Level" start="0" size="7" />
+      <BitField name="F1GI" description="Rx FIFO 1 Get Index" start="8" size="7" />
+      <BitField name="F1PI" description="Rx FIFO 1 Put Index" start="16" size="7" />
+      <BitField name="F1F" description="Rx FIFO 1 Full" start="24" size="1" />
+      <BitField name="RF1L" description="Rx FIFO 1 Message Lost" start="25" size="1" />
+      <BitField name="DMS" description="Debug Message Status" start="30" size="2" />
+    </Register>
+    <Register name="FDCAN_RXF1A" description="FDCAN Rx FIFO 1 Acknowledge Register" start="+0xB8" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="F1AI" description="Rx FIFO 1 Acknowledge Index" start="0" size="6" />
+    </Register>
+    <Register name="FDCAN_RXESC" description="FDCAN Rx Buffer Element Size Configuration Register" start="+0xBC" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="F0DS" description="Rx FIFO 1 Data Field Size:" start="0" size="3" />
+      <BitField name="F1DS" description="Rx FIFO 0 Data Field Size:" start="4" size="3" />
+      <BitField name="RBDS" description="Rx Buffer Data Field Size:" start="8" size="3" />
+    </Register>
+    <Register name="FDCAN_TXBC" description="FDCAN Tx Buffer Configuration Register" start="+0xC0" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TBSA" description="Tx Buffers Start Address" start="2" size="14" />
+      <BitField name="NDTB" description="Number of Dedicated Transmit Buffers" start="16" size="6" />
+      <BitField name="TFQS" description="Transmit FIFO/Queue Size" start="24" size="6" />
+      <BitField name="TFQM" description="Tx FIFO/Queue Mode" start="30" size="1" />
+    </Register>
+    <Register name="FDCAN_TXFQS" description="FDCAN Tx FIFO/Queue Status Register" start="+0xC4" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TFFL" description="Tx FIFO Free Level" start="0" size="6" />
+      <BitField name="TFGI" description="TFGI" start="8" size="5" />
+      <BitField name="TFQPI" description="Tx FIFO/Queue Put Index" start="16" size="5" />
+      <BitField name="TFQF" description="Tx FIFO/Queue Full" start="21" size="1" />
+    </Register>
+    <Register name="FDCAN_TXESC" description="FDCAN Tx Buffer Element Size Configuration Register" start="+0xC8" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TBDS" description="Tx Buffer Data Field Size:" start="0" size="3" />
+    </Register>
+    <Register name="FDCAN_TXBRP" description="FDCAN Tx Buffer Request Pending Register" start="+0xCC" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TRP" description="Transmission Request Pending" start="0" size="32" />
+    </Register>
+    <Register name="FDCAN_TXBAR" description="FDCAN Tx Buffer Add Request Register" start="+0xD0" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AR" description="Add Request" start="0" size="32" />
+    </Register>
+    <Register name="FDCAN_TXBCR" description="FDCAN Tx Buffer Cancellation Request Register" start="+0xD4" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CR" description="Cancellation Request" start="0" size="32" />
+    </Register>
+    <Register name="FDCAN_TXBTO" description="FDCAN Tx Buffer Transmission Occurred Register" start="+0xD8" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TO" description="Transmission Occurred." start="0" size="32" />
+    </Register>
+    <Register name="FDCAN_TXBCF" description="FDCAN Tx Buffer Cancellation Finished Register" start="+0xDC" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CF" description="Cancellation Finished" start="0" size="32" />
+    </Register>
+    <Register name="FDCAN_TXBTIE" description="FDCAN Tx Buffer Transmission Interrupt Enable Register" start="+0xE0" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TIE" description="Transmission Interrupt Enable" start="0" size="32" />
+    </Register>
+    <Register name="FDCAN_TXBCIE" description="FDCAN Tx Buffer Cancellation Finished Interrupt Enable Register" start="+0xE4" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CF" description="Cancellation Finished Interrupt Enable" start="0" size="32" />
+    </Register>
+    <Register name="FDCAN_TXEFC" description="FDCAN Tx Event FIFO Configuration Register" start="+0xF0" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EFSA" description="Event FIFO Start Address" start="2" size="14" />
+      <BitField name="EFS" description="Event FIFO Size" start="16" size="6" />
+      <BitField name="EFWM" description="Event FIFO Watermark" start="24" size="6" />
+    </Register>
+    <Register name="FDCAN_TXEFS" description="FDCAN Tx Event FIFO Status Register" start="+0xF4" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EFFL" description="Event FIFO Fill Level" start="0" size="6" />
+      <BitField name="EFGI" description="Event FIFO Get Index." start="8" size="5" />
+      <BitField name="EFF" description="Event FIFO Full." start="24" size="1" />
+      <BitField name="TEFL" description="Tx Event FIFO Element Lost." start="25" size="1" />
+    </Register>
+    <Register name="FDCAN_TXEFA" description="FDCAN Tx Event FIFO Acknowledge Register" start="+0xF8" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EFAI" description="Event FIFO Acknowledge Index" start="0" size="5" />
+    </Register>
+    <Register name="FDCAN_TTTMC" description="FDCAN TT Trigger Memory Configuration Register" start="+0x100" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TMSA" description="Trigger Memory Start Address" start="2" size="14" />
+      <BitField name="TME" description="Trigger Memory Elements" start="16" size="7" />
+    </Register>
+    <Register name="FDCAN_TTRMC" description="FDCAN TT Reference Message Configuration Register" start="+0x104" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RID" description="Reference Identifier." start="0" size="29" />
+      <BitField name="XTD" description="Extended Identifier" start="30" size="1" />
+      <BitField name="RMPS" description="Reference Message Payload Select" start="31" size="1" />
+    </Register>
+    <Register name="FDCAN_TTOCF" description="FDCAN TT Operation Configuration Register" start="+0x108" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OM" description="Operation Mode" start="0" size="2" />
+      <BitField name="GEN" description="Gap Enable" start="3" size="1" />
+      <BitField name="TM" description="Time Master" start="4" size="1" />
+      <BitField name="LDSDL" description="LD of Synchronization Deviation Limit" start="5" size="3" />
+      <BitField name="IRTO" description="Initial Reference Trigger Offset" start="8" size="7" />
+      <BitField name="EECS" description="Enable External Clock Synchronization" start="15" size="1" />
+      <BitField name="AWL" description="Application Watchdog Limit" start="16" size="8" />
+      <BitField name="EGTF" description="Enable Global Time Filtering" start="24" size="1" />
+      <BitField name="ECC" description="Enable Clock Calibration" start="25" size="1" />
+      <BitField name="EVTP" description="Event Trigger Polarity" start="26" size="1" />
+    </Register>
+    <Register name="FDCAN_TTMLM" description="FDCAN TT Matrix Limits Register" start="+0x10C" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCM" description="Cycle Count Max" start="0" size="6" />
+      <BitField name="CSS" description="Cycle Start Synchronization" start="6" size="2" />
+      <BitField name="TXEW" description="Tx Enable Window" start="8" size="4" />
+      <BitField name="ENTT" description="Expected Number of Tx Triggers" start="16" size="12" />
+    </Register>
+    <Register name="FDCAN_TURCF" description="FDCAN TUR Configuration Register" start="+0x110" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="NCL" description="Numerator Configuration Low." start="0" size="16" />
+      <BitField name="DC" description="Denominator Configuration." start="16" size="14" />
+      <BitField name="ELT" description="Enable Local Time" start="31" size="1" />
+    </Register>
+    <Register name="FDCAN_TTOCN" description="FDCAN TT Operation Control Register" start="+0x114" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SGT" description="Set Global time" start="0" size="1" />
+      <BitField name="ECS" description="External Clock Synchronization" start="1" size="1" />
+      <BitField name="SWP" description="Stop Watch Polarity" start="2" size="1" />
+      <BitField name="SWS" description="Stop Watch Source." start="3" size="2" />
+      <BitField name="RTIE" description="Register Time Mark Interrupt Pulse Enable" start="5" size="1" />
+      <BitField name="TMC" description="Register Time Mark Compare" start="6" size="2" />
+      <BitField name="TTIE" description="Trigger Time Mark Interrupt Pulse Enable" start="8" size="1" />
+      <BitField name="GCS" description="Gap Control Select" start="9" size="1" />
+      <BitField name="FGP" description="Finish Gap." start="10" size="1" />
+      <BitField name="TMG" description="Time Mark Gap" start="11" size="1" />
+      <BitField name="NIG" description="Next is Gap" start="12" size="1" />
+      <BitField name="ESCN" description="External Synchronization Control" start="13" size="1" />
+      <BitField name="LCKC" description="TT Operation Control Register Locked" start="15" size="1" />
+    </Register>
+    <Register name="CAN_TTGTP" description="FDCAN TT Global Time Preset Register" start="+0x118" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="NCL" description="Time Preset" start="0" size="16" />
+      <BitField name="CTP" description="Cycle Time Target Phase" start="16" size="16" />
+    </Register>
+    <Register name="FDCAN_TTTMK" description="FDCAN TT Time Mark Register" start="+0x11C" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TM" description="Time Mark" start="0" size="16" />
+      <BitField name="TICC" description="Time Mark Cycle Code" start="16" size="7" />
+      <BitField name="LCKM" description="TT Time Mark Register Locked" start="31" size="1" />
+    </Register>
+    <Register name="FDCAN_TTIR" description="FDCAN TT Interrupt Register" start="+0x120" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SBC" description="Start of Basic Cycle" start="0" size="1" />
+      <BitField name="SMC" description="Start of Matrix Cycle" start="1" size="1" />
+      <BitField name="CSM" description="Change of Synchronization Mode" start="2" size="1" />
+      <BitField name="SOG" description="Start of Gap" start="3" size="1" />
+      <BitField name="RTMI" description="Register Time Mark Interrupt." start="4" size="1" />
+      <BitField name="TTMI" description="Trigger Time Mark Event Internal" start="5" size="1" />
+      <BitField name="SWE" description="Stop Watch Event" start="6" size="1" />
+      <BitField name="GTW" description="Global Time Wrap" start="7" size="1" />
+      <BitField name="GTD" description="Global Time Discontinuity" start="8" size="1" />
+      <BitField name="GTE" description="Global Time Error" start="9" size="1" />
+      <BitField name="TXU" description="Tx Count Underflow" start="10" size="1" />
+      <BitField name="TXO" description="Tx Count Overflow" start="11" size="1" />
+      <BitField name="SE1" description="Scheduling Error 1" start="12" size="1" />
+      <BitField name="SE2" description="Scheduling Error 2" start="13" size="1" />
+      <BitField name="ELC" description="Error Level Changed." start="14" size="1" />
+      <BitField name="IWTG" description="Initialization Watch Trigger" start="15" size="1" />
+      <BitField name="WT" description="Watch Trigger" start="16" size="1" />
+      <BitField name="AW" description="Application Watchdog" start="17" size="1" />
+      <BitField name="CER" description="Configuration Error" start="18" size="1" />
+    </Register>
+    <Register name="FDCAN_TTIE" description="FDCAN TT Interrupt Enable Register" start="+0x124" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SBCE" description="Start of Basic Cycle Interrupt Enable" start="0" size="1" />
+      <BitField name="SMCE" description="Start of Matrix Cycle Interrupt Enable" start="1" size="1" />
+      <BitField name="CSME" description="Change of Synchronization Mode Interrupt Enable" start="2" size="1" />
+      <BitField name="SOGE" description="Start of Gap Interrupt Enable" start="3" size="1" />
+      <BitField name="RTMIE" description="Register Time Mark Interrupt Enable" start="4" size="1" />
+      <BitField name="TTMIE" description="Trigger Time Mark Event Internal Interrupt Enable" start="5" size="1" />
+      <BitField name="SWEE" description="Stop Watch Event Interrupt Enable" start="6" size="1" />
+      <BitField name="GTWE" description="Global Time Wrap Interrupt Enable" start="7" size="1" />
+      <BitField name="GTDE" description="Global Time Discontinuity Interrupt Enable" start="8" size="1" />
+      <BitField name="GTEE" description="Global Time Error Interrupt Enable" start="9" size="1" />
+      <BitField name="TXUE" description="Tx Count Underflow Interrupt Enable" start="10" size="1" />
+      <BitField name="TXOE" description="Tx Count Overflow Interrupt Enable" start="11" size="1" />
+      <BitField name="SE1E" description="Scheduling Error 1 Interrupt Enable" start="12" size="1" />
+      <BitField name="SE2E" description="Scheduling Error 2 Interrupt Enable" start="13" size="1" />
+      <BitField name="ELCE" description="Change Error Level Interrupt Enable" start="14" size="1" />
+      <BitField name="IWTGE" description="Initialization Watch Trigger Interrupt Enable" start="15" size="1" />
+      <BitField name="WTE" description="Watch Trigger Interrupt Enable" start="16" size="1" />
+      <BitField name="AWE" description="Application Watchdog Interrupt Enable" start="17" size="1" />
+      <BitField name="CERE" description="Configuration Error Interrupt Enable" start="18" size="1" />
+    </Register>
+    <Register name="FDCAN_TTILS" description="FDCAN TT Interrupt Line Select Register" start="+0x128" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SBCL" description="Start of Basic Cycle Interrupt Line" start="0" size="1" />
+      <BitField name="SMCL" description="Start of Matrix Cycle Interrupt Line" start="1" size="1" />
+      <BitField name="CSML" description="Change of Synchronization Mode Interrupt Line" start="2" size="1" />
+      <BitField name="SOGL" description="Start of Gap Interrupt Line" start="3" size="1" />
+      <BitField name="RTMIL" description="Register Time Mark Interrupt Line" start="4" size="1" />
+      <BitField name="TTMIL" description="Trigger Time Mark Event Internal Interrupt Line" start="5" size="1" />
+      <BitField name="SWEL" description="Stop Watch Event Interrupt Line" start="6" size="1" />
+      <BitField name="GTWL" description="Global Time Wrap Interrupt Line" start="7" size="1" />
+      <BitField name="GTDL" description="Global Time Discontinuity Interrupt Line" start="8" size="1" />
+      <BitField name="GTEL" description="Global Time Error Interrupt Line" start="9" size="1" />
+      <BitField name="TXUL" description="Tx Count Underflow Interrupt Line" start="10" size="1" />
+      <BitField name="TXOL" description="Tx Count Overflow Interrupt Line" start="11" size="1" />
+      <BitField name="SE1L" description="Scheduling Error 1 Interrupt Line" start="12" size="1" />
+      <BitField name="SE2L" description="Scheduling Error 2 Interrupt Line" start="13" size="1" />
+      <BitField name="ELCL" description="Change Error Level Interrupt Line" start="14" size="1" />
+      <BitField name="IWTGL" description="Initialization Watch Trigger Interrupt Line" start="15" size="1" />
+      <BitField name="WTL" description="Watch Trigger Interrupt Line" start="16" size="1" />
+      <BitField name="AWL" description="Application Watchdog Interrupt Line" start="17" size="1" />
+      <BitField name="CERL" description="Configuration Error Interrupt Line" start="18" size="1" />
+    </Register>
+    <Register name="FDCAN_TTOST" description="FDCAN TT Operation Status Register" start="+0x12C" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EL" description="Error Level" start="0" size="2" />
+      <BitField name="MS" description="Master State." start="2" size="2" />
+      <BitField name="SYS" description="Synchronization State" start="4" size="2" />
+      <BitField name="GTP" description="Quality of Global Time Phase" start="6" size="1" />
+      <BitField name="QCS" description="Quality of Clock Speed" start="7" size="1" />
+      <BitField name="RTO" description="Reference Trigger Offset" start="8" size="8" />
+      <BitField name="WGTD" description="Wait for Global Time Discontinuity" start="22" size="1" />
+      <BitField name="GFI" description="Gap Finished Indicator." start="23" size="1" />
+      <BitField name="TMP" description="Time Master Priority" start="24" size="3" />
+      <BitField name="GSI" description="Gap Started Indicator." start="27" size="1" />
+      <BitField name="WFE" description="Wait for Event" start="28" size="1" />
+      <BitField name="AWE" description="Application Watchdog Event" start="29" size="1" />
+      <BitField name="WECS" description="Wait for External Clock Synchronization" start="30" size="1" />
+      <BitField name="SPL" description="Schedule Phase Lock" start="31" size="1" />
+    </Register>
+    <Register name="FDCAN_TURNA" description="FDCAN TUR Numerator Actual Register" start="+0x130" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="NAV" description="Numerator Actual Value" start="0" size="18" />
+    </Register>
+    <Register name="FDCAN_TTLGT" description="FDCAN TT Local and Global Time Register" start="+0x134" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LT" description="Local Time" start="0" size="16" />
+      <BitField name="GT" description="Global Time" start="16" size="16" />
+    </Register>
+    <Register name="FDCAN_TTCTC" description="FDCAN TT Cycle Time and Count Register" start="+0x138" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CT" description="Cycle Time" start="0" size="16" />
+      <BitField name="CC" description="Cycle Count" start="16" size="6" />
+    </Register>
+    <Register name="FDCAN_TTCPT" description="FDCAN TT Capture Time Register" start="+0x13C" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CT" description="Cycle Count Value" start="0" size="6" />
+      <BitField name="SWV" description="Stop Watch Value" start="16" size="16" />
+    </Register>
+    <Register name="FDCAN_TTCSM" description="FDCAN TT Cycle Sync Mark Register" start="+0x140" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CSM" description="Cycle Sync Mark" start="0" size="16" />
+    </Register>
+    <Register name="FDCAN_TTTS" description="FDCAN TT Trigger Select Register" start="+0x300" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWTDEL" description="Stop watch trigger input selection" start="0" size="2" />
+      <BitField name="EVTSEL" description="Event trigger input selection" start="4" size="2" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="FDCAN3" description="FDCAN1" start="0x4000D400">
+    <Register name="FDCAN_CREL" description="FDCAN Core Release Register" start="+0x0" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="REL" description="Core release" start="28" size="4" />
+      <BitField name="STEP" description="Step of Core release" start="24" size="4" />
+      <BitField name="SUBSTEP" description="Sub-step of Core release" start="20" size="4" />
+      <BitField name="YEAR" description="Timestamp Year" start="16" size="4" />
+      <BitField name="MON" description="Timestamp Month" start="8" size="8" />
+      <BitField name="DAY" description="Timestamp Day" start="0" size="8" />
+    </Register>
+    <Register name="FDCAN_ENDN" description="FDCAN Core Release Register" start="+0x4" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ETV" description="Endiannes Test Value" start="0" size="32" />
+    </Register>
+    <Register name="FDCAN_DBTP" description="FDCAN Data Bit Timing and Prescaler Register" start="+0xC" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DSJW" description="Synchronization Jump Width" start="0" size="4" />
+      <BitField name="DTSEG2" description="Data time segment after sample point" start="4" size="4" />
+      <BitField name="DTSEG1" description="Data time segment after sample point" start="8" size="5" />
+      <BitField name="DBRP" description="Data BIt Rate Prescaler" start="16" size="5" />
+      <BitField name="TDC" description="Transceiver Delay Compensation" start="23" size="1" />
+    </Register>
+    <Register name="FDCAN_TEST" description="FDCAN Test Register" start="+0x10" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LBCK" description="Loop Back mode" start="4" size="1" />
+      <BitField name="TX" description="Loop Back mode" start="5" size="2" />
+      <BitField name="RX" description="Control of Transmit Pin" start="7" size="1" />
+    </Register>
+    <Register name="FDCAN_RWD" description="FDCAN RAM Watchdog Register" start="+0x14" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="WDV" description="Watchdog value" start="8" size="8" />
+      <BitField name="WDC" description="Watchdog configuration" start="0" size="8" />
+    </Register>
+    <Register name="FDCAN_CCCR" description="FDCAN CC Control Register" start="+0x18" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="INIT" description="Initialization" start="0" size="1" />
+      <BitField name="CCE" description="Configuration Change Enable" start="1" size="1" />
+      <BitField name="ASM" description="ASM Restricted Operation Mode" start="2" size="1" />
+      <BitField name="CSA" description="Clock Stop Acknowledge" start="3" size="1" />
+      <BitField name="CSR" description="Clock Stop Request" start="4" size="1" />
+      <BitField name="MON" description="Bus Monitoring Mode" start="5" size="1" />
+      <BitField name="DAR" description="Disable Automatic Retransmission" start="6" size="1" />
+      <BitField name="TEST" description="Test Mode Enable" start="7" size="1" />
+      <BitField name="FDOE" description="FD Operation Enable" start="8" size="1" />
+      <BitField name="BSE" description="FDCAN Bit Rate Switching" start="9" size="1" />
+      <BitField name="PXHD" description="Protocol Exception Handling Disable" start="12" size="1" />
+      <BitField name="EFBI" description="Edge Filtering during Bus Integration" start="13" size="1" />
+      <BitField name="TXP" description="TXP" start="14" size="1" />
+      <BitField name="NISO" description="Non ISO Operation" start="15" size="1" />
+    </Register>
+    <Register name="FDCAN_NBTP" description="FDCAN Nominal Bit Timing and Prescaler Register" start="+0x1C" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="NSJW" description="NSJW: Nominal (Re)Synchronization Jump Width" start="25" size="7" />
+      <BitField name="NBRP" description="Bit Rate Prescaler" start="16" size="9" />
+      <BitField name="NTSEG1" description="Nominal Time segment before sample point" start="8" size="8" />
+      <BitField name="TSEG2" description="Nominal Time segment after sample point" start="0" size="7" />
+    </Register>
+    <Register name="FDCAN_TSCC" description="FDCAN Timestamp Counter Configuration Register" start="+0x20" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TCP" description="Timestamp Counter Prescaler" start="16" size="4" />
+      <BitField name="TSS" description="Timestamp Select" start="0" size="2" />
+    </Register>
+    <Register name="FDCAN_TSCV" description="FDCAN Timestamp Counter Value Register" start="+0x24" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TSC" description="Timestamp Counter" start="0" size="16" />
+    </Register>
+    <Register name="FDCAN_TOCC" description="FDCAN Timeout Counter Configuration Register" start="+0x28" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ETOC" description="Enable Timeout Counter" start="0" size="1" />
+      <BitField name="TOS" description="Timeout Select" start="1" size="2" />
+      <BitField name="TOP" description="Timeout Period" start="16" size="16" />
+    </Register>
+    <Register name="FDCAN_TOCV" description="FDCAN Timeout Counter Value Register" start="+0x2C" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TOC" description="Timeout Counter" start="0" size="16" />
+    </Register>
+    <Register name="FDCAN_ECR" description="FDCAN Error Counter Register" start="+0x40" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CEL" description="AN Error Logging" start="16" size="8" />
+      <BitField name="RP" description="Receive Error Passive" start="15" size="1" />
+      <BitField name="TREC" description="Receive Error Counter" start="8" size="7" />
+      <BitField name="TEC" description="Transmit Error Counter" start="0" size="8" />
+    </Register>
+    <Register name="FDCAN_PSR" description="FDCAN Protocol Status Register" start="+0x44" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LEC" description="Last Error Code" start="0" size="3" />
+      <BitField name="ACT" description="Activity" start="3" size="2" />
+      <BitField name="EP" description="Error Passive" start="5" size="1" />
+      <BitField name="EW" description="Warning Status" start="6" size="1" />
+      <BitField name="BO" description="Bus_Off Status" start="7" size="1" />
+      <BitField name="DLEC" description="Data Last Error Code" start="8" size="3" />
+      <BitField name="RESI" description="ESI flag of last received FDCAN Message" start="11" size="1" />
+      <BitField name="RBRS" description="BRS flag of last received FDCAN Message" start="12" size="1" />
+      <BitField name="REDL" description="Received FDCAN Message" start="13" size="1" />
+      <BitField name="PXE" description="Protocol Exception Event" start="14" size="1" />
+      <BitField name="TDCV" description="Transmitter Delay Compensation Value" start="16" size="7" />
+    </Register>
+    <Register name="FDCAN_TDCR" description="FDCAN Transmitter Delay Compensation Register" start="+0x48" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TDCF" description="Transmitter Delay Compensation Filter Window Length" start="0" size="7" />
+      <BitField name="TDCO" description="Transmitter Delay Compensation Offset" start="8" size="7" />
+    </Register>
+    <Register name="FDCAN_IR" description="FDCAN Interrupt Register" start="+0x50" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RF0N" description="Rx FIFO 0 New Message" start="0" size="1" />
+      <BitField name="RF0W" description="Rx FIFO 0 Full" start="1" size="1" />
+      <BitField name="RF0F" description="Rx FIFO 0 Full" start="2" size="1" />
+      <BitField name="RF0L" description="Rx FIFO 0 Message Lost" start="3" size="1" />
+      <BitField name="RF1N" description="Rx FIFO 1 New Message" start="4" size="1" />
+      <BitField name="RF1W" description="Rx FIFO 1 Watermark Reached" start="5" size="1" />
+      <BitField name="RF1F" description="Rx FIFO 1 Watermark Reached" start="6" size="1" />
+      <BitField name="RF1L" description="Rx FIFO 1 Message Lost" start="7" size="1" />
+      <BitField name="HPM" description="High Priority Message" start="8" size="1" />
+      <BitField name="TC" description="Transmission Completed" start="9" size="1" />
+      <BitField name="TCF" description="Transmission Cancellation Finished" start="10" size="1" />
+      <BitField name="TEF" description="Tx FIFO Empty" start="11" size="1" />
+      <BitField name="TEFN" description="Tx Event FIFO New Entry" start="12" size="1" />
+      <BitField name="TEFW" description="Tx Event FIFO Watermark Reached" start="13" size="1" />
+      <BitField name="TEFF" description="Tx Event FIFO Full" start="14" size="1" />
+      <BitField name="TEFL" description="Tx Event FIFO Element Lost" start="15" size="1" />
+      <BitField name="TSW" description="Timestamp Wraparound" start="16" size="1" />
+      <BitField name="MRAF" description="Message RAM Access Failure" start="17" size="1" />
+      <BitField name="TOO" description="Timeout Occurred" start="18" size="1" />
+      <BitField name="DRX" description="Message stored to Dedicated Rx Buffer" start="19" size="1" />
+      <BitField name="ELO" description="Error Logging Overflow" start="22" size="1" />
+      <BitField name="EP" description="Error Passive" start="23" size="1" />
+      <BitField name="EW" description="Warning Status" start="24" size="1" />
+      <BitField name="BO" description="Bus_Off Status" start="25" size="1" />
+      <BitField name="WDI" description="Watchdog Interrupt" start="26" size="1" />
+      <BitField name="PEA" description="Protocol Error in Arbitration Phase (Nominal Bit Time is used)" start="27" size="1" />
+      <BitField name="PED" description="Protocol Error in Data Phase (Data Bit Time is used)" start="28" size="1" />
+      <BitField name="ARA" description="Access to Reserved Address" start="29" size="1" />
+    </Register>
+    <Register name="FDCAN_IE" description="FDCAN Interrupt Enable Register" start="+0x54" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RF0NE" description="Rx FIFO 0 New Message Enable" start="0" size="1" />
+      <BitField name="RF0WE" description="Rx FIFO 0 Full Enable" start="1" size="1" />
+      <BitField name="RF0FE" description="Rx FIFO 0 Full Enable" start="2" size="1" />
+      <BitField name="RF0LE" description="Rx FIFO 0 Message Lost Enable" start="3" size="1" />
+      <BitField name="RF1NE" description="Rx FIFO 1 New Message Enable" start="4" size="1" />
+      <BitField name="RF1WE" description="Rx FIFO 1 Watermark Reached Enable" start="5" size="1" />
+      <BitField name="RF1FE" description="Rx FIFO 1 Watermark Reached Enable" start="6" size="1" />
+      <BitField name="RF1LE" description="Rx FIFO 1 Message Lost Enable" start="7" size="1" />
+      <BitField name="HPME" description="High Priority Message Enable" start="8" size="1" />
+      <BitField name="TCE" description="Transmission Completed Enable" start="9" size="1" />
+      <BitField name="TCFE" description="Transmission Cancellation Finished Enable" start="10" size="1" />
+      <BitField name="TEFE" description="Tx FIFO Empty Enable" start="11" size="1" />
+      <BitField name="TEFNE" description="Tx Event FIFO New Entry Enable" start="12" size="1" />
+      <BitField name="TEFWE" description="Tx Event FIFO Watermark Reached Enable" start="13" size="1" />
+      <BitField name="TEFFE" description="Tx Event FIFO Full Enable" start="14" size="1" />
+      <BitField name="TEFLE" description="Tx Event FIFO Element Lost Enable" start="15" size="1" />
+      <BitField name="TSWE" description="Timestamp Wraparound Enable" start="16" size="1" />
+      <BitField name="MRAFE" description="Message RAM Access Failure Enable" start="17" size="1" />
+      <BitField name="TOOE" description="Timeout Occurred Enable" start="18" size="1" />
+      <BitField name="DRXE" description="Message stored to Dedicated Rx Buffer Enable" start="19" size="1" />
+      <BitField name="BECE" description="Bit Error Corrected Interrupt Enable" start="20" size="1" />
+      <BitField name="BEUE" description="Bit Error Uncorrected Interrupt Enable" start="21" size="1" />
+      <BitField name="ELOE" description="Error Logging Overflow Enable" start="22" size="1" />
+      <BitField name="EPE" description="Error Passive Enable" start="23" size="1" />
+      <BitField name="EWE" description="Warning Status Enable" start="24" size="1" />
+      <BitField name="BOE" description="Bus_Off Status Enable" start="25" size="1" />
+      <BitField name="WDIE" description="Watchdog Interrupt Enable" start="26" size="1" />
+      <BitField name="PEAE" description="Protocol Error in Arbitration Phase Enable" start="27" size="1" />
+      <BitField name="PEDE" description="Protocol Error in Data Phase Enable" start="28" size="1" />
+      <BitField name="ARAE" description="Access to Reserved Address Enable" start="29" size="1" />
+    </Register>
+    <Register name="FDCAN_ILS" description="FDCAN Interrupt Line Select Register" start="+0x58" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RF0NL" description="Rx FIFO 0 New Message Interrupt Line" start="0" size="1" />
+      <BitField name="RF0WL" description="Rx FIFO 0 Watermark Reached Interrupt Line" start="1" size="1" />
+      <BitField name="RF0FL" description="Rx FIFO 0 Full Interrupt Line" start="2" size="1" />
+      <BitField name="RF0LL" description="Rx FIFO 0 Message Lost Interrupt Line" start="3" size="1" />
+      <BitField name="RF1NL" description="Rx FIFO 1 New Message Interrupt Line" start="4" size="1" />
+      <BitField name="RF1WL" description="Rx FIFO 1 Watermark Reached Interrupt Line" start="5" size="1" />
+      <BitField name="RF1FL" description="Rx FIFO 1 Full Interrupt Line" start="6" size="1" />
+      <BitField name="RF1LL" description="Rx FIFO 1 Message Lost Interrupt Line" start="7" size="1" />
+      <BitField name="HPML" description="High Priority Message Interrupt Line" start="8" size="1" />
+      <BitField name="TCL" description="Transmission Completed Interrupt Line" start="9" size="1" />
+      <BitField name="TCFL" description="Transmission Cancellation Finished Interrupt Line" start="10" size="1" />
+      <BitField name="TEFL" description="Tx FIFO Empty Interrupt Line" start="11" size="1" />
+      <BitField name="TEFNL" description="Tx Event FIFO New Entry Interrupt Line" start="12" size="1" />
+      <BitField name="TEFWL" description="Tx Event FIFO Watermark Reached Interrupt Line" start="13" size="1" />
+      <BitField name="TEFFL" description="Tx Event FIFO Full Interrupt Line" start="14" size="1" />
+      <BitField name="TEFLL" description="Tx Event FIFO Element Lost Interrupt Line" start="15" size="1" />
+      <BitField name="TSWL" description="Timestamp Wraparound Interrupt Line" start="16" size="1" />
+      <BitField name="MRAFL" description="Message RAM Access Failure Interrupt Line" start="17" size="1" />
+      <BitField name="TOOL" description="Timeout Occurred Interrupt Line" start="18" size="1" />
+      <BitField name="DRXL" description="Message stored to Dedicated Rx Buffer Interrupt Line" start="19" size="1" />
+      <BitField name="BECL" description="Bit Error Corrected Interrupt Line" start="20" size="1" />
+      <BitField name="BEUL" description="Bit Error Uncorrected Interrupt Line" start="21" size="1" />
+      <BitField name="ELOL" description="Error Logging Overflow Interrupt Line" start="22" size="1" />
+      <BitField name="EPL" description="Error Passive Interrupt Line" start="23" size="1" />
+      <BitField name="EWL" description="Warning Status Interrupt Line" start="24" size="1" />
+      <BitField name="BOL" description="Bus_Off Status" start="25" size="1" />
+      <BitField name="WDIL" description="Watchdog Interrupt Line" start="26" size="1" />
+      <BitField name="PEAL" description="Protocol Error in Arbitration Phase Line" start="27" size="1" />
+      <BitField name="PEDL" description="Protocol Error in Data Phase Line" start="28" size="1" />
+      <BitField name="ARAL" description="Access to Reserved Address Line" start="29" size="1" />
+    </Register>
+    <Register name="FDCAN_ILE" description="FDCAN Interrupt Line Enable Register" start="+0x5C" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EINT0" description="Enable Interrupt Line 0" start="0" size="1" />
+      <BitField name="EINT1" description="Enable Interrupt Line 1" start="1" size="1" />
+    </Register>
+    <Register name="FDCAN_GFC" description="FDCAN Global Filter Configuration Register" start="+0x80" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RRFE" description="Reject Remote Frames Extended" start="0" size="1" />
+      <BitField name="RRFS" description="Reject Remote Frames Standard" start="1" size="1" />
+      <BitField name="ANFE" description="Accept Non-matching Frames Extended" start="2" size="2" />
+      <BitField name="ANFS" description="Accept Non-matching Frames Standard" start="4" size="2" />
+    </Register>
+    <Register name="FDCAN_SIDFC" description="FDCAN Standard ID Filter Configuration Register" start="+0x84" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FLSSA" description="Filter List Standard Start Address" start="2" size="14" />
+      <BitField name="LSS" description="List Size Standard" start="16" size="8" />
+    </Register>
+    <Register name="FDCAN_XIDFC" description="FDCAN Extended ID Filter Configuration Register" start="+0x88" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FLESA" description="Filter List Standard Start Address" start="2" size="14" />
+      <BitField name="LSE" description="List Size Extended" start="16" size="8" />
+    </Register>
+    <Register name="FDCAN_XIDAM" description="FDCAN Extended ID and Mask Register" start="+0x90" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EIDM" description="Extended ID Mask" start="0" size="29" />
+    </Register>
+    <Register name="FDCAN_HPMS" description="FDCAN High Priority Message Status Register" start="+0x94" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BIDX" description="Buffer Index" start="0" size="6" />
+      <BitField name="MSI" description="Message Storage Indicator" start="6" size="2" />
+      <BitField name="FIDX" description="Filter Index" start="8" size="7" />
+      <BitField name="FLST" description="Filter List" start="15" size="1" />
+    </Register>
+    <Register name="FDCAN_NDAT1" description="FDCAN New Data 1 Register" start="+0x98" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ND0" description="New data" start="0" size="1" />
+      <BitField name="ND1" description="New data" start="1" size="1" />
+      <BitField name="ND2" description="New data" start="2" size="1" />
+      <BitField name="ND3" description="New data" start="3" size="1" />
+      <BitField name="ND4" description="New data" start="4" size="1" />
+      <BitField name="ND5" description="New data" start="5" size="1" />
+      <BitField name="ND6" description="New data" start="6" size="1" />
+      <BitField name="ND7" description="New data" start="7" size="1" />
+      <BitField name="ND8" description="New data" start="8" size="1" />
+      <BitField name="ND9" description="New data" start="9" size="1" />
+      <BitField name="ND10" description="New data" start="10" size="1" />
+      <BitField name="ND11" description="New data" start="11" size="1" />
+      <BitField name="ND12" description="New data" start="12" size="1" />
+      <BitField name="ND13" description="New data" start="13" size="1" />
+      <BitField name="ND14" description="New data" start="14" size="1" />
+      <BitField name="ND15" description="New data" start="15" size="1" />
+      <BitField name="ND16" description="New data" start="16" size="1" />
+      <BitField name="ND17" description="New data" start="17" size="1" />
+      <BitField name="ND18" description="New data" start="18" size="1" />
+      <BitField name="ND19" description="New data" start="19" size="1" />
+      <BitField name="ND20" description="New data" start="20" size="1" />
+      <BitField name="ND21" description="New data" start="21" size="1" />
+      <BitField name="ND22" description="New data" start="22" size="1" />
+      <BitField name="ND23" description="New data" start="23" size="1" />
+      <BitField name="ND24" description="New data" start="24" size="1" />
+      <BitField name="ND25" description="New data" start="25" size="1" />
+      <BitField name="ND26" description="New data" start="26" size="1" />
+      <BitField name="ND27" description="New data" start="27" size="1" />
+      <BitField name="ND28" description="New data" start="28" size="1" />
+      <BitField name="ND29" description="New data" start="29" size="1" />
+      <BitField name="ND30" description="New data" start="30" size="1" />
+      <BitField name="ND31" description="New data" start="31" size="1" />
+    </Register>
+    <Register name="FDCAN_NDAT2" description="FDCAN New Data 2 Register" start="+0x9C" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ND32" description="New data" start="0" size="1" />
+      <BitField name="ND33" description="New data" start="1" size="1" />
+      <BitField name="ND34" description="New data" start="2" size="1" />
+      <BitField name="ND35" description="New data" start="3" size="1" />
+      <BitField name="ND36" description="New data" start="4" size="1" />
+      <BitField name="ND37" description="New data" start="5" size="1" />
+      <BitField name="ND38" description="New data" start="6" size="1" />
+      <BitField name="ND39" description="New data" start="7" size="1" />
+      <BitField name="ND40" description="New data" start="8" size="1" />
+      <BitField name="ND41" description="New data" start="9" size="1" />
+      <BitField name="ND42" description="New data" start="10" size="1" />
+      <BitField name="ND43" description="New data" start="11" size="1" />
+      <BitField name="ND44" description="New data" start="12" size="1" />
+      <BitField name="ND45" description="New data" start="13" size="1" />
+      <BitField name="ND46" description="New data" start="14" size="1" />
+      <BitField name="ND47" description="New data" start="15" size="1" />
+      <BitField name="ND48" description="New data" start="16" size="1" />
+      <BitField name="ND49" description="New data" start="17" size="1" />
+      <BitField name="ND50" description="New data" start="18" size="1" />
+      <BitField name="ND51" description="New data" start="19" size="1" />
+      <BitField name="ND52" description="New data" start="20" size="1" />
+      <BitField name="ND53" description="New data" start="21" size="1" />
+      <BitField name="ND54" description="New data" start="22" size="1" />
+      <BitField name="ND55" description="New data" start="23" size="1" />
+      <BitField name="ND56" description="New data" start="24" size="1" />
+      <BitField name="ND57" description="New data" start="25" size="1" />
+      <BitField name="ND58" description="New data" start="26" size="1" />
+      <BitField name="ND59" description="New data" start="27" size="1" />
+      <BitField name="ND60" description="New data" start="28" size="1" />
+      <BitField name="ND61" description="New data" start="29" size="1" />
+      <BitField name="ND62" description="New data" start="30" size="1" />
+      <BitField name="ND63" description="New data" start="31" size="1" />
+    </Register>
+    <Register name="FDCAN_RXF0C" description="FDCAN Rx FIFO 0 Configuration Register" start="+0xA0" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="F0SA" description="Rx FIFO 0 Start Address" start="2" size="14" />
+      <BitField name="F0S" description="Rx FIFO 0 Size" start="16" size="8" />
+      <BitField name="F0WM" description="FIFO 0 Watermark" start="24" size="8" />
+    </Register>
+    <Register name="FDCAN_RXF0S" description="FDCAN Rx FIFO 0 Status Register" start="+0xA4" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="F0FL" description="Rx FIFO 0 Fill Level" start="0" size="7" />
+      <BitField name="F0G" description="Rx FIFO 0 Get Index" start="8" size="6" />
+      <BitField name="F0P" description="Rx FIFO 0 Put Index" start="16" size="6" />
+      <BitField name="F0F" description="Rx FIFO 0 Full" start="24" size="1" />
+      <BitField name="RF0L" description="Rx FIFO 0 Message Lost" start="25" size="1" />
+    </Register>
+    <Register name="FDCAN_RXF0A" description="CAN Rx FIFO 0 Acknowledge Register" start="+0xA8" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FA01" description="Rx FIFO 0 Acknowledge Index" start="0" size="6" />
+    </Register>
+    <Register name="FDCAN_RXBC" description="FDCAN Rx Buffer Configuration Register" start="+0xAC" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RBSA" description="Rx Buffer Start Address" start="2" size="14" />
+    </Register>
+    <Register name="FDCAN_RXF1C" description="FDCAN Rx FIFO 1 Configuration Register" start="+0xB0" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="F1SA" description="Rx FIFO 1 Start Address" start="2" size="14" />
+      <BitField name="F1S" description="Rx FIFO 1 Size" start="16" size="7" />
+      <BitField name="F1WM" description="Rx FIFO 1 Watermark" start="24" size="7" />
+    </Register>
+    <Register name="FDCAN_RXF1S" description="FDCAN Rx FIFO 1 Status Register" start="+0xB4" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="F1FL" description="Rx FIFO 1 Fill Level" start="0" size="7" />
+      <BitField name="F1GI" description="Rx FIFO 1 Get Index" start="8" size="7" />
+      <BitField name="F1PI" description="Rx FIFO 1 Put Index" start="16" size="7" />
+      <BitField name="F1F" description="Rx FIFO 1 Full" start="24" size="1" />
+      <BitField name="RF1L" description="Rx FIFO 1 Message Lost" start="25" size="1" />
+      <BitField name="DMS" description="Debug Message Status" start="30" size="2" />
+    </Register>
+    <Register name="FDCAN_RXF1A" description="FDCAN Rx FIFO 1 Acknowledge Register" start="+0xB8" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="F1AI" description="Rx FIFO 1 Acknowledge Index" start="0" size="6" />
+    </Register>
+    <Register name="FDCAN_RXESC" description="FDCAN Rx Buffer Element Size Configuration Register" start="+0xBC" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="F0DS" description="Rx FIFO 1 Data Field Size:" start="0" size="3" />
+      <BitField name="F1DS" description="Rx FIFO 0 Data Field Size:" start="4" size="3" />
+      <BitField name="RBDS" description="Rx Buffer Data Field Size:" start="8" size="3" />
+    </Register>
+    <Register name="FDCAN_TXBC" description="FDCAN Tx Buffer Configuration Register" start="+0xC0" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TBSA" description="Tx Buffers Start Address" start="2" size="14" />
+      <BitField name="NDTB" description="Number of Dedicated Transmit Buffers" start="16" size="6" />
+      <BitField name="TFQS" description="Transmit FIFO/Queue Size" start="24" size="6" />
+      <BitField name="TFQM" description="Tx FIFO/Queue Mode" start="30" size="1" />
+    </Register>
+    <Register name="FDCAN_TXFQS" description="FDCAN Tx FIFO/Queue Status Register" start="+0xC4" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TFFL" description="Tx FIFO Free Level" start="0" size="6" />
+      <BitField name="TFGI" description="TFGI" start="8" size="5" />
+      <BitField name="TFQPI" description="Tx FIFO/Queue Put Index" start="16" size="5" />
+      <BitField name="TFQF" description="Tx FIFO/Queue Full" start="21" size="1" />
+    </Register>
+    <Register name="FDCAN_TXESC" description="FDCAN Tx Buffer Element Size Configuration Register" start="+0xC8" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TBDS" description="Tx Buffer Data Field Size:" start="0" size="3" />
+    </Register>
+    <Register name="FDCAN_TXBRP" description="FDCAN Tx Buffer Request Pending Register" start="+0xCC" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TRP" description="Transmission Request Pending" start="0" size="32" />
+    </Register>
+    <Register name="FDCAN_TXBAR" description="FDCAN Tx Buffer Add Request Register" start="+0xD0" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AR" description="Add Request" start="0" size="32" />
+    </Register>
+    <Register name="FDCAN_TXBCR" description="FDCAN Tx Buffer Cancellation Request Register" start="+0xD4" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CR" description="Cancellation Request" start="0" size="32" />
+    </Register>
+    <Register name="FDCAN_TXBTO" description="FDCAN Tx Buffer Transmission Occurred Register" start="+0xD8" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TO" description="Transmission Occurred." start="0" size="32" />
+    </Register>
+    <Register name="FDCAN_TXBCF" description="FDCAN Tx Buffer Cancellation Finished Register" start="+0xDC" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CF" description="Cancellation Finished" start="0" size="32" />
+    </Register>
+    <Register name="FDCAN_TXBTIE" description="FDCAN Tx Buffer Transmission Interrupt Enable Register" start="+0xE0" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TIE" description="Transmission Interrupt Enable" start="0" size="32" />
+    </Register>
+    <Register name="FDCAN_TXBCIE" description="FDCAN Tx Buffer Cancellation Finished Interrupt Enable Register" start="+0xE4" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CF" description="Cancellation Finished Interrupt Enable" start="0" size="32" />
+    </Register>
+    <Register name="FDCAN_TXEFC" description="FDCAN Tx Event FIFO Configuration Register" start="+0xF0" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EFSA" description="Event FIFO Start Address" start="2" size="14" />
+      <BitField name="EFS" description="Event FIFO Size" start="16" size="6" />
+      <BitField name="EFWM" description="Event FIFO Watermark" start="24" size="6" />
+    </Register>
+    <Register name="FDCAN_TXEFS" description="FDCAN Tx Event FIFO Status Register" start="+0xF4" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EFFL" description="Event FIFO Fill Level" start="0" size="6" />
+      <BitField name="EFGI" description="Event FIFO Get Index." start="8" size="5" />
+      <BitField name="EFF" description="Event FIFO Full." start="24" size="1" />
+      <BitField name="TEFL" description="Tx Event FIFO Element Lost." start="25" size="1" />
+    </Register>
+    <Register name="FDCAN_TXEFA" description="FDCAN Tx Event FIFO Acknowledge Register" start="+0xF8" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EFAI" description="Event FIFO Acknowledge Index" start="0" size="5" />
+    </Register>
+    <Register name="FDCAN_TTTMC" description="FDCAN TT Trigger Memory Configuration Register" start="+0x100" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TMSA" description="Trigger Memory Start Address" start="2" size="14" />
+      <BitField name="TME" description="Trigger Memory Elements" start="16" size="7" />
+    </Register>
+    <Register name="FDCAN_TTRMC" description="FDCAN TT Reference Message Configuration Register" start="+0x104" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RID" description="Reference Identifier." start="0" size="29" />
+      <BitField name="XTD" description="Extended Identifier" start="30" size="1" />
+      <BitField name="RMPS" description="Reference Message Payload Select" start="31" size="1" />
+    </Register>
+    <Register name="FDCAN_TTOCF" description="FDCAN TT Operation Configuration Register" start="+0x108" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OM" description="Operation Mode" start="0" size="2" />
+      <BitField name="GEN" description="Gap Enable" start="3" size="1" />
+      <BitField name="TM" description="Time Master" start="4" size="1" />
+      <BitField name="LDSDL" description="LD of Synchronization Deviation Limit" start="5" size="3" />
+      <BitField name="IRTO" description="Initial Reference Trigger Offset" start="8" size="7" />
+      <BitField name="EECS" description="Enable External Clock Synchronization" start="15" size="1" />
+      <BitField name="AWL" description="Application Watchdog Limit" start="16" size="8" />
+      <BitField name="EGTF" description="Enable Global Time Filtering" start="24" size="1" />
+      <BitField name="ECC" description="Enable Clock Calibration" start="25" size="1" />
+      <BitField name="EVTP" description="Event Trigger Polarity" start="26" size="1" />
+    </Register>
+    <Register name="FDCAN_TTMLM" description="FDCAN TT Matrix Limits Register" start="+0x10C" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCM" description="Cycle Count Max" start="0" size="6" />
+      <BitField name="CSS" description="Cycle Start Synchronization" start="6" size="2" />
+      <BitField name="TXEW" description="Tx Enable Window" start="8" size="4" />
+      <BitField name="ENTT" description="Expected Number of Tx Triggers" start="16" size="12" />
+    </Register>
+    <Register name="FDCAN_TURCF" description="FDCAN TUR Configuration Register" start="+0x110" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="NCL" description="Numerator Configuration Low." start="0" size="16" />
+      <BitField name="DC" description="Denominator Configuration." start="16" size="14" />
+      <BitField name="ELT" description="Enable Local Time" start="31" size="1" />
+    </Register>
+    <Register name="FDCAN_TTOCN" description="FDCAN TT Operation Control Register" start="+0x114" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SGT" description="Set Global time" start="0" size="1" />
+      <BitField name="ECS" description="External Clock Synchronization" start="1" size="1" />
+      <BitField name="SWP" description="Stop Watch Polarity" start="2" size="1" />
+      <BitField name="SWS" description="Stop Watch Source." start="3" size="2" />
+      <BitField name="RTIE" description="Register Time Mark Interrupt Pulse Enable" start="5" size="1" />
+      <BitField name="TMC" description="Register Time Mark Compare" start="6" size="2" />
+      <BitField name="TTIE" description="Trigger Time Mark Interrupt Pulse Enable" start="8" size="1" />
+      <BitField name="GCS" description="Gap Control Select" start="9" size="1" />
+      <BitField name="FGP" description="Finish Gap." start="10" size="1" />
+      <BitField name="TMG" description="Time Mark Gap" start="11" size="1" />
+      <BitField name="NIG" description="Next is Gap" start="12" size="1" />
+      <BitField name="ESCN" description="External Synchronization Control" start="13" size="1" />
+      <BitField name="LCKC" description="TT Operation Control Register Locked" start="15" size="1" />
+    </Register>
+    <Register name="CAN_TTGTP" description="FDCAN TT Global Time Preset Register" start="+0x118" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="NCL" description="Time Preset" start="0" size="16" />
+      <BitField name="CTP" description="Cycle Time Target Phase" start="16" size="16" />
+    </Register>
+    <Register name="FDCAN_TTTMK" description="FDCAN TT Time Mark Register" start="+0x11C" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TM" description="Time Mark" start="0" size="16" />
+      <BitField name="TICC" description="Time Mark Cycle Code" start="16" size="7" />
+      <BitField name="LCKM" description="TT Time Mark Register Locked" start="31" size="1" />
+    </Register>
+    <Register name="FDCAN_TTIR" description="FDCAN TT Interrupt Register" start="+0x120" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SBC" description="Start of Basic Cycle" start="0" size="1" />
+      <BitField name="SMC" description="Start of Matrix Cycle" start="1" size="1" />
+      <BitField name="CSM" description="Change of Synchronization Mode" start="2" size="1" />
+      <BitField name="SOG" description="Start of Gap" start="3" size="1" />
+      <BitField name="RTMI" description="Register Time Mark Interrupt." start="4" size="1" />
+      <BitField name="TTMI" description="Trigger Time Mark Event Internal" start="5" size="1" />
+      <BitField name="SWE" description="Stop Watch Event" start="6" size="1" />
+      <BitField name="GTW" description="Global Time Wrap" start="7" size="1" />
+      <BitField name="GTD" description="Global Time Discontinuity" start="8" size="1" />
+      <BitField name="GTE" description="Global Time Error" start="9" size="1" />
+      <BitField name="TXU" description="Tx Count Underflow" start="10" size="1" />
+      <BitField name="TXO" description="Tx Count Overflow" start="11" size="1" />
+      <BitField name="SE1" description="Scheduling Error 1" start="12" size="1" />
+      <BitField name="SE2" description="Scheduling Error 2" start="13" size="1" />
+      <BitField name="ELC" description="Error Level Changed." start="14" size="1" />
+      <BitField name="IWTG" description="Initialization Watch Trigger" start="15" size="1" />
+      <BitField name="WT" description="Watch Trigger" start="16" size="1" />
+      <BitField name="AW" description="Application Watchdog" start="17" size="1" />
+      <BitField name="CER" description="Configuration Error" start="18" size="1" />
+    </Register>
+    <Register name="FDCAN_TTIE" description="FDCAN TT Interrupt Enable Register" start="+0x124" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SBCE" description="Start of Basic Cycle Interrupt Enable" start="0" size="1" />
+      <BitField name="SMCE" description="Start of Matrix Cycle Interrupt Enable" start="1" size="1" />
+      <BitField name="CSME" description="Change of Synchronization Mode Interrupt Enable" start="2" size="1" />
+      <BitField name="SOGE" description="Start of Gap Interrupt Enable" start="3" size="1" />
+      <BitField name="RTMIE" description="Register Time Mark Interrupt Enable" start="4" size="1" />
+      <BitField name="TTMIE" description="Trigger Time Mark Event Internal Interrupt Enable" start="5" size="1" />
+      <BitField name="SWEE" description="Stop Watch Event Interrupt Enable" start="6" size="1" />
+      <BitField name="GTWE" description="Global Time Wrap Interrupt Enable" start="7" size="1" />
+      <BitField name="GTDE" description="Global Time Discontinuity Interrupt Enable" start="8" size="1" />
+      <BitField name="GTEE" description="Global Time Error Interrupt Enable" start="9" size="1" />
+      <BitField name="TXUE" description="Tx Count Underflow Interrupt Enable" start="10" size="1" />
+      <BitField name="TXOE" description="Tx Count Overflow Interrupt Enable" start="11" size="1" />
+      <BitField name="SE1E" description="Scheduling Error 1 Interrupt Enable" start="12" size="1" />
+      <BitField name="SE2E" description="Scheduling Error 2 Interrupt Enable" start="13" size="1" />
+      <BitField name="ELCE" description="Change Error Level Interrupt Enable" start="14" size="1" />
+      <BitField name="IWTGE" description="Initialization Watch Trigger Interrupt Enable" start="15" size="1" />
+      <BitField name="WTE" description="Watch Trigger Interrupt Enable" start="16" size="1" />
+      <BitField name="AWE" description="Application Watchdog Interrupt Enable" start="17" size="1" />
+      <BitField name="CERE" description="Configuration Error Interrupt Enable" start="18" size="1" />
+    </Register>
+    <Register name="FDCAN_TTILS" description="FDCAN TT Interrupt Line Select Register" start="+0x128" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SBCL" description="Start of Basic Cycle Interrupt Line" start="0" size="1" />
+      <BitField name="SMCL" description="Start of Matrix Cycle Interrupt Line" start="1" size="1" />
+      <BitField name="CSML" description="Change of Synchronization Mode Interrupt Line" start="2" size="1" />
+      <BitField name="SOGL" description="Start of Gap Interrupt Line" start="3" size="1" />
+      <BitField name="RTMIL" description="Register Time Mark Interrupt Line" start="4" size="1" />
+      <BitField name="TTMIL" description="Trigger Time Mark Event Internal Interrupt Line" start="5" size="1" />
+      <BitField name="SWEL" description="Stop Watch Event Interrupt Line" start="6" size="1" />
+      <BitField name="GTWL" description="Global Time Wrap Interrupt Line" start="7" size="1" />
+      <BitField name="GTDL" description="Global Time Discontinuity Interrupt Line" start="8" size="1" />
+      <BitField name="GTEL" description="Global Time Error Interrupt Line" start="9" size="1" />
+      <BitField name="TXUL" description="Tx Count Underflow Interrupt Line" start="10" size="1" />
+      <BitField name="TXOL" description="Tx Count Overflow Interrupt Line" start="11" size="1" />
+      <BitField name="SE1L" description="Scheduling Error 1 Interrupt Line" start="12" size="1" />
+      <BitField name="SE2L" description="Scheduling Error 2 Interrupt Line" start="13" size="1" />
+      <BitField name="ELCL" description="Change Error Level Interrupt Line" start="14" size="1" />
+      <BitField name="IWTGL" description="Initialization Watch Trigger Interrupt Line" start="15" size="1" />
+      <BitField name="WTL" description="Watch Trigger Interrupt Line" start="16" size="1" />
+      <BitField name="AWL" description="Application Watchdog Interrupt Line" start="17" size="1" />
+      <BitField name="CERL" description="Configuration Error Interrupt Line" start="18" size="1" />
+    </Register>
+    <Register name="FDCAN_TTOST" description="FDCAN TT Operation Status Register" start="+0x12C" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EL" description="Error Level" start="0" size="2" />
+      <BitField name="MS" description="Master State." start="2" size="2" />
+      <BitField name="SYS" description="Synchronization State" start="4" size="2" />
+      <BitField name="GTP" description="Quality of Global Time Phase" start="6" size="1" />
+      <BitField name="QCS" description="Quality of Clock Speed" start="7" size="1" />
+      <BitField name="RTO" description="Reference Trigger Offset" start="8" size="8" />
+      <BitField name="WGTD" description="Wait for Global Time Discontinuity" start="22" size="1" />
+      <BitField name="GFI" description="Gap Finished Indicator." start="23" size="1" />
+      <BitField name="TMP" description="Time Master Priority" start="24" size="3" />
+      <BitField name="GSI" description="Gap Started Indicator." start="27" size="1" />
+      <BitField name="WFE" description="Wait for Event" start="28" size="1" />
+      <BitField name="AWE" description="Application Watchdog Event" start="29" size="1" />
+      <BitField name="WECS" description="Wait for External Clock Synchronization" start="30" size="1" />
+      <BitField name="SPL" description="Schedule Phase Lock" start="31" size="1" />
+    </Register>
+    <Register name="FDCAN_TURNA" description="FDCAN TUR Numerator Actual Register" start="+0x130" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="NAV" description="Numerator Actual Value" start="0" size="18" />
+    </Register>
+    <Register name="FDCAN_TTLGT" description="FDCAN TT Local and Global Time Register" start="+0x134" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LT" description="Local Time" start="0" size="16" />
+      <BitField name="GT" description="Global Time" start="16" size="16" />
+    </Register>
+    <Register name="FDCAN_TTCTC" description="FDCAN TT Cycle Time and Count Register" start="+0x138" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CT" description="Cycle Time" start="0" size="16" />
+      <BitField name="CC" description="Cycle Count" start="16" size="6" />
+    </Register>
+    <Register name="FDCAN_TTCPT" description="FDCAN TT Capture Time Register" start="+0x13C" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CT" description="Cycle Count Value" start="0" size="6" />
+      <BitField name="SWV" description="Stop Watch Value" start="16" size="16" />
+    </Register>
+    <Register name="FDCAN_TTCSM" description="FDCAN TT Cycle Sync Mark Register" start="+0x140" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CSM" description="Cycle Sync Mark" start="0" size="16" />
+    </Register>
+    <Register name="FDCAN_TTTS" description="FDCAN TT Trigger Select Register" start="+0x300" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWTDEL" description="Stop watch trigger input selection" start="0" size="2" />
+      <BitField name="EVTSEL" description="Event trigger input selection" start="4" size="2" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="FMAC" description="FMAC register block" start="0x48024000">
+    <Register name="FMAC_X1BUFCFG" description="FMAC X1 buffer configuration register " start="+0x0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="X1_BASE" description="Base address of X1 buffer" start="0" size="8" access="Read/Write" />
+      <BitField name="X1_BUF_SIZE" description="Allocated size of X1 buffer in 16-bit words The minimum buffer size is the number of feed-forward taps in the filter (+ the watermark threshold - 1)." start="8" size="8" access="Read/Write" />
+      <BitField name="FULL_WM" description="Watermark for buffer full flag Defines the threshold for setting the X1 buffer full flag when operating in circular mode. The flag is set if the number of free spaces in the buffer is less than 2FULL_WM. 2: Threshold = 4 3: Threshold = 8 Setting a threshold greater than 1 allows several data to be transferred into the buffer under one interrupt. Threshold should be set to 1 if DMA write requests are enabled (DMAWEN = 1 in FMAC_CR register)." start="24" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Threshold = 1" start="0x0" />
+        <Enum name="B_0x1" description="Threshold = 2" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="FMAC_X2BUFCFG" description="FMAC X2 buffer configuration register " start="+0x4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="X2_BASE" description="Base address of X2 buffer The X2 buffer base address can be modified while START=1, for example to change coefficient values. The filter should be stalled when doing this, since changing the coefficients while a calculation is ongoing affects the result." start="0" size="8" access="Read/Write" />
+      <BitField name="X2_BUF_SIZE" description="Size of X2 buffer in 16-bit words This bitfield can not be modified when a function is ongoing (START = 1)." start="8" size="8" access="Read/Write" />
+    </Register>
+    <Register name="FMAC_YBUFCFG" description="FMAC Y buffer configuration register " start="+0x8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="Y_BASE" description="Base address of Y buffer" start="0" size="8" access="Read/Write" />
+      <BitField name="Y_BUF_SIZE" description="Size of Y buffer in 16-bit words For FIR filters, the minimum buffer size is 1 (+ the watermark threshold). For IIR filters the minimum buffer size is the number of feedback taps (+ the watermark threshold)." start="8" size="8" access="Read/Write" />
+      <BitField name="EMPTY_WM" description="Watermark for buffer empty flag Defines the threshold for setting the Y buffer empty flag when operating in circular mode. The flag is set if the number of unread values in the buffer is less than 2EMPTY_WM. 2: Threshold = 4 3: Threshold = 8 Setting a threshold greater than 1 allows several data to be transferred from the buffer under one interrupt. Threshold should be set to 1 if DMA read requests are enabled (DMAREN = 1 in FMAC_CR register)." start="24" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Threshold = 1" start="0x0" />
+        <Enum name="B_0x1" description="Threshold = 2" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="FMAC_PARAM" description="FMAC parameter register " start="+0xc" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="P" description="Input parameter P. The value of this parameter is dependent on the function This bitfield can not be modified when a function is ongoing (START = 1)" start="0" size="8" access="Read/Write" />
+      <BitField name="Q" description="Input parameter Q. The value of this parameter is dependent on the function. This bitfield can not be modified when a function is ongoing (START = 1)" start="8" size="8" access="Read/Write" />
+      <BitField name="R" description="Input parameter R. The value of this parameter is dependent on the function. This bitfield can not be modified when a function is ongoing (START = 1)" start="16" size="8" access="Read/Write" />
+      <BitField name="FUNC" description="Function 2: Load X2 buffer 3: Load Y buffer 4 to 7: Reserved 8: Convolution (FIR filter) 9: IIR filter (direct form 1) This bitfield can not be modified when a function is ongoing (START = 1)" start="24" size="7" access="Read/Write">
+        <Enum name="B_0x1" description="Load X1 buffer" start="0x1" />
+      </BitField>
+      <BitField name="START" description="Enable execution Setting this bit triggers the execution of the function selected in the FUNC bitfield. Resetting it by software stops any ongoing function. For initialization functions, this bit is reset by hardware." start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Stop execution" start="0x0" />
+        <Enum name="B_0x1" description="Start execution" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="FMAC_CR" description="FMAC control register " start="+0x10" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RIEN" description="Enable read interrupt This bit is set and cleared by software. A read returns the current state of the bit." start="0" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Disabled. No read interrupt requests are generated." start="0x0" />
+        <Enum name="B_0x1" description="Enabled. An interrupt request is generated while the Y buffer EMPTY flag is not set." start="0x1" />
+      </BitField>
+      <BitField name="WIEN" description="Enable write interrupt This bit is set and cleared by software. A read returns the current state of the bit." start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Disabled. No write interrupt requests are generated." start="0x0" />
+        <Enum name="B_0x1" description="Enabled. An interrupt request is generated while the X1 buffer FULL flag is not set. " start="0x1" />
+      </BitField>
+      <BitField name="OVFLIEN" description="Enable overflow error interrupts This bit is set and cleared by software. A read returns the current state of the bit." start="2" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Disabled. No interrupts are generated upon overflow detection." start="0x0" />
+        <Enum name="B_0x1" description="Enabled. An interrupt request is generated if the OVFL flag is set" start="0x1" />
+      </BitField>
+      <BitField name="UNFLIEN" description="Enable underflow error interrupts This bit is set and cleared by software. A read returns the current state of the bit." start="3" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Disabled. No interrupts are generated upon underflow detection." start="0x0" />
+        <Enum name="B_0x1" description="Enabled. An interrupt request is generated if the UNFL flag is set" start="0x1" />
+      </BitField>
+      <BitField name="SATIEN" description="Enable saturation error interrupts This bit is set and cleared by software. A read returns the current state of the bit." start="4" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Disabled. No interrupts are generated upon saturation detection." start="0x0" />
+        <Enum name="B_0x1" description="Enabled. An interrupt request is generated if the SAT flag is set" start="0x1" />
+      </BitField>
+      <BitField name="DMAREN" description="Enable DMA read channel requests This bit can only be modified when START= 0 in the FMAC_PARAM register. A read returns the current state of the bit." start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Disable. No DMA requests are generated" start="0x0" />
+        <Enum name="B_0x1" description="Enable. DMA requests are generated while the Y buffer is not empty." start="0x1" />
+      </BitField>
+      <BitField name="DMAWEN" description="Enable DMA write channel requests This bit can only be modified when START= 0 in the FMAC_PARAM register. A read returns the current state of the bit." start="9" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Disable. No DMA requests are generated" start="0x0" />
+        <Enum name="B_0x1" description="Enable. DMA requests are generated while the X1 buffer is not full." start="0x1" />
+      </BitField>
+      <BitField name="CLIPEN" description="Enable clipping" start="15" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Clipping disabled. Values at the output of the accumulator which exceed the q1.15 range, wrap." start="0x0" />
+        <Enum name="B_0x1" description="Clipping enabled. Values at the output of the accumulator which exceed the q1.15 range are saturated to the maximum positive or negative value (+1 or -1) according to the sign." start="0x1" />
+      </BitField>
+      <BitField name="RESET" description="Reset FMAC unit This resets the write and read pointers, the internal control logic, the FMAC_SR register and the FMAC_PARAM register, including the START bit if active. Other register settings are not affected. This bit is reset by hardware." start="16" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Reset inactive" start="0x0" />
+        <Enum name="B_0x1" description="Reset active" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="FMAC_SR" description="FMAC status register " start="+0x14" size="4" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField name="YEMPTY" description="Y buffer empty flag The buffer is flagged as empty if the number of unread data is less than the EMPTY_WM threshold. The number of unread data is the difference between the read pointer and the current output destination address. This flag is set and cleared by hardware, or by a reset. Note: after the last sample is read from the Y buffer there is a delay of 3 clock cycles before the YEMPTY flag goes high. To avoid any risk of underflow it is recommended to insert a software delay after reading from the Y buffer before reading the FMAC_SR. Alternatively, an EMPTY_WM threshold of 2 can be used." start="0" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="Y buffer not empty. If the RIEN bit is set, the interrupt request is asserted until the flag is set. If DMAREN is set, DMA read channel requests are generated until the flag is set." start="0x0" />
+        <Enum name="B_0x1" description="Y buffer empty." start="0x1" />
+      </BitField>
+      <BitField name="X1FULL" description="X1 buffer full flag The buffer is flagged as full if the number of available spaces is less than the FULL_WM threshold. The number of available spaces is the difference between the write pointer and the least recent sample currently in use. This flag is set and cleared by hardware, or by a reset. Note: after the last available space in the X1 buffer is filled there is a delay of 3 clock cycles before the X1FULL flag goes high. To avoid any risk of overflow it is recommended to insert a software delay after writing to the X1 buffer before reading the FMAC_SR. Alternatively, a FULL_WM threshold of 2 can be used." start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="X1 buffer not full. If the WIEN bit is set, the interrupt request is asserted until the flag is set. If DMAWEN is set, DMA write channel requests are generated until the flag is set." start="0x0" />
+        <Enum name="B_0x1" description="X1 buffer full." start="0x1" />
+      </BitField>
+      <BitField name="OVFL" description="Overflow error flag An overflow occurs when a write is made to FMAC_WDATA when no free space is available in the X1 buffer. This flag is cleared by a reset of the unit." start="8" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No overflow detected" start="0x0" />
+        <Enum name="B_0x1" description="Overflow detected. If the OVFLIEN bit is set, an interrupt is generated." start="0x1" />
+      </BitField>
+      <BitField name="UNFL" description="Underflow error flag An underflow occurs when a read is made from FMAC_RDATA when no valid data is available in the Y buffer. This flag is cleared by a reset of the unit." start="9" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No underflow detected" start="0x0" />
+        <Enum name="B_0x1" description="Underflow detected. If the UNFLIEN bit is set, an interrupt is generated." start="0x1" />
+      </BitField>
+      <BitField name="SAT" description="Saturation error flag Saturation occurs when the result of an accumulation exceeds the numeric range of the accumulator. This flag is cleared by a reset of the unit." start="10" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No saturation detected" start="0x0" />
+        <Enum name="B_0x1" description="Saturation detected. If the SATIEN bit is set, an interrupt is generated." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="FMAC_WDATA" description="FMAC write data register " start="+0x18" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="WDATA" description="Write data When a write access to this register occurs, the write data are transferred to the address offset indicated by the write pointer. The pointer address is automatically incremented after each write access." start="0" size="16" access="WriteOnly" />
+    </Register>
+    <Register name="FMAC_RDATA" description="FMAC read data register " start="+0x1c" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RDATA" description="Read data When a read access to this register occurs, the read data are the contents of the Y output buffer at the address offset indicated by the READ pointer. The pointer address is automatically incremented after each read access." start="0" size="16" access="ReadOnly" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="FMC" description="FMC" start="0x52004000">
+    <Register name="BCR1" description="This register contains the control information of each memory bank, used for SRAMs, PSRAM and NOR Flash memories." start="+0x0" size="4" access="Read/Write" reset_value="0x000030DB" reset_mask="0xFFFFFFFF">
+      <BitField name="MBKEN" description="Memory bank enable bit This bit enables the memory bank. After reset Bank1 is enabled, all others are disabled. Accessing a disabled bank causes an ERROR on AXI bus." start="0" size="1" />
+      <BitField name="MUXEN" description="Address/data multiplexing enable bit When this bit is set, the address and data values are multiplexed on the data bus, valid only with NOR and PSRAM memories:" start="1" size="1" />
+      <BitField name="MTYP" description="Memory type These bits define the type of external memory attached to the corresponding memory bank:" start="2" size="2" />
+      <BitField name="MWID" description="Memory data bus width Defines the external memory device width, valid for all type of memories." start="4" size="2" />
+      <BitField name="FACCEN" description="Flash access enable This bit enables NOR Flash memory access operations." start="6" size="1" />
+      <BitField name="BURSTEN" description="Burst enable bit This bit enables/disables synchronous accesses during read operations. It is valid only for synchronous memories operating in Burst mode:" start="8" size="1" />
+      <BitField name="WAITPOL" description="Wait signal polarity bit This bit defines the polarity of the wait signal from memory used for either in synchronous or asynchronous mode:" start="9" size="1" />
+      <BitField name="WAITCFG" description="Wait timing configuration The NWAIT signal indicates whether the data from the memory are valid or if a wait state must be inserted when accessing the memory in synchronous mode. This configuration bit determines if NWAIT is asserted by the memory one clock cycle before the wait state or during the wait state:" start="11" size="1" />
+      <BitField name="WREN" description="Write enable bit This bit indicates whether write operations are enabled/disabled in the bank by the FMC:" start="12" size="1" />
+      <BitField name="WAITEN" description="Wait enable bit This bit enables/disables wait-state insertion via the NWAIT signal when accessing the memory in synchronous mode." start="13" size="1" />
+      <BitField name="EXTMOD" description="Extended mode enable. This bit enables the FMC to program the write timings for asynchronous accesses inside the FMC_BWTR register, thus resulting in different timings for read and write operations. Note: When the extended mode is disabled, the FMC can operate in Mode1 or Mode2 as follows: ** Mode 1 is the default mode when the SRAM/PSRAM memory type is selected (MTYP =0x0 or 0x01) ** Mode 2 is the default mode when the NOR memory type is selected (MTYP = 0x10)." start="14" size="1" />
+      <BitField name="ASYNCWAIT" description="Wait signal during asynchronous transfers This bit enables/disables the FMC to use the wait signal even during an asynchronous protocol." start="15" size="1" />
+      <BitField name="CPSIZE" description="CRAM Page Size These are used for Cellular RAM 1.5 which does not allow burst access to cross the address boundaries between pages. When these bits are configured, the FMC controller splits automatically the burst access when the memory page size is reached (refer to memory datasheet for page size). Other configuration: reserved." start="16" size="3" />
+      <BitField name="CBURSTRW" description="Write burst enable For PSRAM (CRAM) operating in Burst mode, the bit enables synchronous accesses during write operations. The enable bit for synchronous read accesses is the BURSTEN bit in the FMC_BCRx register." start="19" size="1" />
+      <BitField name="CCLKEN" description="Continuous Clock Enable This bit enables the FMC_CLK clock output to external memory devices. Note: The CCLKEN bit of the FMC_BCR2..4 registers is dont care. It is only enabled through the FMC_BCR1 register. Bank 1 must be configured in synchronous mode to generate the FMC_CLK continuous clock. If CCLKEN bit is set, the FMC_CLK clock ratio is specified by CLKDIV value in the FMC_BTR1 register. CLKDIV in FMC_BWTR1 is dont care. If the synchronous mode is used and CCLKEN bit is set, the synchronous memories connected to other banks than Bank 1 are clocked by the same clock (the CLKDIV value in the FMC_BTR2..4 and FMC_BWTR2..4 registers for other banks has no effect.)" start="20" size="1" />
+      <BitField name="WFDIS" description="Write FIFO Disable This bit disables the Write FIFO used by the FMC controller. Note: The WFDIS bit of the FMC_BCR2..4 registers is dont care. It is only enabled through the FMC_BCR1 register." start="21" size="1" />
+      <BitField name="BMAP" description="FMC bank mapping These bits allows different to remap SDRAM bank2 or swap the FMC NOR/PSRAM and SDRAM banks.Refer to Table 10 for Note: The BMAP bits of the FMC_BCR2..4 registers are dont care. It is only enabled through the FMC_BCR1 register." start="24" size="2" />
+      <BitField name="FMCEN" description="FMC controller Enable This bit enables/disables the FMC controller. Note: The FMCEN bit of the FMC_BCR2..4 registers is dont care. It is only enabled through the FMC_BCR1 register." start="31" size="1" />
+    </Register>
+    <Register name="BTR1" description="This register contains the control information of each memory bank, used for SRAMs, PSRAM and NOR Flash memories.If the EXTMOD bit is set in the FMC_BCRx register, then this register is partitioned for write and read access, that is, 2 registers are available: one to configure read accesses (this register) and one to configure write accesses (FMC_BWTRx registers)." start="+0x4" size="4" access="Read/Write" reset_value="0x0FFFFFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="ADDSET" description="Address setup phase duration These bits are written by software to define the duration of the address setup phase (refer to Figure81 to Figure93), used in SRAMs, ROMs and asynchronous NOR Flash: For each access mode address setup phase duration, please refer to the respective figure (refer to Figure81 to Figure93). Note: In synchronous accesses, this value is dont care. In Muxed mode or Mode D, the minimum value for ADDSET is 1." start="0" size="4" />
+      <BitField name="ADDHLD" description="Address-hold phase duration These bits are written by software to define the duration of the address hold phase (refer to Figure81 to Figure93), used in mode D or multiplexed accesses: For each access mode address-hold phase duration, please refer to the respective figure (Figure81 to Figure93). Note: In synchronous accesses, this value is not used, the address hold phase is always 1 memory clock period duration." start="4" size="4" />
+      <BitField name="DATAST" description="Data-phase duration These bits are written by software to define the duration of the data phase (refer to Figure81 to Figure93), used in asynchronous accesses: For each memory type and access mode data-phase duration, please refer to the respective figure (Figure81 to Figure93). Example: Mode1, write access, DATAST=1: Data-phase duration= DATAST+1 = 2 KCK_FMC clock cycles. Note: In synchronous accesses, this value is dont care." start="8" size="8" />
+      <BitField name="BUSTURN" description="Bus turnaround phase duration These bits are written by software to add a delay at the end of a write-to-read or read-to write transaction. The programmed bus turnaround delay is inserted between an asynchronous read (in muxed or mode D) or write transaction and any other asynchronous /synchronous read/write from/to a static bank. If a read operation is performed, the bank can be the same or a different one, whereas it must be different in case of write operation to the bank, except in muxed mode or mode D. In some cases, whatever the programmed BUSTRUN values, the bus turnaround delay is fixed as follows: The bus turnaround delay is not inserted between two consecutive asynchronous write transfers to the same static memory bank except in muxed mode and mode D. There is a bus turnaround delay of 1 FMC clock cycle between: Two consecutive asynchronous read transfers to the same static memory bank except for modes muxed and D. An asynchronous read to an asynchronous or synchronous write to any static bank or dynamic bank except in modes muxed and D mode. There is a bus turnaround delay of 2 FMC clock cycle between: Two consecutive synchronous write operations (in Burst or Single mode) to the same bank. A synchronous write (burst or single) access and an asynchronous write or read transfer to or from static memory bank (the bank can be the same or a different one in case of a read operation. Two consecutive synchronous read operations (in Burst or Single mode) followed by any synchronous/asynchronous read or write from/to another static memory bank. There is a bus turnaround delay of 3 FMC clock cycle between: Two consecutive synchronous write operations (in Burst or Single mode) to different static banks. A synchronous write access (in Burst or Single mode) and a synchronous read from the same or a different bank. The bus turnaround delay allows to match the minimum time between consecutive transactions (tEHEL from NEx high to NEx low) and the maximum time required by the memory to free the data bus after a read access (tEHQZ): (BUSTRUN + 1) KCK_FMC period &amp;#8805; tEHELmin and (BUSTRUN + 2)KCK_FMC period &amp;#8805; tEHQZmax if EXTMOD = 0 (BUSTRUN + 2)KCK_FMC period &amp;#8805; max (tEHELmin, tEHQZmax) if EXTMOD = 126. ..." start="16" size="4" />
+      <BitField name="CLKDIV" description="Clock divide ratio (for FMC_CLK signal) These bits define the period of FMC_CLK clock output signal, expressed in number of KCK_FMC cycles: In asynchronous NOR Flash, SRAM or PSRAM accesses, this value is dont care. Note: Refer to Section20.6.5: Synchronous transactions for FMC_CLK divider ratio formula)" start="20" size="4" />
+      <BitField name="DATLAT" description="Data latency for synchronous memory For synchronous access with read write burst mode enabled these bits define the number of memory clock cycles" start="24" size="4" />
+      <BitField name="ACCMOD" description="Access mode These bits specify the asynchronous access modes as shown in the timing diagrams. They are taken into account only when the EXTMOD bit in the FMC_BCRx register is 1." start="28" size="2" />
+    </Register>
+    <Register name="BCR2" description="This register contains the control information of each memory bank, used for SRAMs, PSRAM and NOR Flash memories." start="+0x8" size="4" access="Read/Write" reset_value="0x000030D2" reset_mask="0xFFFFFFFF">
+      <BitField name="MBKEN" description="Memory bank enable bit This bit enables the memory bank. After reset Bank1 is enabled, all others are disabled. Accessing a disabled bank causes an ERROR on AXI bus." start="0" size="1" />
+      <BitField name="MUXEN" description="Address/data multiplexing enable bit When this bit is set, the address and data values are multiplexed on the data bus, valid only with NOR and PSRAM memories:" start="1" size="1" />
+      <BitField name="MTYP" description="Memory type These bits define the type of external memory attached to the corresponding memory bank:" start="2" size="2" />
+      <BitField name="MWID" description="Memory data bus width Defines the external memory device width, valid for all type of memories." start="4" size="2" />
+      <BitField name="FACCEN" description="Flash access enable This bit enables NOR Flash memory access operations." start="6" size="1" />
+      <BitField name="BURSTEN" description="Burst enable bit This bit enables/disables synchronous accesses during read operations. It is valid only for synchronous memories operating in Burst mode:" start="8" size="1" />
+      <BitField name="WAITPOL" description="Wait signal polarity bit This bit defines the polarity of the wait signal from memory used for either in synchronous or asynchronous mode:" start="9" size="1" />
+      <BitField name="WAITCFG" description="Wait timing configuration The NWAIT signal indicates whether the data from the memory are valid or if a wait state must be inserted when accessing the memory in synchronous mode. This configuration bit determines if NWAIT is asserted by the memory one clock cycle before the wait state or during the wait state:" start="11" size="1" />
+      <BitField name="WREN" description="Write enable bit This bit indicates whether write operations are enabled/disabled in the bank by the FMC:" start="12" size="1" />
+      <BitField name="WAITEN" description="Wait enable bit This bit enables/disables wait-state insertion via the NWAIT signal when accessing the memory in synchronous mode." start="13" size="1" />
+      <BitField name="EXTMOD" description="Extended mode enable. This bit enables the FMC to program the write timings for asynchronous accesses inside the FMC_BWTR register, thus resulting in different timings for read and write operations. Note: When the extended mode is disabled, the FMC can operate in Mode1 or Mode2 as follows: ** Mode 1 is the default mode when the SRAM/PSRAM memory type is selected (MTYP =0x0 or 0x01) ** Mode 2 is the default mode when the NOR memory type is selected (MTYP = 0x10)." start="14" size="1" />
+      <BitField name="ASYNCWAIT" description="Wait signal during asynchronous transfers This bit enables/disables the FMC to use the wait signal even during an asynchronous protocol." start="15" size="1" />
+      <BitField name="CPSIZE" description="CRAM Page Size These are used for Cellular RAM 1.5 which does not allow burst access to cross the address boundaries between pages. When these bits are configured, the FMC controller splits automatically the burst access when the memory page size is reached (refer to memory datasheet for page size). Other configuration: reserved." start="16" size="3" />
+      <BitField name="CBURSTRW" description="Write burst enable For PSRAM (CRAM) operating in Burst mode, the bit enables synchronous accesses during write operations. The enable bit for synchronous read accesses is the BURSTEN bit in the FMC_BCRx register." start="19" size="1" />
+      <BitField name="CCLKEN" description="Continuous Clock Enable This bit enables the FMC_CLK clock output to external memory devices. Note: The CCLKEN bit of the FMC_BCR2..4 registers is dont care. It is only enabled through the FMC_BCR1 register. Bank 1 must be configured in synchronous mode to generate the FMC_CLK continuous clock. If CCLKEN bit is set, the FMC_CLK clock ratio is specified by CLKDIV value in the FMC_BTR1 register. CLKDIV in FMC_BWTR1 is dont care. If the synchronous mode is used and CCLKEN bit is set, the synchronous memories connected to other banks than Bank 1 are clocked by the same clock (the CLKDIV value in the FMC_BTR2..4 and FMC_BWTR2..4 registers for other banks has no effect.)" start="20" size="1" />
+      <BitField name="WFDIS" description="Write FIFO Disable This bit disables the Write FIFO used by the FMC controller. Note: The WFDIS bit of the FMC_BCR2..4 registers is dont care. It is only enabled through the FMC_BCR1 register." start="21" size="1" />
+      <BitField name="BMAP" description="FMC bank mapping These bits allows different to remap SDRAM bank2 or swap the FMC NOR/PSRAM and SDRAM banks.Refer to Table 10 for Note: The BMAP bits of the FMC_BCR2..4 registers are dont care. It is only enabled through the FMC_BCR1 register." start="24" size="2" />
+      <BitField name="FMCEN" description="FMC controller Enable This bit enables/disables the FMC controller. Note: The FMCEN bit of the FMC_BCR2..4 registers is dont care. It is only enabled through the FMC_BCR1 register." start="31" size="1" />
+    </Register>
+    <Register name="BTR2" description="This register contains the control information of each memory bank, used for SRAMs, PSRAM and NOR Flash memories.If the EXTMOD bit is set in the FMC_BCRx register, then this register is partitioned for write and read access, that is, 2 registers are available: one to configure read accesses (this register) and one to configure write accesses (FMC_BWTRx registers)." start="+0xC" size="4" access="Read/Write" reset_value="0x0FFFFFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="ADDSET" description="Address setup phase duration These bits are written by software to define the duration of the address setup phase (refer to Figure81 to Figure93), used in SRAMs, ROMs and asynchronous NOR Flash: For each access mode address setup phase duration, please refer to the respective figure (refer to Figure81 to Figure93). Note: In synchronous accesses, this value is dont care. In Muxed mode or Mode D, the minimum value for ADDSET is 1." start="0" size="4" />
+      <BitField name="ADDHLD" description="Address-hold phase duration These bits are written by software to define the duration of the address hold phase (refer to Figure81 to Figure93), used in mode D or multiplexed accesses: For each access mode address-hold phase duration, please refer to the respective figure (Figure81 to Figure93). Note: In synchronous accesses, this value is not used, the address hold phase is always 1 memory clock period duration." start="4" size="4" />
+      <BitField name="DATAST" description="Data-phase duration These bits are written by software to define the duration of the data phase (refer to Figure81 to Figure93), used in asynchronous accesses: For each memory type and access mode data-phase duration, please refer to the respective figure (Figure81 to Figure93). Example: Mode1, write access, DATAST=1: Data-phase duration= DATAST+1 = 2 KCK_FMC clock cycles. Note: In synchronous accesses, this value is dont care." start="8" size="8" />
+      <BitField name="BUSTURN" description="Bus turnaround phase duration These bits are written by software to add a delay at the end of a write-to-read or read-to write transaction. The programmed bus turnaround delay is inserted between an asynchronous read (in muxed or mode D) or write transaction and any other asynchronous /synchronous read/write from/to a static bank. If a read operation is performed, the bank can be the same or a different one, whereas it must be different in case of write operation to the bank, except in muxed mode or mode D. In some cases, whatever the programmed BUSTRUN values, the bus turnaround delay is fixed as follows: The bus turnaround delay is not inserted between two consecutive asynchronous write transfers to the same static memory bank except in muxed mode and mode D. There is a bus turnaround delay of 1 FMC clock cycle between: Two consecutive asynchronous read transfers to the same static memory bank except for modes muxed and D. An asynchronous read to an asynchronous or synchronous write to any static bank or dynamic bank except in modes muxed and D mode. There is a bus turnaround delay of 2 FMC clock cycle between: Two consecutive synchronous write operations (in Burst or Single mode) to the same bank. A synchronous write (burst or single) access and an asynchronous write or read transfer to or from static memory bank (the bank can be the same or a different one in case of a read operation. Two consecutive synchronous read operations (in Burst or Single mode) followed by any synchronous/asynchronous read or write from/to another static memory bank. There is a bus turnaround delay of 3 FMC clock cycle between: Two consecutive synchronous write operations (in Burst or Single mode) to different static banks. A synchronous write access (in Burst or Single mode) and a synchronous read from the same or a different bank. The bus turnaround delay allows to match the minimum time between consecutive transactions (tEHEL from NEx high to NEx low) and the maximum time required by the memory to free the data bus after a read access (tEHQZ): (BUSTRUN + 1) KCK_FMC period &amp;#8805; tEHELmin and (BUSTRUN + 2)KCK_FMC period &amp;#8805; tEHQZmax if EXTMOD = 0 (BUSTRUN + 2)KCK_FMC period &amp;#8805; max (tEHELmin, tEHQZmax) if EXTMOD = 1. ..." start="16" size="4" />
+      <BitField name="CLKDIV" description="Clock divide ratio (for FMC_CLK signal) These bits define the period of FMC_CLK clock output signal, expressed in number of KCK_FMC cycles: In asynchronous NOR Flash, SRAM or PSRAM accesses, this value is dont care. Note: Refer to Section20.6.5: Synchronous transactions for FMC_CLK divider ratio formula)" start="20" size="4" />
+      <BitField name="DATLAT" description="Data latency for synchronous memory For synchronous access with read write burst mode enabled these bits define the number of memory clock cycles" start="24" size="4" />
+      <BitField name="ACCMOD" description="Access mode These bits specify the asynchronous access modes as shown in the timing diagrams. They are taken into account only when the EXTMOD bit in the FMC_BCRx register is 1." start="28" size="2" />
+    </Register>
+    <Register name="BCR3" description="This register contains the control information of each memory bank, used for SRAMs, PSRAM and NOR Flash memories." start="+0x10" size="4" access="Read/Write" reset_value="0x000030D2" reset_mask="0xFFFFFFFF">
+      <BitField name="MBKEN" description="Memory bank enable bit This bit enables the memory bank. After reset Bank1 is enabled, all others are disabled. Accessing a disabled bank causes an ERROR on AXI bus." start="0" size="1" />
+      <BitField name="MUXEN" description="Address/data multiplexing enable bit When this bit is set, the address and data values are multiplexed on the data bus, valid only with NOR and PSRAM memories:" start="1" size="1" />
+      <BitField name="MTYP" description="Memory type These bits define the type of external memory attached to the corresponding memory bank:" start="2" size="2" />
+      <BitField name="MWID" description="Memory data bus width Defines the external memory device width, valid for all type of memories." start="4" size="2" />
+      <BitField name="FACCEN" description="Flash access enable This bit enables NOR Flash memory access operations." start="6" size="1" />
+      <BitField name="BURSTEN" description="Burst enable bit This bit enables/disables synchronous accesses during read operations. It is valid only for synchronous memories operating in Burst mode:" start="8" size="1" />
+      <BitField name="WAITPOL" description="Wait signal polarity bit This bit defines the polarity of the wait signal from memory used for either in synchronous or asynchronous mode:" start="9" size="1" />
+      <BitField name="WAITCFG" description="Wait timing configuration The NWAIT signal indicates whether the data from the memory are valid or if a wait state must be inserted when accessing the memory in synchronous mode. This configuration bit determines if NWAIT is asserted by the memory one clock cycle before the wait state or during the wait state:" start="11" size="1" />
+      <BitField name="WREN" description="Write enable bit This bit indicates whether write operations are enabled/disabled in the bank by the FMC:" start="12" size="1" />
+      <BitField name="WAITEN" description="Wait enable bit This bit enables/disables wait-state insertion via the NWAIT signal when accessing the memory in synchronous mode." start="13" size="1" />
+      <BitField name="EXTMOD" description="Extended mode enable. This bit enables the FMC to program the write timings for asynchronous accesses inside the FMC_BWTR register, thus resulting in different timings for read and write operations. Note: When the extended mode is disabled, the FMC can operate in Mode1 or Mode2 as follows: ** Mode 1 is the default mode when the SRAM/PSRAM memory type is selected (MTYP =0x0 or 0x01) ** Mode 2 is the default mode when the NOR memory type is selected (MTYP = 0x10)." start="14" size="1" />
+      <BitField name="ASYNCWAIT" description="Wait signal during asynchronous transfers This bit enables/disables the FMC to use the wait signal even during an asynchronous protocol." start="15" size="1" />
+      <BitField name="CPSIZE" description="CRAM Page Size These are used for Cellular RAM 1.5 which does not allow burst access to cross the address boundaries between pages. When these bits are configured, the FMC controller splits automatically the burst access when the memory page size is reached (refer to memory datasheet for page size). Other configuration: reserved." start="16" size="3" />
+      <BitField name="CBURSTRW" description="Write burst enable For PSRAM (CRAM) operating in Burst mode, the bit enables synchronous accesses during write operations. The enable bit for synchronous read accesses is the BURSTEN bit in the FMC_BCRx register." start="19" size="1" />
+      <BitField name="CCLKEN" description="Continuous Clock Enable This bit enables the FMC_CLK clock output to external memory devices. Note: The CCLKEN bit of the FMC_BCR2..4 registers is dont care. It is only enabled through the FMC_BCR1 register. Bank 1 must be configured in synchronous mode to generate the FMC_CLK continuous clock. If CCLKEN bit is set, the FMC_CLK clock ratio is specified by CLKDIV value in the FMC_BTR1 register. CLKDIV in FMC_BWTR1 is dont care. If the synchronous mode is used and CCLKEN bit is set, the synchronous memories connected to other banks than Bank 1 are clocked by the same clock (the CLKDIV value in the FMC_BTR2..4 and FMC_BWTR2..4 registers for other banks has no effect.)" start="20" size="1" />
+      <BitField name="WFDIS" description="Write FIFO Disable This bit disables the Write FIFO used by the FMC controller. Note: The WFDIS bit of the FMC_BCR2..4 registers is dont care. It is only enabled through the FMC_BCR1 register." start="21" size="1" />
+      <BitField name="BMAP" description="FMC bank mapping These bits allows different to remap SDRAM bank2 or swap the FMC NOR/PSRAM and SDRAM banks.Refer to Table 10 for Note: The BMAP bits of the FMC_BCR2..4 registers are dont care. It is only enabled through the FMC_BCR1 register." start="24" size="2" />
+      <BitField name="FMCEN" description="FMC controller Enable This bit enables/disables the FMC controller. Note: The FMCEN bit of the FMC_BCR2..4 registers is dont care. It is only enabled through the FMC_BCR1 register." start="31" size="1" />
+    </Register>
+    <Register name="BTR3" description="This register contains the control information of each memory bank, used for SRAMs, PSRAM and NOR Flash memories.If the EXTMOD bit is set in the FMC_BCRx register, then this register is partitioned for write and read access, that is, 2 registers are available: one to configure read accesses (this register) and one to configure write accesses (FMC_BWTRx registers)." start="+0x14" size="4" access="Read/Write" reset_value="0x0FFFFFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="ADDSET" description="Address setup phase duration These bits are written by software to define the duration of the address setup phase (refer to Figure81 to Figure93), used in SRAMs, ROMs and asynchronous NOR Flash: For each access mode address setup phase duration, please refer to the respective figure (refer to Figure81 to Figure93). Note: In synchronous accesses, this value is dont care. In Muxed mode or Mode D, the minimum value for ADDSET is 1." start="0" size="4" />
+      <BitField name="ADDHLD" description="Address-hold phase duration These bits are written by software to define the duration of the address hold phase (refer to Figure81 to Figure93), used in mode D or multiplexed accesses: For each access mode address-hold phase duration, please refer to the respective figure (Figure81 to Figure93). Note: In synchronous accesses, this value is not used, the address hold phase is always 1 memory clock period duration." start="4" size="4" />
+      <BitField name="DATAST" description="Data-phase duration These bits are written by software to define the duration of the data phase (refer to Figure81 to Figure93), used in asynchronous accesses: For each memory type and access mode data-phase duration, please refer to the respective figure (Figure81 to Figure93). Example: Mode1, write access, DATAST=1: Data-phase duration= DATAST+1 = 2 KCK_FMC clock cycles. Note: In synchronous accesses, this value is dont care." start="8" size="8" />
+      <BitField name="BUSTURN" description="Bus turnaround phase duration These bits are written by software to add a delay at the end of a write-to-read or read-to write transaction. The programmed bus turnaround delay is inserted between an asynchronous read (in muxed or mode D) or write transaction and any other asynchronous /synchronous read/write from/to a static bank. If a read operation is performed, the bank can be the same or a different one, whereas it must be different in case of write operation to the bank, except in muxed mode or mode D. In some cases, whatever the programmed BUSTRUN values, the bus turnaround delay is fixed as follows: The bus turnaround delay is not inserted between two consecutive asynchronous write transfers to the same static memory bank except in muxed mode and mode D. There is a bus turnaround delay of 1 FMC clock cycle between: Two consecutive asynchronous read transfers to the same static memory bank except for modes muxed and D. An asynchronous read to an asynchronous or synchronous write to any static bank or dynamic bank except in modes muxed and D mode. There is a bus turnaround delay of 2 FMC clock cycle between: Two consecutive synchronous write operations (in Burst or Single mode) to the same bank. A synchronous write (burst or single) access and an asynchronous write or read transfer to or from static memory bank (the bank can be the same or a different one in case of a read operation. Two consecutive synchronous read operations (in Burst or Single mode) followed by any synchronous/asynchronous read or write from/to another static memory bank. There is a bus turnaround delay of 3 FMC clock cycle between: Two consecutive synchronous write operations (in Burst or Single mode) to different static banks. A synchronous write access (in Burst or Single mode) and a synchronous read from the same or a different bank. The bus turnaround delay allows to match the minimum time between consecutive transactions (tEHEL from NEx high to NEx low) and the maximum time required by the memory to free the data bus after a read access (tEHQZ): (BUSTRUN + 1) KCK_FMC period &amp;#8805; tEHELmin and (BUSTRUN + 2)KCK_FMC period &amp;#8805; tEHQZmax if EXTMOD = 0 (BUSTRUN + 2)KCK_FMC period &amp;#8805; max (tEHELmin, tEHQZmax) if EXTMOD =1. ..." start="16" size="4" />
+      <BitField name="CLKDIV" description="Clock divide ratio (for FMC_CLK signal) These bits define the period of FMC_CLK clock output signal, expressed in number of KCK_FMC cycles: In asynchronous NOR Flash, SRAM or PSRAM accesses, this value is dont care. Note: Refer to Section20.6.5: Synchronous transactions for FMC_CLK divider ratio formula)" start="20" size="4" />
+      <BitField name="DATLAT" description="Data latency for synchronous memory For synchronous access with read write burst mode enabled these bits define the number of memory clock cycles" start="24" size="4" />
+      <BitField name="ACCMOD" description="Access mode These bits specify the asynchronous access modes as shown in the timing diagrams. They are taken into account only when the EXTMOD bit in the FMC_BCRx register is 1." start="28" size="2" />
+    </Register>
+    <Register name="BCR4" description="This register contains the control information of each memory bank, used for SRAMs, PSRAM and NOR Flash memories." start="+0x18" size="4" access="Read/Write" reset_value="0x000030D2" reset_mask="0xFFFFFFFF">
+      <BitField name="MBKEN" description="Memory bank enable bit This bit enables the memory bank. After reset Bank1 is enabled, all others are disabled. Accessing a disabled bank causes an ERROR on AXI bus." start="0" size="1" />
+      <BitField name="MUXEN" description="Address/data multiplexing enable bit When this bit is set, the address and data values are multiplexed on the data bus, valid only with NOR and PSRAM memories:" start="1" size="1" />
+      <BitField name="MTYP" description="Memory type These bits define the type of external memory attached to the corresponding memory bank:" start="2" size="2" />
+      <BitField name="MWID" description="Memory data bus width Defines the external memory device width, valid for all type of memories." start="4" size="2" />
+      <BitField name="FACCEN" description="Flash access enable This bit enables NOR Flash memory access operations." start="6" size="1" />
+      <BitField name="BURSTEN" description="Burst enable bit This bit enables/disables synchronous accesses during read operations. It is valid only for synchronous memories operating in Burst mode:" start="8" size="1" />
+      <BitField name="WAITPOL" description="Wait signal polarity bit This bit defines the polarity of the wait signal from memory used for either in synchronous or asynchronous mode:" start="9" size="1" />
+      <BitField name="WAITCFG" description="Wait timing configuration The NWAIT signal indicates whether the data from the memory are valid or if a wait state must be inserted when accessing the memory in synchronous mode. This configuration bit determines if NWAIT is asserted by the memory one clock cycle before the wait state or during the wait state:" start="11" size="1" />
+      <BitField name="WREN" description="Write enable bit This bit indicates whether write operations are enabled/disabled in the bank by the FMC:" start="12" size="1" />
+      <BitField name="WAITEN" description="Wait enable bit This bit enables/disables wait-state insertion via the NWAIT signal when accessing the memory in synchronous mode." start="13" size="1" />
+      <BitField name="EXTMOD" description="Extended mode enable. This bit enables the FMC to program the write timings for asynchronous accesses inside the FMC_BWTR register, thus resulting in different timings for read and write operations. Note: When the extended mode is disabled, the FMC can operate in Mode1 or Mode2 as follows: ** Mode 1 is the default mode when the SRAM/PSRAM memory type is selected (MTYP =0x0 or 0x01) ** Mode 2 is the default mode when the NOR memory type is selected (MTYP = 0x10)." start="14" size="1" />
+      <BitField name="ASYNCWAIT" description="Wait signal during asynchronous transfers This bit enables/disables the FMC to use the wait signal even during an asynchronous protocol." start="15" size="1" />
+      <BitField name="CPSIZE" description="CRAM Page Size These are used for Cellular RAM 1.5 which does not allow burst access to cross the address boundaries between pages. When these bits are configured, the FMC controller splits automatically the burst access when the memory page size is reached (refer to memory datasheet for page size). Other configuration: reserved." start="16" size="3" />
+      <BitField name="CBURSTRW" description="Write burst enable For PSRAM (CRAM) operating in Burst mode, the bit enables synchronous accesses during write operations. The enable bit for synchronous read accesses is the BURSTEN bit in the FMC_BCRx register." start="19" size="1" />
+      <BitField name="CCLKEN" description="Continuous Clock Enable This bit enables the FMC_CLK clock output to external memory devices. Note: The CCLKEN bit of the FMC_BCR2..4 registers is dont care. It is only enabled through the FMC_BCR1 register. Bank 1 must be configured in synchronous mode to generate the FMC_CLK continuous clock. If CCLKEN bit is set, the FMC_CLK clock ratio is specified by CLKDIV value in the FMC_BTR1 register. CLKDIV in FMC_BWTR1 is dont care. If the synchronous mode is used and CCLKEN bit is set, the synchronous memories connected to other banks than Bank 1 are clocked by the same clock (the CLKDIV value in the FMC_BTR2..4 and FMC_BWTR2..4 registers for other banks has no effect.)" start="20" size="1" />
+      <BitField name="WFDIS" description="Write FIFO Disable This bit disables the Write FIFO used by the FMC controller. Note: The WFDIS bit of the FMC_BCR2..4 registers is dont care. It is only enabled through the FMC_BCR1 register." start="21" size="1" />
+      <BitField name="BMAP" description="FMC bank mapping These bits allows different to remap SDRAM bank2 or swap the FMC NOR/PSRAM and SDRAM banks.Refer to Table 10 for Note: The BMAP bits of the FMC_BCR2..4 registers are dont care. It is only enabled through the FMC_BCR1 register." start="24" size="2" />
+      <BitField name="FMCEN" description="FMC controller Enable This bit enables/disables the FMC controller. Note: The FMCEN bit of the FMC_BCR2..4 registers is dont care. It is only enabled through the FMC_BCR1 register." start="31" size="1" />
+    </Register>
+    <Register name="BTR4" description="This register contains the control information of each memory bank, used for SRAMs, PSRAM and NOR Flash memories.If the EXTMOD bit is set in the FMC_BCRx register, then this register is partitioned for write and read access, that is, 2 registers are available: one to configure read accesses (this register) and one to configure write accesses (FMC_BWTRx registers)." start="+0x1C" size="4" access="Read/Write" reset_value="0x0FFFFFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="ADDSET" description="Address setup phase duration These bits are written by software to define the duration of the address setup phase (refer to Figure81 to Figure93), used in SRAMs, ROMs and asynchronous NOR Flash: For each access mode address setup phase duration, please refer to the respective figure (refer to Figure81 to Figure93). Note: In synchronous accesses, this value is dont care. In Muxed mode or Mode D, the minimum value for ADDSET is 1." start="0" size="4" />
+      <BitField name="ADDHLD" description="Address-hold phase duration These bits are written by software to define the duration of the address hold phase (refer to Figure81 to Figure93), used in mode D or multiplexed accesses: For each access mode address-hold phase duration, please refer to the respective figure (Figure81 to Figure93). Note: In synchronous accesses, this value is not used, the address hold phase is always 1 memory clock period duration." start="4" size="4" />
+      <BitField name="DATAST" description="Data-phase duration These bits are written by software to define the duration of the data phase (refer to Figure81 to Figure93), used in asynchronous accesses: For each memory type and access mode data-phase duration, please refer to the respective figure (Figure81 to Figure93). Example: Mode1, write access, DATAST=1: Data-phase duration= DATAST+1 = 2 KCK_FMC clock cycles. Note: In synchronous accesses, this value is dont care." start="8" size="8" />
+      <BitField name="BUSTURN" description="Bus turnaround phase duration These bits are written by software to add a delay at the end of a write-to-read or read-to write transaction. The programmed bus turnaround delay is inserted between an asynchronous read (in muxed or mode D) or write transaction and any other asynchronous /synchronous read/write from/to a static bank. If a read operation is performed, the bank can be the same or a different one, whereas it must be different in case of write operation to the bank, except in muxed mode or mode D. In some cases, whatever the programmed BUSTRUN values, the bus turnaround delay is fixed as follows: The bus turnaround delay is not inserted between two consecutive asynchronous write transfers to the same static memory bank except in muxed mode and mode D. There is a bus turnaround delay of 1 FMC clock cycle between: Two consecutive asynchronous read transfers to the same static memory bank except for modes muxed and D. An asynchronous read to an asynchronous or synchronous write to any static bank or dynamic bank except in modes muxed and D mode. There is a bus turnaround delay of 2 FMC clock cycle between: Two consecutive synchronous write operations (in Burst or Single mode) to the same bank. A synchronous write (burst or single) access and an asynchronous write or read transfer to or from static memory bank (the bank can be the same or a different one in case of a read operation. Two consecutive synchronous read operations (in Burst or Single mode) followed by any synchronous/asynchronous read or write from/to another static memory bank. There is a bus turnaround delay of 3 FMC clock cycle between: Two consecutive synchronous write operations (in Burst or Single mode) to different static banks. A synchronous write access (in Burst or Single mode) and a synchronous read from the same or a different bank. The bus turnaround delay allows to match the minimum time between consecutive transactions (tEHEL from NEx high to NEx low) and the maximum time required by the memory to free the data bus after a read access (tEHQZ): (BUSTRUN + 1) KCK_FMC period &amp;#8805; tEHELmin and (BUSTRUN + 2)KCK_FMC period &amp;#8805; tEHQZmax if EXTMOD = 0 (BUSTRUN + 2)KCK_FMC period &amp;#8805; max (tEHELmin, tEHQZmax) if EXTMOD =1. ..." start="16" size="4" />
+      <BitField name="CLKDIV" description="Clock divide ratio (for FMC_CLK signal) These bits define the period of FMC_CLK clock output signal, expressed in number of KCK_FMC cycles: In asynchronous NOR Flash, SRAM or PSRAM accesses, this value is dont care. Note: Refer to Section20.6.5: Synchronous transactions for FMC_CLK divider ratio formula)" start="20" size="4" />
+      <BitField name="DATLAT" description="Data latency for synchronous memory For synchronous access with read write burst mode enabled these bits define the number of memory clock cycles" start="24" size="4" />
+      <BitField name="ACCMOD" description="Access mode These bits specify the asynchronous access modes as shown in the timing diagrams. They are taken into account only when the EXTMOD bit in the FMC_BCRx register is 1." start="28" size="2" />
+    </Register>
+    <Register name="PCR" description="NAND Flash control registers" start="+0x80" size="4" access="Read/Write" reset_value="0x00000018" reset_mask="0xFFFFFFFF">
+      <BitField name="PWAITEN" description="Wait feature enable bit. This bit enables the Wait feature for the NAND Flash memory bank:" start="1" size="1" />
+      <BitField name="PBKEN" description="NAND Flash memory bank enable bit. This bit enables the memory bank. Accessing a disabled memory bank causes an ERROR on AXI bus" start="2" size="1" />
+      <BitField name="PWID" description="Data bus width. These bits define the external memory device width." start="4" size="2" />
+      <BitField name="ECCEN" description="ECC computation logic enable bit" start="6" size="1" />
+      <BitField name="TCLR" description="CLE to RE delay. These bits set time from CLE low to RE low in number of KCK_FMC clock cycles. The time is give by the following formula: t_clr = (TCLR + SET + 2) TKCK_FMC where TKCK_FMC is the KCK_FMC clock period Note: Set is MEMSET or ATTSET according to the addressed space." start="9" size="4" />
+      <BitField name="TAR" description="ALE to RE delay. These bits set time from ALE low to RE low in number of KCK_FMC clock cycles. Time is: t_ar = (TAR + SET + 2) TKCK_FMC where TKCK_FMC is the FMC clock period Note: Set is MEMSET or ATTSET according to the addressed space." start="13" size="4" />
+      <BitField name="ECCPS" description="ECC page size. These bits define the page size for the extended ECC:" start="17" size="3" />
+    </Register>
+    <Register name="SR" description="This register contains information about the FIFO status and interrupt. The FMC features a FIFO that is used when writing to memories to transfer up to 16 words of data.This is used to quickly write to the FIFO and free the AXI bus for transactions to peripherals other than the FMC, while the FMC is draining its FIFO into the memory. One of these register bits indicates the status of the FIFO, for ECC purposes.The ECC is calculated while the data are written to the memory. To read the correct ECC, the software must consequently wait until the FIFO is empty." start="+0x84" size="4" reset_value="0x00000040" reset_mask="0xFFFFFFFF">
+      <BitField name="IRS" description="Interrupt rising edge status The flag is set by hardware and reset by software. Note: If this bit is written by software to 1 it will be set." start="0" size="1" access="Read/Write" />
+      <BitField name="ILS" description="Interrupt high-level status The flag is set by hardware and reset by software." start="1" size="1" access="Read/Write" />
+      <BitField name="IFS" description="Interrupt falling edge status The flag is set by hardware and reset by software. Note: If this bit is written by software to 1 it will be set." start="2" size="1" access="Read/Write" />
+      <BitField name="IREN" description="Interrupt rising edge detection enable bit" start="3" size="1" access="Read/Write" />
+      <BitField name="ILEN" description="Interrupt high-level detection enable bit" start="4" size="1" access="Read/Write" />
+      <BitField name="IFEN" description="Interrupt falling edge detection enable bit" start="5" size="1" access="Read/Write" />
+      <BitField name="FEMPT" description="FIFO empty. Read-only bit that provides the status of the FIFO" start="6" size="1" access="ReadOnly" />
+    </Register>
+    <Register name="PMEM" description="The FMC_PMEM read/write register contains the timing information for NAND Flash memory bank. This information is used to access either the common memory space of the NAND Flash for command, address write access and data read/write access." start="+0x88" size="4" access="Read/Write" reset_value="0xFCFCFCFC" reset_mask="0xFFFFFFFF">
+      <BitField name="MEMSET" description="Common memory x setup time These bits define the number of KCK_FMC (+1) clock cycles to set up the address before the command assertion (NWE, NOE), for NAND Flash read or write access to common memory space:" start="0" size="8" />
+      <BitField name="MEMWAIT" description="Common memory wait time These bits define the minimum number of KCK_FMC (+1) clock cycles to assert the command (NWE, NOE), for NAND Flash read or write access to common memory space. The duration of command assertion is extended if the wait signal (NWAIT) is active (low) at the end of the programmed value of KCK_FMC:" start="8" size="8" />
+      <BitField name="MEMHOLD" description="Common memory hold time These bits define the number of KCK_FMC clock cycles for write accesses and KCK_FMC+1 clock cycles for read accesses during which the address is held (and data for write accesses) after the command is de-asserted (NWE, NOE), for NAND Flash read or write access to common memory space:" start="16" size="8" />
+      <BitField name="MEMHIZ" description="Common memory x data bus Hi-Z time These bits define the number of KCK_FMC clock cycles during which the data bus is kept Hi-Z after the start of a NAND Flash write access to common memory space. This is only valid for write transactions:" start="24" size="8" />
+    </Register>
+    <Register name="PATT" description="The FMC_PATT read/write register contains the timing information for NAND Flash memory bank. It is used for 8-bit accesses to the attribute memory space of the NAND Flash for the last address write access if the timing must differ from that of previous accesses (for Ready/Busy management, refer to Section20.8.5: NAND Flash prewait feature)." start="+0x8C" size="4" access="Read/Write" reset_value="0xFCFCFCFC" reset_mask="0xFFFFFFFF">
+      <BitField name="ATTSET" description="Attribute memory setup time These bits define the number of KCK_FMC (+1) clock cycles to set up address before the command assertion (NWE, NOE), for NAND Flash read or write access to attribute memory space:" start="0" size="8" />
+      <BitField name="ATTWAIT" description="Attribute memory wait time These bits define the minimum number of x KCK_FMC (+1) clock cycles to assert the command (NWE, NOE), for NAND Flash read or write access to attribute memory space. The duration for command assertion is extended if the wait signal (NWAIT) is active (low) at the end of the programmed value of KCK_FMC:" start="8" size="8" />
+      <BitField name="ATTHOLD" description="Attribute memory hold time These bits define the number of KCK_FMC clock cycles during which the address is held (and data for write access) after the command de-assertion (NWE, NOE), for NAND Flash read or write access to attribute memory space:" start="16" size="8" />
+      <BitField name="ATTHIZ" description="Attribute memory data bus Hi-Z time These bits define the number of KCK_FMC clock cycles during which the data bus is kept in Hi-Z after the start of a NAND Flash write access to attribute memory space on socket. Only valid for writ transaction:" start="24" size="8" />
+    </Register>
+    <Register name="ECCR" description="This register contain the current error correction code value computed by the ECC computation modules of the FMC NAND controller. When the CPU reads/writes the data from a NAND Flash memory page at the correct address (refer to Section20.8.6: Computation of the error correction code (ECC) in NAND Flash memory), the data read/written from/to the NAND Flash memory are processed automatically by the ECC computation module. When X bytes have been read (according to the ECCPS field in the FMC_PCR registers), the CPU must read the computed ECC value from the FMC_ECC registers. It then verifies if these computed parity data are the same as the parity value recorded in the spare area, to determine whether a page is valid, and, to correct it otherwise. The FMC_ECCR register should be cleared after being read by setting the ECCEN bit to 0. To compute a new data block, the ECCEN bit must be set to 1." start="+0x94" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ECC" description="ECC result This field contains the value computed by the ECC computation logic. Table167 describes the contents of these bit fields." start="0" size="32" />
+    </Register>
+    <Register name="BWTR1" description="This register contains the control information of each memory bank. It is used for SRAMs, PSRAMs and NOR Flash memories. When the EXTMOD bit is set in the FMC_BCRx register, then this register is active for write access." start="+0x104" size="4" access="Read/Write" reset_value="0x0FFFFFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="ADDSET" description="Address setup phase duration. These bits are written by software to define the duration of the address setup phase in KCK_FMC cycles (refer to Figure81 to Figure93), used in asynchronous accesses: ... Note: In synchronous accesses, this value is not used, the address setup phase is always 1 Flash clock period duration. In muxed mode, the minimum ADDSET value is 1." start="0" size="4" />
+      <BitField name="ADDHLD" description="Address-hold phase duration. These bits are written by software to define the duration of the address hold phase (refer to Figure81 to Figure93), used in asynchronous multiplexed accesses: ... Note: In synchronous NOR Flash accesses, this value is not used, the address hold phase is always 1 Flash clock period duration." start="4" size="4" />
+      <BitField name="DATAST" description="Data-phase duration. These bits are written by software to define the duration of the data phase (refer to Figure81 to Figure93), used in asynchronous SRAM, PSRAM and NOR Flash memory accesses:" start="8" size="8" />
+      <BitField name="BUSTURN" description="Bus turnaround phase duration These bits are written by software to add a delay at the end of a write transaction to match the minimum time between consecutive transactions (tEHEL from ENx high to ENx low): (BUSTRUN + 1) KCK_FMC period &amp;#8805; tEHELmin. The programmed bus turnaround delay is inserted between a an asynchronous write transfer and any other asynchronous /synchronous read or write transfer to or from a static bank. If a read operation is performed, the bank can be the same or a different one, whereas it must be different in case of write operation to the bank, except in muxed mode or mode D. In some cases, whatever the programmed BUSTRUN values, the bus turnaround delay is fixed as follows: The bus turnaround delay is not inserted between two consecutive asynchronous write transfers to the same static memory bank except for muxed mode and mode D. There is a bus turnaround delay of 2 FMC clock cycle between: Two consecutive synchronous write operations (in Burst or Single mode) to the same bank A synchronous write transfer ((in Burst or Single mode) and an asynchronous write or read transfer to or from static memory bank. There is a bus turnaround delay of 3 FMC clock cycle between: Two consecutive synchronous write operations (in Burst or Single mode) to different static banks. A synchronous write transfer (in Burst or Single mode) and a synchronous read from the same or a different bank. ..." start="16" size="4" />
+      <BitField name="ACCMOD" description="Access mode. These bits specify the asynchronous access modes as shown in the next timing diagrams.These bits are taken into account only when the EXTMOD bit in the FMC_BCRx register is 1." start="28" size="2" />
+    </Register>
+    <Register name="BWTR2" description="This register contains the control information of each memory bank. It is used for SRAMs, PSRAMs and NOR Flash memories. When the EXTMOD bit is set in the FMC_BCRx register, then this register is active for write access." start="+0x10C" size="4" access="Read/Write" reset_value="0x0FFFFFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="ADDSET" description="Address setup phase duration. These bits are written by software to define the duration of the address setup phase in KCK_FMC cycles (refer to Figure81 to Figure93), used in asynchronous accesses: ... Note: In synchronous accesses, this value is not used, the address setup phase is always 1 Flash clock period duration. In muxed mode, the minimum ADDSET value is 1." start="0" size="4" />
+      <BitField name="ADDHLD" description="Address-hold phase duration. These bits are written by software to define the duration of the address hold phase (refer to Figure81 to Figure93), used in asynchronous multiplexed accesses: ... Note: In synchronous NOR Flash accesses, this value is not used, the address hold phase is always 1 Flash clock period duration." start="4" size="4" />
+      <BitField name="DATAST" description="Data-phase duration. These bits are written by software to define the duration of the data phase (refer to Figure81 to Figure93), used in asynchronous SRAM, PSRAM and NOR Flash memory accesses:" start="8" size="8" />
+      <BitField name="BUSTURN" description="Bus turnaround phase duration These bits are written by software to add a delay at the end of a write transaction to match the minimum time between consecutive transactions (tEHEL from ENx high to ENx low): (BUSTRUN + 1) KCK_FMC period &amp;#8805; tEHELmin. The programmed bus turnaround delay is inserted between a an asynchronous write transfer and any other asynchronous /synchronous read or write transfer to or from a static bank. If a read operation is performed, the bank can be the same or a different one, whereas it must be different in case of write operation to the bank, except in muxed mode or mode D. In some cases, whatever the programmed BUSTRUN values, the bus turnaround delay is fixed as follows: The bus turnaround delay is not inserted between two consecutive asynchronous write transfers to the same static memory bank except for muxed mode and mode D. There is a bus turnaround delay of 2 FMC clock cycle between: Two consecutive synchronous write operations (in Burst or Single mode) to the same bank A synchronous write transfer ((in Burst or Single mode) and an asynchronous write or read transfer to or from static memory bank. There is a bus turnaround delay of 3 FMC clock cycle between: Two consecutive synchronous write operations (in Burst or Single mode) to different static banks. A synchronous write transfer (in Burst or Single mode) and a synchronous read from the same or a different bank. ..." start="16" size="4" />
+      <BitField name="ACCMOD" description="Access mode. These bits specify the asynchronous access modes as shown in the next timing diagrams.These bits are taken into account only when the EXTMOD bit in the FMC_BCRx register is 1." start="28" size="2" />
+    </Register>
+    <Register name="BWTR3" description="This register contains the control information of each memory bank. It is used for SRAMs, PSRAMs and NOR Flash memories. When the EXTMOD bit is set in the FMC_BCRx register, then this register is active for write access." start="+0x114" size="4" access="Read/Write" reset_value="0x0FFFFFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="ADDSET" description="Address setup phase duration. These bits are written by software to define the duration of the address setup phase in KCK_FMC cycles (refer to Figure81 to Figure93), used in asynchronous accesses: ... Note: In synchronous accesses, this value is not used, the address setup phase is always 1 Flash clock period duration. In muxed mode, the minimum ADDSET value is 1." start="0" size="4" />
+      <BitField name="ADDHLD" description="Address-hold phase duration. These bits are written by software to define the duration of the address hold phase (refer to Figure81 to Figure93), used in asynchronous multiplexed accesses: ... Note: In synchronous NOR Flash accesses, this value is not used, the address hold phase is always 1 Flash clock period duration." start="4" size="4" />
+      <BitField name="DATAST" description="Data-phase duration. These bits are written by software to define the duration of the data phase (refer to Figure81 to Figure93), used in asynchronous SRAM, PSRAM and NOR Flash memory accesses:" start="8" size="8" />
+      <BitField name="BUSTURN" description="Bus turnaround phase duration These bits are written by software to add a delay at the end of a write transaction to match the minimum time between consecutive transactions (tEHEL from ENx high to ENx low): (BUSTRUN + 1) KCK_FMC period &amp;#8805; tEHELmin. The programmed bus turnaround delay is inserted between a an asynchronous write transfer and any other asynchronous /synchronous read or write transfer to or from a static bank. If a read operation is performed, the bank can be the same or a different one, whereas it must be different in case of write operation to the bank, except in muxed mode or mode D. In some cases, whatever the programmed BUSTRUN values, the bus turnaround delay is fixed as follows: The bus turnaround delay is not inserted between two consecutive asynchronous write transfers to the same static memory bank except for muxed mode and mode D. There is a bus turnaround delay of 2 FMC clock cycle between: Two consecutive synchronous write operations (in Burst or Single mode) to the same bank A synchronous write transfer ((in Burst or Single mode) and an asynchronous write or read transfer to or from static memory bank. There is a bus turnaround delay of 3 FMC clock cycle between: Two consecutive synchronous write operations (in Burst or Single mode) to different static banks. A synchronous write transfer (in Burst or Single mode) and a synchronous read from the same or a different bank. ..." start="16" size="4" />
+      <BitField name="ACCMOD" description="Access mode. These bits specify the asynchronous access modes as shown in the next timing diagrams.These bits are taken into account only when the EXTMOD bit in the FMC_BCRx register is 1." start="28" size="2" />
+    </Register>
+    <Register name="BWTR4" description="This register contains the control information of each memory bank. It is used for SRAMs, PSRAMs and NOR Flash memories. When the EXTMOD bit is set in the FMC_BCRx register, then this register is active for write access." start="+0x11C" size="4" access="Read/Write" reset_value="0x0FFFFFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="ADDSET" description="Address setup phase duration. These bits are written by software to define the duration of the address setup phase in KCK_FMC cycles (refer to Figure81 to Figure93), used in asynchronous accesses: ... Note: In synchronous accesses, this value is not used, the address setup phase is always 1 Flash clock period duration. In muxed mode, the minimum ADDSET value is 1." start="0" size="4" />
+      <BitField name="ADDHLD" description="Address-hold phase duration. These bits are written by software to define the duration of the address hold phase (refer to Figure81 to Figure93), used in asynchronous multiplexed accesses: ... Note: In synchronous NOR Flash accesses, this value is not used, the address hold phase is always 1 Flash clock period duration." start="4" size="4" />
+      <BitField name="DATAST" description="Data-phase duration. These bits are written by software to define the duration of the data phase (refer to Figure81 to Figure93), used in asynchronous SRAM, PSRAM and NOR Flash memory accesses:" start="8" size="8" />
+      <BitField name="BUSTURN" description="Bus turnaround phase duration These bits are written by software to add a delay at the end of a write transaction to match the minimum time between consecutive transactions (tEHEL from ENx high to ENx low): (BUSTRUN + 1) KCK_FMC period &amp;#8805; tEHELmin. The programmed bus turnaround delay is inserted between a an asynchronous write transfer and any other asynchronous /synchronous read or write transfer to or from a static bank. If a read operation is performed, the bank can be the same or a different one, whereas it must be different in case of write operation to the bank, except in muxed mode or mode D. In some cases, whatever the programmed BUSTRUN values, the bus turnaround delay is fixed as follows: The bus turnaround delay is not inserted between two consecutive asynchronous write transfers to the same static memory bank except for muxed mode and mode D. There is a bus turnaround delay of 2 FMC clock cycle between: Two consecutive synchronous write operations (in Burst or Single mode) to the same bank A synchronous write transfer ((in Burst or Single mode) and an asynchronous write or read transfer to or from static memory bank. There is a bus turnaround delay of 3 FMC clock cycle between: Two consecutive synchronous write operations (in Burst or Single mode) to different static banks. A synchronous write transfer (in Burst or Single mode) and a synchronous read from the same or a different bank. ..." start="16" size="4" />
+      <BitField name="ACCMOD" description="Access mode. These bits specify the asynchronous access modes as shown in the next timing diagrams.These bits are taken into account only when the EXTMOD bit in the FMC_BCRx register is 1." start="28" size="2" />
+    </Register>
+    <Register name="SDCR1" description="This register contains the control parameters for each SDRAM memory bank" start="+0x140" size="4" access="Read/Write" reset_value="0x000002D0" reset_mask="0xFFFFFFFF">
+      <BitField name="NC" description="Number of column address bits These bits define the number of bits of a column address." start="0" size="2" />
+      <BitField name="NR" description="Number of row address bits These bits define the number of bits of a row address." start="2" size="2" />
+      <BitField name="MWID" description="Memory data bus width. These bits define the memory device width." start="4" size="2" />
+      <BitField name="NB" description="Number of internal banks This bit sets the number of internal banks." start="6" size="1" />
+      <BitField name="CAS" description="CAS Latency This bits sets the SDRAM CAS latency in number of memory clock cycles" start="7" size="2" />
+      <BitField name="WP" description="Write protection This bit enables write mode access to the SDRAM bank." start="9" size="1" />
+      <BitField name="SDCLK" description="SDRAM clock configuration These bits define the SDRAM clock period for both SDRAM banks and allow disabling the clock before changing the frequency. In this case the SDRAM must be re-initialized. Note: The corresponding bits in the FMC_SDCR2 register is read only." start="10" size="2" />
+      <BitField name="RBURST" description="Burst read This bit enables burst read mode. The SDRAM controller anticipates the next read commands during the CAS latency and stores data in the Read FIFO. Note: The corresponding bit in the FMC_SDCR2 register is read only." start="12" size="1" />
+      <BitField name="RPIPE" description="Read pipe These bits define the delay, in KCK_FMC clock cycles, for reading data after CAS latency. Note: The corresponding bits in the FMC_SDCR2 register is read only." start="13" size="2" />
+    </Register>
+    <Register name="SDCR2" description="This register contains the control parameters for each SDRAM memory bank" start="+0x144" size="4" access="Read/Write" reset_value="0x000002D0" reset_mask="0xFFFFFFFF">
+      <BitField name="NC" description="Number of column address bits These bits define the number of bits of a column address." start="0" size="2" />
+      <BitField name="NR" description="Number of row address bits These bits define the number of bits of a row address." start="2" size="2" />
+      <BitField name="MWID" description="Memory data bus width. These bits define the memory device width." start="4" size="2" />
+      <BitField name="NB" description="Number of internal banks This bit sets the number of internal banks." start="6" size="1" />
+      <BitField name="CAS" description="CAS Latency This bits sets the SDRAM CAS latency in number of memory clock cycles" start="7" size="2" />
+      <BitField name="WP" description="Write protection This bit enables write mode access to the SDRAM bank." start="9" size="1" />
+      <BitField name="SDCLK" description="SDRAM clock configuration These bits define the SDRAM clock period for both SDRAM banks and allow disabling the clock before changing the frequency. In this case the SDRAM must be re-initialized. Note: The corresponding bits in the FMC_SDCR2 register is read only." start="10" size="2" />
+      <BitField name="RBURST" description="Burst read This bit enables burst read mode. The SDRAM controller anticipates the next read commands during the CAS latency and stores data in the Read FIFO. Note: The corresponding bit in the FMC_SDCR2 register is read only." start="12" size="1" />
+      <BitField name="RPIPE" description="Read pipe These bits define the delay, in KCK_FMC clock cycles, for reading data after CAS latency. Note: The corresponding bits in the FMC_SDCR2 register is read only." start="13" size="2" />
+    </Register>
+    <Register name="SDTR1" description="This register contains the timing parameters of each SDRAM bank" start="+0x148" size="4" access="Read/Write" reset_value="0x0FFFFFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="TMRD" description="Load Mode Register to Active These bits define the delay between a Load Mode Register command and an Active or Refresh command in number of memory clock cycles. ...." start="0" size="4" />
+      <BitField name="TXSR" description="Exit Self-refresh delay These bits define the delay from releasing the Self-refresh command to issuing the Activate command in number of memory clock cycles. .... Note: If two SDRAM devices are used, the FMC_SDTR1 and FMC_SDTR2 must be programmed with the same TXSR timing corresponding to the slowest SDRAM device." start="4" size="4" />
+      <BitField name="TRAS" description="Self refresh time These bits define the minimum Self-refresh period in number of memory clock cycles. ...." start="8" size="4" />
+      <BitField name="TRC" description="Row cycle delay These bits define the delay between the Refresh command and the Activate command, as well as the delay between two consecutive Refresh commands. It is expressed in number of memory clock cycles. The TRC timing is only configured in the FMC_SDTR1 register. If two SDRAM devices are used, the TRC must be programmed with the timings of the slowest device. .... Note: TRC must match the TRC and TRFC (Auto Refresh period) timings defined in the SDRAM device datasheet. Note: The corresponding bits in the FMC_SDTR2 register are dont care." start="12" size="4" />
+      <BitField name="TWR" description="Recovery delay These bits define the delay between a Write and a Precharge command in number of memory clock cycles. .... Note: TWR must be programmed to match the write recovery time (tWR) defined in the SDRAM datasheet, and to guarantee that: TWR &amp;#8805; TRAS - TRCD and TWR &amp;#8805;TRC - TRCD - TRP Example: TRAS= 4 cycles, TRCD= 2 cycles. So, TWR &amp;gt;= 2 cycles. TWR must be programmed to 0x1. If two SDRAM devices are used, the FMC_SDTR1 and FMC_SDTR2 must be programmed with the same TWR timing corresponding to the slowest SDRAM device." start="16" size="4" />
+      <BitField name="TRP" description="Row precharge delay These bits define the delay between a Precharge command and another command in number of memory clock cycles. The TRP timing is only configured in the FMC_SDTR1 register. If two SDRAM devices are used, the TRP must be programmed with the timing of the slowest device. .... Note: The corresponding bits in the FMC_SDTR2 register are dont care." start="20" size="4" />
+      <BitField name="TRCD" description="Row to column delay These bits define the delay between the Activate command and a Read/Write command in number of memory clock cycles. ...." start="24" size="4" />
+    </Register>
+    <Register name="SDTR2" description="This register contains the timing parameters of each SDRAM bank" start="+0x14C" size="4" access="Read/Write" reset_value="0x0FFFFFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="TMRD" description="Load Mode Register to Active These bits define the delay between a Load Mode Register command and an Active or Refresh command in number of memory clock cycles. ...." start="0" size="4" />
+      <BitField name="TXSR" description="Exit Self-refresh delay These bits define the delay from releasing the Self-refresh command to issuing the Activate command in number of memory clock cycles. .... Note: If two SDRAM devices are used, the FMC_SDTR1 and FMC_SDTR2 must be programmed with the same TXSR timing corresponding to the slowest SDRAM device." start="4" size="4" />
+      <BitField name="TRAS" description="Self refresh time These bits define the minimum Self-refresh period in number of memory clock cycles. ...." start="8" size="4" />
+      <BitField name="TRC" description="Row cycle delay These bits define the delay between the Refresh command and the Activate command, as well as the delay between two consecutive Refresh commands. It is expressed in number of memory clock cycles. The TRC timing is only configured in the FMC_SDTR1 register. If two SDRAM devices are used, the TRC must be programmed with the timings of the slowest device. .... Note: TRC must match the TRC and TRFC (Auto Refresh period) timings defined in the SDRAM device datasheet. Note: The corresponding bits in the FMC_SDTR2 register are dont care." start="12" size="4" />
+      <BitField name="TWR" description="Recovery delay These bits define the delay between a Write and a Precharge command in number of memory clock cycles. .... Note: TWR must be programmed to match the write recovery time (tWR) defined in the SDRAM datasheet, and to guarantee that: TWR &amp;#8805; TRAS - TRCD and TWR &amp;#8805;TRC - TRCD - TRP Example: TRAS= 4 cycles, TRCD= 2 cycles. So, TWR &amp;gt;= 2 cycles. TWR must be programmed to 0x1. If two SDRAM devices are used, the FMC_SDTR1 and FMC_SDTR2 must be programmed with the same TWR timing corresponding to the slowest SDRAM device." start="16" size="4" />
+      <BitField name="TRP" description="Row precharge delay These bits define the delay between a Precharge command and another command in number of memory clock cycles. The TRP timing is only configured in the FMC_SDTR1 register. If two SDRAM devices are used, the TRP must be programmed with the timing of the slowest device. .... Note: The corresponding bits in the FMC_SDTR2 register are dont care." start="20" size="4" />
+      <BitField name="TRCD" description="Row to column delay These bits define the delay between the Activate command and a Read/Write command in number of memory clock cycles. ...." start="24" size="4" />
+    </Register>
+    <Register name="SDCMR" description="This register contains the command issued when the SDRAM device is accessed. This register is used to initialize the SDRAM device, and to activate the Self-refresh and the Power-down modes. As soon as the MODE field is written, the command will be issued only to one or to both SDRAM banks according to CTB1 and CTB2 command bits. This register is the same for both SDRAM banks." start="+0x150" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MODE" description="Command mode These bits define the command issued to the SDRAM device. Note: When a command is issued, at least one Command Target Bank bit ( CTB1 or CTB2) must be set otherwise the command will be ignored. Note: If two SDRAM banks are used, the Auto-refresh and PALL command must be issued simultaneously to the two devices with CTB1 and CTB2 bits set otherwise the command will be ignored. Note: If only one SDRAM bank is used and a command is issued with its associated CTB bit set, the other CTB bit of the unused bank must be kept to 0." start="0" size="3" />
+      <BitField name="CTB2" description="Command Target Bank 2 This bit indicates whether the command will be issued to SDRAM Bank 2 or not." start="3" size="1" />
+      <BitField name="CTB1" description="Command Target Bank 1 This bit indicates whether the command will be issued to SDRAM Bank 1 or not." start="4" size="1" />
+      <BitField name="NRFS" description="Number of Auto-refresh These bits define the number of consecutive Auto-refresh commands issued when MODE = 011. ...." start="5" size="4" />
+      <BitField name="MRD" description="Mode Register definition This 14-bit field defines the SDRAM Mode Register content. The Mode Register is programmed using the Load Mode Register command. The MRD[13:0] bits are also used to program the extended mode register for mobile SDRAM." start="9" size="14" />
+    </Register>
+    <Register name="SDRTR" description="This register sets the refresh rate in number of SDCLK clock cycles between the refresh cycles by configuring the Refresh Timer Count value.Examplewhere 64 ms is the SDRAM refresh period.The refresh rate must be increased by 20 SDRAM clock cycles (as in the above example) to obtain a safe margin if an internal refresh request occurs when a read request has been accepted. It corresponds to a COUNT value of 0000111000000 (448). This 13-bit field is loaded into a timer which is decremented using the SDRAM clock. This timer generates a refresh pulse when zero is reached. The COUNT value must be set at least to 41 SDRAM clock cycles.As soon as the FMC_SDRTR register is programmed, the timer starts counting. If the value programmed in the register is 0, no refresh is carried out. This register must not be reprogrammed after the initialization procedure to avoid modifying the refresh rate.Each time a refresh pulse is generated, this 13-bit COUNT field is reloaded into the counter.If a memory access is in progress, the Auto-refresh request is delayed. However, if the memory access and Auto-refresh requests are generated simultaneously, the Auto-refresh takes precedence. If the memory access occurs during a refresh operation, the request is buffered to be processed when the refresh is complete.This register is common to SDRAM bank 1 and bank 2." start="+0x154" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CRE" description="Clear Refresh error flag This bit is used to clear the Refresh Error Flag (RE) in the Status Register." start="0" size="1" access="WriteOnly" />
+      <BitField name="COUNT" description="Refresh Timer Count This 13-bit field defines the refresh rate of the SDRAM device. It is expressed in number of memory clock cycles. It must be set at least to 41 SDRAM clock cycles (0x29). Refresh rate = (COUNT + 1) x SDRAM frequency clock COUNT = (SDRAM refresh period / Number of rows) - 20" start="1" size="13" access="Read/Write" />
+      <BitField name="REIE" description="RES Interrupt Enable" start="14" size="1" access="Read/Write" />
+    </Register>
+    <Register name="SDSR" description="SDRAM Status register" start="+0x158" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RE" description="Refresh error flag An interrupt is generated if REIE = 1 and RE = 1" start="0" size="1" />
+      <BitField name="MODES1" description="Status Mode for Bank 1 These bits define the Status Mode of SDRAM Bank 1." start="1" size="2" />
+      <BitField name="MODES2" description="Status Mode for Bank 2 These bits define the Status Mode of SDRAM Bank 2." start="3" size="2" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="FPU" description="Floting point unit" start="0xE000EF34">
+    <Register name="FPCCR" description="Floating-point context control register" start="+0x0" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LSPACT" description="LSPACT" start="0" size="1" />
+      <BitField name="USER" description="USER" start="1" size="1" />
+      <BitField name="THREAD" description="THREAD" start="3" size="1" />
+      <BitField name="HFRDY" description="HFRDY" start="4" size="1" />
+      <BitField name="MMRDY" description="MMRDY" start="5" size="1" />
+      <BitField name="BFRDY" description="BFRDY" start="6" size="1" />
+      <BitField name="MONRDY" description="MONRDY" start="8" size="1" />
+      <BitField name="LSPEN" description="LSPEN" start="30" size="1" />
+      <BitField name="ASPEN" description="ASPEN" start="31" size="1" />
+    </Register>
+    <Register name="FPCAR" description="Floating-point context address register" start="+0x4" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ADDRESS" description="Location of unpopulated floating-point" start="3" size="29" />
+    </Register>
+    <Register name="FPSCR" description="Floating-point status control register" start="+0x8" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IOC" description="Invalid operation cumulative exception bit" start="0" size="1" />
+      <BitField name="DZC" description="Division by zero cumulative exception bit." start="1" size="1" />
+      <BitField name="OFC" description="Overflow cumulative exception bit" start="2" size="1" />
+      <BitField name="UFC" description="Underflow cumulative exception bit" start="3" size="1" />
+      <BitField name="IXC" description="Inexact cumulative exception bit" start="4" size="1" />
+      <BitField name="IDC" description="Input denormal cumulative exception bit." start="7" size="1" />
+      <BitField name="RMode" description="Rounding Mode control field" start="22" size="2" />
+      <BitField name="FZ" description="Flush-to-zero mode control bit:" start="24" size="1" />
+      <BitField name="DN" description="Default NaN mode control bit" start="25" size="1" />
+      <BitField name="AHP" description="Alternative half-precision control bit" start="26" size="1" />
+      <BitField name="V" description="Overflow condition code flag" start="28" size="1" />
+      <BitField name="C" description="Carry condition code flag" start="29" size="1" />
+      <BitField name="Z" description="Zero condition code flag" start="30" size="1" />
+      <BitField name="N" description="Negative condition code flag" start="31" size="1" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="FPU_CPACR" description="Floating point unit CPACR" start="0xE000ED88">
+    <Register name="CPACR" description="Coprocessor access control register" start="+0x0" size="4" access="Read/Write" reset_value="0x0000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CP" description="CP" start="20" size="4" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="Flash" description="Flash" start="0x52002000">
+    <Register name="ACR" description="Access control register" start="+0x0" size="4" access="Read/Write" reset_value="0x00000600" reset_mask="0xFFFFFFFF">
+      <BitField name="LATENCY" description="Read latency" start="0" size="3" />
+      <BitField name="WRHIGHFREQ" description="Flash signal delay" start="4" size="2" />
+    </Register>
+    <Register name="ACR_" description="Access control register" start="+0x100" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LATENCY" description="Read latency" start="0" size="3" />
+      <BitField name="WRHIGHFREQ" description="Flash signal delay" start="4" size="2" />
+    </Register>
+    <Register name="KEYR1" description="FLASH key register for bank 1" start="+0x4" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="KEYR1" description="Bank 1 access configuration unlock key" start="0" size="32" />
+    </Register>
+    <Register name="OPTKEYR" description="FLASH option key register" start="+0x8" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OPTKEYR" description="Unlock key option bytes" start="0" size="32" />
+    </Register>
+    <Register name="OPTKEYR_" description="FLASH option key register" start="+0x108" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OPTKEYR" description="Unlock key option bytes" start="0" size="32" />
+    </Register>
+    <Register name="CR1" description="FLASH control register for bank 1" start="+0xC" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LOCK1" description="Bank 1 configuration lock bit" start="0" size="1" />
+      <BitField name="PG1" description="Bank 1 program enable bit" start="1" size="1" />
+      <BitField name="SER1" description="Bank 1 sector erase request" start="2" size="1" />
+      <BitField name="BER1" description="Bank 1 erase request" start="3" size="1" />
+      <BitField name="PSIZE1" description="Bank 1 program size" start="4" size="2" />
+      <BitField name="FW1" description="Bank 1 write forcing control bit" start="6" size="1" />
+      <BitField name="START1" description="Bank 1 bank or sector erase start control bit" start="7" size="1" />
+      <BitField name="SNB1" description="Bank 1 sector erase selection number" start="8" size="3" />
+      <BitField name="CRC_EN" description="Bank 1 CRC control bit" start="15" size="1" />
+      <BitField name="EOPIE1" description="Bank 1 end-of-program interrupt control bit" start="16" size="1" />
+      <BitField name="WRPERRIE1" description="Bank 1 write protection error interrupt enable bit" start="17" size="1" />
+      <BitField name="PGSERRIE1" description="Bank 1 programming sequence error interrupt enable bit" start="18" size="1" />
+      <BitField name="STRBERRIE1" description="Bank 1 strobe error interrupt enable bit" start="19" size="1" />
+      <BitField name="INCERRIE1" description="Bank 1 inconsistency error interrupt enable bit" start="21" size="1" />
+      <BitField name="OPERRIE1" description="Bank 1 write/erase error interrupt enable bit" start="22" size="1" />
+      <BitField name="RDPERRIE1" description="Bank 1 read protection error interrupt enable bit" start="23" size="1" />
+      <BitField name="RDSERRIE1" description="Bank 1 secure error interrupt enable bit" start="24" size="1" />
+      <BitField name="SNECCERRIE1" description="Bank 1 ECC single correction error interrupt enable bit" start="25" size="1" />
+      <BitField name="DBECCERRIE1" description="Bank 1 ECC double detection error interrupt enable bit" start="26" size="1" />
+      <BitField name="CRCENDIE1" description="Bank 1 end of CRC calculation interrupt enable bit" start="27" size="1" />
+    </Register>
+    <Register name="SR1" description="FLASH status register for bank 1" start="+0x10" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BSY1" description="Bank 1 ongoing program flag" start="0" size="1" />
+      <BitField name="WBNE1" description="Bank 1 write buffer not empty flag" start="1" size="1" />
+      <BitField name="QW1" description="Bank 1 wait queue flag" start="2" size="1" />
+      <BitField name="CRC_BUSY1" description="Bank 1 CRC busy flag" start="3" size="1" />
+      <BitField name="EOP1" description="Bank 1 end-of-program flag" start="16" size="1" />
+      <BitField name="WRPERR1" description="Bank 1 write protection error flag" start="17" size="1" />
+      <BitField name="PGSERR1" description="Bank 1 programming sequence error flag" start="18" size="1" />
+      <BitField name="STRBERR1" description="Bank 1 strobe error flag" start="19" size="1" />
+      <BitField name="INCERR1" description="Bank 1 inconsistency error flag" start="21" size="1" />
+      <BitField name="OPERR1" description="Bank 1 write/erase error flag" start="22" size="1" />
+      <BitField name="RDPERR1" description="Bank 1 read protection error flag" start="23" size="1" />
+      <BitField name="RDSERR1" description="Bank 1 secure error flag" start="24" size="1" />
+      <BitField name="SNECCERR11" description="Bank 1 single correction error flag" start="25" size="1" />
+      <BitField name="DBECCERR1" description="Bank 1 ECC double detection error flag" start="26" size="1" />
+      <BitField name="CRCEND1" description="Bank 1 CRC-complete flag" start="27" size="1" />
+    </Register>
+    <Register name="CCR1" description="FLASH clear control register for bank 1" start="+0x14" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CLR_EOP1" description="Bank 1 EOP1 flag clear bit" start="16" size="1" />
+      <BitField name="CLR_WRPERR1" description="Bank 1 WRPERR1 flag clear bit" start="17" size="1" />
+      <BitField name="CLR_PGSERR1" description="Bank 1 PGSERR1 flag clear bi" start="18" size="1" />
+      <BitField name="CLR_STRBERR1" description="Bank 1 STRBERR1 flag clear bit" start="19" size="1" />
+      <BitField name="CLR_INCERR1" description="Bank 1 INCERR1 flag clear bit" start="21" size="1" />
+      <BitField name="CLR_OPERR1" description="Bank 1 OPERR1 flag clear bit" start="22" size="1" />
+      <BitField name="CLR_RDPERR1" description="Bank 1 RDPERR1 flag clear bit" start="23" size="1" />
+      <BitField name="CLR_RDSERR1" description="Bank 1 RDSERR1 flag clear bit" start="24" size="1" />
+      <BitField name="CLR_SNECCERR1" description="Bank 1 SNECCERR1 flag clear bit" start="25" size="1" />
+      <BitField name="CLR_DBECCERR1" description="Bank 1 DBECCERR1 flag clear bit" start="26" size="1" />
+      <BitField name="CLR_CRCEND1" description="Bank 1 CRCEND1 flag clear bit" start="27" size="1" />
+    </Register>
+    <Register name="OPTCR" description="FLASH option control register" start="+0x18" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OPTLOCK" description="FLASH_OPTCR lock option configuration bit" start="0" size="1" />
+      <BitField name="OPTSTART" description="Option byte start change option configuration bit" start="1" size="1" />
+      <BitField name="MER" description="Flash mass erase enable bit" start="4" size="1" />
+      <BitField name="OPTCHANGEERRIE" description="Option byte change error interrupt enable bit" start="30" size="1" />
+      <BitField name="SWAP_BANK" description="Bank swapping configuration bit" start="31" size="1" />
+    </Register>
+    <Register name="OPTCR_" description="FLASH option control register" start="+0x118" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OPTLOCK" description="FLASH_OPTCR lock option configuration bit" start="0" size="1" />
+      <BitField name="OPTSTART" description="Option byte start change option configuration bit" start="1" size="1" />
+      <BitField name="MER" description="Flash mass erase enable bit" start="4" size="1" />
+      <BitField name="OPTCHANGEERRIE" description="Option byte change error interrupt enable bit" start="30" size="1" />
+      <BitField name="SWAP_BANK" description="Bank swapping configuration bit" start="31" size="1" />
+    </Register>
+    <Register name="OPTSR_CUR_" description="FLASH option status register" start="+0x11C" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OPT_BUSY" description="Option byte change ongoing flag" start="0" size="1" />
+      <BitField name="BOR_LEV" description="Brownout level option status bit" start="2" size="2" />
+      <BitField name="IWDG1_HW" description="IWDG1 control option status bit" start="4" size="1" />
+      <BitField name="nRST_STOP_D1" description="D1 DStop entry reset option status bit" start="6" size="1" />
+      <BitField name="nRST_STBY_D1" description="D1 DStandby entry reset option status bit" start="7" size="1" />
+      <BitField name="RDP" description="Readout protection level option status byte" start="8" size="8" />
+      <BitField name="FZ_IWDG_STOP" description="IWDG Stop mode freeze option status bit" start="17" size="1" />
+      <BitField name="FZ_IWDG_SDBY" description="IWDG Standby mode freeze option status bit" start="18" size="1" />
+      <BitField name="ST_RAM_SIZE" description="DTCM RAM size option status" start="19" size="2" />
+      <BitField name="SECURITY" description="Security enable option status bit" start="21" size="1" />
+      <BitField name="RSS1" description="User option bit 1" start="26" size="1" />
+      <BitField name="PERSO_OK" description="Device personalization status bit" start="28" size="1" />
+      <BitField name="IO_HSLV" description="I/O high-speed at low-voltage status bit (PRODUCT_BELOW_25V)" start="29" size="1" />
+      <BitField name="OPTCHANGEERR" description="Option byte change error flag" start="30" size="1" />
+      <BitField name="SWAP_BANK_OPT" description="Bank swapping option status bit" start="31" size="1" />
+    </Register>
+    <Register name="OPTSR_CUR" description="FLASH option status register" start="+0x1C" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OPT_BUSY" description="Option byte change ongoing flag" start="0" size="1" />
+      <BitField name="BOR_LEV" description="Brownout level option status bit" start="2" size="2" />
+      <BitField name="IWDG1_HW" description="IWDG1 control option status bit" start="4" size="1" />
+      <BitField name="nRST_STOP_D1" description="D1 DStop entry reset option status bit" start="6" size="1" />
+      <BitField name="nRST_STBY_D1" description="D1 DStandby entry reset option status bit" start="7" size="1" />
+      <BitField name="RDP" description="Readout protection level option status byte" start="8" size="8" />
+      <BitField name="FZ_IWDG_STOP" description="IWDG Stop mode freeze option status bit" start="17" size="1" />
+      <BitField name="FZ_IWDG_SDBY" description="IWDG Standby mode freeze option status bit" start="18" size="1" />
+      <BitField name="ST_RAM_SIZE" description="DTCM RAM size option status" start="19" size="2" />
+      <BitField name="SECURITY" description="Security enable option status bit" start="21" size="1" />
+      <BitField name="RSS1" description="User option bit 1" start="26" size="1" />
+      <BitField name="PERSO_OK" description="Device personalization status bit" start="28" size="1" />
+      <BitField name="IO_HSLV" description="I/O high-speed at low-voltage status bit (PRODUCT_BELOW_25V)" start="29" size="1" />
+      <BitField name="OPTCHANGEERR" description="Option byte change error flag" start="30" size="1" />
+      <BitField name="SWAP_BANK_OPT" description="Bank swapping option status bit" start="31" size="1" />
+    </Register>
+    <Register name="OPTSR_PRG" description="FLASH option status register" start="+0x20" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BOR_LEV" description="BOR reset level option configuration bits" start="2" size="2" />
+      <BitField name="IWDG1_HW" description="IWDG1 option configuration bit" start="4" size="1" />
+      <BitField name="nRST_STOP_D1" description="Option byte erase after D1 DStop option configuration bit" start="6" size="1" />
+      <BitField name="nRST_STBY_D1" description="Option byte erase after D1 DStandby option configuration bit" start="7" size="1" />
+      <BitField name="RDP" description="Readout protection level option configuration byte" start="8" size="8" />
+      <BitField name="FZ_IWDG_STOP" description="IWDG Stop mode freeze option configuration bit" start="17" size="1" />
+      <BitField name="FZ_IWDG_SDBY" description="IWDG Standby mode freeze option configuration bit" start="18" size="1" />
+      <BitField name="ST_RAM_SIZE" description="DTCM size select option configuration bits" start="19" size="2" />
+      <BitField name="SECURITY" description="Security option configuration bit" start="21" size="1" />
+      <BitField name="RSS1" description="User option configuration bit 1" start="26" size="1" />
+      <BitField name="RSS2" description="User option configuration bit 2" start="27" size="1" />
+      <BitField name="IO_HSLV" description="I/O high-speed at low-voltage (PRODUCT_BELOW_25V)" start="29" size="1" />
+      <BitField name="SWAP_BANK_OPT" description="Bank swapping option configuration bit" start="31" size="1" />
+    </Register>
+    <Register name="OPTSR_PRG_" description="FLASH option status register" start="+0x120" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BOR_LEV" description="BOR reset level option configuration bits" start="2" size="2" />
+      <BitField name="IWDG1_HW" description="IWDG1 option configuration bit" start="4" size="1" />
+      <BitField name="nRST_STOP_D1" description="Option byte erase after D1 DStop option configuration bit" start="6" size="1" />
+      <BitField name="nRST_STBY_D1" description="Option byte erase after D1 DStandby option configuration bit" start="7" size="1" />
+      <BitField name="RDP" description="Readout protection level option configuration byte" start="8" size="8" />
+      <BitField name="FZ_IWDG_STOP" description="IWDG Stop mode freeze option configuration bit" start="17" size="1" />
+      <BitField name="FZ_IWDG_SDBY" description="IWDG Standby mode freeze option configuration bit" start="18" size="1" />
+      <BitField name="ST_RAM_SIZE" description="DTCM size select option configuration bits" start="19" size="2" />
+      <BitField name="SECURITY" description="Security option configuration bit" start="21" size="1" />
+      <BitField name="RSS1" description="User option configuration bit 1" start="26" size="1" />
+      <BitField name="RSS2" description="User option configuration bit 2" start="27" size="1" />
+      <BitField name="IO_HSLV" description="I/O high-speed at low-voltage (PRODUCT_BELOW_25V)" start="29" size="1" />
+      <BitField name="SWAP_BANK_OPT" description="Bank swapping option configuration bit" start="31" size="1" />
+    </Register>
+    <Register name="OPTCCR_" description="FLASH option clear control register" start="+0x124" size="4" access="WriteOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CLR_OPTCHANGEERR" description="OPTCHANGEERR reset bit" start="30" size="1" />
+    </Register>
+    <Register name="OPTCCR" description="FLASH option clear control register" start="+0x24" size="4" access="WriteOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CLR_OPTCHANGEERR" description="OPTCHANGEERR reset bit" start="30" size="1" />
+    </Register>
+    <Register name="PRAR_CUR1" description="FLASH protection address for bank 1" start="+0x28" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PROT_AREA_START1" description="Bank 1 lowest PCROP protected address" start="0" size="12" />
+      <BitField name="PROT_AREA_END1" description="Bank 1 highest PCROP protected address" start="16" size="12" />
+      <BitField name="DMEP1" description="Bank 1 PCROP protected erase enable option status bit" start="31" size="1" />
+    </Register>
+    <Register name="PRAR_PRG1" description="FLASH protection address for bank 1" start="+0x2C" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PROT_AREA_START1" description="Bank 1 lowest PCROP protected address configuration" start="0" size="12" />
+      <BitField name="PROT_AREA_END1" description="Bank 1 highest PCROP protected address configuration" start="16" size="12" />
+      <BitField name="DMEP1" description="Bank 1 PCROP protected erase enable option configuration bit" start="31" size="1" />
+    </Register>
+    <Register name="SCAR_CUR1" description="FLASH secure address for bank 1" start="+0x30" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SEC_AREA_START1" description="Bank 1 lowest secure protected address" start="0" size="12" />
+      <BitField name="SEC_AREA_END1" description="Bank 1 highest secure protected address" start="16" size="12" />
+      <BitField name="DMES1" description="Bank 1 secure protected erase enable option status bit" start="31" size="1" />
+    </Register>
+    <Register name="SCAR_PRG1" description="FLASH secure address for bank 1" start="+0x34" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SEC_AREA_START1" description="Bank 1 lowest secure protected address configuration" start="0" size="12" />
+      <BitField name="SEC_AREA_END1" description="Bank 1 highest secure protected address configuration" start="16" size="12" />
+      <BitField name="DMES1" description="Bank 1 secure protected erase enable option configuration bit" start="31" size="1" />
+    </Register>
+    <Register name="WPSN_CUR1R" description="FLASH write sector protection for bank 1" start="+0x38" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="WRPSn1" description="Bank 1 sector write protection option status byte" start="0" size="8" />
+    </Register>
+    <Register name="WPSN_PRG1R" description="FLASH write sector protection for bank 1" start="+0x3C" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="WRPSn1" description="Bank 1 sector write protection configuration byte" start="0" size="8" />
+    </Register>
+    <Register name="BOOT_CURR" description="FLASH register with boot address" start="+0x40" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BOOT_ADD0" description="Boot address 0" start="0" size="16" />
+      <BitField name="BOOT_ADD1" description="Boot address 1" start="16" size="16" />
+    </Register>
+    <Register name="BOOT_PRGR" description="FLASH register with boot address" start="+0x44" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BOOT_ADD0" description="Boot address 0" start="0" size="16" />
+      <BitField name="BOOT_ADD1" description="Boot address 1" start="16" size="16" />
+    </Register>
+    <Register name="CRCCR1" description="FLASH CRC control register for bank 1" start="+0x50" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CRC_SECT" description="Bank 1 CRC sector number" start="0" size="3" />
+      <BitField name="ALL_BANK" description="Bank 1 CRC select bit" start="7" size="1" />
+      <BitField name="CRC_BY_SECT" description="Bank 1 CRC sector mode select bit" start="8" size="1" />
+      <BitField name="ADD_SECT" description="Bank 1 CRC sector select bit" start="9" size="1" />
+      <BitField name="CLEAN_SECT" description="Bank 1 CRC sector list clear bit" start="10" size="1" />
+      <BitField name="START_CRC" description="Bank 1 CRC start bit" start="16" size="1" />
+      <BitField name="CLEAN_CRC" description="Bank 1 CRC clear bit" start="17" size="1" />
+      <BitField name="CRC_BURST" description="Bank 1 CRC burst size" start="20" size="2" />
+    </Register>
+    <Register name="CRCSADD1R" description="FLASH CRC start address register for bank 1" start="+0x54" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CRC_START_ADDR" description="CRC start address on bank 1" start="0" size="32" />
+    </Register>
+    <Register name="CRCEADD1R" description="FLASH CRC end address register for bank 1" start="+0x58" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CRC_END_ADDR" description="CRC end address on bank 1" start="0" size="32" />
+    </Register>
+    <Register name="CRCDATAR" description="FLASH CRC data register" start="+0x5C" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CRC_DATA" description="CRC result" start="0" size="32" />
+    </Register>
+    <Register name="ECC_FA1R" description="FLASH ECC fail address for bank 1" start="+0x60" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FAIL_ECC_ADDR1" description="Bank 1 ECC error address" start="0" size="15" />
+    </Register>
+    <Register name="KEYR2" description="FLASH key register for bank 2" start="+0x104" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="KEYR2" description="Bank 2 access configuration unlock key" start="0" size="32" />
+    </Register>
+    <Register name="CR2" description="FLASH control register for bank 2" start="+0x10C" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LOCK2" description="Bank 2 configuration lock bit" start="0" size="1" />
+      <BitField name="PG2" description="Bank 2 program enable bit" start="1" size="1" />
+      <BitField name="SER2" description="Bank 2 sector erase request" start="2" size="1" />
+      <BitField name="BER2" description="Bank 2 erase request" start="3" size="1" />
+      <BitField name="PSIZE2" description="Bank 2 program size" start="4" size="2" />
+      <BitField name="FW2" description="Bank 2 write forcing control bit" start="6" size="1" />
+      <BitField name="START2" description="Bank 2 bank or sector erase start control bit" start="7" size="1" />
+      <BitField name="SNB2" description="Bank 2 sector erase selection number" start="8" size="3" />
+      <BitField name="CRC_EN" description="Bank 2 CRC control bit" start="15" size="1" />
+      <BitField name="EOPIE2" description="Bank 2 end-of-program interrupt control bit" start="16" size="1" />
+      <BitField name="WRPERRIE2" description="Bank 2 write protection error interrupt enable bit" start="17" size="1" />
+      <BitField name="PGSERRIE2" description="Bank 2 programming sequence error interrupt enable bit" start="18" size="1" />
+      <BitField name="STRBERRIE2" description="Bank 2 strobe error interrupt enable bit" start="19" size="1" />
+      <BitField name="INCERRIE2" description="Bank 2 inconsistency error interrupt enable bit" start="21" size="1" />
+      <BitField name="OPERRIE2" description="Bank 2 write/erase error interrupt enable bit" start="22" size="1" />
+      <BitField name="RDPERRIE2" description="Bank 2 read protection error interrupt enable bit" start="23" size="1" />
+      <BitField name="RDSERRIE2" description="Bank 2 secure error interrupt enable bit" start="24" size="1" />
+      <BitField name="SNECCERRIE2" description="Bank 2 ECC single correction error interrupt enable bit" start="25" size="1" />
+      <BitField name="DBECCERRIE2" description="Bank 2 ECC double detection error interrupt enable bit" start="26" size="1" />
+      <BitField name="CRCENDIE2" description="Bank 2 end of CRC calculation interrupt enable bit" start="27" size="1" />
+    </Register>
+    <Register name="SR2" description="FLASH status register for bank 2" start="+0x110" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BSY2" description="Bank 2 ongoing program flag" start="0" size="1" />
+      <BitField name="WBNE2" description="Bank 2 write buffer not empty flag" start="1" size="1" />
+      <BitField name="QW2" description="Bank 2 wait queue flag" start="2" size="1" />
+      <BitField name="CRC_BUSY2" description="Bank 2 CRC busy flag" start="3" size="1" />
+      <BitField name="EOP2" description="Bank 2 end-of-program flag" start="16" size="1" />
+      <BitField name="WRPERR2" description="Bank 2 write protection error flag" start="17" size="1" />
+      <BitField name="PGSERR2" description="Bank 2 programming sequence error flag" start="18" size="1" />
+      <BitField name="STRBERR2" description="Bank 2 strobe error flag" start="19" size="1" />
+      <BitField name="INCERR2" description="Bank 2 inconsistency error flag" start="21" size="1" />
+      <BitField name="OPERR2" description="Bank 2 write/erase error flag" start="22" size="1" />
+      <BitField name="RDPERR2" description="Bank 2 read protection error flag" start="23" size="1" />
+      <BitField name="RDSERR2" description="Bank 2 secure error flag" start="24" size="1" />
+      <BitField name="SNECCERR2" description="Bank 2 single correction error flag" start="25" size="1" />
+      <BitField name="DBECCERR2" description="Bank 2 ECC double detection error flag" start="26" size="1" />
+      <BitField name="CRCEND2" description="Bank 2 CRC-complete flag" start="27" size="1" />
+    </Register>
+    <Register name="CCR2" description="FLASH clear control register for bank 2" start="+0x114" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CLR_EOP2" description="Bank 1 EOP1 flag clear bit" start="16" size="1" />
+      <BitField name="CLR_WRPERR2" description="Bank 2 WRPERR1 flag clear bit" start="17" size="1" />
+      <BitField name="CLR_PGSERR2" description="Bank 2 PGSERR1 flag clear bi" start="18" size="1" />
+      <BitField name="CLR_STRBERR2" description="Bank 2 STRBERR1 flag clear bit" start="19" size="1" />
+      <BitField name="CLR_INCERR2" description="Bank 2 INCERR1 flag clear bit" start="21" size="1" />
+      <BitField name="CLR_OPERR2" description="Bank 2 OPERR1 flag clear bit" start="22" size="1" />
+      <BitField name="CLR_RDPERR2" description="Bank 2 RDPERR1 flag clear bit" start="23" size="1" />
+      <BitField name="CLR_RDSERR1" description="Bank 1 RDSERR1 flag clear bit" start="24" size="1" />
+      <BitField name="CLR_SNECCERR2" description="Bank 2 SNECCERR1 flag clear bit" start="25" size="1" />
+      <BitField name="CLR_DBECCERR1" description="Bank 1 DBECCERR1 flag clear bit" start="26" size="1" />
+      <BitField name="CLR_CRCEND2" description="Bank 2 CRCEND1 flag clear bit" start="27" size="1" />
+    </Register>
+    <Register name="PRAR_CUR2" description="FLASH protection address for bank 1" start="+0x128" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PROT_AREA_START2" description="Bank 2 lowest PCROP protected address" start="0" size="12" />
+      <BitField name="PROT_AREA_END2" description="Bank 2 highest PCROP protected address" start="16" size="12" />
+      <BitField name="DMEP2" description="Bank 2 PCROP protected erase enable option status bit" start="31" size="1" />
+    </Register>
+    <Register name="PRAR_PRG2" description="FLASH protection address for bank 2" start="+0x2C" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PROT_AREA_START2" description="Bank 2 lowest PCROP protected address configuration" start="0" size="12" />
+      <BitField name="PROT_AREA_END2" description="Bank 2 highest PCROP protected address configuration" start="16" size="12" />
+      <BitField name="DMEP2" description="Bank 2 PCROP protected erase enable option configuration bit" start="31" size="1" />
+    </Register>
+    <Register name="SCAR_CUR2" description="FLASH secure address for bank 2" start="+0x130" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SEC_AREA_START2" description="Bank 2 lowest secure protected address" start="0" size="12" />
+      <BitField name="SEC_AREA_END2" description="Bank 2 highest secure protected address" start="16" size="12" />
+      <BitField name="DMES2" description="Bank 2 secure protected erase enable option status bit" start="31" size="1" />
+    </Register>
+    <Register name="SCAR_PRG2" description="FLASH secure address for bank 2" start="+0x134" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SEC_AREA_START2" description="Bank 2 lowest secure protected address configuration" start="0" size="12" />
+      <BitField name="SEC_AREA_END2" description="Bank 2 highest secure protected address configuration" start="16" size="12" />
+      <BitField name="DMES2" description="Bank 2 secure protected erase enable option configuration bit" start="31" size="1" />
+    </Register>
+    <Register name="WPSN_CUR2R" description="FLASH write sector protection for bank 2" start="+0x138" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="WRPSn2" description="Bank 2 sector write protection option status byte" start="0" size="8" />
+    </Register>
+    <Register name="WPSN_PRG2R" description="FLASH write sector protection for bank 2" start="+0x13C" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="WRPSn2" description="Bank 2 sector write protection configuration byte" start="0" size="8" />
+    </Register>
+    <Register name="CRCCR2" description="FLASH CRC control register for bank 1" start="+0x150" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CRC_SECT" description="Bank 2 CRC sector number" start="0" size="3" />
+      <BitField name="ALL_BANK" description="Bank 2 CRC select bit" start="7" size="1" />
+      <BitField name="CRC_BY_SECT" description="Bank 2 CRC sector mode select bit" start="8" size="1" />
+      <BitField name="ADD_SECT" description="Bank 2 CRC sector select bit" start="9" size="1" />
+      <BitField name="CLEAN_SECT" description="Bank 2 CRC sector list clear bit" start="10" size="1" />
+      <BitField name="START_CRC" description="Bank 2 CRC start bit" start="16" size="1" />
+      <BitField name="CLEAN_CRC" description="Bank 2 CRC clear bit" start="17" size="1" />
+      <BitField name="CRC_BURST" description="Bank 2 CRC burst size" start="20" size="2" />
+    </Register>
+    <Register name="CRCSADD2R" description="FLASH CRC start address register for bank 2" start="+0x154" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CRC_START_ADDR" description="CRC start address on bank 2" start="0" size="32" />
+    </Register>
+    <Register name="CRCEADD2R" description="FLASH CRC end address register for bank 2" start="+0x158" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CRC_END_ADDR" description="CRC end address on bank 2" start="0" size="32" />
+    </Register>
+    <Register name="ECC_FA2R" description="FLASH ECC fail address for bank 2" start="+0x160" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FAIL_ECC_ADDR2" description="Bank 2 ECC error address" start="0" size="15" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="GPIOA" description="GPIO" start="0x58020000">
+    <Register name="MODER" description="GPIO port mode register" start="+0x0" size="4" access="Read/Write" reset_value="0xABFFFFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="MODE0" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O mode." start="0" size="2" />
+      <BitField name="MODE1" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O mode." start="2" size="2" />
+      <BitField name="MODE2" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O mode." start="4" size="2" />
+      <BitField name="MODE3" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O mode." start="6" size="2" />
+      <BitField name="MODE4" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O mode." start="8" size="2" />
+      <BitField name="MODE5" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O mode." start="10" size="2" />
+      <BitField name="MODE6" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O mode." start="12" size="2" />
+      <BitField name="MODE7" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O mode." start="14" size="2" />
+      <BitField name="MODE8" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O mode." start="16" size="2" />
+      <BitField name="MODE9" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O mode." start="18" size="2" />
+      <BitField name="MODE10" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O mode." start="20" size="2" />
+      <BitField name="MODE11" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O mode." start="22" size="2" />
+      <BitField name="MODE12" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O mode." start="24" size="2" />
+      <BitField name="MODE13" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O mode." start="26" size="2" />
+      <BitField name="MODE14" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O mode." start="28" size="2" />
+      <BitField name="MODE15" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O mode." start="30" size="2" />
+    </Register>
+    <Register name="OTYPER" description="GPIO port output type register" start="+0x4" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OT0" description="Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output type." start="0" size="1" />
+      <BitField name="OT1" description="Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output type." start="1" size="1" />
+      <BitField name="OT2" description="Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output type." start="2" size="1" />
+      <BitField name="OT3" description="Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output type." start="3" size="1" />
+      <BitField name="OT4" description="Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output type." start="4" size="1" />
+      <BitField name="OT5" description="Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output type." start="5" size="1" />
+      <BitField name="OT6" description="Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output type." start="6" size="1" />
+      <BitField name="OT7" description="Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output type." start="7" size="1" />
+      <BitField name="OT8" description="Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output type." start="8" size="1" />
+      <BitField name="OT9" description="Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output type." start="9" size="1" />
+      <BitField name="OT10" description="Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output type." start="10" size="1" />
+      <BitField name="OT11" description="Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output type." start="11" size="1" />
+      <BitField name="OT12" description="Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output type." start="12" size="1" />
+      <BitField name="OT13" description="Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output type." start="13" size="1" />
+      <BitField name="OT14" description="Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output type." start="14" size="1" />
+      <BitField name="OT15" description="Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output type." start="15" size="1" />
+    </Register>
+    <Register name="OSPEEDR" description="GPIO port output speed register" start="+0x8" size="4" access="Read/Write" reset_value="0x0C000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OSPEED0" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed." start="0" size="2" />
+      <BitField name="OSPEED1" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed." start="2" size="2" />
+      <BitField name="OSPEED2" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed." start="4" size="2" />
+      <BitField name="OSPEED3" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed." start="6" size="2" />
+      <BitField name="OSPEED4" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed." start="8" size="2" />
+      <BitField name="OSPEED5" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed." start="10" size="2" />
+      <BitField name="OSPEED6" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed." start="12" size="2" />
+      <BitField name="OSPEED7" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed." start="14" size="2" />
+      <BitField name="OSPEED8" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed." start="16" size="2" />
+      <BitField name="OSPEED9" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed." start="18" size="2" />
+      <BitField name="OSPEED10" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed." start="20" size="2" />
+      <BitField name="OSPEED11" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed." start="22" size="2" />
+      <BitField name="OSPEED12" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed." start="24" size="2" />
+      <BitField name="OSPEED13" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed." start="26" size="2" />
+      <BitField name="OSPEED14" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed." start="28" size="2" />
+      <BitField name="OSPEED15" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed." start="30" size="2" />
+    </Register>
+    <Register name="PUPDR" description="GPIO port pull-up/pull-down register" start="+0xC" size="4" access="Read/Write" reset_value="0x12100000" reset_mask="0xFFFFFFFF">
+      <BitField name="PUPD0" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O pull-up or pull-down" start="0" size="2" />
+      <BitField name="PUPD1" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O pull-up or pull-down" start="2" size="2" />
+      <BitField name="PUPD2" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O pull-up or pull-down" start="4" size="2" />
+      <BitField name="PUPD3" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O pull-up or pull-down" start="6" size="2" />
+      <BitField name="PUPD4" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O pull-up or pull-down" start="8" size="2" />
+      <BitField name="PUPD5" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O pull-up or pull-down" start="10" size="2" />
+      <BitField name="PUPD6" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O pull-up or pull-down" start="12" size="2" />
+      <BitField name="PUPD7" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O pull-up or pull-down" start="14" size="2" />
+      <BitField name="PUPD8" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O pull-up or pull-down" start="16" size="2" />
+      <BitField name="PUPD9" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O pull-up or pull-down" start="18" size="2" />
+      <BitField name="PUPD10" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O pull-up or pull-down" start="20" size="2" />
+      <BitField name="PUPD11" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O pull-up or pull-down" start="22" size="2" />
+      <BitField name="PUPD12" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O pull-up or pull-down" start="24" size="2" />
+      <BitField name="PUPD13" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O pull-up or pull-down" start="26" size="2" />
+      <BitField name="PUPD14" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O pull-up or pull-down" start="28" size="2" />
+      <BitField name="PUPD15" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O pull-up or pull-down" start="30" size="2" />
+    </Register>
+    <Register name="IDR" description="GPIO port input data register" start="+0x10" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ID0" description="Port input data bit (y = 0..15) These bits are read-only. They contain the input value of the corresponding I/O port." start="0" size="1" />
+      <BitField name="ID1" description="Port input data bit (y = 0..15) These bits are read-only. They contain the input value of the corresponding I/O port." start="1" size="1" />
+      <BitField name="ID2" description="Port input data bit (y = 0..15) These bits are read-only. They contain the input value of the corresponding I/O port." start="2" size="1" />
+      <BitField name="ID3" description="Port input data bit (y = 0..15) These bits are read-only. They contain the input value of the corresponding I/O port." start="3" size="1" />
+      <BitField name="ID4" description="Port input data bit (y = 0..15) These bits are read-only. They contain the input value of the corresponding I/O port." start="4" size="1" />
+      <BitField name="ID5" description="Port input data bit (y = 0..15) These bits are read-only. They contain the input value of the corresponding I/O port." start="5" size="1" />
+      <BitField name="ID6" description="Port input data bit (y = 0..15) These bits are read-only. They contain the input value of the corresponding I/O port." start="6" size="1" />
+      <BitField name="ID7" description="Port input data bit (y = 0..15) These bits are read-only. They contain the input value of the corresponding I/O port." start="7" size="1" />
+      <BitField name="ID8" description="Port input data bit (y = 0..15) These bits are read-only. They contain the input value of the corresponding I/O port." start="8" size="1" />
+      <BitField name="ID9" description="Port input data bit (y = 0..15) These bits are read-only. They contain the input value of the corresponding I/O port." start="9" size="1" />
+      <BitField name="ID10" description="Port input data bit (y = 0..15) These bits are read-only. They contain the input value of the corresponding I/O port." start="10" size="1" />
+      <BitField name="ID11" description="Port input data bit (y = 0..15) These bits are read-only. They contain the input value of the corresponding I/O port." start="11" size="1" />
+      <BitField name="ID12" description="Port input data bit (y = 0..15) These bits are read-only. They contain the input value of the corresponding I/O port." start="12" size="1" />
+      <BitField name="ID13" description="Port input data bit (y = 0..15) These bits are read-only. They contain the input value of the corresponding I/O port." start="13" size="1" />
+      <BitField name="ID14" description="Port input data bit (y = 0..15) These bits are read-only. They contain the input value of the corresponding I/O port." start="14" size="1" />
+      <BitField name="ID15" description="Port input data bit (y = 0..15) These bits are read-only. They contain the input value of the corresponding I/O port." start="15" size="1" />
+    </Register>
+    <Register name="ODR" description="GPIO port output data register" start="+0x14" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OD0" description="Port output data bit These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR or GPIOx_BRR registers (x = A..F)." start="0" size="1" />
+      <BitField name="OD1" description="Port output data bit These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR or GPIOx_BRR registers (x = A..F)." start="1" size="1" />
+      <BitField name="OD2" description="Port output data bit These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR or GPIOx_BRR registers (x = A..F)." start="2" size="1" />
+      <BitField name="OD3" description="Port output data bit These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR or GPIOx_BRR registers (x = A..F)." start="3" size="1" />
+      <BitField name="OD4" description="Port output data bit These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR or GPIOx_BRR registers (x = A..F)." start="4" size="1" />
+      <BitField name="OD5" description="Port output data bit These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR or GPIOx_BRR registers (x = A..F)." start="5" size="1" />
+      <BitField name="OD6" description="Port output data bit These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR or GPIOx_BRR registers (x = A..F)." start="6" size="1" />
+      <BitField name="OD7" description="Port output data bit These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR or GPIOx_BRR registers (x = A..F)." start="7" size="1" />
+      <BitField name="OD8" description="Port output data bit These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR or GPIOx_BRR registers (x = A..F)." start="8" size="1" />
+      <BitField name="OD9" description="Port output data bit These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR or GPIOx_BRR registers (x = A..F)." start="9" size="1" />
+      <BitField name="OD10" description="Port output data bit These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR or GPIOx_BRR registers (x = A..F)." start="10" size="1" />
+      <BitField name="OD11" description="Port output data bit These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR or GPIOx_BRR registers (x = A..F)." start="11" size="1" />
+      <BitField name="OD12" description="Port output data bit These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR or GPIOx_BRR registers (x = A..F)." start="12" size="1" />
+      <BitField name="OD13" description="Port output data bit These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR or GPIOx_BRR registers (x = A..F)." start="13" size="1" />
+      <BitField name="OD14" description="Port output data bit These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR or GPIOx_BRR registers (x = A..F)." start="14" size="1" />
+      <BitField name="OD15" description="Port output data bit These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR or GPIOx_BRR registers (x = A..F)." start="15" size="1" />
+    </Register>
+    <Register name="BSRR" description="GPIO port bit set/reset register" start="+0x18" size="4" access="WriteOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BS0" description="Port x set bit y (y= 0..15) These bits are write-only. A read to these bits returns the value 0x0000." start="0" size="1" />
+      <BitField name="BS1" description="Port x set bit y (y= 0..15) These bits are write-only. A read to these bits returns the value 0x0000." start="1" size="1" />
+      <BitField name="BS2" description="Port x set bit y (y= 0..15) These bits are write-only. A read to these bits returns the value 0x0000." start="2" size="1" />
+      <BitField name="BS3" description="Port x set bit y (y= 0..15) These bits are write-only. A read to these bits returns the value 0x0000." start="3" size="1" />
+      <BitField name="BS4" description="Port x set bit y (y= 0..15) These bits are write-only. A read to these bits returns the value 0x0000." start="4" size="1" />
+      <BitField name="BS5" description="Port x set bit y (y= 0..15) These bits are write-only. A read to these bits returns the value 0x0000." start="5" size="1" />
+      <BitField name="BS6" description="Port x set bit y (y= 0..15) These bits are write-only. A read to these bits returns the value 0x0000." start="6" size="1" />
+      <BitField name="BS7" description="Port x set bit y (y= 0..15) These bits are write-only. A read to these bits returns the value 0x0000." start="7" size="1" />
+      <BitField name="BS8" description="Port x set bit y (y= 0..15) These bits are write-only. A read to these bits returns the value 0x0000." start="8" size="1" />
+      <BitField name="BS9" description="Port x set bit y (y= 0..15) These bits are write-only. A read to these bits returns the value 0x0000." start="9" size="1" />
+      <BitField name="BS10" description="Port x set bit y (y= 0..15) These bits are write-only. A read to these bits returns the value 0x0000." start="10" size="1" />
+      <BitField name="BS11" description="Port x set bit y (y= 0..15) These bits are write-only. A read to these bits returns the value 0x0000." start="11" size="1" />
+      <BitField name="BS12" description="Port x set bit y (y= 0..15) These bits are write-only. A read to these bits returns the value 0x0000." start="12" size="1" />
+      <BitField name="BS13" description="Port x set bit y (y= 0..15) These bits are write-only. A read to these bits returns the value 0x0000." start="13" size="1" />
+      <BitField name="BS14" description="Port x set bit y (y= 0..15) These bits are write-only. A read to these bits returns the value 0x0000." start="14" size="1" />
+      <BitField name="BS15" description="Port x set bit y (y= 0..15) These bits are write-only. A read to these bits returns the value 0x0000." start="15" size="1" />
+      <BitField name="BR0" description="Port x reset bit y (y = 0..15) These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="16" size="1" />
+      <BitField name="BR1" description="Port x reset bit y (y = 0..15) These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="17" size="1" />
+      <BitField name="BR2" description="Port x reset bit y (y = 0..15) These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="18" size="1" />
+      <BitField name="BR3" description="Port x reset bit y (y = 0..15) These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="19" size="1" />
+      <BitField name="BR4" description="Port x reset bit y (y = 0..15) These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="20" size="1" />
+      <BitField name="BR5" description="Port x reset bit y (y = 0..15) These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="21" size="1" />
+      <BitField name="BR6" description="Port x reset bit y (y = 0..15) These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="22" size="1" />
+      <BitField name="BR7" description="Port x reset bit y (y = 0..15) These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="23" size="1" />
+      <BitField name="BR8" description="Port x reset bit y (y = 0..15) These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="24" size="1" />
+      <BitField name="BR9" description="Port x reset bit y (y = 0..15) These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="25" size="1" />
+      <BitField name="BR10" description="Port x reset bit y (y = 0..15) These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="26" size="1" />
+      <BitField name="BR11" description="Port x reset bit y (y = 0..15) These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="27" size="1" />
+      <BitField name="BR12" description="Port x reset bit y (y = 0..15) These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="28" size="1" />
+      <BitField name="BR13" description="Port x reset bit y (y = 0..15) These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="29" size="1" />
+      <BitField name="BR14" description="Port x reset bit y (y = 0..15) These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="30" size="1" />
+      <BitField name="BR15" description="Port x reset bit y (y = 0..15) These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="31" size="1" />
+    </Register>
+    <Register name="LCKR" description="This register is used to lock the configuration of the port bits when a correct write sequence is applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the GPIO. During the write sequence, the value of LCKR[15:0] must not change. When the LOCK sequence has been applied on a port bit, the value of this port bit can no longer be modified until the next MCU reset or peripheral reset.A specific write sequence is used to write to the GPIOx_LCKR register. Only word access (32-bit long) is allowed during this locking sequence.Each lock bit freezes a specific configuration register (control and alternate function registers)." start="+0x1C" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LCK0" description="Port x lock bit y (y= 0..15) These bits are read/write but can only be written when the LCKK bit is 0." start="0" size="1" />
+      <BitField name="LCK1" description="Port x lock bit y (y= 0..15) These bits are read/write but can only be written when the LCKK bit is 0." start="1" size="1" />
+      <BitField name="LCK2" description="Port x lock bit y (y= 0..15) These bits are read/write but can only be written when the LCKK bit is 0." start="2" size="1" />
+      <BitField name="LCK3" description="Port x lock bit y (y= 0..15) These bits are read/write but can only be written when the LCKK bit is 0." start="3" size="1" />
+      <BitField name="LCK4" description="Port x lock bit y (y= 0..15) These bits are read/write but can only be written when the LCKK bit is 0." start="4" size="1" />
+      <BitField name="LCK5" description="Port x lock bit y (y= 0..15) These bits are read/write but can only be written when the LCKK bit is 0." start="5" size="1" />
+      <BitField name="LCK6" description="Port x lock bit y (y= 0..15) These bits are read/write but can only be written when the LCKK bit is 0." start="6" size="1" />
+      <BitField name="LCK7" description="Port x lock bit y (y= 0..15) These bits are read/write but can only be written when the LCKK bit is 0." start="7" size="1" />
+      <BitField name="LCK8" description="Port x lock bit y (y= 0..15) These bits are read/write but can only be written when the LCKK bit is 0." start="8" size="1" />
+      <BitField name="LCK9" description="Port x lock bit y (y= 0..15) These bits are read/write but can only be written when the LCKK bit is 0." start="9" size="1" />
+      <BitField name="LCK10" description="Port x lock bit y (y= 0..15) These bits are read/write but can only be written when the LCKK bit is 0." start="10" size="1" />
+      <BitField name="LCK11" description="Port x lock bit y (y= 0..15) These bits are read/write but can only be written when the LCKK bit is 0." start="11" size="1" />
+      <BitField name="LCK12" description="Port x lock bit y (y= 0..15) These bits are read/write but can only be written when the LCKK bit is 0." start="12" size="1" />
+      <BitField name="LCK13" description="Port x lock bit y (y= 0..15) These bits are read/write but can only be written when the LCKK bit is 0." start="13" size="1" />
+      <BitField name="LCK14" description="Port x lock bit y (y= 0..15) These bits are read/write but can only be written when the LCKK bit is 0." start="14" size="1" />
+      <BitField name="LCK15" description="Port x lock bit y (y= 0..15) These bits are read/write but can only be written when the LCKK bit is 0." start="15" size="1" />
+      <BitField name="LCKK" description="Lock key This bit can be read any time. It can only be modified using the lock key write sequence. LOCK key write sequence: WR LCKR[16] = 1 + LCKR[15:0] WR LCKR[16] = 0 + LCKR[15:0] WR LCKR[16] = 1 + LCKR[15:0] RD LCKR RD LCKR[16] = 1 (this read operation is optional but it confirms that the lock is active) Note: During the LOCK key write sequence, the value of LCK[15:0] must not change. Any error in the lock sequence aborts the lock. After the first lock sequence on any bit of the port, any read access on the LCKK bit will return 1 until the next MCU reset or peripheral reset." start="16" size="1" />
+    </Register>
+    <Register name="AFRL" description="GPIO alternate function low register" start="+0x20" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AFSEL0" description="[3:0]: Alternate function selection for port x pin y (y = 0..7) These bits are written by software to configure alternate function I/Os AFSELy selection:" start="0" size="4" />
+      <BitField name="AFSEL1" description="[3:0]: Alternate function selection for port x pin y (y = 0..7) These bits are written by software to configure alternate function I/Os AFSELy selection:" start="4" size="4" />
+      <BitField name="AFSEL2" description="[3:0]: Alternate function selection for port x pin y (y = 0..7) These bits are written by software to configure alternate function I/Os AFSELy selection:" start="8" size="4" />
+      <BitField name="AFSEL3" description="[3:0]: Alternate function selection for port x pin y (y = 0..7) These bits are written by software to configure alternate function I/Os AFSELy selection:" start="12" size="4" />
+      <BitField name="AFSEL4" description="[3:0]: Alternate function selection for port x pin y (y = 0..7) These bits are written by software to configure alternate function I/Os AFSELy selection:" start="16" size="4" />
+      <BitField name="AFSEL5" description="[3:0]: Alternate function selection for port x pin y (y = 0..7) These bits are written by software to configure alternate function I/Os AFSELy selection:" start="20" size="4" />
+      <BitField name="AFSEL6" description="[3:0]: Alternate function selection for port x pin y (y = 0..7) These bits are written by software to configure alternate function I/Os AFSELy selection:" start="24" size="4" />
+      <BitField name="AFSEL7" description="[3:0]: Alternate function selection for port x pin y (y = 0..7) These bits are written by software to configure alternate function I/Os AFSELy selection:" start="28" size="4" />
+    </Register>
+    <Register name="AFRH" description="GPIO alternate function high register" start="+0x24" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AFSEL8" description="[3:0]: Alternate function selection for port x pin y (y = 8..15) These bits are written by software to configure alternate function I/Os" start="0" size="4" />
+      <BitField name="AFSEL9" description="[3:0]: Alternate function selection for port x pin y (y = 8..15) These bits are written by software to configure alternate function I/Os" start="4" size="4" />
+      <BitField name="AFSEL10" description="[3:0]: Alternate function selection for port x pin y (y = 8..15) These bits are written by software to configure alternate function I/Os" start="8" size="4" />
+      <BitField name="AFSEL11" description="[3:0]: Alternate function selection for port x pin y (y = 8..15) These bits are written by software to configure alternate function I/Os" start="12" size="4" />
+      <BitField name="AFSEL12" description="[3:0]: Alternate function selection for port x pin y (y = 8..15) These bits are written by software to configure alternate function I/Os" start="16" size="4" />
+      <BitField name="AFSEL13" description="[3:0]: Alternate function selection for port x pin y (y = 8..15) These bits are written by software to configure alternate function I/Os" start="20" size="4" />
+      <BitField name="AFSEL14" description="[3:0]: Alternate function selection for port x pin y (y = 8..15) These bits are written by software to configure alternate function I/Os" start="24" size="4" />
+      <BitField name="AFSEL15" description="[3:0]: Alternate function selection for port x pin y (y = 8..15) These bits are written by software to configure alternate function I/Os" start="28" size="4" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="GPIOB" description="GPIO" start="0x58020400">
+    <Register name="MODER" description="GPIO port mode register" start="+0x0" size="4" access="Read/Write" reset_value="0xABFFFFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="MODE0" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O mode." start="0" size="2" />
+      <BitField name="MODE1" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O mode." start="2" size="2" />
+      <BitField name="MODE2" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O mode." start="4" size="2" />
+      <BitField name="MODE3" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O mode." start="6" size="2" />
+      <BitField name="MODE4" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O mode." start="8" size="2" />
+      <BitField name="MODE5" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O mode." start="10" size="2" />
+      <BitField name="MODE6" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O mode." start="12" size="2" />
+      <BitField name="MODE7" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O mode." start="14" size="2" />
+      <BitField name="MODE8" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O mode." start="16" size="2" />
+      <BitField name="MODE9" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O mode." start="18" size="2" />
+      <BitField name="MODE10" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O mode." start="20" size="2" />
+      <BitField name="MODE11" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O mode." start="22" size="2" />
+      <BitField name="MODE12" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O mode." start="24" size="2" />
+      <BitField name="MODE13" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O mode." start="26" size="2" />
+      <BitField name="MODE14" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O mode." start="28" size="2" />
+      <BitField name="MODE15" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O mode." start="30" size="2" />
+    </Register>
+    <Register name="OTYPER" description="GPIO port output type register" start="+0x4" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OT0" description="Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output type." start="0" size="1" />
+      <BitField name="OT1" description="Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output type." start="1" size="1" />
+      <BitField name="OT2" description="Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output type." start="2" size="1" />
+      <BitField name="OT3" description="Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output type." start="3" size="1" />
+      <BitField name="OT4" description="Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output type." start="4" size="1" />
+      <BitField name="OT5" description="Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output type." start="5" size="1" />
+      <BitField name="OT6" description="Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output type." start="6" size="1" />
+      <BitField name="OT7" description="Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output type." start="7" size="1" />
+      <BitField name="OT8" description="Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output type." start="8" size="1" />
+      <BitField name="OT9" description="Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output type." start="9" size="1" />
+      <BitField name="OT10" description="Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output type." start="10" size="1" />
+      <BitField name="OT11" description="Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output type." start="11" size="1" />
+      <BitField name="OT12" description="Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output type." start="12" size="1" />
+      <BitField name="OT13" description="Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output type." start="13" size="1" />
+      <BitField name="OT14" description="Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output type." start="14" size="1" />
+      <BitField name="OT15" description="Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output type." start="15" size="1" />
+    </Register>
+    <Register name="OSPEEDR" description="GPIO port output speed register" start="+0x8" size="4" access="Read/Write" reset_value="0x0C000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OSPEED0" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed." start="0" size="2" />
+      <BitField name="OSPEED1" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed." start="2" size="2" />
+      <BitField name="OSPEED2" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed." start="4" size="2" />
+      <BitField name="OSPEED3" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed." start="6" size="2" />
+      <BitField name="OSPEED4" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed." start="8" size="2" />
+      <BitField name="OSPEED5" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed." start="10" size="2" />
+      <BitField name="OSPEED6" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed." start="12" size="2" />
+      <BitField name="OSPEED7" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed." start="14" size="2" />
+      <BitField name="OSPEED8" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed." start="16" size="2" />
+      <BitField name="OSPEED9" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed." start="18" size="2" />
+      <BitField name="OSPEED10" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed." start="20" size="2" />
+      <BitField name="OSPEED11" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed." start="22" size="2" />
+      <BitField name="OSPEED12" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed." start="24" size="2" />
+      <BitField name="OSPEED13" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed." start="26" size="2" />
+      <BitField name="OSPEED14" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed." start="28" size="2" />
+      <BitField name="OSPEED15" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed." start="30" size="2" />
+    </Register>
+    <Register name="PUPDR" description="GPIO port pull-up/pull-down register" start="+0xC" size="4" access="Read/Write" reset_value="0x12100000" reset_mask="0xFFFFFFFF">
+      <BitField name="PUPD0" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O pull-up or pull-down" start="0" size="2" />
+      <BitField name="PUPD1" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O pull-up or pull-down" start="2" size="2" />
+      <BitField name="PUPD2" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O pull-up or pull-down" start="4" size="2" />
+      <BitField name="PUPD3" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O pull-up or pull-down" start="6" size="2" />
+      <BitField name="PUPD4" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O pull-up or pull-down" start="8" size="2" />
+      <BitField name="PUPD5" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O pull-up or pull-down" start="10" size="2" />
+      <BitField name="PUPD6" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O pull-up or pull-down" start="12" size="2" />
+      <BitField name="PUPD7" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O pull-up or pull-down" start="14" size="2" />
+      <BitField name="PUPD8" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O pull-up or pull-down" start="16" size="2" />
+      <BitField name="PUPD9" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O pull-up or pull-down" start="18" size="2" />
+      <BitField name="PUPD10" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O pull-up or pull-down" start="20" size="2" />
+      <BitField name="PUPD11" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O pull-up or pull-down" start="22" size="2" />
+      <BitField name="PUPD12" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O pull-up or pull-down" start="24" size="2" />
+      <BitField name="PUPD13" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O pull-up or pull-down" start="26" size="2" />
+      <BitField name="PUPD14" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O pull-up or pull-down" start="28" size="2" />
+      <BitField name="PUPD15" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O pull-up or pull-down" start="30" size="2" />
+    </Register>
+    <Register name="IDR" description="GPIO port input data register" start="+0x10" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ID0" description="Port input data bit (y = 0..15) These bits are read-only. They contain the input value of the corresponding I/O port." start="0" size="1" />
+      <BitField name="ID1" description="Port input data bit (y = 0..15) These bits are read-only. They contain the input value of the corresponding I/O port." start="1" size="1" />
+      <BitField name="ID2" description="Port input data bit (y = 0..15) These bits are read-only. They contain the input value of the corresponding I/O port." start="2" size="1" />
+      <BitField name="ID3" description="Port input data bit (y = 0..15) These bits are read-only. They contain the input value of the corresponding I/O port." start="3" size="1" />
+      <BitField name="ID4" description="Port input data bit (y = 0..15) These bits are read-only. They contain the input value of the corresponding I/O port." start="4" size="1" />
+      <BitField name="ID5" description="Port input data bit (y = 0..15) These bits are read-only. They contain the input value of the corresponding I/O port." start="5" size="1" />
+      <BitField name="ID6" description="Port input data bit (y = 0..15) These bits are read-only. They contain the input value of the corresponding I/O port." start="6" size="1" />
+      <BitField name="ID7" description="Port input data bit (y = 0..15) These bits are read-only. They contain the input value of the corresponding I/O port." start="7" size="1" />
+      <BitField name="ID8" description="Port input data bit (y = 0..15) These bits are read-only. They contain the input value of the corresponding I/O port." start="8" size="1" />
+      <BitField name="ID9" description="Port input data bit (y = 0..15) These bits are read-only. They contain the input value of the corresponding I/O port." start="9" size="1" />
+      <BitField name="ID10" description="Port input data bit (y = 0..15) These bits are read-only. They contain the input value of the corresponding I/O port." start="10" size="1" />
+      <BitField name="ID11" description="Port input data bit (y = 0..15) These bits are read-only. They contain the input value of the corresponding I/O port." start="11" size="1" />
+      <BitField name="ID12" description="Port input data bit (y = 0..15) These bits are read-only. They contain the input value of the corresponding I/O port." start="12" size="1" />
+      <BitField name="ID13" description="Port input data bit (y = 0..15) These bits are read-only. They contain the input value of the corresponding I/O port." start="13" size="1" />
+      <BitField name="ID14" description="Port input data bit (y = 0..15) These bits are read-only. They contain the input value of the corresponding I/O port." start="14" size="1" />
+      <BitField name="ID15" description="Port input data bit (y = 0..15) These bits are read-only. They contain the input value of the corresponding I/O port." start="15" size="1" />
+    </Register>
+    <Register name="ODR" description="GPIO port output data register" start="+0x14" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OD0" description="Port output data bit These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR or GPIOx_BRR registers (x = A..F)." start="0" size="1" />
+      <BitField name="OD1" description="Port output data bit These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR or GPIOx_BRR registers (x = A..F)." start="1" size="1" />
+      <BitField name="OD2" description="Port output data bit These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR or GPIOx_BRR registers (x = A..F)." start="2" size="1" />
+      <BitField name="OD3" description="Port output data bit These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR or GPIOx_BRR registers (x = A..F)." start="3" size="1" />
+      <BitField name="OD4" description="Port output data bit These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR or GPIOx_BRR registers (x = A..F)." start="4" size="1" />
+      <BitField name="OD5" description="Port output data bit These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR or GPIOx_BRR registers (x = A..F)." start="5" size="1" />
+      <BitField name="OD6" description="Port output data bit These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR or GPIOx_BRR registers (x = A..F)." start="6" size="1" />
+      <BitField name="OD7" description="Port output data bit These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR or GPIOx_BRR registers (x = A..F)." start="7" size="1" />
+      <BitField name="OD8" description="Port output data bit These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR or GPIOx_BRR registers (x = A..F)." start="8" size="1" />
+      <BitField name="OD9" description="Port output data bit These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR or GPIOx_BRR registers (x = A..F)." start="9" size="1" />
+      <BitField name="OD10" description="Port output data bit These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR or GPIOx_BRR registers (x = A..F)." start="10" size="1" />
+      <BitField name="OD11" description="Port output data bit These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR or GPIOx_BRR registers (x = A..F)." start="11" size="1" />
+      <BitField name="OD12" description="Port output data bit These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR or GPIOx_BRR registers (x = A..F)." start="12" size="1" />
+      <BitField name="OD13" description="Port output data bit These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR or GPIOx_BRR registers (x = A..F)." start="13" size="1" />
+      <BitField name="OD14" description="Port output data bit These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR or GPIOx_BRR registers (x = A..F)." start="14" size="1" />
+      <BitField name="OD15" description="Port output data bit These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR or GPIOx_BRR registers (x = A..F)." start="15" size="1" />
+    </Register>
+    <Register name="BSRR" description="GPIO port bit set/reset register" start="+0x18" size="4" access="WriteOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BS0" description="Port x set bit y (y= 0..15) These bits are write-only. A read to these bits returns the value 0x0000." start="0" size="1" />
+      <BitField name="BS1" description="Port x set bit y (y= 0..15) These bits are write-only. A read to these bits returns the value 0x0000." start="1" size="1" />
+      <BitField name="BS2" description="Port x set bit y (y= 0..15) These bits are write-only. A read to these bits returns the value 0x0000." start="2" size="1" />
+      <BitField name="BS3" description="Port x set bit y (y= 0..15) These bits are write-only. A read to these bits returns the value 0x0000." start="3" size="1" />
+      <BitField name="BS4" description="Port x set bit y (y= 0..15) These bits are write-only. A read to these bits returns the value 0x0000." start="4" size="1" />
+      <BitField name="BS5" description="Port x set bit y (y= 0..15) These bits are write-only. A read to these bits returns the value 0x0000." start="5" size="1" />
+      <BitField name="BS6" description="Port x set bit y (y= 0..15) These bits are write-only. A read to these bits returns the value 0x0000." start="6" size="1" />
+      <BitField name="BS7" description="Port x set bit y (y= 0..15) These bits are write-only. A read to these bits returns the value 0x0000." start="7" size="1" />
+      <BitField name="BS8" description="Port x set bit y (y= 0..15) These bits are write-only. A read to these bits returns the value 0x0000." start="8" size="1" />
+      <BitField name="BS9" description="Port x set bit y (y= 0..15) These bits are write-only. A read to these bits returns the value 0x0000." start="9" size="1" />
+      <BitField name="BS10" description="Port x set bit y (y= 0..15) These bits are write-only. A read to these bits returns the value 0x0000." start="10" size="1" />
+      <BitField name="BS11" description="Port x set bit y (y= 0..15) These bits are write-only. A read to these bits returns the value 0x0000." start="11" size="1" />
+      <BitField name="BS12" description="Port x set bit y (y= 0..15) These bits are write-only. A read to these bits returns the value 0x0000." start="12" size="1" />
+      <BitField name="BS13" description="Port x set bit y (y= 0..15) These bits are write-only. A read to these bits returns the value 0x0000." start="13" size="1" />
+      <BitField name="BS14" description="Port x set bit y (y= 0..15) These bits are write-only. A read to these bits returns the value 0x0000." start="14" size="1" />
+      <BitField name="BS15" description="Port x set bit y (y= 0..15) These bits are write-only. A read to these bits returns the value 0x0000." start="15" size="1" />
+      <BitField name="BR0" description="Port x reset bit y (y = 0..15) These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="16" size="1" />
+      <BitField name="BR1" description="Port x reset bit y (y = 0..15) These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="17" size="1" />
+      <BitField name="BR2" description="Port x reset bit y (y = 0..15) These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="18" size="1" />
+      <BitField name="BR3" description="Port x reset bit y (y = 0..15) These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="19" size="1" />
+      <BitField name="BR4" description="Port x reset bit y (y = 0..15) These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="20" size="1" />
+      <BitField name="BR5" description="Port x reset bit y (y = 0..15) These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="21" size="1" />
+      <BitField name="BR6" description="Port x reset bit y (y = 0..15) These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="22" size="1" />
+      <BitField name="BR7" description="Port x reset bit y (y = 0..15) These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="23" size="1" />
+      <BitField name="BR8" description="Port x reset bit y (y = 0..15) These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="24" size="1" />
+      <BitField name="BR9" description="Port x reset bit y (y = 0..15) These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="25" size="1" />
+      <BitField name="BR10" description="Port x reset bit y (y = 0..15) These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="26" size="1" />
+      <BitField name="BR11" description="Port x reset bit y (y = 0..15) These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="27" size="1" />
+      <BitField name="BR12" description="Port x reset bit y (y = 0..15) These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="28" size="1" />
+      <BitField name="BR13" description="Port x reset bit y (y = 0..15) These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="29" size="1" />
+      <BitField name="BR14" description="Port x reset bit y (y = 0..15) These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="30" size="1" />
+      <BitField name="BR15" description="Port x reset bit y (y = 0..15) These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="31" size="1" />
+    </Register>
+    <Register name="LCKR" description="This register is used to lock the configuration of the port bits when a correct write sequence is applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the GPIO. During the write sequence, the value of LCKR[15:0] must not change. When the LOCK sequence has been applied on a port bit, the value of this port bit can no longer be modified until the next MCU reset or peripheral reset.A specific write sequence is used to write to the GPIOx_LCKR register. Only word access (32-bit long) is allowed during this locking sequence.Each lock bit freezes a specific configuration register (control and alternate function registers)." start="+0x1C" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LCK0" description="Port x lock bit y (y= 0..15) These bits are read/write but can only be written when the LCKK bit is 0." start="0" size="1" />
+      <BitField name="LCK1" description="Port x lock bit y (y= 0..15) These bits are read/write but can only be written when the LCKK bit is 0." start="1" size="1" />
+      <BitField name="LCK2" description="Port x lock bit y (y= 0..15) These bits are read/write but can only be written when the LCKK bit is 0." start="2" size="1" />
+      <BitField name="LCK3" description="Port x lock bit y (y= 0..15) These bits are read/write but can only be written when the LCKK bit is 0." start="3" size="1" />
+      <BitField name="LCK4" description="Port x lock bit y (y= 0..15) These bits are read/write but can only be written when the LCKK bit is 0." start="4" size="1" />
+      <BitField name="LCK5" description="Port x lock bit y (y= 0..15) These bits are read/write but can only be written when the LCKK bit is 0." start="5" size="1" />
+      <BitField name="LCK6" description="Port x lock bit y (y= 0..15) These bits are read/write but can only be written when the LCKK bit is 0." start="6" size="1" />
+      <BitField name="LCK7" description="Port x lock bit y (y= 0..15) These bits are read/write but can only be written when the LCKK bit is 0." start="7" size="1" />
+      <BitField name="LCK8" description="Port x lock bit y (y= 0..15) These bits are read/write but can only be written when the LCKK bit is 0." start="8" size="1" />
+      <BitField name="LCK9" description="Port x lock bit y (y= 0..15) These bits are read/write but can only be written when the LCKK bit is 0." start="9" size="1" />
+      <BitField name="LCK10" description="Port x lock bit y (y= 0..15) These bits are read/write but can only be written when the LCKK bit is 0." start="10" size="1" />
+      <BitField name="LCK11" description="Port x lock bit y (y= 0..15) These bits are read/write but can only be written when the LCKK bit is 0." start="11" size="1" />
+      <BitField name="LCK12" description="Port x lock bit y (y= 0..15) These bits are read/write but can only be written when the LCKK bit is 0." start="12" size="1" />
+      <BitField name="LCK13" description="Port x lock bit y (y= 0..15) These bits are read/write but can only be written when the LCKK bit is 0." start="13" size="1" />
+      <BitField name="LCK14" description="Port x lock bit y (y= 0..15) These bits are read/write but can only be written when the LCKK bit is 0." start="14" size="1" />
+      <BitField name="LCK15" description="Port x lock bit y (y= 0..15) These bits are read/write but can only be written when the LCKK bit is 0." start="15" size="1" />
+      <BitField name="LCKK" description="Lock key This bit can be read any time. It can only be modified using the lock key write sequence. LOCK key write sequence: WR LCKR[16] = 1 + LCKR[15:0] WR LCKR[16] = 0 + LCKR[15:0] WR LCKR[16] = 1 + LCKR[15:0] RD LCKR RD LCKR[16] = 1 (this read operation is optional but it confirms that the lock is active) Note: During the LOCK key write sequence, the value of LCK[15:0] must not change. Any error in the lock sequence aborts the lock. After the first lock sequence on any bit of the port, any read access on the LCKK bit will return 1 until the next MCU reset or peripheral reset." start="16" size="1" />
+    </Register>
+    <Register name="AFRL" description="GPIO alternate function low register" start="+0x20" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AFSEL0" description="[3:0]: Alternate function selection for port x pin y (y = 0..7) These bits are written by software to configure alternate function I/Os AFSELy selection:" start="0" size="4" />
+      <BitField name="AFSEL1" description="[3:0]: Alternate function selection for port x pin y (y = 0..7) These bits are written by software to configure alternate function I/Os AFSELy selection:" start="4" size="4" />
+      <BitField name="AFSEL2" description="[3:0]: Alternate function selection for port x pin y (y = 0..7) These bits are written by software to configure alternate function I/Os AFSELy selection:" start="8" size="4" />
+      <BitField name="AFSEL3" description="[3:0]: Alternate function selection for port x pin y (y = 0..7) These bits are written by software to configure alternate function I/Os AFSELy selection:" start="12" size="4" />
+      <BitField name="AFSEL4" description="[3:0]: Alternate function selection for port x pin y (y = 0..7) These bits are written by software to configure alternate function I/Os AFSELy selection:" start="16" size="4" />
+      <BitField name="AFSEL5" description="[3:0]: Alternate function selection for port x pin y (y = 0..7) These bits are written by software to configure alternate function I/Os AFSELy selection:" start="20" size="4" />
+      <BitField name="AFSEL6" description="[3:0]: Alternate function selection for port x pin y (y = 0..7) These bits are written by software to configure alternate function I/Os AFSELy selection:" start="24" size="4" />
+      <BitField name="AFSEL7" description="[3:0]: Alternate function selection for port x pin y (y = 0..7) These bits are written by software to configure alternate function I/Os AFSELy selection:" start="28" size="4" />
+    </Register>
+    <Register name="AFRH" description="GPIO alternate function high register" start="+0x24" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AFSEL8" description="[3:0]: Alternate function selection for port x pin y (y = 8..15) These bits are written by software to configure alternate function I/Os" start="0" size="4" />
+      <BitField name="AFSEL9" description="[3:0]: Alternate function selection for port x pin y (y = 8..15) These bits are written by software to configure alternate function I/Os" start="4" size="4" />
+      <BitField name="AFSEL10" description="[3:0]: Alternate function selection for port x pin y (y = 8..15) These bits are written by software to configure alternate function I/Os" start="8" size="4" />
+      <BitField name="AFSEL11" description="[3:0]: Alternate function selection for port x pin y (y = 8..15) These bits are written by software to configure alternate function I/Os" start="12" size="4" />
+      <BitField name="AFSEL12" description="[3:0]: Alternate function selection for port x pin y (y = 8..15) These bits are written by software to configure alternate function I/Os" start="16" size="4" />
+      <BitField name="AFSEL13" description="[3:0]: Alternate function selection for port x pin y (y = 8..15) These bits are written by software to configure alternate function I/Os" start="20" size="4" />
+      <BitField name="AFSEL14" description="[3:0]: Alternate function selection for port x pin y (y = 8..15) These bits are written by software to configure alternate function I/Os" start="24" size="4" />
+      <BitField name="AFSEL15" description="[3:0]: Alternate function selection for port x pin y (y = 8..15) These bits are written by software to configure alternate function I/Os" start="28" size="4" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="GPIOC" description="GPIO" start="0x58020800">
+    <Register name="MODER" description="GPIO port mode register" start="+0x0" size="4" access="Read/Write" reset_value="0xABFFFFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="MODE0" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O mode." start="0" size="2" />
+      <BitField name="MODE1" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O mode." start="2" size="2" />
+      <BitField name="MODE2" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O mode." start="4" size="2" />
+      <BitField name="MODE3" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O mode." start="6" size="2" />
+      <BitField name="MODE4" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O mode." start="8" size="2" />
+      <BitField name="MODE5" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O mode." start="10" size="2" />
+      <BitField name="MODE6" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O mode." start="12" size="2" />
+      <BitField name="MODE7" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O mode." start="14" size="2" />
+      <BitField name="MODE8" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O mode." start="16" size="2" />
+      <BitField name="MODE9" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O mode." start="18" size="2" />
+      <BitField name="MODE10" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O mode." start="20" size="2" />
+      <BitField name="MODE11" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O mode." start="22" size="2" />
+      <BitField name="MODE12" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O mode." start="24" size="2" />
+      <BitField name="MODE13" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O mode." start="26" size="2" />
+      <BitField name="MODE14" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O mode." start="28" size="2" />
+      <BitField name="MODE15" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O mode." start="30" size="2" />
+    </Register>
+    <Register name="OTYPER" description="GPIO port output type register" start="+0x4" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OT0" description="Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output type." start="0" size="1" />
+      <BitField name="OT1" description="Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output type." start="1" size="1" />
+      <BitField name="OT2" description="Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output type." start="2" size="1" />
+      <BitField name="OT3" description="Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output type." start="3" size="1" />
+      <BitField name="OT4" description="Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output type." start="4" size="1" />
+      <BitField name="OT5" description="Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output type." start="5" size="1" />
+      <BitField name="OT6" description="Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output type." start="6" size="1" />
+      <BitField name="OT7" description="Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output type." start="7" size="1" />
+      <BitField name="OT8" description="Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output type." start="8" size="1" />
+      <BitField name="OT9" description="Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output type." start="9" size="1" />
+      <BitField name="OT10" description="Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output type." start="10" size="1" />
+      <BitField name="OT11" description="Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output type." start="11" size="1" />
+      <BitField name="OT12" description="Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output type." start="12" size="1" />
+      <BitField name="OT13" description="Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output type." start="13" size="1" />
+      <BitField name="OT14" description="Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output type." start="14" size="1" />
+      <BitField name="OT15" description="Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output type." start="15" size="1" />
+    </Register>
+    <Register name="OSPEEDR" description="GPIO port output speed register" start="+0x8" size="4" access="Read/Write" reset_value="0x0C000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OSPEED0" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed." start="0" size="2" />
+      <BitField name="OSPEED1" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed." start="2" size="2" />
+      <BitField name="OSPEED2" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed." start="4" size="2" />
+      <BitField name="OSPEED3" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed." start="6" size="2" />
+      <BitField name="OSPEED4" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed." start="8" size="2" />
+      <BitField name="OSPEED5" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed." start="10" size="2" />
+      <BitField name="OSPEED6" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed." start="12" size="2" />
+      <BitField name="OSPEED7" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed." start="14" size="2" />
+      <BitField name="OSPEED8" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed." start="16" size="2" />
+      <BitField name="OSPEED9" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed." start="18" size="2" />
+      <BitField name="OSPEED10" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed." start="20" size="2" />
+      <BitField name="OSPEED11" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed." start="22" size="2" />
+      <BitField name="OSPEED12" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed." start="24" size="2" />
+      <BitField name="OSPEED13" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed." start="26" size="2" />
+      <BitField name="OSPEED14" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed." start="28" size="2" />
+      <BitField name="OSPEED15" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed." start="30" size="2" />
+    </Register>
+    <Register name="PUPDR" description="GPIO port pull-up/pull-down register" start="+0xC" size="4" access="Read/Write" reset_value="0x12100000" reset_mask="0xFFFFFFFF">
+      <BitField name="PUPD0" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O pull-up or pull-down" start="0" size="2" />
+      <BitField name="PUPD1" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O pull-up or pull-down" start="2" size="2" />
+      <BitField name="PUPD2" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O pull-up or pull-down" start="4" size="2" />
+      <BitField name="PUPD3" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O pull-up or pull-down" start="6" size="2" />
+      <BitField name="PUPD4" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O pull-up or pull-down" start="8" size="2" />
+      <BitField name="PUPD5" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O pull-up or pull-down" start="10" size="2" />
+      <BitField name="PUPD6" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O pull-up or pull-down" start="12" size="2" />
+      <BitField name="PUPD7" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O pull-up or pull-down" start="14" size="2" />
+      <BitField name="PUPD8" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O pull-up or pull-down" start="16" size="2" />
+      <BitField name="PUPD9" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O pull-up or pull-down" start="18" size="2" />
+      <BitField name="PUPD10" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O pull-up or pull-down" start="20" size="2" />
+      <BitField name="PUPD11" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O pull-up or pull-down" start="22" size="2" />
+      <BitField name="PUPD12" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O pull-up or pull-down" start="24" size="2" />
+      <BitField name="PUPD13" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O pull-up or pull-down" start="26" size="2" />
+      <BitField name="PUPD14" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O pull-up or pull-down" start="28" size="2" />
+      <BitField name="PUPD15" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O pull-up or pull-down" start="30" size="2" />
+    </Register>
+    <Register name="IDR" description="GPIO port input data register" start="+0x10" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ID0" description="Port input data bit (y = 0..15) These bits are read-only. They contain the input value of the corresponding I/O port." start="0" size="1" />
+      <BitField name="ID1" description="Port input data bit (y = 0..15) These bits are read-only. They contain the input value of the corresponding I/O port." start="1" size="1" />
+      <BitField name="ID2" description="Port input data bit (y = 0..15) These bits are read-only. They contain the input value of the corresponding I/O port." start="2" size="1" />
+      <BitField name="ID3" description="Port input data bit (y = 0..15) These bits are read-only. They contain the input value of the corresponding I/O port." start="3" size="1" />
+      <BitField name="ID4" description="Port input data bit (y = 0..15) These bits are read-only. They contain the input value of the corresponding I/O port." start="4" size="1" />
+      <BitField name="ID5" description="Port input data bit (y = 0..15) These bits are read-only. They contain the input value of the corresponding I/O port." start="5" size="1" />
+      <BitField name="ID6" description="Port input data bit (y = 0..15) These bits are read-only. They contain the input value of the corresponding I/O port." start="6" size="1" />
+      <BitField name="ID7" description="Port input data bit (y = 0..15) These bits are read-only. They contain the input value of the corresponding I/O port." start="7" size="1" />
+      <BitField name="ID8" description="Port input data bit (y = 0..15) These bits are read-only. They contain the input value of the corresponding I/O port." start="8" size="1" />
+      <BitField name="ID9" description="Port input data bit (y = 0..15) These bits are read-only. They contain the input value of the corresponding I/O port." start="9" size="1" />
+      <BitField name="ID10" description="Port input data bit (y = 0..15) These bits are read-only. They contain the input value of the corresponding I/O port." start="10" size="1" />
+      <BitField name="ID11" description="Port input data bit (y = 0..15) These bits are read-only. They contain the input value of the corresponding I/O port." start="11" size="1" />
+      <BitField name="ID12" description="Port input data bit (y = 0..15) These bits are read-only. They contain the input value of the corresponding I/O port." start="12" size="1" />
+      <BitField name="ID13" description="Port input data bit (y = 0..15) These bits are read-only. They contain the input value of the corresponding I/O port." start="13" size="1" />
+      <BitField name="ID14" description="Port input data bit (y = 0..15) These bits are read-only. They contain the input value of the corresponding I/O port." start="14" size="1" />
+      <BitField name="ID15" description="Port input data bit (y = 0..15) These bits are read-only. They contain the input value of the corresponding I/O port." start="15" size="1" />
+    </Register>
+    <Register name="ODR" description="GPIO port output data register" start="+0x14" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OD0" description="Port output data bit These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR or GPIOx_BRR registers (x = A..F)." start="0" size="1" />
+      <BitField name="OD1" description="Port output data bit These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR or GPIOx_BRR registers (x = A..F)." start="1" size="1" />
+      <BitField name="OD2" description="Port output data bit These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR or GPIOx_BRR registers (x = A..F)." start="2" size="1" />
+      <BitField name="OD3" description="Port output data bit These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR or GPIOx_BRR registers (x = A..F)." start="3" size="1" />
+      <BitField name="OD4" description="Port output data bit These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR or GPIOx_BRR registers (x = A..F)." start="4" size="1" />
+      <BitField name="OD5" description="Port output data bit These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR or GPIOx_BRR registers (x = A..F)." start="5" size="1" />
+      <BitField name="OD6" description="Port output data bit These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR or GPIOx_BRR registers (x = A..F)." start="6" size="1" />
+      <BitField name="OD7" description="Port output data bit These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR or GPIOx_BRR registers (x = A..F)." start="7" size="1" />
+      <BitField name="OD8" description="Port output data bit These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR or GPIOx_BRR registers (x = A..F)." start="8" size="1" />
+      <BitField name="OD9" description="Port output data bit These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR or GPIOx_BRR registers (x = A..F)." start="9" size="1" />
+      <BitField name="OD10" description="Port output data bit These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR or GPIOx_BRR registers (x = A..F)." start="10" size="1" />
+      <BitField name="OD11" description="Port output data bit These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR or GPIOx_BRR registers (x = A..F)." start="11" size="1" />
+      <BitField name="OD12" description="Port output data bit These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR or GPIOx_BRR registers (x = A..F)." start="12" size="1" />
+      <BitField name="OD13" description="Port output data bit These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR or GPIOx_BRR registers (x = A..F)." start="13" size="1" />
+      <BitField name="OD14" description="Port output data bit These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR or GPIOx_BRR registers (x = A..F)." start="14" size="1" />
+      <BitField name="OD15" description="Port output data bit These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR or GPIOx_BRR registers (x = A..F)." start="15" size="1" />
+    </Register>
+    <Register name="BSRR" description="GPIO port bit set/reset register" start="+0x18" size="4" access="WriteOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BS0" description="Port x set bit y (y= 0..15) These bits are write-only. A read to these bits returns the value 0x0000." start="0" size="1" />
+      <BitField name="BS1" description="Port x set bit y (y= 0..15) These bits are write-only. A read to these bits returns the value 0x0000." start="1" size="1" />
+      <BitField name="BS2" description="Port x set bit y (y= 0..15) These bits are write-only. A read to these bits returns the value 0x0000." start="2" size="1" />
+      <BitField name="BS3" description="Port x set bit y (y= 0..15) These bits are write-only. A read to these bits returns the value 0x0000." start="3" size="1" />
+      <BitField name="BS4" description="Port x set bit y (y= 0..15) These bits are write-only. A read to these bits returns the value 0x0000." start="4" size="1" />
+      <BitField name="BS5" description="Port x set bit y (y= 0..15) These bits are write-only. A read to these bits returns the value 0x0000." start="5" size="1" />
+      <BitField name="BS6" description="Port x set bit y (y= 0..15) These bits are write-only. A read to these bits returns the value 0x0000." start="6" size="1" />
+      <BitField name="BS7" description="Port x set bit y (y= 0..15) These bits are write-only. A read to these bits returns the value 0x0000." start="7" size="1" />
+      <BitField name="BS8" description="Port x set bit y (y= 0..15) These bits are write-only. A read to these bits returns the value 0x0000." start="8" size="1" />
+      <BitField name="BS9" description="Port x set bit y (y= 0..15) These bits are write-only. A read to these bits returns the value 0x0000." start="9" size="1" />
+      <BitField name="BS10" description="Port x set bit y (y= 0..15) These bits are write-only. A read to these bits returns the value 0x0000." start="10" size="1" />
+      <BitField name="BS11" description="Port x set bit y (y= 0..15) These bits are write-only. A read to these bits returns the value 0x0000." start="11" size="1" />
+      <BitField name="BS12" description="Port x set bit y (y= 0..15) These bits are write-only. A read to these bits returns the value 0x0000." start="12" size="1" />
+      <BitField name="BS13" description="Port x set bit y (y= 0..15) These bits are write-only. A read to these bits returns the value 0x0000." start="13" size="1" />
+      <BitField name="BS14" description="Port x set bit y (y= 0..15) These bits are write-only. A read to these bits returns the value 0x0000." start="14" size="1" />
+      <BitField name="BS15" description="Port x set bit y (y= 0..15) These bits are write-only. A read to these bits returns the value 0x0000." start="15" size="1" />
+      <BitField name="BR0" description="Port x reset bit y (y = 0..15) These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="16" size="1" />
+      <BitField name="BR1" description="Port x reset bit y (y = 0..15) These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="17" size="1" />
+      <BitField name="BR2" description="Port x reset bit y (y = 0..15) These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="18" size="1" />
+      <BitField name="BR3" description="Port x reset bit y (y = 0..15) These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="19" size="1" />
+      <BitField name="BR4" description="Port x reset bit y (y = 0..15) These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="20" size="1" />
+      <BitField name="BR5" description="Port x reset bit y (y = 0..15) These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="21" size="1" />
+      <BitField name="BR6" description="Port x reset bit y (y = 0..15) These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="22" size="1" />
+      <BitField name="BR7" description="Port x reset bit y (y = 0..15) These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="23" size="1" />
+      <BitField name="BR8" description="Port x reset bit y (y = 0..15) These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="24" size="1" />
+      <BitField name="BR9" description="Port x reset bit y (y = 0..15) These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="25" size="1" />
+      <BitField name="BR10" description="Port x reset bit y (y = 0..15) These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="26" size="1" />
+      <BitField name="BR11" description="Port x reset bit y (y = 0..15) These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="27" size="1" />
+      <BitField name="BR12" description="Port x reset bit y (y = 0..15) These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="28" size="1" />
+      <BitField name="BR13" description="Port x reset bit y (y = 0..15) These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="29" size="1" />
+      <BitField name="BR14" description="Port x reset bit y (y = 0..15) These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="30" size="1" />
+      <BitField name="BR15" description="Port x reset bit y (y = 0..15) These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="31" size="1" />
+    </Register>
+    <Register name="LCKR" description="This register is used to lock the configuration of the port bits when a correct write sequence is applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the GPIO. During the write sequence, the value of LCKR[15:0] must not change. When the LOCK sequence has been applied on a port bit, the value of this port bit can no longer be modified until the next MCU reset or peripheral reset.A specific write sequence is used to write to the GPIOx_LCKR register. Only word access (32-bit long) is allowed during this locking sequence.Each lock bit freezes a specific configuration register (control and alternate function registers)." start="+0x1C" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LCK0" description="Port x lock bit y (y= 0..15) These bits are read/write but can only be written when the LCKK bit is 0." start="0" size="1" />
+      <BitField name="LCK1" description="Port x lock bit y (y= 0..15) These bits are read/write but can only be written when the LCKK bit is 0." start="1" size="1" />
+      <BitField name="LCK2" description="Port x lock bit y (y= 0..15) These bits are read/write but can only be written when the LCKK bit is 0." start="2" size="1" />
+      <BitField name="LCK3" description="Port x lock bit y (y= 0..15) These bits are read/write but can only be written when the LCKK bit is 0." start="3" size="1" />
+      <BitField name="LCK4" description="Port x lock bit y (y= 0..15) These bits are read/write but can only be written when the LCKK bit is 0." start="4" size="1" />
+      <BitField name="LCK5" description="Port x lock bit y (y= 0..15) These bits are read/write but can only be written when the LCKK bit is 0." start="5" size="1" />
+      <BitField name="LCK6" description="Port x lock bit y (y= 0..15) These bits are read/write but can only be written when the LCKK bit is 0." start="6" size="1" />
+      <BitField name="LCK7" description="Port x lock bit y (y= 0..15) These bits are read/write but can only be written when the LCKK bit is 0." start="7" size="1" />
+      <BitField name="LCK8" description="Port x lock bit y (y= 0..15) These bits are read/write but can only be written when the LCKK bit is 0." start="8" size="1" />
+      <BitField name="LCK9" description="Port x lock bit y (y= 0..15) These bits are read/write but can only be written when the LCKK bit is 0." start="9" size="1" />
+      <BitField name="LCK10" description="Port x lock bit y (y= 0..15) These bits are read/write but can only be written when the LCKK bit is 0." start="10" size="1" />
+      <BitField name="LCK11" description="Port x lock bit y (y= 0..15) These bits are read/write but can only be written when the LCKK bit is 0." start="11" size="1" />
+      <BitField name="LCK12" description="Port x lock bit y (y= 0..15) These bits are read/write but can only be written when the LCKK bit is 0." start="12" size="1" />
+      <BitField name="LCK13" description="Port x lock bit y (y= 0..15) These bits are read/write but can only be written when the LCKK bit is 0." start="13" size="1" />
+      <BitField name="LCK14" description="Port x lock bit y (y= 0..15) These bits are read/write but can only be written when the LCKK bit is 0." start="14" size="1" />
+      <BitField name="LCK15" description="Port x lock bit y (y= 0..15) These bits are read/write but can only be written when the LCKK bit is 0." start="15" size="1" />
+      <BitField name="LCKK" description="Lock key This bit can be read any time. It can only be modified using the lock key write sequence. LOCK key write sequence: WR LCKR[16] = 1 + LCKR[15:0] WR LCKR[16] = 0 + LCKR[15:0] WR LCKR[16] = 1 + LCKR[15:0] RD LCKR RD LCKR[16] = 1 (this read operation is optional but it confirms that the lock is active) Note: During the LOCK key write sequence, the value of LCK[15:0] must not change. Any error in the lock sequence aborts the lock. After the first lock sequence on any bit of the port, any read access on the LCKK bit will return 1 until the next MCU reset or peripheral reset." start="16" size="1" />
+    </Register>
+    <Register name="AFRL" description="GPIO alternate function low register" start="+0x20" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AFSEL0" description="[3:0]: Alternate function selection for port x pin y (y = 0..7) These bits are written by software to configure alternate function I/Os AFSELy selection:" start="0" size="4" />
+      <BitField name="AFSEL1" description="[3:0]: Alternate function selection for port x pin y (y = 0..7) These bits are written by software to configure alternate function I/Os AFSELy selection:" start="4" size="4" />
+      <BitField name="AFSEL2" description="[3:0]: Alternate function selection for port x pin y (y = 0..7) These bits are written by software to configure alternate function I/Os AFSELy selection:" start="8" size="4" />
+      <BitField name="AFSEL3" description="[3:0]: Alternate function selection for port x pin y (y = 0..7) These bits are written by software to configure alternate function I/Os AFSELy selection:" start="12" size="4" />
+      <BitField name="AFSEL4" description="[3:0]: Alternate function selection for port x pin y (y = 0..7) These bits are written by software to configure alternate function I/Os AFSELy selection:" start="16" size="4" />
+      <BitField name="AFSEL5" description="[3:0]: Alternate function selection for port x pin y (y = 0..7) These bits are written by software to configure alternate function I/Os AFSELy selection:" start="20" size="4" />
+      <BitField name="AFSEL6" description="[3:0]: Alternate function selection for port x pin y (y = 0..7) These bits are written by software to configure alternate function I/Os AFSELy selection:" start="24" size="4" />
+      <BitField name="AFSEL7" description="[3:0]: Alternate function selection for port x pin y (y = 0..7) These bits are written by software to configure alternate function I/Os AFSELy selection:" start="28" size="4" />
+    </Register>
+    <Register name="AFRH" description="GPIO alternate function high register" start="+0x24" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AFSEL8" description="[3:0]: Alternate function selection for port x pin y (y = 8..15) These bits are written by software to configure alternate function I/Os" start="0" size="4" />
+      <BitField name="AFSEL9" description="[3:0]: Alternate function selection for port x pin y (y = 8..15) These bits are written by software to configure alternate function I/Os" start="4" size="4" />
+      <BitField name="AFSEL10" description="[3:0]: Alternate function selection for port x pin y (y = 8..15) These bits are written by software to configure alternate function I/Os" start="8" size="4" />
+      <BitField name="AFSEL11" description="[3:0]: Alternate function selection for port x pin y (y = 8..15) These bits are written by software to configure alternate function I/Os" start="12" size="4" />
+      <BitField name="AFSEL12" description="[3:0]: Alternate function selection for port x pin y (y = 8..15) These bits are written by software to configure alternate function I/Os" start="16" size="4" />
+      <BitField name="AFSEL13" description="[3:0]: Alternate function selection for port x pin y (y = 8..15) These bits are written by software to configure alternate function I/Os" start="20" size="4" />
+      <BitField name="AFSEL14" description="[3:0]: Alternate function selection for port x pin y (y = 8..15) These bits are written by software to configure alternate function I/Os" start="24" size="4" />
+      <BitField name="AFSEL15" description="[3:0]: Alternate function selection for port x pin y (y = 8..15) These bits are written by software to configure alternate function I/Os" start="28" size="4" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="GPIOD" description="GPIO" start="0x58020C00">
+    <Register name="MODER" description="GPIO port mode register" start="+0x0" size="4" access="Read/Write" reset_value="0xABFFFFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="MODE0" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O mode." start="0" size="2" />
+      <BitField name="MODE1" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O mode." start="2" size="2" />
+      <BitField name="MODE2" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O mode." start="4" size="2" />
+      <BitField name="MODE3" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O mode." start="6" size="2" />
+      <BitField name="MODE4" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O mode." start="8" size="2" />
+      <BitField name="MODE5" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O mode." start="10" size="2" />
+      <BitField name="MODE6" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O mode." start="12" size="2" />
+      <BitField name="MODE7" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O mode." start="14" size="2" />
+      <BitField name="MODE8" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O mode." start="16" size="2" />
+      <BitField name="MODE9" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O mode." start="18" size="2" />
+      <BitField name="MODE10" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O mode." start="20" size="2" />
+      <BitField name="MODE11" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O mode." start="22" size="2" />
+      <BitField name="MODE12" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O mode." start="24" size="2" />
+      <BitField name="MODE13" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O mode." start="26" size="2" />
+      <BitField name="MODE14" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O mode." start="28" size="2" />
+      <BitField name="MODE15" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O mode." start="30" size="2" />
+    </Register>
+    <Register name="OTYPER" description="GPIO port output type register" start="+0x4" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OT0" description="Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output type." start="0" size="1" />
+      <BitField name="OT1" description="Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output type." start="1" size="1" />
+      <BitField name="OT2" description="Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output type." start="2" size="1" />
+      <BitField name="OT3" description="Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output type." start="3" size="1" />
+      <BitField name="OT4" description="Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output type." start="4" size="1" />
+      <BitField name="OT5" description="Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output type." start="5" size="1" />
+      <BitField name="OT6" description="Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output type." start="6" size="1" />
+      <BitField name="OT7" description="Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output type." start="7" size="1" />
+      <BitField name="OT8" description="Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output type." start="8" size="1" />
+      <BitField name="OT9" description="Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output type." start="9" size="1" />
+      <BitField name="OT10" description="Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output type." start="10" size="1" />
+      <BitField name="OT11" description="Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output type." start="11" size="1" />
+      <BitField name="OT12" description="Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output type." start="12" size="1" />
+      <BitField name="OT13" description="Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output type." start="13" size="1" />
+      <BitField name="OT14" description="Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output type." start="14" size="1" />
+      <BitField name="OT15" description="Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output type." start="15" size="1" />
+    </Register>
+    <Register name="OSPEEDR" description="GPIO port output speed register" start="+0x8" size="4" access="Read/Write" reset_value="0x0C000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OSPEED0" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed." start="0" size="2" />
+      <BitField name="OSPEED1" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed." start="2" size="2" />
+      <BitField name="OSPEED2" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed." start="4" size="2" />
+      <BitField name="OSPEED3" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed." start="6" size="2" />
+      <BitField name="OSPEED4" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed." start="8" size="2" />
+      <BitField name="OSPEED5" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed." start="10" size="2" />
+      <BitField name="OSPEED6" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed." start="12" size="2" />
+      <BitField name="OSPEED7" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed." start="14" size="2" />
+      <BitField name="OSPEED8" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed." start="16" size="2" />
+      <BitField name="OSPEED9" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed." start="18" size="2" />
+      <BitField name="OSPEED10" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed." start="20" size="2" />
+      <BitField name="OSPEED11" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed." start="22" size="2" />
+      <BitField name="OSPEED12" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed." start="24" size="2" />
+      <BitField name="OSPEED13" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed." start="26" size="2" />
+      <BitField name="OSPEED14" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed." start="28" size="2" />
+      <BitField name="OSPEED15" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed." start="30" size="2" />
+    </Register>
+    <Register name="PUPDR" description="GPIO port pull-up/pull-down register" start="+0xC" size="4" access="Read/Write" reset_value="0x12100000" reset_mask="0xFFFFFFFF">
+      <BitField name="PUPD0" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O pull-up or pull-down" start="0" size="2" />
+      <BitField name="PUPD1" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O pull-up or pull-down" start="2" size="2" />
+      <BitField name="PUPD2" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O pull-up or pull-down" start="4" size="2" />
+      <BitField name="PUPD3" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O pull-up or pull-down" start="6" size="2" />
+      <BitField name="PUPD4" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O pull-up or pull-down" start="8" size="2" />
+      <BitField name="PUPD5" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O pull-up or pull-down" start="10" size="2" />
+      <BitField name="PUPD6" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O pull-up or pull-down" start="12" size="2" />
+      <BitField name="PUPD7" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O pull-up or pull-down" start="14" size="2" />
+      <BitField name="PUPD8" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O pull-up or pull-down" start="16" size="2" />
+      <BitField name="PUPD9" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O pull-up or pull-down" start="18" size="2" />
+      <BitField name="PUPD10" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O pull-up or pull-down" start="20" size="2" />
+      <BitField name="PUPD11" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O pull-up or pull-down" start="22" size="2" />
+      <BitField name="PUPD12" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O pull-up or pull-down" start="24" size="2" />
+      <BitField name="PUPD13" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O pull-up or pull-down" start="26" size="2" />
+      <BitField name="PUPD14" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O pull-up or pull-down" start="28" size="2" />
+      <BitField name="PUPD15" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O pull-up or pull-down" start="30" size="2" />
+    </Register>
+    <Register name="IDR" description="GPIO port input data register" start="+0x10" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ID0" description="Port input data bit (y = 0..15) These bits are read-only. They contain the input value of the corresponding I/O port." start="0" size="1" />
+      <BitField name="ID1" description="Port input data bit (y = 0..15) These bits are read-only. They contain the input value of the corresponding I/O port." start="1" size="1" />
+      <BitField name="ID2" description="Port input data bit (y = 0..15) These bits are read-only. They contain the input value of the corresponding I/O port." start="2" size="1" />
+      <BitField name="ID3" description="Port input data bit (y = 0..15) These bits are read-only. They contain the input value of the corresponding I/O port." start="3" size="1" />
+      <BitField name="ID4" description="Port input data bit (y = 0..15) These bits are read-only. They contain the input value of the corresponding I/O port." start="4" size="1" />
+      <BitField name="ID5" description="Port input data bit (y = 0..15) These bits are read-only. They contain the input value of the corresponding I/O port." start="5" size="1" />
+      <BitField name="ID6" description="Port input data bit (y = 0..15) These bits are read-only. They contain the input value of the corresponding I/O port." start="6" size="1" />
+      <BitField name="ID7" description="Port input data bit (y = 0..15) These bits are read-only. They contain the input value of the corresponding I/O port." start="7" size="1" />
+      <BitField name="ID8" description="Port input data bit (y = 0..15) These bits are read-only. They contain the input value of the corresponding I/O port." start="8" size="1" />
+      <BitField name="ID9" description="Port input data bit (y = 0..15) These bits are read-only. They contain the input value of the corresponding I/O port." start="9" size="1" />
+      <BitField name="ID10" description="Port input data bit (y = 0..15) These bits are read-only. They contain the input value of the corresponding I/O port." start="10" size="1" />
+      <BitField name="ID11" description="Port input data bit (y = 0..15) These bits are read-only. They contain the input value of the corresponding I/O port." start="11" size="1" />
+      <BitField name="ID12" description="Port input data bit (y = 0..15) These bits are read-only. They contain the input value of the corresponding I/O port." start="12" size="1" />
+      <BitField name="ID13" description="Port input data bit (y = 0..15) These bits are read-only. They contain the input value of the corresponding I/O port." start="13" size="1" />
+      <BitField name="ID14" description="Port input data bit (y = 0..15) These bits are read-only. They contain the input value of the corresponding I/O port." start="14" size="1" />
+      <BitField name="ID15" description="Port input data bit (y = 0..15) These bits are read-only. They contain the input value of the corresponding I/O port." start="15" size="1" />
+    </Register>
+    <Register name="ODR" description="GPIO port output data register" start="+0x14" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OD0" description="Port output data bit These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR or GPIOx_BRR registers (x = A..F)." start="0" size="1" />
+      <BitField name="OD1" description="Port output data bit These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR or GPIOx_BRR registers (x = A..F)." start="1" size="1" />
+      <BitField name="OD2" description="Port output data bit These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR or GPIOx_BRR registers (x = A..F)." start="2" size="1" />
+      <BitField name="OD3" description="Port output data bit These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR or GPIOx_BRR registers (x = A..F)." start="3" size="1" />
+      <BitField name="OD4" description="Port output data bit These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR or GPIOx_BRR registers (x = A..F)." start="4" size="1" />
+      <BitField name="OD5" description="Port output data bit These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR or GPIOx_BRR registers (x = A..F)." start="5" size="1" />
+      <BitField name="OD6" description="Port output data bit These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR or GPIOx_BRR registers (x = A..F)." start="6" size="1" />
+      <BitField name="OD7" description="Port output data bit These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR or GPIOx_BRR registers (x = A..F)." start="7" size="1" />
+      <BitField name="OD8" description="Port output data bit These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR or GPIOx_BRR registers (x = A..F)." start="8" size="1" />
+      <BitField name="OD9" description="Port output data bit These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR or GPIOx_BRR registers (x = A..F)." start="9" size="1" />
+      <BitField name="OD10" description="Port output data bit These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR or GPIOx_BRR registers (x = A..F)." start="10" size="1" />
+      <BitField name="OD11" description="Port output data bit These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR or GPIOx_BRR registers (x = A..F)." start="11" size="1" />
+      <BitField name="OD12" description="Port output data bit These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR or GPIOx_BRR registers (x = A..F)." start="12" size="1" />
+      <BitField name="OD13" description="Port output data bit These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR or GPIOx_BRR registers (x = A..F)." start="13" size="1" />
+      <BitField name="OD14" description="Port output data bit These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR or GPIOx_BRR registers (x = A..F)." start="14" size="1" />
+      <BitField name="OD15" description="Port output data bit These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR or GPIOx_BRR registers (x = A..F)." start="15" size="1" />
+    </Register>
+    <Register name="BSRR" description="GPIO port bit set/reset register" start="+0x18" size="4" access="WriteOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BS0" description="Port x set bit y (y= 0..15) These bits are write-only. A read to these bits returns the value 0x0000." start="0" size="1" />
+      <BitField name="BS1" description="Port x set bit y (y= 0..15) These bits are write-only. A read to these bits returns the value 0x0000." start="1" size="1" />
+      <BitField name="BS2" description="Port x set bit y (y= 0..15) These bits are write-only. A read to these bits returns the value 0x0000." start="2" size="1" />
+      <BitField name="BS3" description="Port x set bit y (y= 0..15) These bits are write-only. A read to these bits returns the value 0x0000." start="3" size="1" />
+      <BitField name="BS4" description="Port x set bit y (y= 0..15) These bits are write-only. A read to these bits returns the value 0x0000." start="4" size="1" />
+      <BitField name="BS5" description="Port x set bit y (y= 0..15) These bits are write-only. A read to these bits returns the value 0x0000." start="5" size="1" />
+      <BitField name="BS6" description="Port x set bit y (y= 0..15) These bits are write-only. A read to these bits returns the value 0x0000." start="6" size="1" />
+      <BitField name="BS7" description="Port x set bit y (y= 0..15) These bits are write-only. A read to these bits returns the value 0x0000." start="7" size="1" />
+      <BitField name="BS8" description="Port x set bit y (y= 0..15) These bits are write-only. A read to these bits returns the value 0x0000." start="8" size="1" />
+      <BitField name="BS9" description="Port x set bit y (y= 0..15) These bits are write-only. A read to these bits returns the value 0x0000." start="9" size="1" />
+      <BitField name="BS10" description="Port x set bit y (y= 0..15) These bits are write-only. A read to these bits returns the value 0x0000." start="10" size="1" />
+      <BitField name="BS11" description="Port x set bit y (y= 0..15) These bits are write-only. A read to these bits returns the value 0x0000." start="11" size="1" />
+      <BitField name="BS12" description="Port x set bit y (y= 0..15) These bits are write-only. A read to these bits returns the value 0x0000." start="12" size="1" />
+      <BitField name="BS13" description="Port x set bit y (y= 0..15) These bits are write-only. A read to these bits returns the value 0x0000." start="13" size="1" />
+      <BitField name="BS14" description="Port x set bit y (y= 0..15) These bits are write-only. A read to these bits returns the value 0x0000." start="14" size="1" />
+      <BitField name="BS15" description="Port x set bit y (y= 0..15) These bits are write-only. A read to these bits returns the value 0x0000." start="15" size="1" />
+      <BitField name="BR0" description="Port x reset bit y (y = 0..15) These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="16" size="1" />
+      <BitField name="BR1" description="Port x reset bit y (y = 0..15) These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="17" size="1" />
+      <BitField name="BR2" description="Port x reset bit y (y = 0..15) These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="18" size="1" />
+      <BitField name="BR3" description="Port x reset bit y (y = 0..15) These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="19" size="1" />
+      <BitField name="BR4" description="Port x reset bit y (y = 0..15) These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="20" size="1" />
+      <BitField name="BR5" description="Port x reset bit y (y = 0..15) These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="21" size="1" />
+      <BitField name="BR6" description="Port x reset bit y (y = 0..15) These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="22" size="1" />
+      <BitField name="BR7" description="Port x reset bit y (y = 0..15) These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="23" size="1" />
+      <BitField name="BR8" description="Port x reset bit y (y = 0..15) These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="24" size="1" />
+      <BitField name="BR9" description="Port x reset bit y (y = 0..15) These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="25" size="1" />
+      <BitField name="BR10" description="Port x reset bit y (y = 0..15) These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="26" size="1" />
+      <BitField name="BR11" description="Port x reset bit y (y = 0..15) These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="27" size="1" />
+      <BitField name="BR12" description="Port x reset bit y (y = 0..15) These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="28" size="1" />
+      <BitField name="BR13" description="Port x reset bit y (y = 0..15) These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="29" size="1" />
+      <BitField name="BR14" description="Port x reset bit y (y = 0..15) These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="30" size="1" />
+      <BitField name="BR15" description="Port x reset bit y (y = 0..15) These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="31" size="1" />
+    </Register>
+    <Register name="LCKR" description="This register is used to lock the configuration of the port bits when a correct write sequence is applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the GPIO. During the write sequence, the value of LCKR[15:0] must not change. When the LOCK sequence has been applied on a port bit, the value of this port bit can no longer be modified until the next MCU reset or peripheral reset.A specific write sequence is used to write to the GPIOx_LCKR register. Only word access (32-bit long) is allowed during this locking sequence.Each lock bit freezes a specific configuration register (control and alternate function registers)." start="+0x1C" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LCK0" description="Port x lock bit y (y= 0..15) These bits are read/write but can only be written when the LCKK bit is 0." start="0" size="1" />
+      <BitField name="LCK1" description="Port x lock bit y (y= 0..15) These bits are read/write but can only be written when the LCKK bit is 0." start="1" size="1" />
+      <BitField name="LCK2" description="Port x lock bit y (y= 0..15) These bits are read/write but can only be written when the LCKK bit is 0." start="2" size="1" />
+      <BitField name="LCK3" description="Port x lock bit y (y= 0..15) These bits are read/write but can only be written when the LCKK bit is 0." start="3" size="1" />
+      <BitField name="LCK4" description="Port x lock bit y (y= 0..15) These bits are read/write but can only be written when the LCKK bit is 0." start="4" size="1" />
+      <BitField name="LCK5" description="Port x lock bit y (y= 0..15) These bits are read/write but can only be written when the LCKK bit is 0." start="5" size="1" />
+      <BitField name="LCK6" description="Port x lock bit y (y= 0..15) These bits are read/write but can only be written when the LCKK bit is 0." start="6" size="1" />
+      <BitField name="LCK7" description="Port x lock bit y (y= 0..15) These bits are read/write but can only be written when the LCKK bit is 0." start="7" size="1" />
+      <BitField name="LCK8" description="Port x lock bit y (y= 0..15) These bits are read/write but can only be written when the LCKK bit is 0." start="8" size="1" />
+      <BitField name="LCK9" description="Port x lock bit y (y= 0..15) These bits are read/write but can only be written when the LCKK bit is 0." start="9" size="1" />
+      <BitField name="LCK10" description="Port x lock bit y (y= 0..15) These bits are read/write but can only be written when the LCKK bit is 0." start="10" size="1" />
+      <BitField name="LCK11" description="Port x lock bit y (y= 0..15) These bits are read/write but can only be written when the LCKK bit is 0." start="11" size="1" />
+      <BitField name="LCK12" description="Port x lock bit y (y= 0..15) These bits are read/write but can only be written when the LCKK bit is 0." start="12" size="1" />
+      <BitField name="LCK13" description="Port x lock bit y (y= 0..15) These bits are read/write but can only be written when the LCKK bit is 0." start="13" size="1" />
+      <BitField name="LCK14" description="Port x lock bit y (y= 0..15) These bits are read/write but can only be written when the LCKK bit is 0." start="14" size="1" />
+      <BitField name="LCK15" description="Port x lock bit y (y= 0..15) These bits are read/write but can only be written when the LCKK bit is 0." start="15" size="1" />
+      <BitField name="LCKK" description="Lock key This bit can be read any time. It can only be modified using the lock key write sequence. LOCK key write sequence: WR LCKR[16] = 1 + LCKR[15:0] WR LCKR[16] = 0 + LCKR[15:0] WR LCKR[16] = 1 + LCKR[15:0] RD LCKR RD LCKR[16] = 1 (this read operation is optional but it confirms that the lock is active) Note: During the LOCK key write sequence, the value of LCK[15:0] must not change. Any error in the lock sequence aborts the lock. After the first lock sequence on any bit of the port, any read access on the LCKK bit will return 1 until the next MCU reset or peripheral reset." start="16" size="1" />
+    </Register>
+    <Register name="AFRL" description="GPIO alternate function low register" start="+0x20" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AFSEL0" description="[3:0]: Alternate function selection for port x pin y (y = 0..7) These bits are written by software to configure alternate function I/Os AFSELy selection:" start="0" size="4" />
+      <BitField name="AFSEL1" description="[3:0]: Alternate function selection for port x pin y (y = 0..7) These bits are written by software to configure alternate function I/Os AFSELy selection:" start="4" size="4" />
+      <BitField name="AFSEL2" description="[3:0]: Alternate function selection for port x pin y (y = 0..7) These bits are written by software to configure alternate function I/Os AFSELy selection:" start="8" size="4" />
+      <BitField name="AFSEL3" description="[3:0]: Alternate function selection for port x pin y (y = 0..7) These bits are written by software to configure alternate function I/Os AFSELy selection:" start="12" size="4" />
+      <BitField name="AFSEL4" description="[3:0]: Alternate function selection for port x pin y (y = 0..7) These bits are written by software to configure alternate function I/Os AFSELy selection:" start="16" size="4" />
+      <BitField name="AFSEL5" description="[3:0]: Alternate function selection for port x pin y (y = 0..7) These bits are written by software to configure alternate function I/Os AFSELy selection:" start="20" size="4" />
+      <BitField name="AFSEL6" description="[3:0]: Alternate function selection for port x pin y (y = 0..7) These bits are written by software to configure alternate function I/Os AFSELy selection:" start="24" size="4" />
+      <BitField name="AFSEL7" description="[3:0]: Alternate function selection for port x pin y (y = 0..7) These bits are written by software to configure alternate function I/Os AFSELy selection:" start="28" size="4" />
+    </Register>
+    <Register name="AFRH" description="GPIO alternate function high register" start="+0x24" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AFSEL8" description="[3:0]: Alternate function selection for port x pin y (y = 8..15) These bits are written by software to configure alternate function I/Os" start="0" size="4" />
+      <BitField name="AFSEL9" description="[3:0]: Alternate function selection for port x pin y (y = 8..15) These bits are written by software to configure alternate function I/Os" start="4" size="4" />
+      <BitField name="AFSEL10" description="[3:0]: Alternate function selection for port x pin y (y = 8..15) These bits are written by software to configure alternate function I/Os" start="8" size="4" />
+      <BitField name="AFSEL11" description="[3:0]: Alternate function selection for port x pin y (y = 8..15) These bits are written by software to configure alternate function I/Os" start="12" size="4" />
+      <BitField name="AFSEL12" description="[3:0]: Alternate function selection for port x pin y (y = 8..15) These bits are written by software to configure alternate function I/Os" start="16" size="4" />
+      <BitField name="AFSEL13" description="[3:0]: Alternate function selection for port x pin y (y = 8..15) These bits are written by software to configure alternate function I/Os" start="20" size="4" />
+      <BitField name="AFSEL14" description="[3:0]: Alternate function selection for port x pin y (y = 8..15) These bits are written by software to configure alternate function I/Os" start="24" size="4" />
+      <BitField name="AFSEL15" description="[3:0]: Alternate function selection for port x pin y (y = 8..15) These bits are written by software to configure alternate function I/Os" start="28" size="4" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="GPIOE" description="GPIO" start="0x58021000">
+    <Register name="MODER" description="GPIO port mode register" start="+0x0" size="4" access="Read/Write" reset_value="0xABFFFFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="MODE0" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O mode." start="0" size="2" />
+      <BitField name="MODE1" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O mode." start="2" size="2" />
+      <BitField name="MODE2" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O mode." start="4" size="2" />
+      <BitField name="MODE3" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O mode." start="6" size="2" />
+      <BitField name="MODE4" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O mode." start="8" size="2" />
+      <BitField name="MODE5" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O mode." start="10" size="2" />
+      <BitField name="MODE6" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O mode." start="12" size="2" />
+      <BitField name="MODE7" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O mode." start="14" size="2" />
+      <BitField name="MODE8" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O mode." start="16" size="2" />
+      <BitField name="MODE9" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O mode." start="18" size="2" />
+      <BitField name="MODE10" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O mode." start="20" size="2" />
+      <BitField name="MODE11" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O mode." start="22" size="2" />
+      <BitField name="MODE12" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O mode." start="24" size="2" />
+      <BitField name="MODE13" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O mode." start="26" size="2" />
+      <BitField name="MODE14" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O mode." start="28" size="2" />
+      <BitField name="MODE15" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O mode." start="30" size="2" />
+    </Register>
+    <Register name="OTYPER" description="GPIO port output type register" start="+0x4" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OT0" description="Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output type." start="0" size="1" />
+      <BitField name="OT1" description="Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output type." start="1" size="1" />
+      <BitField name="OT2" description="Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output type." start="2" size="1" />
+      <BitField name="OT3" description="Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output type." start="3" size="1" />
+      <BitField name="OT4" description="Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output type." start="4" size="1" />
+      <BitField name="OT5" description="Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output type." start="5" size="1" />
+      <BitField name="OT6" description="Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output type." start="6" size="1" />
+      <BitField name="OT7" description="Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output type." start="7" size="1" />
+      <BitField name="OT8" description="Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output type." start="8" size="1" />
+      <BitField name="OT9" description="Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output type." start="9" size="1" />
+      <BitField name="OT10" description="Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output type." start="10" size="1" />
+      <BitField name="OT11" description="Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output type." start="11" size="1" />
+      <BitField name="OT12" description="Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output type." start="12" size="1" />
+      <BitField name="OT13" description="Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output type." start="13" size="1" />
+      <BitField name="OT14" description="Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output type." start="14" size="1" />
+      <BitField name="OT15" description="Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output type." start="15" size="1" />
+    </Register>
+    <Register name="OSPEEDR" description="GPIO port output speed register" start="+0x8" size="4" access="Read/Write" reset_value="0x0C000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OSPEED0" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed." start="0" size="2" />
+      <BitField name="OSPEED1" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed." start="2" size="2" />
+      <BitField name="OSPEED2" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed." start="4" size="2" />
+      <BitField name="OSPEED3" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed." start="6" size="2" />
+      <BitField name="OSPEED4" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed." start="8" size="2" />
+      <BitField name="OSPEED5" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed." start="10" size="2" />
+      <BitField name="OSPEED6" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed." start="12" size="2" />
+      <BitField name="OSPEED7" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed." start="14" size="2" />
+      <BitField name="OSPEED8" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed." start="16" size="2" />
+      <BitField name="OSPEED9" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed." start="18" size="2" />
+      <BitField name="OSPEED10" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed." start="20" size="2" />
+      <BitField name="OSPEED11" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed." start="22" size="2" />
+      <BitField name="OSPEED12" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed." start="24" size="2" />
+      <BitField name="OSPEED13" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed." start="26" size="2" />
+      <BitField name="OSPEED14" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed." start="28" size="2" />
+      <BitField name="OSPEED15" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed." start="30" size="2" />
+    </Register>
+    <Register name="PUPDR" description="GPIO port pull-up/pull-down register" start="+0xC" size="4" access="Read/Write" reset_value="0x12100000" reset_mask="0xFFFFFFFF">
+      <BitField name="PUPD0" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O pull-up or pull-down" start="0" size="2" />
+      <BitField name="PUPD1" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O pull-up or pull-down" start="2" size="2" />
+      <BitField name="PUPD2" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O pull-up or pull-down" start="4" size="2" />
+      <BitField name="PUPD3" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O pull-up or pull-down" start="6" size="2" />
+      <BitField name="PUPD4" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O pull-up or pull-down" start="8" size="2" />
+      <BitField name="PUPD5" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O pull-up or pull-down" start="10" size="2" />
+      <BitField name="PUPD6" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O pull-up or pull-down" start="12" size="2" />
+      <BitField name="PUPD7" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O pull-up or pull-down" start="14" size="2" />
+      <BitField name="PUPD8" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O pull-up or pull-down" start="16" size="2" />
+      <BitField name="PUPD9" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O pull-up or pull-down" start="18" size="2" />
+      <BitField name="PUPD10" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O pull-up or pull-down" start="20" size="2" />
+      <BitField name="PUPD11" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O pull-up or pull-down" start="22" size="2" />
+      <BitField name="PUPD12" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O pull-up or pull-down" start="24" size="2" />
+      <BitField name="PUPD13" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O pull-up or pull-down" start="26" size="2" />
+      <BitField name="PUPD14" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O pull-up or pull-down" start="28" size="2" />
+      <BitField name="PUPD15" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O pull-up or pull-down" start="30" size="2" />
+    </Register>
+    <Register name="IDR" description="GPIO port input data register" start="+0x10" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ID0" description="Port input data bit (y = 0..15) These bits are read-only. They contain the input value of the corresponding I/O port." start="0" size="1" />
+      <BitField name="ID1" description="Port input data bit (y = 0..15) These bits are read-only. They contain the input value of the corresponding I/O port." start="1" size="1" />
+      <BitField name="ID2" description="Port input data bit (y = 0..15) These bits are read-only. They contain the input value of the corresponding I/O port." start="2" size="1" />
+      <BitField name="ID3" description="Port input data bit (y = 0..15) These bits are read-only. They contain the input value of the corresponding I/O port." start="3" size="1" />
+      <BitField name="ID4" description="Port input data bit (y = 0..15) These bits are read-only. They contain the input value of the corresponding I/O port." start="4" size="1" />
+      <BitField name="ID5" description="Port input data bit (y = 0..15) These bits are read-only. They contain the input value of the corresponding I/O port." start="5" size="1" />
+      <BitField name="ID6" description="Port input data bit (y = 0..15) These bits are read-only. They contain the input value of the corresponding I/O port." start="6" size="1" />
+      <BitField name="ID7" description="Port input data bit (y = 0..15) These bits are read-only. They contain the input value of the corresponding I/O port." start="7" size="1" />
+      <BitField name="ID8" description="Port input data bit (y = 0..15) These bits are read-only. They contain the input value of the corresponding I/O port." start="8" size="1" />
+      <BitField name="ID9" description="Port input data bit (y = 0..15) These bits are read-only. They contain the input value of the corresponding I/O port." start="9" size="1" />
+      <BitField name="ID10" description="Port input data bit (y = 0..15) These bits are read-only. They contain the input value of the corresponding I/O port." start="10" size="1" />
+      <BitField name="ID11" description="Port input data bit (y = 0..15) These bits are read-only. They contain the input value of the corresponding I/O port." start="11" size="1" />
+      <BitField name="ID12" description="Port input data bit (y = 0..15) These bits are read-only. They contain the input value of the corresponding I/O port." start="12" size="1" />
+      <BitField name="ID13" description="Port input data bit (y = 0..15) These bits are read-only. They contain the input value of the corresponding I/O port." start="13" size="1" />
+      <BitField name="ID14" description="Port input data bit (y = 0..15) These bits are read-only. They contain the input value of the corresponding I/O port." start="14" size="1" />
+      <BitField name="ID15" description="Port input data bit (y = 0..15) These bits are read-only. They contain the input value of the corresponding I/O port." start="15" size="1" />
+    </Register>
+    <Register name="ODR" description="GPIO port output data register" start="+0x14" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OD0" description="Port output data bit These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR or GPIOx_BRR registers (x = A..F)." start="0" size="1" />
+      <BitField name="OD1" description="Port output data bit These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR or GPIOx_BRR registers (x = A..F)." start="1" size="1" />
+      <BitField name="OD2" description="Port output data bit These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR or GPIOx_BRR registers (x = A..F)." start="2" size="1" />
+      <BitField name="OD3" description="Port output data bit These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR or GPIOx_BRR registers (x = A..F)." start="3" size="1" />
+      <BitField name="OD4" description="Port output data bit These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR or GPIOx_BRR registers (x = A..F)." start="4" size="1" />
+      <BitField name="OD5" description="Port output data bit These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR or GPIOx_BRR registers (x = A..F)." start="5" size="1" />
+      <BitField name="OD6" description="Port output data bit These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR or GPIOx_BRR registers (x = A..F)." start="6" size="1" />
+      <BitField name="OD7" description="Port output data bit These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR or GPIOx_BRR registers (x = A..F)." start="7" size="1" />
+      <BitField name="OD8" description="Port output data bit These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR or GPIOx_BRR registers (x = A..F)." start="8" size="1" />
+      <BitField name="OD9" description="Port output data bit These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR or GPIOx_BRR registers (x = A..F)." start="9" size="1" />
+      <BitField name="OD10" description="Port output data bit These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR or GPIOx_BRR registers (x = A..F)." start="10" size="1" />
+      <BitField name="OD11" description="Port output data bit These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR or GPIOx_BRR registers (x = A..F)." start="11" size="1" />
+      <BitField name="OD12" description="Port output data bit These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR or GPIOx_BRR registers (x = A..F)." start="12" size="1" />
+      <BitField name="OD13" description="Port output data bit These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR or GPIOx_BRR registers (x = A..F)." start="13" size="1" />
+      <BitField name="OD14" description="Port output data bit These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR or GPIOx_BRR registers (x = A..F)." start="14" size="1" />
+      <BitField name="OD15" description="Port output data bit These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR or GPIOx_BRR registers (x = A..F)." start="15" size="1" />
+    </Register>
+    <Register name="BSRR" description="GPIO port bit set/reset register" start="+0x18" size="4" access="WriteOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BS0" description="Port x set bit y (y= 0..15) These bits are write-only. A read to these bits returns the value 0x0000." start="0" size="1" />
+      <BitField name="BS1" description="Port x set bit y (y= 0..15) These bits are write-only. A read to these bits returns the value 0x0000." start="1" size="1" />
+      <BitField name="BS2" description="Port x set bit y (y= 0..15) These bits are write-only. A read to these bits returns the value 0x0000." start="2" size="1" />
+      <BitField name="BS3" description="Port x set bit y (y= 0..15) These bits are write-only. A read to these bits returns the value 0x0000." start="3" size="1" />
+      <BitField name="BS4" description="Port x set bit y (y= 0..15) These bits are write-only. A read to these bits returns the value 0x0000." start="4" size="1" />
+      <BitField name="BS5" description="Port x set bit y (y= 0..15) These bits are write-only. A read to these bits returns the value 0x0000." start="5" size="1" />
+      <BitField name="BS6" description="Port x set bit y (y= 0..15) These bits are write-only. A read to these bits returns the value 0x0000." start="6" size="1" />
+      <BitField name="BS7" description="Port x set bit y (y= 0..15) These bits are write-only. A read to these bits returns the value 0x0000." start="7" size="1" />
+      <BitField name="BS8" description="Port x set bit y (y= 0..15) These bits are write-only. A read to these bits returns the value 0x0000." start="8" size="1" />
+      <BitField name="BS9" description="Port x set bit y (y= 0..15) These bits are write-only. A read to these bits returns the value 0x0000." start="9" size="1" />
+      <BitField name="BS10" description="Port x set bit y (y= 0..15) These bits are write-only. A read to these bits returns the value 0x0000." start="10" size="1" />
+      <BitField name="BS11" description="Port x set bit y (y= 0..15) These bits are write-only. A read to these bits returns the value 0x0000." start="11" size="1" />
+      <BitField name="BS12" description="Port x set bit y (y= 0..15) These bits are write-only. A read to these bits returns the value 0x0000." start="12" size="1" />
+      <BitField name="BS13" description="Port x set bit y (y= 0..15) These bits are write-only. A read to these bits returns the value 0x0000." start="13" size="1" />
+      <BitField name="BS14" description="Port x set bit y (y= 0..15) These bits are write-only. A read to these bits returns the value 0x0000." start="14" size="1" />
+      <BitField name="BS15" description="Port x set bit y (y= 0..15) These bits are write-only. A read to these bits returns the value 0x0000." start="15" size="1" />
+      <BitField name="BR0" description="Port x reset bit y (y = 0..15) These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="16" size="1" />
+      <BitField name="BR1" description="Port x reset bit y (y = 0..15) These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="17" size="1" />
+      <BitField name="BR2" description="Port x reset bit y (y = 0..15) These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="18" size="1" />
+      <BitField name="BR3" description="Port x reset bit y (y = 0..15) These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="19" size="1" />
+      <BitField name="BR4" description="Port x reset bit y (y = 0..15) These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="20" size="1" />
+      <BitField name="BR5" description="Port x reset bit y (y = 0..15) These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="21" size="1" />
+      <BitField name="BR6" description="Port x reset bit y (y = 0..15) These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="22" size="1" />
+      <BitField name="BR7" description="Port x reset bit y (y = 0..15) These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="23" size="1" />
+      <BitField name="BR8" description="Port x reset bit y (y = 0..15) These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="24" size="1" />
+      <BitField name="BR9" description="Port x reset bit y (y = 0..15) These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="25" size="1" />
+      <BitField name="BR10" description="Port x reset bit y (y = 0..15) These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="26" size="1" />
+      <BitField name="BR11" description="Port x reset bit y (y = 0..15) These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="27" size="1" />
+      <BitField name="BR12" description="Port x reset bit y (y = 0..15) These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="28" size="1" />
+      <BitField name="BR13" description="Port x reset bit y (y = 0..15) These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="29" size="1" />
+      <BitField name="BR14" description="Port x reset bit y (y = 0..15) These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="30" size="1" />
+      <BitField name="BR15" description="Port x reset bit y (y = 0..15) These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="31" size="1" />
+    </Register>
+    <Register name="LCKR" description="This register is used to lock the configuration of the port bits when a correct write sequence is applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the GPIO. During the write sequence, the value of LCKR[15:0] must not change. When the LOCK sequence has been applied on a port bit, the value of this port bit can no longer be modified until the next MCU reset or peripheral reset.A specific write sequence is used to write to the GPIOx_LCKR register. Only word access (32-bit long) is allowed during this locking sequence.Each lock bit freezes a specific configuration register (control and alternate function registers)." start="+0x1C" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LCK0" description="Port x lock bit y (y= 0..15) These bits are read/write but can only be written when the LCKK bit is 0." start="0" size="1" />
+      <BitField name="LCK1" description="Port x lock bit y (y= 0..15) These bits are read/write but can only be written when the LCKK bit is 0." start="1" size="1" />
+      <BitField name="LCK2" description="Port x lock bit y (y= 0..15) These bits are read/write but can only be written when the LCKK bit is 0." start="2" size="1" />
+      <BitField name="LCK3" description="Port x lock bit y (y= 0..15) These bits are read/write but can only be written when the LCKK bit is 0." start="3" size="1" />
+      <BitField name="LCK4" description="Port x lock bit y (y= 0..15) These bits are read/write but can only be written when the LCKK bit is 0." start="4" size="1" />
+      <BitField name="LCK5" description="Port x lock bit y (y= 0..15) These bits are read/write but can only be written when the LCKK bit is 0." start="5" size="1" />
+      <BitField name="LCK6" description="Port x lock bit y (y= 0..15) These bits are read/write but can only be written when the LCKK bit is 0." start="6" size="1" />
+      <BitField name="LCK7" description="Port x lock bit y (y= 0..15) These bits are read/write but can only be written when the LCKK bit is 0." start="7" size="1" />
+      <BitField name="LCK8" description="Port x lock bit y (y= 0..15) These bits are read/write but can only be written when the LCKK bit is 0." start="8" size="1" />
+      <BitField name="LCK9" description="Port x lock bit y (y= 0..15) These bits are read/write but can only be written when the LCKK bit is 0." start="9" size="1" />
+      <BitField name="LCK10" description="Port x lock bit y (y= 0..15) These bits are read/write but can only be written when the LCKK bit is 0." start="10" size="1" />
+      <BitField name="LCK11" description="Port x lock bit y (y= 0..15) These bits are read/write but can only be written when the LCKK bit is 0." start="11" size="1" />
+      <BitField name="LCK12" description="Port x lock bit y (y= 0..15) These bits are read/write but can only be written when the LCKK bit is 0." start="12" size="1" />
+      <BitField name="LCK13" description="Port x lock bit y (y= 0..15) These bits are read/write but can only be written when the LCKK bit is 0." start="13" size="1" />
+      <BitField name="LCK14" description="Port x lock bit y (y= 0..15) These bits are read/write but can only be written when the LCKK bit is 0." start="14" size="1" />
+      <BitField name="LCK15" description="Port x lock bit y (y= 0..15) These bits are read/write but can only be written when the LCKK bit is 0." start="15" size="1" />
+      <BitField name="LCKK" description="Lock key This bit can be read any time. It can only be modified using the lock key write sequence. LOCK key write sequence: WR LCKR[16] = 1 + LCKR[15:0] WR LCKR[16] = 0 + LCKR[15:0] WR LCKR[16] = 1 + LCKR[15:0] RD LCKR RD LCKR[16] = 1 (this read operation is optional but it confirms that the lock is active) Note: During the LOCK key write sequence, the value of LCK[15:0] must not change. Any error in the lock sequence aborts the lock. After the first lock sequence on any bit of the port, any read access on the LCKK bit will return 1 until the next MCU reset or peripheral reset." start="16" size="1" />
+    </Register>
+    <Register name="AFRL" description="GPIO alternate function low register" start="+0x20" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AFSEL0" description="[3:0]: Alternate function selection for port x pin y (y = 0..7) These bits are written by software to configure alternate function I/Os AFSELy selection:" start="0" size="4" />
+      <BitField name="AFSEL1" description="[3:0]: Alternate function selection for port x pin y (y = 0..7) These bits are written by software to configure alternate function I/Os AFSELy selection:" start="4" size="4" />
+      <BitField name="AFSEL2" description="[3:0]: Alternate function selection for port x pin y (y = 0..7) These bits are written by software to configure alternate function I/Os AFSELy selection:" start="8" size="4" />
+      <BitField name="AFSEL3" description="[3:0]: Alternate function selection for port x pin y (y = 0..7) These bits are written by software to configure alternate function I/Os AFSELy selection:" start="12" size="4" />
+      <BitField name="AFSEL4" description="[3:0]: Alternate function selection for port x pin y (y = 0..7) These bits are written by software to configure alternate function I/Os AFSELy selection:" start="16" size="4" />
+      <BitField name="AFSEL5" description="[3:0]: Alternate function selection for port x pin y (y = 0..7) These bits are written by software to configure alternate function I/Os AFSELy selection:" start="20" size="4" />
+      <BitField name="AFSEL6" description="[3:0]: Alternate function selection for port x pin y (y = 0..7) These bits are written by software to configure alternate function I/Os AFSELy selection:" start="24" size="4" />
+      <BitField name="AFSEL7" description="[3:0]: Alternate function selection for port x pin y (y = 0..7) These bits are written by software to configure alternate function I/Os AFSELy selection:" start="28" size="4" />
+    </Register>
+    <Register name="AFRH" description="GPIO alternate function high register" start="+0x24" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AFSEL8" description="[3:0]: Alternate function selection for port x pin y (y = 8..15) These bits are written by software to configure alternate function I/Os" start="0" size="4" />
+      <BitField name="AFSEL9" description="[3:0]: Alternate function selection for port x pin y (y = 8..15) These bits are written by software to configure alternate function I/Os" start="4" size="4" />
+      <BitField name="AFSEL10" description="[3:0]: Alternate function selection for port x pin y (y = 8..15) These bits are written by software to configure alternate function I/Os" start="8" size="4" />
+      <BitField name="AFSEL11" description="[3:0]: Alternate function selection for port x pin y (y = 8..15) These bits are written by software to configure alternate function I/Os" start="12" size="4" />
+      <BitField name="AFSEL12" description="[3:0]: Alternate function selection for port x pin y (y = 8..15) These bits are written by software to configure alternate function I/Os" start="16" size="4" />
+      <BitField name="AFSEL13" description="[3:0]: Alternate function selection for port x pin y (y = 8..15) These bits are written by software to configure alternate function I/Os" start="20" size="4" />
+      <BitField name="AFSEL14" description="[3:0]: Alternate function selection for port x pin y (y = 8..15) These bits are written by software to configure alternate function I/Os" start="24" size="4" />
+      <BitField name="AFSEL15" description="[3:0]: Alternate function selection for port x pin y (y = 8..15) These bits are written by software to configure alternate function I/Os" start="28" size="4" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="GPIOF" description="GPIO" start="0x58021400">
+    <Register name="MODER" description="GPIO port mode register" start="+0x0" size="4" access="Read/Write" reset_value="0xABFFFFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="MODE0" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O mode." start="0" size="2" />
+      <BitField name="MODE1" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O mode." start="2" size="2" />
+      <BitField name="MODE2" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O mode." start="4" size="2" />
+      <BitField name="MODE3" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O mode." start="6" size="2" />
+      <BitField name="MODE4" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O mode." start="8" size="2" />
+      <BitField name="MODE5" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O mode." start="10" size="2" />
+      <BitField name="MODE6" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O mode." start="12" size="2" />
+      <BitField name="MODE7" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O mode." start="14" size="2" />
+      <BitField name="MODE8" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O mode." start="16" size="2" />
+      <BitField name="MODE9" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O mode." start="18" size="2" />
+      <BitField name="MODE10" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O mode." start="20" size="2" />
+      <BitField name="MODE11" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O mode." start="22" size="2" />
+      <BitField name="MODE12" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O mode." start="24" size="2" />
+      <BitField name="MODE13" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O mode." start="26" size="2" />
+      <BitField name="MODE14" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O mode." start="28" size="2" />
+      <BitField name="MODE15" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O mode." start="30" size="2" />
+    </Register>
+    <Register name="OTYPER" description="GPIO port output type register" start="+0x4" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OT0" description="Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output type." start="0" size="1" />
+      <BitField name="OT1" description="Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output type." start="1" size="1" />
+      <BitField name="OT2" description="Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output type." start="2" size="1" />
+      <BitField name="OT3" description="Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output type." start="3" size="1" />
+      <BitField name="OT4" description="Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output type." start="4" size="1" />
+      <BitField name="OT5" description="Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output type." start="5" size="1" />
+      <BitField name="OT6" description="Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output type." start="6" size="1" />
+      <BitField name="OT7" description="Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output type." start="7" size="1" />
+      <BitField name="OT8" description="Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output type." start="8" size="1" />
+      <BitField name="OT9" description="Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output type." start="9" size="1" />
+      <BitField name="OT10" description="Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output type." start="10" size="1" />
+      <BitField name="OT11" description="Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output type." start="11" size="1" />
+      <BitField name="OT12" description="Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output type." start="12" size="1" />
+      <BitField name="OT13" description="Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output type." start="13" size="1" />
+      <BitField name="OT14" description="Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output type." start="14" size="1" />
+      <BitField name="OT15" description="Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output type." start="15" size="1" />
+    </Register>
+    <Register name="OSPEEDR" description="GPIO port output speed register" start="+0x8" size="4" access="Read/Write" reset_value="0x0C000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OSPEED0" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed." start="0" size="2" />
+      <BitField name="OSPEED1" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed." start="2" size="2" />
+      <BitField name="OSPEED2" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed." start="4" size="2" />
+      <BitField name="OSPEED3" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed." start="6" size="2" />
+      <BitField name="OSPEED4" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed." start="8" size="2" />
+      <BitField name="OSPEED5" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed." start="10" size="2" />
+      <BitField name="OSPEED6" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed." start="12" size="2" />
+      <BitField name="OSPEED7" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed." start="14" size="2" />
+      <BitField name="OSPEED8" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed." start="16" size="2" />
+      <BitField name="OSPEED9" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed." start="18" size="2" />
+      <BitField name="OSPEED10" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed." start="20" size="2" />
+      <BitField name="OSPEED11" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed." start="22" size="2" />
+      <BitField name="OSPEED12" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed." start="24" size="2" />
+      <BitField name="OSPEED13" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed." start="26" size="2" />
+      <BitField name="OSPEED14" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed." start="28" size="2" />
+      <BitField name="OSPEED15" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed." start="30" size="2" />
+    </Register>
+    <Register name="PUPDR" description="GPIO port pull-up/pull-down register" start="+0xC" size="4" access="Read/Write" reset_value="0x12100000" reset_mask="0xFFFFFFFF">
+      <BitField name="PUPD0" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O pull-up or pull-down" start="0" size="2" />
+      <BitField name="PUPD1" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O pull-up or pull-down" start="2" size="2" />
+      <BitField name="PUPD2" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O pull-up or pull-down" start="4" size="2" />
+      <BitField name="PUPD3" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O pull-up or pull-down" start="6" size="2" />
+      <BitField name="PUPD4" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O pull-up or pull-down" start="8" size="2" />
+      <BitField name="PUPD5" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O pull-up or pull-down" start="10" size="2" />
+      <BitField name="PUPD6" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O pull-up or pull-down" start="12" size="2" />
+      <BitField name="PUPD7" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O pull-up or pull-down" start="14" size="2" />
+      <BitField name="PUPD8" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O pull-up or pull-down" start="16" size="2" />
+      <BitField name="PUPD9" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O pull-up or pull-down" start="18" size="2" />
+      <BitField name="PUPD10" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O pull-up or pull-down" start="20" size="2" />
+      <BitField name="PUPD11" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O pull-up or pull-down" start="22" size="2" />
+      <BitField name="PUPD12" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O pull-up or pull-down" start="24" size="2" />
+      <BitField name="PUPD13" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O pull-up or pull-down" start="26" size="2" />
+      <BitField name="PUPD14" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O pull-up or pull-down" start="28" size="2" />
+      <BitField name="PUPD15" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O pull-up or pull-down" start="30" size="2" />
+    </Register>
+    <Register name="IDR" description="GPIO port input data register" start="+0x10" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ID0" description="Port input data bit (y = 0..15) These bits are read-only. They contain the input value of the corresponding I/O port." start="0" size="1" />
+      <BitField name="ID1" description="Port input data bit (y = 0..15) These bits are read-only. They contain the input value of the corresponding I/O port." start="1" size="1" />
+      <BitField name="ID2" description="Port input data bit (y = 0..15) These bits are read-only. They contain the input value of the corresponding I/O port." start="2" size="1" />
+      <BitField name="ID3" description="Port input data bit (y = 0..15) These bits are read-only. They contain the input value of the corresponding I/O port." start="3" size="1" />
+      <BitField name="ID4" description="Port input data bit (y = 0..15) These bits are read-only. They contain the input value of the corresponding I/O port." start="4" size="1" />
+      <BitField name="ID5" description="Port input data bit (y = 0..15) These bits are read-only. They contain the input value of the corresponding I/O port." start="5" size="1" />
+      <BitField name="ID6" description="Port input data bit (y = 0..15) These bits are read-only. They contain the input value of the corresponding I/O port." start="6" size="1" />
+      <BitField name="ID7" description="Port input data bit (y = 0..15) These bits are read-only. They contain the input value of the corresponding I/O port." start="7" size="1" />
+      <BitField name="ID8" description="Port input data bit (y = 0..15) These bits are read-only. They contain the input value of the corresponding I/O port." start="8" size="1" />
+      <BitField name="ID9" description="Port input data bit (y = 0..15) These bits are read-only. They contain the input value of the corresponding I/O port." start="9" size="1" />
+      <BitField name="ID10" description="Port input data bit (y = 0..15) These bits are read-only. They contain the input value of the corresponding I/O port." start="10" size="1" />
+      <BitField name="ID11" description="Port input data bit (y = 0..15) These bits are read-only. They contain the input value of the corresponding I/O port." start="11" size="1" />
+      <BitField name="ID12" description="Port input data bit (y = 0..15) These bits are read-only. They contain the input value of the corresponding I/O port." start="12" size="1" />
+      <BitField name="ID13" description="Port input data bit (y = 0..15) These bits are read-only. They contain the input value of the corresponding I/O port." start="13" size="1" />
+      <BitField name="ID14" description="Port input data bit (y = 0..15) These bits are read-only. They contain the input value of the corresponding I/O port." start="14" size="1" />
+      <BitField name="ID15" description="Port input data bit (y = 0..15) These bits are read-only. They contain the input value of the corresponding I/O port." start="15" size="1" />
+    </Register>
+    <Register name="ODR" description="GPIO port output data register" start="+0x14" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OD0" description="Port output data bit These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR or GPIOx_BRR registers (x = A..F)." start="0" size="1" />
+      <BitField name="OD1" description="Port output data bit These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR or GPIOx_BRR registers (x = A..F)." start="1" size="1" />
+      <BitField name="OD2" description="Port output data bit These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR or GPIOx_BRR registers (x = A..F)." start="2" size="1" />
+      <BitField name="OD3" description="Port output data bit These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR or GPIOx_BRR registers (x = A..F)." start="3" size="1" />
+      <BitField name="OD4" description="Port output data bit These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR or GPIOx_BRR registers (x = A..F)." start="4" size="1" />
+      <BitField name="OD5" description="Port output data bit These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR or GPIOx_BRR registers (x = A..F)." start="5" size="1" />
+      <BitField name="OD6" description="Port output data bit These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR or GPIOx_BRR registers (x = A..F)." start="6" size="1" />
+      <BitField name="OD7" description="Port output data bit These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR or GPIOx_BRR registers (x = A..F)." start="7" size="1" />
+      <BitField name="OD8" description="Port output data bit These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR or GPIOx_BRR registers (x = A..F)." start="8" size="1" />
+      <BitField name="OD9" description="Port output data bit These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR or GPIOx_BRR registers (x = A..F)." start="9" size="1" />
+      <BitField name="OD10" description="Port output data bit These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR or GPIOx_BRR registers (x = A..F)." start="10" size="1" />
+      <BitField name="OD11" description="Port output data bit These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR or GPIOx_BRR registers (x = A..F)." start="11" size="1" />
+      <BitField name="OD12" description="Port output data bit These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR or GPIOx_BRR registers (x = A..F)." start="12" size="1" />
+      <BitField name="OD13" description="Port output data bit These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR or GPIOx_BRR registers (x = A..F)." start="13" size="1" />
+      <BitField name="OD14" description="Port output data bit These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR or GPIOx_BRR registers (x = A..F)." start="14" size="1" />
+      <BitField name="OD15" description="Port output data bit These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR or GPIOx_BRR registers (x = A..F)." start="15" size="1" />
+    </Register>
+    <Register name="BSRR" description="GPIO port bit set/reset register" start="+0x18" size="4" access="WriteOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BS0" description="Port x set bit y (y= 0..15) These bits are write-only. A read to these bits returns the value 0x0000." start="0" size="1" />
+      <BitField name="BS1" description="Port x set bit y (y= 0..15) These bits are write-only. A read to these bits returns the value 0x0000." start="1" size="1" />
+      <BitField name="BS2" description="Port x set bit y (y= 0..15) These bits are write-only. A read to these bits returns the value 0x0000." start="2" size="1" />
+      <BitField name="BS3" description="Port x set bit y (y= 0..15) These bits are write-only. A read to these bits returns the value 0x0000." start="3" size="1" />
+      <BitField name="BS4" description="Port x set bit y (y= 0..15) These bits are write-only. A read to these bits returns the value 0x0000." start="4" size="1" />
+      <BitField name="BS5" description="Port x set bit y (y= 0..15) These bits are write-only. A read to these bits returns the value 0x0000." start="5" size="1" />
+      <BitField name="BS6" description="Port x set bit y (y= 0..15) These bits are write-only. A read to these bits returns the value 0x0000." start="6" size="1" />
+      <BitField name="BS7" description="Port x set bit y (y= 0..15) These bits are write-only. A read to these bits returns the value 0x0000." start="7" size="1" />
+      <BitField name="BS8" description="Port x set bit y (y= 0..15) These bits are write-only. A read to these bits returns the value 0x0000." start="8" size="1" />
+      <BitField name="BS9" description="Port x set bit y (y= 0..15) These bits are write-only. A read to these bits returns the value 0x0000." start="9" size="1" />
+      <BitField name="BS10" description="Port x set bit y (y= 0..15) These bits are write-only. A read to these bits returns the value 0x0000." start="10" size="1" />
+      <BitField name="BS11" description="Port x set bit y (y= 0..15) These bits are write-only. A read to these bits returns the value 0x0000." start="11" size="1" />
+      <BitField name="BS12" description="Port x set bit y (y= 0..15) These bits are write-only. A read to these bits returns the value 0x0000." start="12" size="1" />
+      <BitField name="BS13" description="Port x set bit y (y= 0..15) These bits are write-only. A read to these bits returns the value 0x0000." start="13" size="1" />
+      <BitField name="BS14" description="Port x set bit y (y= 0..15) These bits are write-only. A read to these bits returns the value 0x0000." start="14" size="1" />
+      <BitField name="BS15" description="Port x set bit y (y= 0..15) These bits are write-only. A read to these bits returns the value 0x0000." start="15" size="1" />
+      <BitField name="BR0" description="Port x reset bit y (y = 0..15) These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="16" size="1" />
+      <BitField name="BR1" description="Port x reset bit y (y = 0..15) These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="17" size="1" />
+      <BitField name="BR2" description="Port x reset bit y (y = 0..15) These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="18" size="1" />
+      <BitField name="BR3" description="Port x reset bit y (y = 0..15) These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="19" size="1" />
+      <BitField name="BR4" description="Port x reset bit y (y = 0..15) These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="20" size="1" />
+      <BitField name="BR5" description="Port x reset bit y (y = 0..15) These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="21" size="1" />
+      <BitField name="BR6" description="Port x reset bit y (y = 0..15) These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="22" size="1" />
+      <BitField name="BR7" description="Port x reset bit y (y = 0..15) These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="23" size="1" />
+      <BitField name="BR8" description="Port x reset bit y (y = 0..15) These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="24" size="1" />
+      <BitField name="BR9" description="Port x reset bit y (y = 0..15) These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="25" size="1" />
+      <BitField name="BR10" description="Port x reset bit y (y = 0..15) These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="26" size="1" />
+      <BitField name="BR11" description="Port x reset bit y (y = 0..15) These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="27" size="1" />
+      <BitField name="BR12" description="Port x reset bit y (y = 0..15) These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="28" size="1" />
+      <BitField name="BR13" description="Port x reset bit y (y = 0..15) These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="29" size="1" />
+      <BitField name="BR14" description="Port x reset bit y (y = 0..15) These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="30" size="1" />
+      <BitField name="BR15" description="Port x reset bit y (y = 0..15) These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="31" size="1" />
+    </Register>
+    <Register name="LCKR" description="This register is used to lock the configuration of the port bits when a correct write sequence is applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the GPIO. During the write sequence, the value of LCKR[15:0] must not change. When the LOCK sequence has been applied on a port bit, the value of this port bit can no longer be modified until the next MCU reset or peripheral reset.A specific write sequence is used to write to the GPIOx_LCKR register. Only word access (32-bit long) is allowed during this locking sequence.Each lock bit freezes a specific configuration register (control and alternate function registers)." start="+0x1C" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LCK0" description="Port x lock bit y (y= 0..15) These bits are read/write but can only be written when the LCKK bit is 0." start="0" size="1" />
+      <BitField name="LCK1" description="Port x lock bit y (y= 0..15) These bits are read/write but can only be written when the LCKK bit is 0." start="1" size="1" />
+      <BitField name="LCK2" description="Port x lock bit y (y= 0..15) These bits are read/write but can only be written when the LCKK bit is 0." start="2" size="1" />
+      <BitField name="LCK3" description="Port x lock bit y (y= 0..15) These bits are read/write but can only be written when the LCKK bit is 0." start="3" size="1" />
+      <BitField name="LCK4" description="Port x lock bit y (y= 0..15) These bits are read/write but can only be written when the LCKK bit is 0." start="4" size="1" />
+      <BitField name="LCK5" description="Port x lock bit y (y= 0..15) These bits are read/write but can only be written when the LCKK bit is 0." start="5" size="1" />
+      <BitField name="LCK6" description="Port x lock bit y (y= 0..15) These bits are read/write but can only be written when the LCKK bit is 0." start="6" size="1" />
+      <BitField name="LCK7" description="Port x lock bit y (y= 0..15) These bits are read/write but can only be written when the LCKK bit is 0." start="7" size="1" />
+      <BitField name="LCK8" description="Port x lock bit y (y= 0..15) These bits are read/write but can only be written when the LCKK bit is 0." start="8" size="1" />
+      <BitField name="LCK9" description="Port x lock bit y (y= 0..15) These bits are read/write but can only be written when the LCKK bit is 0." start="9" size="1" />
+      <BitField name="LCK10" description="Port x lock bit y (y= 0..15) These bits are read/write but can only be written when the LCKK bit is 0." start="10" size="1" />
+      <BitField name="LCK11" description="Port x lock bit y (y= 0..15) These bits are read/write but can only be written when the LCKK bit is 0." start="11" size="1" />
+      <BitField name="LCK12" description="Port x lock bit y (y= 0..15) These bits are read/write but can only be written when the LCKK bit is 0." start="12" size="1" />
+      <BitField name="LCK13" description="Port x lock bit y (y= 0..15) These bits are read/write but can only be written when the LCKK bit is 0." start="13" size="1" />
+      <BitField name="LCK14" description="Port x lock bit y (y= 0..15) These bits are read/write but can only be written when the LCKK bit is 0." start="14" size="1" />
+      <BitField name="LCK15" description="Port x lock bit y (y= 0..15) These bits are read/write but can only be written when the LCKK bit is 0." start="15" size="1" />
+      <BitField name="LCKK" description="Lock key This bit can be read any time. It can only be modified using the lock key write sequence. LOCK key write sequence: WR LCKR[16] = 1 + LCKR[15:0] WR LCKR[16] = 0 + LCKR[15:0] WR LCKR[16] = 1 + LCKR[15:0] RD LCKR RD LCKR[16] = 1 (this read operation is optional but it confirms that the lock is active) Note: During the LOCK key write sequence, the value of LCK[15:0] must not change. Any error in the lock sequence aborts the lock. After the first lock sequence on any bit of the port, any read access on the LCKK bit will return 1 until the next MCU reset or peripheral reset." start="16" size="1" />
+    </Register>
+    <Register name="AFRL" description="GPIO alternate function low register" start="+0x20" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AFSEL0" description="[3:0]: Alternate function selection for port x pin y (y = 0..7) These bits are written by software to configure alternate function I/Os AFSELy selection:" start="0" size="4" />
+      <BitField name="AFSEL1" description="[3:0]: Alternate function selection for port x pin y (y = 0..7) These bits are written by software to configure alternate function I/Os AFSELy selection:" start="4" size="4" />
+      <BitField name="AFSEL2" description="[3:0]: Alternate function selection for port x pin y (y = 0..7) These bits are written by software to configure alternate function I/Os AFSELy selection:" start="8" size="4" />
+      <BitField name="AFSEL3" description="[3:0]: Alternate function selection for port x pin y (y = 0..7) These bits are written by software to configure alternate function I/Os AFSELy selection:" start="12" size="4" />
+      <BitField name="AFSEL4" description="[3:0]: Alternate function selection for port x pin y (y = 0..7) These bits are written by software to configure alternate function I/Os AFSELy selection:" start="16" size="4" />
+      <BitField name="AFSEL5" description="[3:0]: Alternate function selection for port x pin y (y = 0..7) These bits are written by software to configure alternate function I/Os AFSELy selection:" start="20" size="4" />
+      <BitField name="AFSEL6" description="[3:0]: Alternate function selection for port x pin y (y = 0..7) These bits are written by software to configure alternate function I/Os AFSELy selection:" start="24" size="4" />
+      <BitField name="AFSEL7" description="[3:0]: Alternate function selection for port x pin y (y = 0..7) These bits are written by software to configure alternate function I/Os AFSELy selection:" start="28" size="4" />
+    </Register>
+    <Register name="AFRH" description="GPIO alternate function high register" start="+0x24" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AFSEL8" description="[3:0]: Alternate function selection for port x pin y (y = 8..15) These bits are written by software to configure alternate function I/Os" start="0" size="4" />
+      <BitField name="AFSEL9" description="[3:0]: Alternate function selection for port x pin y (y = 8..15) These bits are written by software to configure alternate function I/Os" start="4" size="4" />
+      <BitField name="AFSEL10" description="[3:0]: Alternate function selection for port x pin y (y = 8..15) These bits are written by software to configure alternate function I/Os" start="8" size="4" />
+      <BitField name="AFSEL11" description="[3:0]: Alternate function selection for port x pin y (y = 8..15) These bits are written by software to configure alternate function I/Os" start="12" size="4" />
+      <BitField name="AFSEL12" description="[3:0]: Alternate function selection for port x pin y (y = 8..15) These bits are written by software to configure alternate function I/Os" start="16" size="4" />
+      <BitField name="AFSEL13" description="[3:0]: Alternate function selection for port x pin y (y = 8..15) These bits are written by software to configure alternate function I/Os" start="20" size="4" />
+      <BitField name="AFSEL14" description="[3:0]: Alternate function selection for port x pin y (y = 8..15) These bits are written by software to configure alternate function I/Os" start="24" size="4" />
+      <BitField name="AFSEL15" description="[3:0]: Alternate function selection for port x pin y (y = 8..15) These bits are written by software to configure alternate function I/Os" start="28" size="4" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="GPIOG" description="GPIO" start="0x58021800">
+    <Register name="MODER" description="GPIO port mode register" start="+0x0" size="4" access="Read/Write" reset_value="0xABFFFFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="MODE0" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O mode." start="0" size="2" />
+      <BitField name="MODE1" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O mode." start="2" size="2" />
+      <BitField name="MODE2" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O mode." start="4" size="2" />
+      <BitField name="MODE3" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O mode." start="6" size="2" />
+      <BitField name="MODE4" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O mode." start="8" size="2" />
+      <BitField name="MODE5" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O mode." start="10" size="2" />
+      <BitField name="MODE6" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O mode." start="12" size="2" />
+      <BitField name="MODE7" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O mode." start="14" size="2" />
+      <BitField name="MODE8" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O mode." start="16" size="2" />
+      <BitField name="MODE9" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O mode." start="18" size="2" />
+      <BitField name="MODE10" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O mode." start="20" size="2" />
+      <BitField name="MODE11" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O mode." start="22" size="2" />
+      <BitField name="MODE12" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O mode." start="24" size="2" />
+      <BitField name="MODE13" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O mode." start="26" size="2" />
+      <BitField name="MODE14" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O mode." start="28" size="2" />
+      <BitField name="MODE15" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O mode." start="30" size="2" />
+    </Register>
+    <Register name="OTYPER" description="GPIO port output type register" start="+0x4" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OT0" description="Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output type." start="0" size="1" />
+      <BitField name="OT1" description="Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output type." start="1" size="1" />
+      <BitField name="OT2" description="Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output type." start="2" size="1" />
+      <BitField name="OT3" description="Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output type." start="3" size="1" />
+      <BitField name="OT4" description="Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output type." start="4" size="1" />
+      <BitField name="OT5" description="Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output type." start="5" size="1" />
+      <BitField name="OT6" description="Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output type." start="6" size="1" />
+      <BitField name="OT7" description="Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output type." start="7" size="1" />
+      <BitField name="OT8" description="Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output type." start="8" size="1" />
+      <BitField name="OT9" description="Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output type." start="9" size="1" />
+      <BitField name="OT10" description="Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output type." start="10" size="1" />
+      <BitField name="OT11" description="Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output type." start="11" size="1" />
+      <BitField name="OT12" description="Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output type." start="12" size="1" />
+      <BitField name="OT13" description="Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output type." start="13" size="1" />
+      <BitField name="OT14" description="Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output type." start="14" size="1" />
+      <BitField name="OT15" description="Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output type." start="15" size="1" />
+    </Register>
+    <Register name="OSPEEDR" description="GPIO port output speed register" start="+0x8" size="4" access="Read/Write" reset_value="0x0C000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OSPEED0" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed." start="0" size="2" />
+      <BitField name="OSPEED1" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed." start="2" size="2" />
+      <BitField name="OSPEED2" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed." start="4" size="2" />
+      <BitField name="OSPEED3" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed." start="6" size="2" />
+      <BitField name="OSPEED4" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed." start="8" size="2" />
+      <BitField name="OSPEED5" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed." start="10" size="2" />
+      <BitField name="OSPEED6" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed." start="12" size="2" />
+      <BitField name="OSPEED7" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed." start="14" size="2" />
+      <BitField name="OSPEED8" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed." start="16" size="2" />
+      <BitField name="OSPEED9" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed." start="18" size="2" />
+      <BitField name="OSPEED10" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed." start="20" size="2" />
+      <BitField name="OSPEED11" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed." start="22" size="2" />
+      <BitField name="OSPEED12" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed." start="24" size="2" />
+      <BitField name="OSPEED13" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed." start="26" size="2" />
+      <BitField name="OSPEED14" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed." start="28" size="2" />
+      <BitField name="OSPEED15" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed." start="30" size="2" />
+    </Register>
+    <Register name="PUPDR" description="GPIO port pull-up/pull-down register" start="+0xC" size="4" access="Read/Write" reset_value="0x12100000" reset_mask="0xFFFFFFFF">
+      <BitField name="PUPD0" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O pull-up or pull-down" start="0" size="2" />
+      <BitField name="PUPD1" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O pull-up or pull-down" start="2" size="2" />
+      <BitField name="PUPD2" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O pull-up or pull-down" start="4" size="2" />
+      <BitField name="PUPD3" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O pull-up or pull-down" start="6" size="2" />
+      <BitField name="PUPD4" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O pull-up or pull-down" start="8" size="2" />
+      <BitField name="PUPD5" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O pull-up or pull-down" start="10" size="2" />
+      <BitField name="PUPD6" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O pull-up or pull-down" start="12" size="2" />
+      <BitField name="PUPD7" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O pull-up or pull-down" start="14" size="2" />
+      <BitField name="PUPD8" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O pull-up or pull-down" start="16" size="2" />
+      <BitField name="PUPD9" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O pull-up or pull-down" start="18" size="2" />
+      <BitField name="PUPD10" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O pull-up or pull-down" start="20" size="2" />
+      <BitField name="PUPD11" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O pull-up or pull-down" start="22" size="2" />
+      <BitField name="PUPD12" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O pull-up or pull-down" start="24" size="2" />
+      <BitField name="PUPD13" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O pull-up or pull-down" start="26" size="2" />
+      <BitField name="PUPD14" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O pull-up or pull-down" start="28" size="2" />
+      <BitField name="PUPD15" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O pull-up or pull-down" start="30" size="2" />
+    </Register>
+    <Register name="IDR" description="GPIO port input data register" start="+0x10" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ID0" description="Port input data bit (y = 0..15) These bits are read-only. They contain the input value of the corresponding I/O port." start="0" size="1" />
+      <BitField name="ID1" description="Port input data bit (y = 0..15) These bits are read-only. They contain the input value of the corresponding I/O port." start="1" size="1" />
+      <BitField name="ID2" description="Port input data bit (y = 0..15) These bits are read-only. They contain the input value of the corresponding I/O port." start="2" size="1" />
+      <BitField name="ID3" description="Port input data bit (y = 0..15) These bits are read-only. They contain the input value of the corresponding I/O port." start="3" size="1" />
+      <BitField name="ID4" description="Port input data bit (y = 0..15) These bits are read-only. They contain the input value of the corresponding I/O port." start="4" size="1" />
+      <BitField name="ID5" description="Port input data bit (y = 0..15) These bits are read-only. They contain the input value of the corresponding I/O port." start="5" size="1" />
+      <BitField name="ID6" description="Port input data bit (y = 0..15) These bits are read-only. They contain the input value of the corresponding I/O port." start="6" size="1" />
+      <BitField name="ID7" description="Port input data bit (y = 0..15) These bits are read-only. They contain the input value of the corresponding I/O port." start="7" size="1" />
+      <BitField name="ID8" description="Port input data bit (y = 0..15) These bits are read-only. They contain the input value of the corresponding I/O port." start="8" size="1" />
+      <BitField name="ID9" description="Port input data bit (y = 0..15) These bits are read-only. They contain the input value of the corresponding I/O port." start="9" size="1" />
+      <BitField name="ID10" description="Port input data bit (y = 0..15) These bits are read-only. They contain the input value of the corresponding I/O port." start="10" size="1" />
+      <BitField name="ID11" description="Port input data bit (y = 0..15) These bits are read-only. They contain the input value of the corresponding I/O port." start="11" size="1" />
+      <BitField name="ID12" description="Port input data bit (y = 0..15) These bits are read-only. They contain the input value of the corresponding I/O port." start="12" size="1" />
+      <BitField name="ID13" description="Port input data bit (y = 0..15) These bits are read-only. They contain the input value of the corresponding I/O port." start="13" size="1" />
+      <BitField name="ID14" description="Port input data bit (y = 0..15) These bits are read-only. They contain the input value of the corresponding I/O port." start="14" size="1" />
+      <BitField name="ID15" description="Port input data bit (y = 0..15) These bits are read-only. They contain the input value of the corresponding I/O port." start="15" size="1" />
+    </Register>
+    <Register name="ODR" description="GPIO port output data register" start="+0x14" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OD0" description="Port output data bit These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR or GPIOx_BRR registers (x = A..F)." start="0" size="1" />
+      <BitField name="OD1" description="Port output data bit These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR or GPIOx_BRR registers (x = A..F)." start="1" size="1" />
+      <BitField name="OD2" description="Port output data bit These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR or GPIOx_BRR registers (x = A..F)." start="2" size="1" />
+      <BitField name="OD3" description="Port output data bit These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR or GPIOx_BRR registers (x = A..F)." start="3" size="1" />
+      <BitField name="OD4" description="Port output data bit These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR or GPIOx_BRR registers (x = A..F)." start="4" size="1" />
+      <BitField name="OD5" description="Port output data bit These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR or GPIOx_BRR registers (x = A..F)." start="5" size="1" />
+      <BitField name="OD6" description="Port output data bit These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR or GPIOx_BRR registers (x = A..F)." start="6" size="1" />
+      <BitField name="OD7" description="Port output data bit These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR or GPIOx_BRR registers (x = A..F)." start="7" size="1" />
+      <BitField name="OD8" description="Port output data bit These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR or GPIOx_BRR registers (x = A..F)." start="8" size="1" />
+      <BitField name="OD9" description="Port output data bit These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR or GPIOx_BRR registers (x = A..F)." start="9" size="1" />
+      <BitField name="OD10" description="Port output data bit These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR or GPIOx_BRR registers (x = A..F)." start="10" size="1" />
+      <BitField name="OD11" description="Port output data bit These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR or GPIOx_BRR registers (x = A..F)." start="11" size="1" />
+      <BitField name="OD12" description="Port output data bit These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR or GPIOx_BRR registers (x = A..F)." start="12" size="1" />
+      <BitField name="OD13" description="Port output data bit These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR or GPIOx_BRR registers (x = A..F)." start="13" size="1" />
+      <BitField name="OD14" description="Port output data bit These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR or GPIOx_BRR registers (x = A..F)." start="14" size="1" />
+      <BitField name="OD15" description="Port output data bit These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR or GPIOx_BRR registers (x = A..F)." start="15" size="1" />
+    </Register>
+    <Register name="BSRR" description="GPIO port bit set/reset register" start="+0x18" size="4" access="WriteOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BS0" description="Port x set bit y (y= 0..15) These bits are write-only. A read to these bits returns the value 0x0000." start="0" size="1" />
+      <BitField name="BS1" description="Port x set bit y (y= 0..15) These bits are write-only. A read to these bits returns the value 0x0000." start="1" size="1" />
+      <BitField name="BS2" description="Port x set bit y (y= 0..15) These bits are write-only. A read to these bits returns the value 0x0000." start="2" size="1" />
+      <BitField name="BS3" description="Port x set bit y (y= 0..15) These bits are write-only. A read to these bits returns the value 0x0000." start="3" size="1" />
+      <BitField name="BS4" description="Port x set bit y (y= 0..15) These bits are write-only. A read to these bits returns the value 0x0000." start="4" size="1" />
+      <BitField name="BS5" description="Port x set bit y (y= 0..15) These bits are write-only. A read to these bits returns the value 0x0000." start="5" size="1" />
+      <BitField name="BS6" description="Port x set bit y (y= 0..15) These bits are write-only. A read to these bits returns the value 0x0000." start="6" size="1" />
+      <BitField name="BS7" description="Port x set bit y (y= 0..15) These bits are write-only. A read to these bits returns the value 0x0000." start="7" size="1" />
+      <BitField name="BS8" description="Port x set bit y (y= 0..15) These bits are write-only. A read to these bits returns the value 0x0000." start="8" size="1" />
+      <BitField name="BS9" description="Port x set bit y (y= 0..15) These bits are write-only. A read to these bits returns the value 0x0000." start="9" size="1" />
+      <BitField name="BS10" description="Port x set bit y (y= 0..15) These bits are write-only. A read to these bits returns the value 0x0000." start="10" size="1" />
+      <BitField name="BS11" description="Port x set bit y (y= 0..15) These bits are write-only. A read to these bits returns the value 0x0000." start="11" size="1" />
+      <BitField name="BS12" description="Port x set bit y (y= 0..15) These bits are write-only. A read to these bits returns the value 0x0000." start="12" size="1" />
+      <BitField name="BS13" description="Port x set bit y (y= 0..15) These bits are write-only. A read to these bits returns the value 0x0000." start="13" size="1" />
+      <BitField name="BS14" description="Port x set bit y (y= 0..15) These bits are write-only. A read to these bits returns the value 0x0000." start="14" size="1" />
+      <BitField name="BS15" description="Port x set bit y (y= 0..15) These bits are write-only. A read to these bits returns the value 0x0000." start="15" size="1" />
+      <BitField name="BR0" description="Port x reset bit y (y = 0..15) These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="16" size="1" />
+      <BitField name="BR1" description="Port x reset bit y (y = 0..15) These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="17" size="1" />
+      <BitField name="BR2" description="Port x reset bit y (y = 0..15) These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="18" size="1" />
+      <BitField name="BR3" description="Port x reset bit y (y = 0..15) These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="19" size="1" />
+      <BitField name="BR4" description="Port x reset bit y (y = 0..15) These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="20" size="1" />
+      <BitField name="BR5" description="Port x reset bit y (y = 0..15) These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="21" size="1" />
+      <BitField name="BR6" description="Port x reset bit y (y = 0..15) These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="22" size="1" />
+      <BitField name="BR7" description="Port x reset bit y (y = 0..15) These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="23" size="1" />
+      <BitField name="BR8" description="Port x reset bit y (y = 0..15) These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="24" size="1" />
+      <BitField name="BR9" description="Port x reset bit y (y = 0..15) These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="25" size="1" />
+      <BitField name="BR10" description="Port x reset bit y (y = 0..15) These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="26" size="1" />
+      <BitField name="BR11" description="Port x reset bit y (y = 0..15) These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="27" size="1" />
+      <BitField name="BR12" description="Port x reset bit y (y = 0..15) These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="28" size="1" />
+      <BitField name="BR13" description="Port x reset bit y (y = 0..15) These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="29" size="1" />
+      <BitField name="BR14" description="Port x reset bit y (y = 0..15) These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="30" size="1" />
+      <BitField name="BR15" description="Port x reset bit y (y = 0..15) These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="31" size="1" />
+    </Register>
+    <Register name="LCKR" description="This register is used to lock the configuration of the port bits when a correct write sequence is applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the GPIO. During the write sequence, the value of LCKR[15:0] must not change. When the LOCK sequence has been applied on a port bit, the value of this port bit can no longer be modified until the next MCU reset or peripheral reset.A specific write sequence is used to write to the GPIOx_LCKR register. Only word access (32-bit long) is allowed during this locking sequence.Each lock bit freezes a specific configuration register (control and alternate function registers)." start="+0x1C" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LCK0" description="Port x lock bit y (y= 0..15) These bits are read/write but can only be written when the LCKK bit is 0." start="0" size="1" />
+      <BitField name="LCK1" description="Port x lock bit y (y= 0..15) These bits are read/write but can only be written when the LCKK bit is 0." start="1" size="1" />
+      <BitField name="LCK2" description="Port x lock bit y (y= 0..15) These bits are read/write but can only be written when the LCKK bit is 0." start="2" size="1" />
+      <BitField name="LCK3" description="Port x lock bit y (y= 0..15) These bits are read/write but can only be written when the LCKK bit is 0." start="3" size="1" />
+      <BitField name="LCK4" description="Port x lock bit y (y= 0..15) These bits are read/write but can only be written when the LCKK bit is 0." start="4" size="1" />
+      <BitField name="LCK5" description="Port x lock bit y (y= 0..15) These bits are read/write but can only be written when the LCKK bit is 0." start="5" size="1" />
+      <BitField name="LCK6" description="Port x lock bit y (y= 0..15) These bits are read/write but can only be written when the LCKK bit is 0." start="6" size="1" />
+      <BitField name="LCK7" description="Port x lock bit y (y= 0..15) These bits are read/write but can only be written when the LCKK bit is 0." start="7" size="1" />
+      <BitField name="LCK8" description="Port x lock bit y (y= 0..15) These bits are read/write but can only be written when the LCKK bit is 0." start="8" size="1" />
+      <BitField name="LCK9" description="Port x lock bit y (y= 0..15) These bits are read/write but can only be written when the LCKK bit is 0." start="9" size="1" />
+      <BitField name="LCK10" description="Port x lock bit y (y= 0..15) These bits are read/write but can only be written when the LCKK bit is 0." start="10" size="1" />
+      <BitField name="LCK11" description="Port x lock bit y (y= 0..15) These bits are read/write but can only be written when the LCKK bit is 0." start="11" size="1" />
+      <BitField name="LCK12" description="Port x lock bit y (y= 0..15) These bits are read/write but can only be written when the LCKK bit is 0." start="12" size="1" />
+      <BitField name="LCK13" description="Port x lock bit y (y= 0..15) These bits are read/write but can only be written when the LCKK bit is 0." start="13" size="1" />
+      <BitField name="LCK14" description="Port x lock bit y (y= 0..15) These bits are read/write but can only be written when the LCKK bit is 0." start="14" size="1" />
+      <BitField name="LCK15" description="Port x lock bit y (y= 0..15) These bits are read/write but can only be written when the LCKK bit is 0." start="15" size="1" />
+      <BitField name="LCKK" description="Lock key This bit can be read any time. It can only be modified using the lock key write sequence. LOCK key write sequence: WR LCKR[16] = 1 + LCKR[15:0] WR LCKR[16] = 0 + LCKR[15:0] WR LCKR[16] = 1 + LCKR[15:0] RD LCKR RD LCKR[16] = 1 (this read operation is optional but it confirms that the lock is active) Note: During the LOCK key write sequence, the value of LCK[15:0] must not change. Any error in the lock sequence aborts the lock. After the first lock sequence on any bit of the port, any read access on the LCKK bit will return 1 until the next MCU reset or peripheral reset." start="16" size="1" />
+    </Register>
+    <Register name="AFRL" description="GPIO alternate function low register" start="+0x20" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AFSEL0" description="[3:0]: Alternate function selection for port x pin y (y = 0..7) These bits are written by software to configure alternate function I/Os AFSELy selection:" start="0" size="4" />
+      <BitField name="AFSEL1" description="[3:0]: Alternate function selection for port x pin y (y = 0..7) These bits are written by software to configure alternate function I/Os AFSELy selection:" start="4" size="4" />
+      <BitField name="AFSEL2" description="[3:0]: Alternate function selection for port x pin y (y = 0..7) These bits are written by software to configure alternate function I/Os AFSELy selection:" start="8" size="4" />
+      <BitField name="AFSEL3" description="[3:0]: Alternate function selection for port x pin y (y = 0..7) These bits are written by software to configure alternate function I/Os AFSELy selection:" start="12" size="4" />
+      <BitField name="AFSEL4" description="[3:0]: Alternate function selection for port x pin y (y = 0..7) These bits are written by software to configure alternate function I/Os AFSELy selection:" start="16" size="4" />
+      <BitField name="AFSEL5" description="[3:0]: Alternate function selection for port x pin y (y = 0..7) These bits are written by software to configure alternate function I/Os AFSELy selection:" start="20" size="4" />
+      <BitField name="AFSEL6" description="[3:0]: Alternate function selection for port x pin y (y = 0..7) These bits are written by software to configure alternate function I/Os AFSELy selection:" start="24" size="4" />
+      <BitField name="AFSEL7" description="[3:0]: Alternate function selection for port x pin y (y = 0..7) These bits are written by software to configure alternate function I/Os AFSELy selection:" start="28" size="4" />
+    </Register>
+    <Register name="AFRH" description="GPIO alternate function high register" start="+0x24" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AFSEL8" description="[3:0]: Alternate function selection for port x pin y (y = 8..15) These bits are written by software to configure alternate function I/Os" start="0" size="4" />
+      <BitField name="AFSEL9" description="[3:0]: Alternate function selection for port x pin y (y = 8..15) These bits are written by software to configure alternate function I/Os" start="4" size="4" />
+      <BitField name="AFSEL10" description="[3:0]: Alternate function selection for port x pin y (y = 8..15) These bits are written by software to configure alternate function I/Os" start="8" size="4" />
+      <BitField name="AFSEL11" description="[3:0]: Alternate function selection for port x pin y (y = 8..15) These bits are written by software to configure alternate function I/Os" start="12" size="4" />
+      <BitField name="AFSEL12" description="[3:0]: Alternate function selection for port x pin y (y = 8..15) These bits are written by software to configure alternate function I/Os" start="16" size="4" />
+      <BitField name="AFSEL13" description="[3:0]: Alternate function selection for port x pin y (y = 8..15) These bits are written by software to configure alternate function I/Os" start="20" size="4" />
+      <BitField name="AFSEL14" description="[3:0]: Alternate function selection for port x pin y (y = 8..15) These bits are written by software to configure alternate function I/Os" start="24" size="4" />
+      <BitField name="AFSEL15" description="[3:0]: Alternate function selection for port x pin y (y = 8..15) These bits are written by software to configure alternate function I/Os" start="28" size="4" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="GPIOH" description="GPIO" start="0x58021C00">
+    <Register name="MODER" description="GPIO port mode register" start="+0x0" size="4" access="Read/Write" reset_value="0xABFFFFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="MODE0" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O mode." start="0" size="2" />
+      <BitField name="MODE1" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O mode." start="2" size="2" />
+      <BitField name="MODE2" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O mode." start="4" size="2" />
+      <BitField name="MODE3" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O mode." start="6" size="2" />
+      <BitField name="MODE4" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O mode." start="8" size="2" />
+      <BitField name="MODE5" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O mode." start="10" size="2" />
+      <BitField name="MODE6" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O mode." start="12" size="2" />
+      <BitField name="MODE7" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O mode." start="14" size="2" />
+      <BitField name="MODE8" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O mode." start="16" size="2" />
+      <BitField name="MODE9" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O mode." start="18" size="2" />
+      <BitField name="MODE10" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O mode." start="20" size="2" />
+      <BitField name="MODE11" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O mode." start="22" size="2" />
+      <BitField name="MODE12" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O mode." start="24" size="2" />
+      <BitField name="MODE13" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O mode." start="26" size="2" />
+      <BitField name="MODE14" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O mode." start="28" size="2" />
+      <BitField name="MODE15" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O mode." start="30" size="2" />
+    </Register>
+    <Register name="OTYPER" description="GPIO port output type register" start="+0x4" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OT0" description="Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output type." start="0" size="1" />
+      <BitField name="OT1" description="Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output type." start="1" size="1" />
+      <BitField name="OT2" description="Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output type." start="2" size="1" />
+      <BitField name="OT3" description="Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output type." start="3" size="1" />
+      <BitField name="OT4" description="Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output type." start="4" size="1" />
+      <BitField name="OT5" description="Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output type." start="5" size="1" />
+      <BitField name="OT6" description="Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output type." start="6" size="1" />
+      <BitField name="OT7" description="Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output type." start="7" size="1" />
+      <BitField name="OT8" description="Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output type." start="8" size="1" />
+      <BitField name="OT9" description="Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output type." start="9" size="1" />
+      <BitField name="OT10" description="Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output type." start="10" size="1" />
+      <BitField name="OT11" description="Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output type." start="11" size="1" />
+      <BitField name="OT12" description="Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output type." start="12" size="1" />
+      <BitField name="OT13" description="Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output type." start="13" size="1" />
+      <BitField name="OT14" description="Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output type." start="14" size="1" />
+      <BitField name="OT15" description="Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output type." start="15" size="1" />
+    </Register>
+    <Register name="OSPEEDR" description="GPIO port output speed register" start="+0x8" size="4" access="Read/Write" reset_value="0x0C000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OSPEED0" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed." start="0" size="2" />
+      <BitField name="OSPEED1" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed." start="2" size="2" />
+      <BitField name="OSPEED2" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed." start="4" size="2" />
+      <BitField name="OSPEED3" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed." start="6" size="2" />
+      <BitField name="OSPEED4" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed." start="8" size="2" />
+      <BitField name="OSPEED5" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed." start="10" size="2" />
+      <BitField name="OSPEED6" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed." start="12" size="2" />
+      <BitField name="OSPEED7" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed." start="14" size="2" />
+      <BitField name="OSPEED8" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed." start="16" size="2" />
+      <BitField name="OSPEED9" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed." start="18" size="2" />
+      <BitField name="OSPEED10" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed." start="20" size="2" />
+      <BitField name="OSPEED11" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed." start="22" size="2" />
+      <BitField name="OSPEED12" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed." start="24" size="2" />
+      <BitField name="OSPEED13" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed." start="26" size="2" />
+      <BitField name="OSPEED14" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed." start="28" size="2" />
+      <BitField name="OSPEED15" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed." start="30" size="2" />
+    </Register>
+    <Register name="PUPDR" description="GPIO port pull-up/pull-down register" start="+0xC" size="4" access="Read/Write" reset_value="0x12100000" reset_mask="0xFFFFFFFF">
+      <BitField name="PUPD0" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O pull-up or pull-down" start="0" size="2" />
+      <BitField name="PUPD1" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O pull-up or pull-down" start="2" size="2" />
+      <BitField name="PUPD2" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O pull-up or pull-down" start="4" size="2" />
+      <BitField name="PUPD3" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O pull-up or pull-down" start="6" size="2" />
+      <BitField name="PUPD4" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O pull-up or pull-down" start="8" size="2" />
+      <BitField name="PUPD5" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O pull-up or pull-down" start="10" size="2" />
+      <BitField name="PUPD6" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O pull-up or pull-down" start="12" size="2" />
+      <BitField name="PUPD7" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O pull-up or pull-down" start="14" size="2" />
+      <BitField name="PUPD8" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O pull-up or pull-down" start="16" size="2" />
+      <BitField name="PUPD9" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O pull-up or pull-down" start="18" size="2" />
+      <BitField name="PUPD10" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O pull-up or pull-down" start="20" size="2" />
+      <BitField name="PUPD11" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O pull-up or pull-down" start="22" size="2" />
+      <BitField name="PUPD12" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O pull-up or pull-down" start="24" size="2" />
+      <BitField name="PUPD13" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O pull-up or pull-down" start="26" size="2" />
+      <BitField name="PUPD14" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O pull-up or pull-down" start="28" size="2" />
+      <BitField name="PUPD15" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O pull-up or pull-down" start="30" size="2" />
+    </Register>
+    <Register name="IDR" description="GPIO port input data register" start="+0x10" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ID0" description="Port input data bit (y = 0..15) These bits are read-only. They contain the input value of the corresponding I/O port." start="0" size="1" />
+      <BitField name="ID1" description="Port input data bit (y = 0..15) These bits are read-only. They contain the input value of the corresponding I/O port." start="1" size="1" />
+      <BitField name="ID2" description="Port input data bit (y = 0..15) These bits are read-only. They contain the input value of the corresponding I/O port." start="2" size="1" />
+      <BitField name="ID3" description="Port input data bit (y = 0..15) These bits are read-only. They contain the input value of the corresponding I/O port." start="3" size="1" />
+      <BitField name="ID4" description="Port input data bit (y = 0..15) These bits are read-only. They contain the input value of the corresponding I/O port." start="4" size="1" />
+      <BitField name="ID5" description="Port input data bit (y = 0..15) These bits are read-only. They contain the input value of the corresponding I/O port." start="5" size="1" />
+      <BitField name="ID6" description="Port input data bit (y = 0..15) These bits are read-only. They contain the input value of the corresponding I/O port." start="6" size="1" />
+      <BitField name="ID7" description="Port input data bit (y = 0..15) These bits are read-only. They contain the input value of the corresponding I/O port." start="7" size="1" />
+      <BitField name="ID8" description="Port input data bit (y = 0..15) These bits are read-only. They contain the input value of the corresponding I/O port." start="8" size="1" />
+      <BitField name="ID9" description="Port input data bit (y = 0..15) These bits are read-only. They contain the input value of the corresponding I/O port." start="9" size="1" />
+      <BitField name="ID10" description="Port input data bit (y = 0..15) These bits are read-only. They contain the input value of the corresponding I/O port." start="10" size="1" />
+      <BitField name="ID11" description="Port input data bit (y = 0..15) These bits are read-only. They contain the input value of the corresponding I/O port." start="11" size="1" />
+      <BitField name="ID12" description="Port input data bit (y = 0..15) These bits are read-only. They contain the input value of the corresponding I/O port." start="12" size="1" />
+      <BitField name="ID13" description="Port input data bit (y = 0..15) These bits are read-only. They contain the input value of the corresponding I/O port." start="13" size="1" />
+      <BitField name="ID14" description="Port input data bit (y = 0..15) These bits are read-only. They contain the input value of the corresponding I/O port." start="14" size="1" />
+      <BitField name="ID15" description="Port input data bit (y = 0..15) These bits are read-only. They contain the input value of the corresponding I/O port." start="15" size="1" />
+    </Register>
+    <Register name="ODR" description="GPIO port output data register" start="+0x14" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OD0" description="Port output data bit These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR or GPIOx_BRR registers (x = A..F)." start="0" size="1" />
+      <BitField name="OD1" description="Port output data bit These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR or GPIOx_BRR registers (x = A..F)." start="1" size="1" />
+      <BitField name="OD2" description="Port output data bit These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR or GPIOx_BRR registers (x = A..F)." start="2" size="1" />
+      <BitField name="OD3" description="Port output data bit These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR or GPIOx_BRR registers (x = A..F)." start="3" size="1" />
+      <BitField name="OD4" description="Port output data bit These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR or GPIOx_BRR registers (x = A..F)." start="4" size="1" />
+      <BitField name="OD5" description="Port output data bit These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR or GPIOx_BRR registers (x = A..F)." start="5" size="1" />
+      <BitField name="OD6" description="Port output data bit These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR or GPIOx_BRR registers (x = A..F)." start="6" size="1" />
+      <BitField name="OD7" description="Port output data bit These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR or GPIOx_BRR registers (x = A..F)." start="7" size="1" />
+      <BitField name="OD8" description="Port output data bit These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR or GPIOx_BRR registers (x = A..F)." start="8" size="1" />
+      <BitField name="OD9" description="Port output data bit These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR or GPIOx_BRR registers (x = A..F)." start="9" size="1" />
+      <BitField name="OD10" description="Port output data bit These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR or GPIOx_BRR registers (x = A..F)." start="10" size="1" />
+      <BitField name="OD11" description="Port output data bit These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR or GPIOx_BRR registers (x = A..F)." start="11" size="1" />
+      <BitField name="OD12" description="Port output data bit These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR or GPIOx_BRR registers (x = A..F)." start="12" size="1" />
+      <BitField name="OD13" description="Port output data bit These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR or GPIOx_BRR registers (x = A..F)." start="13" size="1" />
+      <BitField name="OD14" description="Port output data bit These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR or GPIOx_BRR registers (x = A..F)." start="14" size="1" />
+      <BitField name="OD15" description="Port output data bit These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR or GPIOx_BRR registers (x = A..F)." start="15" size="1" />
+    </Register>
+    <Register name="BSRR" description="GPIO port bit set/reset register" start="+0x18" size="4" access="WriteOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BS0" description="Port x set bit y (y= 0..15) These bits are write-only. A read to these bits returns the value 0x0000." start="0" size="1" />
+      <BitField name="BS1" description="Port x set bit y (y= 0..15) These bits are write-only. A read to these bits returns the value 0x0000." start="1" size="1" />
+      <BitField name="BS2" description="Port x set bit y (y= 0..15) These bits are write-only. A read to these bits returns the value 0x0000." start="2" size="1" />
+      <BitField name="BS3" description="Port x set bit y (y= 0..15) These bits are write-only. A read to these bits returns the value 0x0000." start="3" size="1" />
+      <BitField name="BS4" description="Port x set bit y (y= 0..15) These bits are write-only. A read to these bits returns the value 0x0000." start="4" size="1" />
+      <BitField name="BS5" description="Port x set bit y (y= 0..15) These bits are write-only. A read to these bits returns the value 0x0000." start="5" size="1" />
+      <BitField name="BS6" description="Port x set bit y (y= 0..15) These bits are write-only. A read to these bits returns the value 0x0000." start="6" size="1" />
+      <BitField name="BS7" description="Port x set bit y (y= 0..15) These bits are write-only. A read to these bits returns the value 0x0000." start="7" size="1" />
+      <BitField name="BS8" description="Port x set bit y (y= 0..15) These bits are write-only. A read to these bits returns the value 0x0000." start="8" size="1" />
+      <BitField name="BS9" description="Port x set bit y (y= 0..15) These bits are write-only. A read to these bits returns the value 0x0000." start="9" size="1" />
+      <BitField name="BS10" description="Port x set bit y (y= 0..15) These bits are write-only. A read to these bits returns the value 0x0000." start="10" size="1" />
+      <BitField name="BS11" description="Port x set bit y (y= 0..15) These bits are write-only. A read to these bits returns the value 0x0000." start="11" size="1" />
+      <BitField name="BS12" description="Port x set bit y (y= 0..15) These bits are write-only. A read to these bits returns the value 0x0000." start="12" size="1" />
+      <BitField name="BS13" description="Port x set bit y (y= 0..15) These bits are write-only. A read to these bits returns the value 0x0000." start="13" size="1" />
+      <BitField name="BS14" description="Port x set bit y (y= 0..15) These bits are write-only. A read to these bits returns the value 0x0000." start="14" size="1" />
+      <BitField name="BS15" description="Port x set bit y (y= 0..15) These bits are write-only. A read to these bits returns the value 0x0000." start="15" size="1" />
+      <BitField name="BR0" description="Port x reset bit y (y = 0..15) These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="16" size="1" />
+      <BitField name="BR1" description="Port x reset bit y (y = 0..15) These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="17" size="1" />
+      <BitField name="BR2" description="Port x reset bit y (y = 0..15) These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="18" size="1" />
+      <BitField name="BR3" description="Port x reset bit y (y = 0..15) These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="19" size="1" />
+      <BitField name="BR4" description="Port x reset bit y (y = 0..15) These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="20" size="1" />
+      <BitField name="BR5" description="Port x reset bit y (y = 0..15) These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="21" size="1" />
+      <BitField name="BR6" description="Port x reset bit y (y = 0..15) These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="22" size="1" />
+      <BitField name="BR7" description="Port x reset bit y (y = 0..15) These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="23" size="1" />
+      <BitField name="BR8" description="Port x reset bit y (y = 0..15) These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="24" size="1" />
+      <BitField name="BR9" description="Port x reset bit y (y = 0..15) These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="25" size="1" />
+      <BitField name="BR10" description="Port x reset bit y (y = 0..15) These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="26" size="1" />
+      <BitField name="BR11" description="Port x reset bit y (y = 0..15) These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="27" size="1" />
+      <BitField name="BR12" description="Port x reset bit y (y = 0..15) These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="28" size="1" />
+      <BitField name="BR13" description="Port x reset bit y (y = 0..15) These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="29" size="1" />
+      <BitField name="BR14" description="Port x reset bit y (y = 0..15) These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="30" size="1" />
+      <BitField name="BR15" description="Port x reset bit y (y = 0..15) These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="31" size="1" />
+    </Register>
+    <Register name="LCKR" description="This register is used to lock the configuration of the port bits when a correct write sequence is applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the GPIO. During the write sequence, the value of LCKR[15:0] must not change. When the LOCK sequence has been applied on a port bit, the value of this port bit can no longer be modified until the next MCU reset or peripheral reset.A specific write sequence is used to write to the GPIOx_LCKR register. Only word access (32-bit long) is allowed during this locking sequence.Each lock bit freezes a specific configuration register (control and alternate function registers)." start="+0x1C" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LCK0" description="Port x lock bit y (y= 0..15) These bits are read/write but can only be written when the LCKK bit is 0." start="0" size="1" />
+      <BitField name="LCK1" description="Port x lock bit y (y= 0..15) These bits are read/write but can only be written when the LCKK bit is 0." start="1" size="1" />
+      <BitField name="LCK2" description="Port x lock bit y (y= 0..15) These bits are read/write but can only be written when the LCKK bit is 0." start="2" size="1" />
+      <BitField name="LCK3" description="Port x lock bit y (y= 0..15) These bits are read/write but can only be written when the LCKK bit is 0." start="3" size="1" />
+      <BitField name="LCK4" description="Port x lock bit y (y= 0..15) These bits are read/write but can only be written when the LCKK bit is 0." start="4" size="1" />
+      <BitField name="LCK5" description="Port x lock bit y (y= 0..15) These bits are read/write but can only be written when the LCKK bit is 0." start="5" size="1" />
+      <BitField name="LCK6" description="Port x lock bit y (y= 0..15) These bits are read/write but can only be written when the LCKK bit is 0." start="6" size="1" />
+      <BitField name="LCK7" description="Port x lock bit y (y= 0..15) These bits are read/write but can only be written when the LCKK bit is 0." start="7" size="1" />
+      <BitField name="LCK8" description="Port x lock bit y (y= 0..15) These bits are read/write but can only be written when the LCKK bit is 0." start="8" size="1" />
+      <BitField name="LCK9" description="Port x lock bit y (y= 0..15) These bits are read/write but can only be written when the LCKK bit is 0." start="9" size="1" />
+      <BitField name="LCK10" description="Port x lock bit y (y= 0..15) These bits are read/write but can only be written when the LCKK bit is 0." start="10" size="1" />
+      <BitField name="LCK11" description="Port x lock bit y (y= 0..15) These bits are read/write but can only be written when the LCKK bit is 0." start="11" size="1" />
+      <BitField name="LCK12" description="Port x lock bit y (y= 0..15) These bits are read/write but can only be written when the LCKK bit is 0." start="12" size="1" />
+      <BitField name="LCK13" description="Port x lock bit y (y= 0..15) These bits are read/write but can only be written when the LCKK bit is 0." start="13" size="1" />
+      <BitField name="LCK14" description="Port x lock bit y (y= 0..15) These bits are read/write but can only be written when the LCKK bit is 0." start="14" size="1" />
+      <BitField name="LCK15" description="Port x lock bit y (y= 0..15) These bits are read/write but can only be written when the LCKK bit is 0." start="15" size="1" />
+      <BitField name="LCKK" description="Lock key This bit can be read any time. It can only be modified using the lock key write sequence. LOCK key write sequence: WR LCKR[16] = 1 + LCKR[15:0] WR LCKR[16] = 0 + LCKR[15:0] WR LCKR[16] = 1 + LCKR[15:0] RD LCKR RD LCKR[16] = 1 (this read operation is optional but it confirms that the lock is active) Note: During the LOCK key write sequence, the value of LCK[15:0] must not change. Any error in the lock sequence aborts the lock. After the first lock sequence on any bit of the port, any read access on the LCKK bit will return 1 until the next MCU reset or peripheral reset." start="16" size="1" />
+    </Register>
+    <Register name="AFRL" description="GPIO alternate function low register" start="+0x20" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AFSEL0" description="[3:0]: Alternate function selection for port x pin y (y = 0..7) These bits are written by software to configure alternate function I/Os AFSELy selection:" start="0" size="4" />
+      <BitField name="AFSEL1" description="[3:0]: Alternate function selection for port x pin y (y = 0..7) These bits are written by software to configure alternate function I/Os AFSELy selection:" start="4" size="4" />
+      <BitField name="AFSEL2" description="[3:0]: Alternate function selection for port x pin y (y = 0..7) These bits are written by software to configure alternate function I/Os AFSELy selection:" start="8" size="4" />
+      <BitField name="AFSEL3" description="[3:0]: Alternate function selection for port x pin y (y = 0..7) These bits are written by software to configure alternate function I/Os AFSELy selection:" start="12" size="4" />
+      <BitField name="AFSEL4" description="[3:0]: Alternate function selection for port x pin y (y = 0..7) These bits are written by software to configure alternate function I/Os AFSELy selection:" start="16" size="4" />
+      <BitField name="AFSEL5" description="[3:0]: Alternate function selection for port x pin y (y = 0..7) These bits are written by software to configure alternate function I/Os AFSELy selection:" start="20" size="4" />
+      <BitField name="AFSEL6" description="[3:0]: Alternate function selection for port x pin y (y = 0..7) These bits are written by software to configure alternate function I/Os AFSELy selection:" start="24" size="4" />
+      <BitField name="AFSEL7" description="[3:0]: Alternate function selection for port x pin y (y = 0..7) These bits are written by software to configure alternate function I/Os AFSELy selection:" start="28" size="4" />
+    </Register>
+    <Register name="AFRH" description="GPIO alternate function high register" start="+0x24" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AFSEL8" description="[3:0]: Alternate function selection for port x pin y (y = 8..15) These bits are written by software to configure alternate function I/Os" start="0" size="4" />
+      <BitField name="AFSEL9" description="[3:0]: Alternate function selection for port x pin y (y = 8..15) These bits are written by software to configure alternate function I/Os" start="4" size="4" />
+      <BitField name="AFSEL10" description="[3:0]: Alternate function selection for port x pin y (y = 8..15) These bits are written by software to configure alternate function I/Os" start="8" size="4" />
+      <BitField name="AFSEL11" description="[3:0]: Alternate function selection for port x pin y (y = 8..15) These bits are written by software to configure alternate function I/Os" start="12" size="4" />
+      <BitField name="AFSEL12" description="[3:0]: Alternate function selection for port x pin y (y = 8..15) These bits are written by software to configure alternate function I/Os" start="16" size="4" />
+      <BitField name="AFSEL13" description="[3:0]: Alternate function selection for port x pin y (y = 8..15) These bits are written by software to configure alternate function I/Os" start="20" size="4" />
+      <BitField name="AFSEL14" description="[3:0]: Alternate function selection for port x pin y (y = 8..15) These bits are written by software to configure alternate function I/Os" start="24" size="4" />
+      <BitField name="AFSEL15" description="[3:0]: Alternate function selection for port x pin y (y = 8..15) These bits are written by software to configure alternate function I/Os" start="28" size="4" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="GPIOJ" description="GPIO" start="0x58022400">
+    <Register name="MODER" description="GPIO port mode register" start="+0x0" size="4" access="Read/Write" reset_value="0xABFFFFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="MODE0" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O mode." start="0" size="2" />
+      <BitField name="MODE1" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O mode." start="2" size="2" />
+      <BitField name="MODE2" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O mode." start="4" size="2" />
+      <BitField name="MODE3" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O mode." start="6" size="2" />
+      <BitField name="MODE4" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O mode." start="8" size="2" />
+      <BitField name="MODE5" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O mode." start="10" size="2" />
+      <BitField name="MODE6" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O mode." start="12" size="2" />
+      <BitField name="MODE7" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O mode." start="14" size="2" />
+      <BitField name="MODE8" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O mode." start="16" size="2" />
+      <BitField name="MODE9" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O mode." start="18" size="2" />
+      <BitField name="MODE10" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O mode." start="20" size="2" />
+      <BitField name="MODE11" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O mode." start="22" size="2" />
+      <BitField name="MODE12" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O mode." start="24" size="2" />
+      <BitField name="MODE13" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O mode." start="26" size="2" />
+      <BitField name="MODE14" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O mode." start="28" size="2" />
+      <BitField name="MODE15" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O mode." start="30" size="2" />
+    </Register>
+    <Register name="OTYPER" description="GPIO port output type register" start="+0x4" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OT0" description="Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output type." start="0" size="1" />
+      <BitField name="OT1" description="Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output type." start="1" size="1" />
+      <BitField name="OT2" description="Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output type." start="2" size="1" />
+      <BitField name="OT3" description="Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output type." start="3" size="1" />
+      <BitField name="OT4" description="Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output type." start="4" size="1" />
+      <BitField name="OT5" description="Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output type." start="5" size="1" />
+      <BitField name="OT6" description="Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output type." start="6" size="1" />
+      <BitField name="OT7" description="Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output type." start="7" size="1" />
+      <BitField name="OT8" description="Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output type." start="8" size="1" />
+      <BitField name="OT9" description="Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output type." start="9" size="1" />
+      <BitField name="OT10" description="Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output type." start="10" size="1" />
+      <BitField name="OT11" description="Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output type." start="11" size="1" />
+      <BitField name="OT12" description="Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output type." start="12" size="1" />
+      <BitField name="OT13" description="Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output type." start="13" size="1" />
+      <BitField name="OT14" description="Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output type." start="14" size="1" />
+      <BitField name="OT15" description="Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output type." start="15" size="1" />
+    </Register>
+    <Register name="OSPEEDR" description="GPIO port output speed register" start="+0x8" size="4" access="Read/Write" reset_value="0x0C000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OSPEED0" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed." start="0" size="2" />
+      <BitField name="OSPEED1" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed." start="2" size="2" />
+      <BitField name="OSPEED2" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed." start="4" size="2" />
+      <BitField name="OSPEED3" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed." start="6" size="2" />
+      <BitField name="OSPEED4" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed." start="8" size="2" />
+      <BitField name="OSPEED5" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed." start="10" size="2" />
+      <BitField name="OSPEED6" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed." start="12" size="2" />
+      <BitField name="OSPEED7" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed." start="14" size="2" />
+      <BitField name="OSPEED8" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed." start="16" size="2" />
+      <BitField name="OSPEED9" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed." start="18" size="2" />
+      <BitField name="OSPEED10" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed." start="20" size="2" />
+      <BitField name="OSPEED11" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed." start="22" size="2" />
+      <BitField name="OSPEED12" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed." start="24" size="2" />
+      <BitField name="OSPEED13" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed." start="26" size="2" />
+      <BitField name="OSPEED14" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed." start="28" size="2" />
+      <BitField name="OSPEED15" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed." start="30" size="2" />
+    </Register>
+    <Register name="PUPDR" description="GPIO port pull-up/pull-down register" start="+0xC" size="4" access="Read/Write" reset_value="0x12100000" reset_mask="0xFFFFFFFF">
+      <BitField name="PUPD0" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O pull-up or pull-down" start="0" size="2" />
+      <BitField name="PUPD1" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O pull-up or pull-down" start="2" size="2" />
+      <BitField name="PUPD2" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O pull-up or pull-down" start="4" size="2" />
+      <BitField name="PUPD3" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O pull-up or pull-down" start="6" size="2" />
+      <BitField name="PUPD4" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O pull-up or pull-down" start="8" size="2" />
+      <BitField name="PUPD5" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O pull-up or pull-down" start="10" size="2" />
+      <BitField name="PUPD6" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O pull-up or pull-down" start="12" size="2" />
+      <BitField name="PUPD7" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O pull-up or pull-down" start="14" size="2" />
+      <BitField name="PUPD8" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O pull-up or pull-down" start="16" size="2" />
+      <BitField name="PUPD9" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O pull-up or pull-down" start="18" size="2" />
+      <BitField name="PUPD10" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O pull-up or pull-down" start="20" size="2" />
+      <BitField name="PUPD11" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O pull-up or pull-down" start="22" size="2" />
+      <BitField name="PUPD12" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O pull-up or pull-down" start="24" size="2" />
+      <BitField name="PUPD13" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O pull-up or pull-down" start="26" size="2" />
+      <BitField name="PUPD14" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O pull-up or pull-down" start="28" size="2" />
+      <BitField name="PUPD15" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O pull-up or pull-down" start="30" size="2" />
+    </Register>
+    <Register name="IDR" description="GPIO port input data register" start="+0x10" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ID0" description="Port input data bit (y = 0..15) These bits are read-only. They contain the input value of the corresponding I/O port." start="0" size="1" />
+      <BitField name="ID1" description="Port input data bit (y = 0..15) These bits are read-only. They contain the input value of the corresponding I/O port." start="1" size="1" />
+      <BitField name="ID2" description="Port input data bit (y = 0..15) These bits are read-only. They contain the input value of the corresponding I/O port." start="2" size="1" />
+      <BitField name="ID3" description="Port input data bit (y = 0..15) These bits are read-only. They contain the input value of the corresponding I/O port." start="3" size="1" />
+      <BitField name="ID4" description="Port input data bit (y = 0..15) These bits are read-only. They contain the input value of the corresponding I/O port." start="4" size="1" />
+      <BitField name="ID5" description="Port input data bit (y = 0..15) These bits are read-only. They contain the input value of the corresponding I/O port." start="5" size="1" />
+      <BitField name="ID6" description="Port input data bit (y = 0..15) These bits are read-only. They contain the input value of the corresponding I/O port." start="6" size="1" />
+      <BitField name="ID7" description="Port input data bit (y = 0..15) These bits are read-only. They contain the input value of the corresponding I/O port." start="7" size="1" />
+      <BitField name="ID8" description="Port input data bit (y = 0..15) These bits are read-only. They contain the input value of the corresponding I/O port." start="8" size="1" />
+      <BitField name="ID9" description="Port input data bit (y = 0..15) These bits are read-only. They contain the input value of the corresponding I/O port." start="9" size="1" />
+      <BitField name="ID10" description="Port input data bit (y = 0..15) These bits are read-only. They contain the input value of the corresponding I/O port." start="10" size="1" />
+      <BitField name="ID11" description="Port input data bit (y = 0..15) These bits are read-only. They contain the input value of the corresponding I/O port." start="11" size="1" />
+      <BitField name="ID12" description="Port input data bit (y = 0..15) These bits are read-only. They contain the input value of the corresponding I/O port." start="12" size="1" />
+      <BitField name="ID13" description="Port input data bit (y = 0..15) These bits are read-only. They contain the input value of the corresponding I/O port." start="13" size="1" />
+      <BitField name="ID14" description="Port input data bit (y = 0..15) These bits are read-only. They contain the input value of the corresponding I/O port." start="14" size="1" />
+      <BitField name="ID15" description="Port input data bit (y = 0..15) These bits are read-only. They contain the input value of the corresponding I/O port." start="15" size="1" />
+    </Register>
+    <Register name="ODR" description="GPIO port output data register" start="+0x14" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OD0" description="Port output data bit These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR or GPIOx_BRR registers (x = A..F)." start="0" size="1" />
+      <BitField name="OD1" description="Port output data bit These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR or GPIOx_BRR registers (x = A..F)." start="1" size="1" />
+      <BitField name="OD2" description="Port output data bit These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR or GPIOx_BRR registers (x = A..F)." start="2" size="1" />
+      <BitField name="OD3" description="Port output data bit These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR or GPIOx_BRR registers (x = A..F)." start="3" size="1" />
+      <BitField name="OD4" description="Port output data bit These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR or GPIOx_BRR registers (x = A..F)." start="4" size="1" />
+      <BitField name="OD5" description="Port output data bit These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR or GPIOx_BRR registers (x = A..F)." start="5" size="1" />
+      <BitField name="OD6" description="Port output data bit These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR or GPIOx_BRR registers (x = A..F)." start="6" size="1" />
+      <BitField name="OD7" description="Port output data bit These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR or GPIOx_BRR registers (x = A..F)." start="7" size="1" />
+      <BitField name="OD8" description="Port output data bit These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR or GPIOx_BRR registers (x = A..F)." start="8" size="1" />
+      <BitField name="OD9" description="Port output data bit These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR or GPIOx_BRR registers (x = A..F)." start="9" size="1" />
+      <BitField name="OD10" description="Port output data bit These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR or GPIOx_BRR registers (x = A..F)." start="10" size="1" />
+      <BitField name="OD11" description="Port output data bit These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR or GPIOx_BRR registers (x = A..F)." start="11" size="1" />
+      <BitField name="OD12" description="Port output data bit These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR or GPIOx_BRR registers (x = A..F)." start="12" size="1" />
+      <BitField name="OD13" description="Port output data bit These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR or GPIOx_BRR registers (x = A..F)." start="13" size="1" />
+      <BitField name="OD14" description="Port output data bit These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR or GPIOx_BRR registers (x = A..F)." start="14" size="1" />
+      <BitField name="OD15" description="Port output data bit These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR or GPIOx_BRR registers (x = A..F)." start="15" size="1" />
+    </Register>
+    <Register name="BSRR" description="GPIO port bit set/reset register" start="+0x18" size="4" access="WriteOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BS0" description="Port x set bit y (y= 0..15) These bits are write-only. A read to these bits returns the value 0x0000." start="0" size="1" />
+      <BitField name="BS1" description="Port x set bit y (y= 0..15) These bits are write-only. A read to these bits returns the value 0x0000." start="1" size="1" />
+      <BitField name="BS2" description="Port x set bit y (y= 0..15) These bits are write-only. A read to these bits returns the value 0x0000." start="2" size="1" />
+      <BitField name="BS3" description="Port x set bit y (y= 0..15) These bits are write-only. A read to these bits returns the value 0x0000." start="3" size="1" />
+      <BitField name="BS4" description="Port x set bit y (y= 0..15) These bits are write-only. A read to these bits returns the value 0x0000." start="4" size="1" />
+      <BitField name="BS5" description="Port x set bit y (y= 0..15) These bits are write-only. A read to these bits returns the value 0x0000." start="5" size="1" />
+      <BitField name="BS6" description="Port x set bit y (y= 0..15) These bits are write-only. A read to these bits returns the value 0x0000." start="6" size="1" />
+      <BitField name="BS7" description="Port x set bit y (y= 0..15) These bits are write-only. A read to these bits returns the value 0x0000." start="7" size="1" />
+      <BitField name="BS8" description="Port x set bit y (y= 0..15) These bits are write-only. A read to these bits returns the value 0x0000." start="8" size="1" />
+      <BitField name="BS9" description="Port x set bit y (y= 0..15) These bits are write-only. A read to these bits returns the value 0x0000." start="9" size="1" />
+      <BitField name="BS10" description="Port x set bit y (y= 0..15) These bits are write-only. A read to these bits returns the value 0x0000." start="10" size="1" />
+      <BitField name="BS11" description="Port x set bit y (y= 0..15) These bits are write-only. A read to these bits returns the value 0x0000." start="11" size="1" />
+      <BitField name="BS12" description="Port x set bit y (y= 0..15) These bits are write-only. A read to these bits returns the value 0x0000." start="12" size="1" />
+      <BitField name="BS13" description="Port x set bit y (y= 0..15) These bits are write-only. A read to these bits returns the value 0x0000." start="13" size="1" />
+      <BitField name="BS14" description="Port x set bit y (y= 0..15) These bits are write-only. A read to these bits returns the value 0x0000." start="14" size="1" />
+      <BitField name="BS15" description="Port x set bit y (y= 0..15) These bits are write-only. A read to these bits returns the value 0x0000." start="15" size="1" />
+      <BitField name="BR0" description="Port x reset bit y (y = 0..15) These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="16" size="1" />
+      <BitField name="BR1" description="Port x reset bit y (y = 0..15) These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="17" size="1" />
+      <BitField name="BR2" description="Port x reset bit y (y = 0..15) These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="18" size="1" />
+      <BitField name="BR3" description="Port x reset bit y (y = 0..15) These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="19" size="1" />
+      <BitField name="BR4" description="Port x reset bit y (y = 0..15) These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="20" size="1" />
+      <BitField name="BR5" description="Port x reset bit y (y = 0..15) These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="21" size="1" />
+      <BitField name="BR6" description="Port x reset bit y (y = 0..15) These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="22" size="1" />
+      <BitField name="BR7" description="Port x reset bit y (y = 0..15) These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="23" size="1" />
+      <BitField name="BR8" description="Port x reset bit y (y = 0..15) These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="24" size="1" />
+      <BitField name="BR9" description="Port x reset bit y (y = 0..15) These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="25" size="1" />
+      <BitField name="BR10" description="Port x reset bit y (y = 0..15) These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="26" size="1" />
+      <BitField name="BR11" description="Port x reset bit y (y = 0..15) These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="27" size="1" />
+      <BitField name="BR12" description="Port x reset bit y (y = 0..15) These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="28" size="1" />
+      <BitField name="BR13" description="Port x reset bit y (y = 0..15) These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="29" size="1" />
+      <BitField name="BR14" description="Port x reset bit y (y = 0..15) These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="30" size="1" />
+      <BitField name="BR15" description="Port x reset bit y (y = 0..15) These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="31" size="1" />
+    </Register>
+    <Register name="LCKR" description="This register is used to lock the configuration of the port bits when a correct write sequence is applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the GPIO. During the write sequence, the value of LCKR[15:0] must not change. When the LOCK sequence has been applied on a port bit, the value of this port bit can no longer be modified until the next MCU reset or peripheral reset.A specific write sequence is used to write to the GPIOx_LCKR register. Only word access (32-bit long) is allowed during this locking sequence.Each lock bit freezes a specific configuration register (control and alternate function registers)." start="+0x1C" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LCK0" description="Port x lock bit y (y= 0..15) These bits are read/write but can only be written when the LCKK bit is 0." start="0" size="1" />
+      <BitField name="LCK1" description="Port x lock bit y (y= 0..15) These bits are read/write but can only be written when the LCKK bit is 0." start="1" size="1" />
+      <BitField name="LCK2" description="Port x lock bit y (y= 0..15) These bits are read/write but can only be written when the LCKK bit is 0." start="2" size="1" />
+      <BitField name="LCK3" description="Port x lock bit y (y= 0..15) These bits are read/write but can only be written when the LCKK bit is 0." start="3" size="1" />
+      <BitField name="LCK4" description="Port x lock bit y (y= 0..15) These bits are read/write but can only be written when the LCKK bit is 0." start="4" size="1" />
+      <BitField name="LCK5" description="Port x lock bit y (y= 0..15) These bits are read/write but can only be written when the LCKK bit is 0." start="5" size="1" />
+      <BitField name="LCK6" description="Port x lock bit y (y= 0..15) These bits are read/write but can only be written when the LCKK bit is 0." start="6" size="1" />
+      <BitField name="LCK7" description="Port x lock bit y (y= 0..15) These bits are read/write but can only be written when the LCKK bit is 0." start="7" size="1" />
+      <BitField name="LCK8" description="Port x lock bit y (y= 0..15) These bits are read/write but can only be written when the LCKK bit is 0." start="8" size="1" />
+      <BitField name="LCK9" description="Port x lock bit y (y= 0..15) These bits are read/write but can only be written when the LCKK bit is 0." start="9" size="1" />
+      <BitField name="LCK10" description="Port x lock bit y (y= 0..15) These bits are read/write but can only be written when the LCKK bit is 0." start="10" size="1" />
+      <BitField name="LCK11" description="Port x lock bit y (y= 0..15) These bits are read/write but can only be written when the LCKK bit is 0." start="11" size="1" />
+      <BitField name="LCK12" description="Port x lock bit y (y= 0..15) These bits are read/write but can only be written when the LCKK bit is 0." start="12" size="1" />
+      <BitField name="LCK13" description="Port x lock bit y (y= 0..15) These bits are read/write but can only be written when the LCKK bit is 0." start="13" size="1" />
+      <BitField name="LCK14" description="Port x lock bit y (y= 0..15) These bits are read/write but can only be written when the LCKK bit is 0." start="14" size="1" />
+      <BitField name="LCK15" description="Port x lock bit y (y= 0..15) These bits are read/write but can only be written when the LCKK bit is 0." start="15" size="1" />
+      <BitField name="LCKK" description="Lock key This bit can be read any time. It can only be modified using the lock key write sequence. LOCK key write sequence: WR LCKR[16] = 1 + LCKR[15:0] WR LCKR[16] = 0 + LCKR[15:0] WR LCKR[16] = 1 + LCKR[15:0] RD LCKR RD LCKR[16] = 1 (this read operation is optional but it confirms that the lock is active) Note: During the LOCK key write sequence, the value of LCK[15:0] must not change. Any error in the lock sequence aborts the lock. After the first lock sequence on any bit of the port, any read access on the LCKK bit will return 1 until the next MCU reset or peripheral reset." start="16" size="1" />
+    </Register>
+    <Register name="AFRL" description="GPIO alternate function low register" start="+0x20" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AFSEL0" description="[3:0]: Alternate function selection for port x pin y (y = 0..7) These bits are written by software to configure alternate function I/Os AFSELy selection:" start="0" size="4" />
+      <BitField name="AFSEL1" description="[3:0]: Alternate function selection for port x pin y (y = 0..7) These bits are written by software to configure alternate function I/Os AFSELy selection:" start="4" size="4" />
+      <BitField name="AFSEL2" description="[3:0]: Alternate function selection for port x pin y (y = 0..7) These bits are written by software to configure alternate function I/Os AFSELy selection:" start="8" size="4" />
+      <BitField name="AFSEL3" description="[3:0]: Alternate function selection for port x pin y (y = 0..7) These bits are written by software to configure alternate function I/Os AFSELy selection:" start="12" size="4" />
+      <BitField name="AFSEL4" description="[3:0]: Alternate function selection for port x pin y (y = 0..7) These bits are written by software to configure alternate function I/Os AFSELy selection:" start="16" size="4" />
+      <BitField name="AFSEL5" description="[3:0]: Alternate function selection for port x pin y (y = 0..7) These bits are written by software to configure alternate function I/Os AFSELy selection:" start="20" size="4" />
+      <BitField name="AFSEL6" description="[3:0]: Alternate function selection for port x pin y (y = 0..7) These bits are written by software to configure alternate function I/Os AFSELy selection:" start="24" size="4" />
+      <BitField name="AFSEL7" description="[3:0]: Alternate function selection for port x pin y (y = 0..7) These bits are written by software to configure alternate function I/Os AFSELy selection:" start="28" size="4" />
+    </Register>
+    <Register name="AFRH" description="GPIO alternate function high register" start="+0x24" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AFSEL8" description="[3:0]: Alternate function selection for port x pin y (y = 8..15) These bits are written by software to configure alternate function I/Os" start="0" size="4" />
+      <BitField name="AFSEL9" description="[3:0]: Alternate function selection for port x pin y (y = 8..15) These bits are written by software to configure alternate function I/Os" start="4" size="4" />
+      <BitField name="AFSEL10" description="[3:0]: Alternate function selection for port x pin y (y = 8..15) These bits are written by software to configure alternate function I/Os" start="8" size="4" />
+      <BitField name="AFSEL11" description="[3:0]: Alternate function selection for port x pin y (y = 8..15) These bits are written by software to configure alternate function I/Os" start="12" size="4" />
+      <BitField name="AFSEL12" description="[3:0]: Alternate function selection for port x pin y (y = 8..15) These bits are written by software to configure alternate function I/Os" start="16" size="4" />
+      <BitField name="AFSEL13" description="[3:0]: Alternate function selection for port x pin y (y = 8..15) These bits are written by software to configure alternate function I/Os" start="20" size="4" />
+      <BitField name="AFSEL14" description="[3:0]: Alternate function selection for port x pin y (y = 8..15) These bits are written by software to configure alternate function I/Os" start="24" size="4" />
+      <BitField name="AFSEL15" description="[3:0]: Alternate function selection for port x pin y (y = 8..15) These bits are written by software to configure alternate function I/Os" start="28" size="4" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="GPIOK" description="GPIO" start="0x58022800">
+    <Register name="MODER" description="GPIO port mode register" start="+0x0" size="4" access="Read/Write" reset_value="0xABFFFFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="MODE0" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O mode." start="0" size="2" />
+      <BitField name="MODE1" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O mode." start="2" size="2" />
+      <BitField name="MODE2" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O mode." start="4" size="2" />
+      <BitField name="MODE3" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O mode." start="6" size="2" />
+      <BitField name="MODE4" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O mode." start="8" size="2" />
+      <BitField name="MODE5" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O mode." start="10" size="2" />
+      <BitField name="MODE6" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O mode." start="12" size="2" />
+      <BitField name="MODE7" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O mode." start="14" size="2" />
+      <BitField name="MODE8" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O mode." start="16" size="2" />
+      <BitField name="MODE9" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O mode." start="18" size="2" />
+      <BitField name="MODE10" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O mode." start="20" size="2" />
+      <BitField name="MODE11" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O mode." start="22" size="2" />
+      <BitField name="MODE12" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O mode." start="24" size="2" />
+      <BitField name="MODE13" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O mode." start="26" size="2" />
+      <BitField name="MODE14" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O mode." start="28" size="2" />
+      <BitField name="MODE15" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O mode." start="30" size="2" />
+    </Register>
+    <Register name="OTYPER" description="GPIO port output type register" start="+0x4" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OT0" description="Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output type." start="0" size="1" />
+      <BitField name="OT1" description="Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output type." start="1" size="1" />
+      <BitField name="OT2" description="Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output type." start="2" size="1" />
+      <BitField name="OT3" description="Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output type." start="3" size="1" />
+      <BitField name="OT4" description="Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output type." start="4" size="1" />
+      <BitField name="OT5" description="Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output type." start="5" size="1" />
+      <BitField name="OT6" description="Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output type." start="6" size="1" />
+      <BitField name="OT7" description="Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output type." start="7" size="1" />
+      <BitField name="OT8" description="Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output type." start="8" size="1" />
+      <BitField name="OT9" description="Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output type." start="9" size="1" />
+      <BitField name="OT10" description="Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output type." start="10" size="1" />
+      <BitField name="OT11" description="Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output type." start="11" size="1" />
+      <BitField name="OT12" description="Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output type." start="12" size="1" />
+      <BitField name="OT13" description="Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output type." start="13" size="1" />
+      <BitField name="OT14" description="Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output type." start="14" size="1" />
+      <BitField name="OT15" description="Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output type." start="15" size="1" />
+    </Register>
+    <Register name="OSPEEDR" description="GPIO port output speed register" start="+0x8" size="4" access="Read/Write" reset_value="0x0C000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OSPEED0" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed." start="0" size="2" />
+      <BitField name="OSPEED1" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed." start="2" size="2" />
+      <BitField name="OSPEED2" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed." start="4" size="2" />
+      <BitField name="OSPEED3" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed." start="6" size="2" />
+      <BitField name="OSPEED4" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed." start="8" size="2" />
+      <BitField name="OSPEED5" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed." start="10" size="2" />
+      <BitField name="OSPEED6" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed." start="12" size="2" />
+      <BitField name="OSPEED7" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed." start="14" size="2" />
+      <BitField name="OSPEED8" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed." start="16" size="2" />
+      <BitField name="OSPEED9" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed." start="18" size="2" />
+      <BitField name="OSPEED10" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed." start="20" size="2" />
+      <BitField name="OSPEED11" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed." start="22" size="2" />
+      <BitField name="OSPEED12" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed." start="24" size="2" />
+      <BitField name="OSPEED13" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed." start="26" size="2" />
+      <BitField name="OSPEED14" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed." start="28" size="2" />
+      <BitField name="OSPEED15" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output speed. Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed." start="30" size="2" />
+    </Register>
+    <Register name="PUPDR" description="GPIO port pull-up/pull-down register" start="+0xC" size="4" access="Read/Write" reset_value="0x12100000" reset_mask="0xFFFFFFFF">
+      <BitField name="PUPD0" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O pull-up or pull-down" start="0" size="2" />
+      <BitField name="PUPD1" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O pull-up or pull-down" start="2" size="2" />
+      <BitField name="PUPD2" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O pull-up or pull-down" start="4" size="2" />
+      <BitField name="PUPD3" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O pull-up or pull-down" start="6" size="2" />
+      <BitField name="PUPD4" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O pull-up or pull-down" start="8" size="2" />
+      <BitField name="PUPD5" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O pull-up or pull-down" start="10" size="2" />
+      <BitField name="PUPD6" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O pull-up or pull-down" start="12" size="2" />
+      <BitField name="PUPD7" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O pull-up or pull-down" start="14" size="2" />
+      <BitField name="PUPD8" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O pull-up or pull-down" start="16" size="2" />
+      <BitField name="PUPD9" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O pull-up or pull-down" start="18" size="2" />
+      <BitField name="PUPD10" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O pull-up or pull-down" start="20" size="2" />
+      <BitField name="PUPD11" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O pull-up or pull-down" start="22" size="2" />
+      <BitField name="PUPD12" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O pull-up or pull-down" start="24" size="2" />
+      <BitField name="PUPD13" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O pull-up or pull-down" start="26" size="2" />
+      <BitField name="PUPD14" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O pull-up or pull-down" start="28" size="2" />
+      <BitField name="PUPD15" description="[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O pull-up or pull-down" start="30" size="2" />
+    </Register>
+    <Register name="IDR" description="GPIO port input data register" start="+0x10" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ID0" description="Port input data bit (y = 0..15) These bits are read-only. They contain the input value of the corresponding I/O port." start="0" size="1" />
+      <BitField name="ID1" description="Port input data bit (y = 0..15) These bits are read-only. They contain the input value of the corresponding I/O port." start="1" size="1" />
+      <BitField name="ID2" description="Port input data bit (y = 0..15) These bits are read-only. They contain the input value of the corresponding I/O port." start="2" size="1" />
+      <BitField name="ID3" description="Port input data bit (y = 0..15) These bits are read-only. They contain the input value of the corresponding I/O port." start="3" size="1" />
+      <BitField name="ID4" description="Port input data bit (y = 0..15) These bits are read-only. They contain the input value of the corresponding I/O port." start="4" size="1" />
+      <BitField name="ID5" description="Port input data bit (y = 0..15) These bits are read-only. They contain the input value of the corresponding I/O port." start="5" size="1" />
+      <BitField name="ID6" description="Port input data bit (y = 0..15) These bits are read-only. They contain the input value of the corresponding I/O port." start="6" size="1" />
+      <BitField name="ID7" description="Port input data bit (y = 0..15) These bits are read-only. They contain the input value of the corresponding I/O port." start="7" size="1" />
+      <BitField name="ID8" description="Port input data bit (y = 0..15) These bits are read-only. They contain the input value of the corresponding I/O port." start="8" size="1" />
+      <BitField name="ID9" description="Port input data bit (y = 0..15) These bits are read-only. They contain the input value of the corresponding I/O port." start="9" size="1" />
+      <BitField name="ID10" description="Port input data bit (y = 0..15) These bits are read-only. They contain the input value of the corresponding I/O port." start="10" size="1" />
+      <BitField name="ID11" description="Port input data bit (y = 0..15) These bits are read-only. They contain the input value of the corresponding I/O port." start="11" size="1" />
+      <BitField name="ID12" description="Port input data bit (y = 0..15) These bits are read-only. They contain the input value of the corresponding I/O port." start="12" size="1" />
+      <BitField name="ID13" description="Port input data bit (y = 0..15) These bits are read-only. They contain the input value of the corresponding I/O port." start="13" size="1" />
+      <BitField name="ID14" description="Port input data bit (y = 0..15) These bits are read-only. They contain the input value of the corresponding I/O port." start="14" size="1" />
+      <BitField name="ID15" description="Port input data bit (y = 0..15) These bits are read-only. They contain the input value of the corresponding I/O port." start="15" size="1" />
+    </Register>
+    <Register name="ODR" description="GPIO port output data register" start="+0x14" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OD0" description="Port output data bit These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR or GPIOx_BRR registers (x = A..F)." start="0" size="1" />
+      <BitField name="OD1" description="Port output data bit These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR or GPIOx_BRR registers (x = A..F)." start="1" size="1" />
+      <BitField name="OD2" description="Port output data bit These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR or GPIOx_BRR registers (x = A..F)." start="2" size="1" />
+      <BitField name="OD3" description="Port output data bit These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR or GPIOx_BRR registers (x = A..F)." start="3" size="1" />
+      <BitField name="OD4" description="Port output data bit These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR or GPIOx_BRR registers (x = A..F)." start="4" size="1" />
+      <BitField name="OD5" description="Port output data bit These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR or GPIOx_BRR registers (x = A..F)." start="5" size="1" />
+      <BitField name="OD6" description="Port output data bit These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR or GPIOx_BRR registers (x = A..F)." start="6" size="1" />
+      <BitField name="OD7" description="Port output data bit These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR or GPIOx_BRR registers (x = A..F)." start="7" size="1" />
+      <BitField name="OD8" description="Port output data bit These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR or GPIOx_BRR registers (x = A..F)." start="8" size="1" />
+      <BitField name="OD9" description="Port output data bit These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR or GPIOx_BRR registers (x = A..F)." start="9" size="1" />
+      <BitField name="OD10" description="Port output data bit These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR or GPIOx_BRR registers (x = A..F)." start="10" size="1" />
+      <BitField name="OD11" description="Port output data bit These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR or GPIOx_BRR registers (x = A..F)." start="11" size="1" />
+      <BitField name="OD12" description="Port output data bit These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR or GPIOx_BRR registers (x = A..F)." start="12" size="1" />
+      <BitField name="OD13" description="Port output data bit These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR or GPIOx_BRR registers (x = A..F)." start="13" size="1" />
+      <BitField name="OD14" description="Port output data bit These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR or GPIOx_BRR registers (x = A..F)." start="14" size="1" />
+      <BitField name="OD15" description="Port output data bit These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR or GPIOx_BRR registers (x = A..F)." start="15" size="1" />
+    </Register>
+    <Register name="BSRR" description="GPIO port bit set/reset register" start="+0x18" size="4" access="WriteOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BS0" description="Port x set bit y (y= 0..15) These bits are write-only. A read to these bits returns the value 0x0000." start="0" size="1" />
+      <BitField name="BS1" description="Port x set bit y (y= 0..15) These bits are write-only. A read to these bits returns the value 0x0000." start="1" size="1" />
+      <BitField name="BS2" description="Port x set bit y (y= 0..15) These bits are write-only. A read to these bits returns the value 0x0000." start="2" size="1" />
+      <BitField name="BS3" description="Port x set bit y (y= 0..15) These bits are write-only. A read to these bits returns the value 0x0000." start="3" size="1" />
+      <BitField name="BS4" description="Port x set bit y (y= 0..15) These bits are write-only. A read to these bits returns the value 0x0000." start="4" size="1" />
+      <BitField name="BS5" description="Port x set bit y (y= 0..15) These bits are write-only. A read to these bits returns the value 0x0000." start="5" size="1" />
+      <BitField name="BS6" description="Port x set bit y (y= 0..15) These bits are write-only. A read to these bits returns the value 0x0000." start="6" size="1" />
+      <BitField name="BS7" description="Port x set bit y (y= 0..15) These bits are write-only. A read to these bits returns the value 0x0000." start="7" size="1" />
+      <BitField name="BS8" description="Port x set bit y (y= 0..15) These bits are write-only. A read to these bits returns the value 0x0000." start="8" size="1" />
+      <BitField name="BS9" description="Port x set bit y (y= 0..15) These bits are write-only. A read to these bits returns the value 0x0000." start="9" size="1" />
+      <BitField name="BS10" description="Port x set bit y (y= 0..15) These bits are write-only. A read to these bits returns the value 0x0000." start="10" size="1" />
+      <BitField name="BS11" description="Port x set bit y (y= 0..15) These bits are write-only. A read to these bits returns the value 0x0000." start="11" size="1" />
+      <BitField name="BS12" description="Port x set bit y (y= 0..15) These bits are write-only. A read to these bits returns the value 0x0000." start="12" size="1" />
+      <BitField name="BS13" description="Port x set bit y (y= 0..15) These bits are write-only. A read to these bits returns the value 0x0000." start="13" size="1" />
+      <BitField name="BS14" description="Port x set bit y (y= 0..15) These bits are write-only. A read to these bits returns the value 0x0000." start="14" size="1" />
+      <BitField name="BS15" description="Port x set bit y (y= 0..15) These bits are write-only. A read to these bits returns the value 0x0000." start="15" size="1" />
+      <BitField name="BR0" description="Port x reset bit y (y = 0..15) These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="16" size="1" />
+      <BitField name="BR1" description="Port x reset bit y (y = 0..15) These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="17" size="1" />
+      <BitField name="BR2" description="Port x reset bit y (y = 0..15) These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="18" size="1" />
+      <BitField name="BR3" description="Port x reset bit y (y = 0..15) These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="19" size="1" />
+      <BitField name="BR4" description="Port x reset bit y (y = 0..15) These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="20" size="1" />
+      <BitField name="BR5" description="Port x reset bit y (y = 0..15) These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="21" size="1" />
+      <BitField name="BR6" description="Port x reset bit y (y = 0..15) These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="22" size="1" />
+      <BitField name="BR7" description="Port x reset bit y (y = 0..15) These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="23" size="1" />
+      <BitField name="BR8" description="Port x reset bit y (y = 0..15) These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="24" size="1" />
+      <BitField name="BR9" description="Port x reset bit y (y = 0..15) These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="25" size="1" />
+      <BitField name="BR10" description="Port x reset bit y (y = 0..15) These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="26" size="1" />
+      <BitField name="BR11" description="Port x reset bit y (y = 0..15) These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="27" size="1" />
+      <BitField name="BR12" description="Port x reset bit y (y = 0..15) These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="28" size="1" />
+      <BitField name="BR13" description="Port x reset bit y (y = 0..15) These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="29" size="1" />
+      <BitField name="BR14" description="Port x reset bit y (y = 0..15) These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="30" size="1" />
+      <BitField name="BR15" description="Port x reset bit y (y = 0..15) These bits are write-only. A read to these bits returns the value 0x0000. Note: If both BSx and BRx are set, BSx has priority." start="31" size="1" />
+    </Register>
+    <Register name="LCKR" description="This register is used to lock the configuration of the port bits when a correct write sequence is applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the GPIO. During the write sequence, the value of LCKR[15:0] must not change. When the LOCK sequence has been applied on a port bit, the value of this port bit can no longer be modified until the next MCU reset or peripheral reset.A specific write sequence is used to write to the GPIOx_LCKR register. Only word access (32-bit long) is allowed during this locking sequence.Each lock bit freezes a specific configuration register (control and alternate function registers)." start="+0x1C" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LCK0" description="Port x lock bit y (y= 0..15) These bits are read/write but can only be written when the LCKK bit is 0." start="0" size="1" />
+      <BitField name="LCK1" description="Port x lock bit y (y= 0..15) These bits are read/write but can only be written when the LCKK bit is 0." start="1" size="1" />
+      <BitField name="LCK2" description="Port x lock bit y (y= 0..15) These bits are read/write but can only be written when the LCKK bit is 0." start="2" size="1" />
+      <BitField name="LCK3" description="Port x lock bit y (y= 0..15) These bits are read/write but can only be written when the LCKK bit is 0." start="3" size="1" />
+      <BitField name="LCK4" description="Port x lock bit y (y= 0..15) These bits are read/write but can only be written when the LCKK bit is 0." start="4" size="1" />
+      <BitField name="LCK5" description="Port x lock bit y (y= 0..15) These bits are read/write but can only be written when the LCKK bit is 0." start="5" size="1" />
+      <BitField name="LCK6" description="Port x lock bit y (y= 0..15) These bits are read/write but can only be written when the LCKK bit is 0." start="6" size="1" />
+      <BitField name="LCK7" description="Port x lock bit y (y= 0..15) These bits are read/write but can only be written when the LCKK bit is 0." start="7" size="1" />
+      <BitField name="LCK8" description="Port x lock bit y (y= 0..15) These bits are read/write but can only be written when the LCKK bit is 0." start="8" size="1" />
+      <BitField name="LCK9" description="Port x lock bit y (y= 0..15) These bits are read/write but can only be written when the LCKK bit is 0." start="9" size="1" />
+      <BitField name="LCK10" description="Port x lock bit y (y= 0..15) These bits are read/write but can only be written when the LCKK bit is 0." start="10" size="1" />
+      <BitField name="LCK11" description="Port x lock bit y (y= 0..15) These bits are read/write but can only be written when the LCKK bit is 0." start="11" size="1" />
+      <BitField name="LCK12" description="Port x lock bit y (y= 0..15) These bits are read/write but can only be written when the LCKK bit is 0." start="12" size="1" />
+      <BitField name="LCK13" description="Port x lock bit y (y= 0..15) These bits are read/write but can only be written when the LCKK bit is 0." start="13" size="1" />
+      <BitField name="LCK14" description="Port x lock bit y (y= 0..15) These bits are read/write but can only be written when the LCKK bit is 0." start="14" size="1" />
+      <BitField name="LCK15" description="Port x lock bit y (y= 0..15) These bits are read/write but can only be written when the LCKK bit is 0." start="15" size="1" />
+      <BitField name="LCKK" description="Lock key This bit can be read any time. It can only be modified using the lock key write sequence. LOCK key write sequence: WR LCKR[16] = 1 + LCKR[15:0] WR LCKR[16] = 0 + LCKR[15:0] WR LCKR[16] = 1 + LCKR[15:0] RD LCKR RD LCKR[16] = 1 (this read operation is optional but it confirms that the lock is active) Note: During the LOCK key write sequence, the value of LCK[15:0] must not change. Any error in the lock sequence aborts the lock. After the first lock sequence on any bit of the port, any read access on the LCKK bit will return 1 until the next MCU reset or peripheral reset." start="16" size="1" />
+    </Register>
+    <Register name="AFRL" description="GPIO alternate function low register" start="+0x20" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AFSEL0" description="[3:0]: Alternate function selection for port x pin y (y = 0..7) These bits are written by software to configure alternate function I/Os AFSELy selection:" start="0" size="4" />
+      <BitField name="AFSEL1" description="[3:0]: Alternate function selection for port x pin y (y = 0..7) These bits are written by software to configure alternate function I/Os AFSELy selection:" start="4" size="4" />
+      <BitField name="AFSEL2" description="[3:0]: Alternate function selection for port x pin y (y = 0..7) These bits are written by software to configure alternate function I/Os AFSELy selection:" start="8" size="4" />
+      <BitField name="AFSEL3" description="[3:0]: Alternate function selection for port x pin y (y = 0..7) These bits are written by software to configure alternate function I/Os AFSELy selection:" start="12" size="4" />
+      <BitField name="AFSEL4" description="[3:0]: Alternate function selection for port x pin y (y = 0..7) These bits are written by software to configure alternate function I/Os AFSELy selection:" start="16" size="4" />
+      <BitField name="AFSEL5" description="[3:0]: Alternate function selection for port x pin y (y = 0..7) These bits are written by software to configure alternate function I/Os AFSELy selection:" start="20" size="4" />
+      <BitField name="AFSEL6" description="[3:0]: Alternate function selection for port x pin y (y = 0..7) These bits are written by software to configure alternate function I/Os AFSELy selection:" start="24" size="4" />
+      <BitField name="AFSEL7" description="[3:0]: Alternate function selection for port x pin y (y = 0..7) These bits are written by software to configure alternate function I/Os AFSELy selection:" start="28" size="4" />
+    </Register>
+    <Register name="AFRH" description="GPIO alternate function high register" start="+0x24" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AFSEL8" description="[3:0]: Alternate function selection for port x pin y (y = 8..15) These bits are written by software to configure alternate function I/Os" start="0" size="4" />
+      <BitField name="AFSEL9" description="[3:0]: Alternate function selection for port x pin y (y = 8..15) These bits are written by software to configure alternate function I/Os" start="4" size="4" />
+      <BitField name="AFSEL10" description="[3:0]: Alternate function selection for port x pin y (y = 8..15) These bits are written by software to configure alternate function I/Os" start="8" size="4" />
+      <BitField name="AFSEL11" description="[3:0]: Alternate function selection for port x pin y (y = 8..15) These bits are written by software to configure alternate function I/Os" start="12" size="4" />
+      <BitField name="AFSEL12" description="[3:0]: Alternate function selection for port x pin y (y = 8..15) These bits are written by software to configure alternate function I/Os" start="16" size="4" />
+      <BitField name="AFSEL13" description="[3:0]: Alternate function selection for port x pin y (y = 8..15) These bits are written by software to configure alternate function I/Os" start="20" size="4" />
+      <BitField name="AFSEL14" description="[3:0]: Alternate function selection for port x pin y (y = 8..15) These bits are written by software to configure alternate function I/Os" start="24" size="4" />
+      <BitField name="AFSEL15" description="[3:0]: Alternate function selection for port x pin y (y = 8..15) These bits are written by software to configure alternate function I/Os" start="28" size="4" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="HSEM" description="HSEM" start="0x58026400">
+    <Register name="HSEM_R0" description="HSEM register HSEM_R0 HSEM_R31" start="+0x0" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PROCID" description="Semaphore ProcessID" start="0" size="8" />
+      <BitField name="MASTERID" description="Semaphore MasterID" start="8" size="8" />
+      <BitField name="LOCK" description="Lock indication" start="31" size="1" />
+    </Register>
+    <Register name="HSEM_R1" description="HSEM register HSEM_R0 HSEM_R31" start="+0x4" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PROCID" description="Semaphore ProcessID" start="0" size="8" />
+      <BitField name="MASTERID" description="Semaphore MasterID" start="8" size="8" />
+      <BitField name="LOCK" description="Lock indication" start="31" size="1" />
+    </Register>
+    <Register name="HSEM_R2" description="HSEM register HSEM_R0 HSEM_R31" start="+0x8" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PROCID" description="Semaphore ProcessID" start="0" size="8" />
+      <BitField name="MASTERID" description="Semaphore MasterID" start="8" size="8" />
+      <BitField name="LOCK" description="Lock indication" start="31" size="1" />
+    </Register>
+    <Register name="HSEM_R3" description="HSEM register HSEM_R0 HSEM_R31" start="+0xC" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PROCID" description="Semaphore ProcessID" start="0" size="8" />
+      <BitField name="MASTERID" description="Semaphore MasterID" start="8" size="8" />
+      <BitField name="LOCK" description="Lock indication" start="31" size="1" />
+    </Register>
+    <Register name="HSEM_R4" description="HSEM register HSEM_R0 HSEM_R31" start="+0x10" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PROCID" description="Semaphore ProcessID" start="0" size="8" />
+      <BitField name="MASTERID" description="Semaphore MasterID" start="8" size="8" />
+      <BitField name="LOCK" description="Lock indication" start="31" size="1" />
+    </Register>
+    <Register name="HSEM_R5" description="HSEM register HSEM_R0 HSEM_R31" start="+0x14" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PROCID" description="Semaphore ProcessID" start="0" size="8" />
+      <BitField name="MASTERID" description="Semaphore MasterID" start="8" size="8" />
+      <BitField name="LOCK" description="Lock indication" start="31" size="1" />
+    </Register>
+    <Register name="HSEM_R6" description="HSEM register HSEM_R0 HSEM_R31" start="+0x18" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PROCID" description="Semaphore ProcessID" start="0" size="8" />
+      <BitField name="MASTERID" description="Semaphore MasterID" start="8" size="8" />
+      <BitField name="LOCK" description="Lock indication" start="31" size="1" />
+    </Register>
+    <Register name="HSEM_R7" description="HSEM register HSEM_R0 HSEM_R31" start="+0x1C" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PROCID" description="Semaphore ProcessID" start="0" size="8" />
+      <BitField name="MASTERID" description="Semaphore MasterID" start="8" size="8" />
+      <BitField name="LOCK" description="Lock indication" start="31" size="1" />
+    </Register>
+    <Register name="HSEM_R8" description="HSEM register HSEM_R0 HSEM_R31" start="+0x20" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PROCID" description="Semaphore ProcessID" start="0" size="8" />
+      <BitField name="MASTERID" description="Semaphore MasterID" start="8" size="8" />
+      <BitField name="LOCK" description="Lock indication" start="31" size="1" />
+    </Register>
+    <Register name="HSEM_R9" description="HSEM register HSEM_R0 HSEM_R31" start="+0x24" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PROCID" description="Semaphore ProcessID" start="0" size="8" />
+      <BitField name="MASTERID" description="Semaphore MasterID" start="8" size="8" />
+      <BitField name="LOCK" description="Lock indication" start="31" size="1" />
+    </Register>
+    <Register name="HSEM_R10" description="HSEM register HSEM_R0 HSEM_R31" start="+0x28" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PROCID" description="Semaphore ProcessID" start="0" size="8" />
+      <BitField name="MASTERID" description="Semaphore MasterID" start="8" size="8" />
+      <BitField name="LOCK" description="Lock indication" start="31" size="1" />
+    </Register>
+    <Register name="HSEM_R11" description="HSEM register HSEM_R0 HSEM_R31" start="+0x2C" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PROCID" description="Semaphore ProcessID" start="0" size="8" />
+      <BitField name="MASTERID" description="Semaphore MasterID" start="8" size="8" />
+      <BitField name="LOCK" description="Lock indication" start="31" size="1" />
+    </Register>
+    <Register name="HSEM_R12" description="HSEM register HSEM_R0 HSEM_R31" start="+0x30" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PROCID" description="Semaphore ProcessID" start="0" size="8" />
+      <BitField name="MASTERID" description="Semaphore MasterID" start="8" size="8" />
+      <BitField name="LOCK" description="Lock indication" start="31" size="1" />
+    </Register>
+    <Register name="HSEM_R13" description="HSEM register HSEM_R0 HSEM_R31" start="+0x34" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PROCID" description="Semaphore ProcessID" start="0" size="8" />
+      <BitField name="MASTERID" description="Semaphore MasterID" start="8" size="8" />
+      <BitField name="LOCK" description="Lock indication" start="31" size="1" />
+    </Register>
+    <Register name="HSEM_R14" description="HSEM register HSEM_R0 HSEM_R31" start="+0x38" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PROCID" description="Semaphore ProcessID" start="0" size="8" />
+      <BitField name="MASTERID" description="Semaphore MasterID" start="8" size="8" />
+      <BitField name="LOCK" description="Lock indication" start="31" size="1" />
+    </Register>
+    <Register name="HSEM_R15" description="HSEM register HSEM_R0 HSEM_R31" start="+0x3C" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PROCID" description="Semaphore ProcessID" start="0" size="8" />
+      <BitField name="MASTERID" description="Semaphore MasterID" start="8" size="8" />
+      <BitField name="LOCK" description="Lock indication" start="31" size="1" />
+    </Register>
+    <Register name="HSEM_R16" description="HSEM register HSEM_R0 HSEM_R31" start="+0x40" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PROCID" description="Semaphore ProcessID" start="0" size="8" />
+      <BitField name="MASTERID" description="Semaphore MasterID" start="8" size="8" />
+      <BitField name="LOCK" description="Lock indication" start="31" size="1" />
+    </Register>
+    <Register name="HSEM_R17" description="HSEM register HSEM_R0 HSEM_R31" start="+0x44" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PROCID" description="Semaphore ProcessID" start="0" size="8" />
+      <BitField name="MASTERID" description="Semaphore MasterID" start="8" size="8" />
+      <BitField name="LOCK" description="Lock indication" start="31" size="1" />
+    </Register>
+    <Register name="HSEM_R18" description="HSEM register HSEM_R0 HSEM_R31" start="+0x48" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PROCID" description="Semaphore ProcessID" start="0" size="8" />
+      <BitField name="MASTERID" description="Semaphore MasterID" start="8" size="8" />
+      <BitField name="LOCK" description="Lock indication" start="31" size="1" />
+    </Register>
+    <Register name="HSEM_R19" description="HSEM register HSEM_R0 HSEM_R31" start="+0x4C" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PROCID" description="Semaphore ProcessID" start="0" size="8" />
+      <BitField name="MASTERID" description="Semaphore MasterID" start="8" size="8" />
+      <BitField name="LOCK" description="Lock indication" start="31" size="1" />
+    </Register>
+    <Register name="HSEM_R20" description="HSEM register HSEM_R0 HSEM_R31" start="+0x50" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PROCID" description="Semaphore ProcessID" start="0" size="8" />
+      <BitField name="MASTERID" description="Semaphore MasterID" start="8" size="8" />
+      <BitField name="LOCK" description="Lock indication" start="31" size="1" />
+    </Register>
+    <Register name="HSEM_R21" description="HSEM register HSEM_R0 HSEM_R31" start="+0x54" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PROCID" description="Semaphore ProcessID" start="0" size="8" />
+      <BitField name="MASTERID" description="Semaphore MasterID" start="8" size="8" />
+      <BitField name="LOCK" description="Lock indication" start="31" size="1" />
+    </Register>
+    <Register name="HSEM_R22" description="HSEM register HSEM_R0 HSEM_R31" start="+0x58" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PROCID" description="Semaphore ProcessID" start="0" size="8" />
+      <BitField name="MASTERID" description="Semaphore MasterID" start="8" size="8" />
+      <BitField name="LOCK" description="Lock indication" start="31" size="1" />
+    </Register>
+    <Register name="HSEM_R23" description="HSEM register HSEM_R0 HSEM_R31" start="+0x5C" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PROCID" description="Semaphore ProcessID" start="0" size="8" />
+      <BitField name="MASTERID" description="Semaphore MasterID" start="8" size="8" />
+      <BitField name="LOCK" description="Lock indication" start="31" size="1" />
+    </Register>
+    <Register name="HSEM_R24" description="HSEM register HSEM_R0 HSEM_R31" start="+0x60" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PROCID" description="Semaphore ProcessID" start="0" size="8" />
+      <BitField name="MASTERID" description="Semaphore MasterID" start="8" size="8" />
+      <BitField name="LOCK" description="Lock indication" start="31" size="1" />
+    </Register>
+    <Register name="HSEM_R25" description="HSEM register HSEM_R0 HSEM_R31" start="+0x64" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PROCID" description="Semaphore ProcessID" start="0" size="8" />
+      <BitField name="MASTERID" description="Semaphore MasterID" start="8" size="8" />
+      <BitField name="LOCK" description="Lock indication" start="31" size="1" />
+    </Register>
+    <Register name="HSEM_R26" description="HSEM register HSEM_R0 HSEM_R31" start="+0x68" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PROCID" description="Semaphore ProcessID" start="0" size="8" />
+      <BitField name="MASTERID" description="Semaphore MasterID" start="8" size="8" />
+      <BitField name="LOCK" description="Lock indication" start="31" size="1" />
+    </Register>
+    <Register name="HSEM_R27" description="HSEM register HSEM_R0 HSEM_R31" start="+0x6C" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PROCID" description="Semaphore ProcessID" start="0" size="8" />
+      <BitField name="MASTERID" description="Semaphore MasterID" start="8" size="8" />
+      <BitField name="LOCK" description="Lock indication" start="31" size="1" />
+    </Register>
+    <Register name="HSEM_R28" description="HSEM register HSEM_R0 HSEM_R31" start="+0x70" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PROCID" description="Semaphore ProcessID" start="0" size="8" />
+      <BitField name="MASTERID" description="Semaphore MasterID" start="8" size="8" />
+      <BitField name="LOCK" description="Lock indication" start="31" size="1" />
+    </Register>
+    <Register name="HSEM_R29" description="HSEM register HSEM_R0 HSEM_R31" start="+0x74" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PROCID" description="Semaphore ProcessID" start="0" size="8" />
+      <BitField name="MASTERID" description="Semaphore MasterID" start="8" size="8" />
+      <BitField name="LOCK" description="Lock indication" start="31" size="1" />
+    </Register>
+    <Register name="HSEM_R30" description="HSEM register HSEM_R0 HSEM_R31" start="+0x78" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PROCID" description="Semaphore ProcessID" start="0" size="8" />
+      <BitField name="MASTERID" description="Semaphore MasterID" start="8" size="8" />
+      <BitField name="LOCK" description="Lock indication" start="31" size="1" />
+    </Register>
+    <Register name="HSEM_R31" description="HSEM register HSEM_R0 HSEM_R31" start="+0x7C" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PROCID" description="Semaphore ProcessID" start="0" size="8" />
+      <BitField name="MASTERID" description="Semaphore MasterID" start="8" size="8" />
+      <BitField name="LOCK" description="Lock indication" start="31" size="1" />
+    </Register>
+    <Register name="HSEM_RLR0" description="HSEM Read lock register" start="+0x80" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PROCID" description="Semaphore ProcessID" start="0" size="8" />
+      <BitField name="MASTERID" description="Semaphore MasterID" start="8" size="8" />
+      <BitField name="LOCK" description="Lock indication" start="31" size="1" />
+    </Register>
+    <Register name="HSEM_RLR1" description="HSEM Read lock register" start="+0x84" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PROCID" description="Semaphore ProcessID" start="0" size="8" />
+      <BitField name="MASTERID" description="Semaphore MasterID" start="8" size="8" />
+      <BitField name="LOCK" description="Lock indication" start="31" size="1" />
+    </Register>
+    <Register name="HSEM_RLR2" description="HSEM Read lock register" start="+0x88" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PROCID" description="Semaphore ProcessID" start="0" size="8" />
+      <BitField name="MASTERID" description="Semaphore MasterID" start="8" size="8" />
+      <BitField name="LOCK" description="Lock indication" start="31" size="1" />
+    </Register>
+    <Register name="HSEM_RLR3" description="HSEM Read lock register" start="+0x8C" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PROCID" description="Semaphore ProcessID" start="0" size="8" />
+      <BitField name="MASTERID" description="Semaphore MasterID" start="8" size="8" />
+      <BitField name="LOCK" description="Lock indication" start="31" size="1" />
+    </Register>
+    <Register name="HSEM_RLR4" description="HSEM Read lock register" start="+0x90" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PROCID" description="Semaphore ProcessID" start="0" size="8" />
+      <BitField name="MASTERID" description="Semaphore MasterID" start="8" size="8" />
+      <BitField name="LOCK" description="Lock indication" start="31" size="1" />
+    </Register>
+    <Register name="HSEM_RLR5" description="HSEM Read lock register" start="+0x94" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PROCID" description="Semaphore ProcessID" start="0" size="8" />
+      <BitField name="MASTERID" description="Semaphore MasterID" start="8" size="8" />
+      <BitField name="LOCK" description="Lock indication" start="31" size="1" />
+    </Register>
+    <Register name="HSEM_RLR6" description="HSEM Read lock register" start="+0x98" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PROCID" description="Semaphore ProcessID" start="0" size="8" />
+      <BitField name="MASTERID" description="Semaphore MasterID" start="8" size="8" />
+      <BitField name="LOCK" description="Lock indication" start="31" size="1" />
+    </Register>
+    <Register name="HSEM_RLR7" description="HSEM Read lock register" start="+0x9C" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PROCID" description="Semaphore ProcessID" start="0" size="8" />
+      <BitField name="MASTERID" description="Semaphore MasterID" start="8" size="8" />
+      <BitField name="LOCK" description="Lock indication" start="31" size="1" />
+    </Register>
+    <Register name="HSEM_RLR8" description="HSEM Read lock register" start="+0xA0" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PROCID" description="Semaphore ProcessID" start="0" size="8" />
+      <BitField name="MASTERID" description="Semaphore MasterID" start="8" size="8" />
+      <BitField name="LOCK" description="Lock indication" start="31" size="1" />
+    </Register>
+    <Register name="HSEM_RLR9" description="HSEM Read lock register" start="+0xA4" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PROCID" description="Semaphore ProcessID" start="0" size="8" />
+      <BitField name="MASTERID" description="Semaphore MasterID" start="8" size="8" />
+      <BitField name="LOCK" description="Lock indication" start="31" size="1" />
+    </Register>
+    <Register name="HSEM_RLR10" description="HSEM Read lock register" start="+0xA8" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PROCID" description="Semaphore ProcessID" start="0" size="8" />
+      <BitField name="MASTERID" description="Semaphore MasterID" start="8" size="8" />
+      <BitField name="LOCK" description="Lock indication" start="31" size="1" />
+    </Register>
+    <Register name="HSEM_RLR11" description="HSEM Read lock register" start="+0xAC" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PROCID" description="Semaphore ProcessID" start="0" size="8" />
+      <BitField name="MASTERID" description="Semaphore MasterID" start="8" size="8" />
+      <BitField name="LOCK" description="Lock indication" start="31" size="1" />
+    </Register>
+    <Register name="HSEM_RLR12" description="HSEM Read lock register" start="+0xB0" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PROCID" description="Semaphore ProcessID" start="0" size="8" />
+      <BitField name="MASTERID" description="Semaphore MasterID" start="8" size="8" />
+      <BitField name="LOCK" description="Lock indication" start="31" size="1" />
+    </Register>
+    <Register name="HSEM_RLR13" description="HSEM Read lock register" start="+0xB4" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PROCID" description="Semaphore ProcessID" start="0" size="8" />
+      <BitField name="MASTERID" description="Semaphore MasterID" start="8" size="8" />
+      <BitField name="LOCK" description="Lock indication" start="31" size="1" />
+    </Register>
+    <Register name="HSEM_RLR14" description="HSEM Read lock register" start="+0xB8" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PROCID" description="Semaphore ProcessID" start="0" size="8" />
+      <BitField name="MASTERID" description="Semaphore MasterID" start="8" size="8" />
+      <BitField name="LOCK" description="Lock indication" start="31" size="1" />
+    </Register>
+    <Register name="HSEM_RLR15" description="HSEM Read lock register" start="+0xBC" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PROCID" description="Semaphore ProcessID" start="0" size="8" />
+      <BitField name="MASTERID" description="Semaphore MasterID" start="8" size="8" />
+      <BitField name="LOCK" description="Lock indication" start="31" size="1" />
+    </Register>
+    <Register name="HSEM_RLR16" description="HSEM Read lock register" start="+0xC0" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PROCID" description="Semaphore ProcessID" start="0" size="8" />
+      <BitField name="MASTERID" description="Semaphore MasterID" start="8" size="8" />
+      <BitField name="LOCK" description="Lock indication" start="31" size="1" />
+    </Register>
+    <Register name="HSEM_RLR17" description="HSEM Read lock register" start="+0xC4" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PROCID" description="Semaphore ProcessID" start="0" size="8" />
+      <BitField name="MASTERID" description="Semaphore MasterID" start="8" size="8" />
+      <BitField name="LOCK" description="Lock indication" start="31" size="1" />
+    </Register>
+    <Register name="HSEM_RLR18" description="HSEM Read lock register" start="+0xC8" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PROCID" description="Semaphore ProcessID" start="0" size="8" />
+      <BitField name="MASTERID" description="Semaphore MasterID" start="8" size="8" />
+      <BitField name="LOCK" description="Lock indication" start="31" size="1" />
+    </Register>
+    <Register name="HSEM_RLR19" description="HSEM Read lock register" start="+0xCC" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PROCID" description="Semaphore ProcessID" start="0" size="8" />
+      <BitField name="MASTERID" description="Semaphore MasterID" start="8" size="8" />
+      <BitField name="LOCK" description="Lock indication" start="31" size="1" />
+    </Register>
+    <Register name="HSEM_RLR20" description="HSEM Read lock register" start="+0xD0" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PROCID" description="Semaphore ProcessID" start="0" size="8" />
+      <BitField name="MASTERID" description="Semaphore MasterID" start="8" size="8" />
+      <BitField name="LOCK" description="Lock indication" start="31" size="1" />
+    </Register>
+    <Register name="HSEM_RLR21" description="HSEM Read lock register" start="+0xD4" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PROCID" description="Semaphore ProcessID" start="0" size="8" />
+      <BitField name="MASTERID" description="Semaphore MasterID" start="8" size="8" />
+      <BitField name="LOCK" description="Lock indication" start="31" size="1" />
+    </Register>
+    <Register name="HSEM_RLR22" description="HSEM Read lock register" start="+0xD8" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PROCID" description="Semaphore ProcessID" start="0" size="8" />
+      <BitField name="MASTERID" description="Semaphore MasterID" start="8" size="8" />
+      <BitField name="LOCK" description="Lock indication" start="31" size="1" />
+    </Register>
+    <Register name="HSEM_RLR23" description="HSEM Read lock register" start="+0xDC" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PROCID" description="Semaphore ProcessID" start="0" size="8" />
+      <BitField name="MASTERID" description="Semaphore MasterID" start="8" size="8" />
+      <BitField name="LOCK" description="Lock indication" start="31" size="1" />
+    </Register>
+    <Register name="HSEM_RLR24" description="HSEM Read lock register" start="+0xE0" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PROCID" description="Semaphore ProcessID" start="0" size="8" />
+      <BitField name="MASTERID" description="Semaphore MasterID" start="8" size="8" />
+      <BitField name="LOCK" description="Lock indication" start="31" size="1" />
+    </Register>
+    <Register name="HSEM_RLR25" description="HSEM Read lock register" start="+0xE4" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PROCID" description="Semaphore ProcessID" start="0" size="8" />
+      <BitField name="MASTERID" description="Semaphore MasterID" start="8" size="8" />
+      <BitField name="LOCK" description="Lock indication" start="31" size="1" />
+    </Register>
+    <Register name="HSEM_RLR26" description="HSEM Read lock register" start="+0xE8" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PROCID" description="Semaphore ProcessID" start="0" size="8" />
+      <BitField name="MASTERID" description="Semaphore MasterID" start="8" size="8" />
+      <BitField name="LOCK" description="Lock indication" start="31" size="1" />
+    </Register>
+    <Register name="HSEM_RLR27" description="HSEM Read lock register" start="+0xEC" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PROCID" description="Semaphore ProcessID" start="0" size="8" />
+      <BitField name="MASTERID" description="Semaphore MasterID" start="8" size="8" />
+      <BitField name="LOCK" description="Lock indication" start="31" size="1" />
+    </Register>
+    <Register name="HSEM_RLR28" description="HSEM Read lock register" start="+0xF0" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PROCID" description="Semaphore ProcessID" start="0" size="8" />
+      <BitField name="MASTERID" description="Semaphore MasterID" start="8" size="8" />
+      <BitField name="LOCK" description="Lock indication" start="31" size="1" />
+    </Register>
+    <Register name="HSEM_RLR29" description="HSEM Read lock register" start="+0xF4" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PROCID" description="Semaphore ProcessID" start="0" size="8" />
+      <BitField name="MASTERID" description="Semaphore MasterID" start="8" size="8" />
+      <BitField name="LOCK" description="Lock indication" start="31" size="1" />
+    </Register>
+    <Register name="HSEM_RLR30" description="HSEM Read lock register" start="+0xF8" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PROCID" description="Semaphore ProcessID" start="0" size="8" />
+      <BitField name="MASTERID" description="Semaphore MasterID" start="8" size="8" />
+      <BitField name="LOCK" description="Lock indication" start="31" size="1" />
+    </Register>
+    <Register name="HSEM_RLR31" description="HSEM Read lock register" start="+0xFC" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PROCID" description="Semaphore ProcessID" start="0" size="8" />
+      <BitField name="MASTERID" description="Semaphore MasterID" start="8" size="8" />
+      <BitField name="LOCK" description="Lock indication" start="31" size="1" />
+    </Register>
+    <Register name="HSEM_C1IER" description="HSEM Interrupt enable register" start="+0x100" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ISEM0" description="Interrupt semaphore n enable bit" start="0" size="1" />
+      <BitField name="ISEM1" description="Interrupt semaphore n enable bit" start="1" size="1" />
+      <BitField name="ISEM2" description="Interrupt semaphore n enable bit" start="2" size="1" />
+      <BitField name="ISEM3" description="Interrupt semaphore n enable bit" start="3" size="1" />
+      <BitField name="ISEM4" description="Interrupt semaphore n enable bit" start="4" size="1" />
+      <BitField name="ISEM5" description="Interrupt semaphore n enable bit" start="5" size="1" />
+      <BitField name="ISEM6" description="Interrupt semaphore n enable bit" start="6" size="1" />
+      <BitField name="ISEM7" description="Interrupt semaphore n enable bit" start="7" size="1" />
+      <BitField name="ISEM8" description="Interrupt semaphore n enable bit" start="8" size="1" />
+      <BitField name="ISEM9" description="Interrupt semaphore n enable bit" start="9" size="1" />
+      <BitField name="ISEM10" description="Interrupt semaphore n enable bit" start="10" size="1" />
+      <BitField name="ISEM11" description="Interrupt semaphore n enable bit" start="11" size="1" />
+      <BitField name="ISEM12" description="Interrupt semaphore n enable bit" start="12" size="1" />
+      <BitField name="ISEM13" description="Interrupt semaphore n enable bit" start="13" size="1" />
+      <BitField name="ISEM14" description="Interrupt semaphore n enable bit" start="14" size="1" />
+      <BitField name="ISEM15" description="Interrupt semaphore n enable bit" start="15" size="1" />
+      <BitField name="ISEM16" description="Interrupt semaphore n enable bit" start="16" size="1" />
+      <BitField name="ISEM17" description="Interrupt semaphore n enable bit" start="17" size="1" />
+      <BitField name="ISEM18" description="Interrupt semaphore n enable bit" start="18" size="1" />
+      <BitField name="ISEM19" description="Interrupt semaphore n enable bit" start="19" size="1" />
+      <BitField name="ISEM20" description="Interrupt semaphore n enable bit" start="20" size="1" />
+      <BitField name="ISEM21" description="Interrupt semaphore n enable bit" start="21" size="1" />
+      <BitField name="ISEM22" description="Interrupt semaphore n enable bit" start="22" size="1" />
+      <BitField name="ISEM23" description="Interrupt semaphore n enable bit" start="23" size="1" />
+      <BitField name="ISEM24" description="Interrupt semaphore n enable bit" start="24" size="1" />
+      <BitField name="ISEM25" description="Interrupt semaphore n enable bit" start="25" size="1" />
+      <BitField name="ISEM26" description="Interrupt semaphore n enable bit" start="26" size="1" />
+      <BitField name="ISEM27" description="Interrupt semaphore n enable bit" start="27" size="1" />
+      <BitField name="ISEM28" description="Interrupt semaphore n enable bit" start="28" size="1" />
+      <BitField name="ISEM29" description="Interrupt semaphore n enable bit" start="29" size="1" />
+      <BitField name="ISEM30" description="Interrupt semaphore n enable bit" start="30" size="1" />
+      <BitField name="ISEM31" description="Interrupt(N) semaphore n enable bit." start="31" size="1" />
+    </Register>
+    <Register name="HSEM_C1ICR" description="HSEM Interrupt clear register" start="+0x104" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ISEM0" description="Interrupt(N) semaphore n clear bit" start="0" size="1" />
+      <BitField name="ISEM1" description="Interrupt(N) semaphore n clear bit" start="1" size="1" />
+      <BitField name="ISEM2" description="Interrupt(N) semaphore n clear bit" start="2" size="1" />
+      <BitField name="ISEM3" description="Interrupt(N) semaphore n clear bit" start="3" size="1" />
+      <BitField name="ISEM4" description="Interrupt(N) semaphore n clear bit" start="4" size="1" />
+      <BitField name="ISEM5" description="Interrupt(N) semaphore n clear bit" start="5" size="1" />
+      <BitField name="ISEM6" description="Interrupt(N) semaphore n clear bit" start="6" size="1" />
+      <BitField name="ISEM7" description="Interrupt(N) semaphore n clear bit" start="7" size="1" />
+      <BitField name="ISEM8" description="Interrupt(N) semaphore n clear bit" start="8" size="1" />
+      <BitField name="ISEM9" description="Interrupt(N) semaphore n clear bit" start="9" size="1" />
+      <BitField name="ISEM10" description="Interrupt(N) semaphore n clear bit" start="10" size="1" />
+      <BitField name="ISEM11" description="Interrupt(N) semaphore n clear bit" start="11" size="1" />
+      <BitField name="ISEM12" description="Interrupt(N) semaphore n clear bit" start="12" size="1" />
+      <BitField name="ISEM13" description="Interrupt(N) semaphore n clear bit" start="13" size="1" />
+      <BitField name="ISEM14" description="Interrupt(N) semaphore n clear bit" start="14" size="1" />
+      <BitField name="ISEM15" description="Interrupt(N) semaphore n clear bit" start="15" size="1" />
+      <BitField name="ISEM16" description="Interrupt(N) semaphore n clear bit" start="16" size="1" />
+      <BitField name="ISEM17" description="Interrupt(N) semaphore n clear bit" start="17" size="1" />
+      <BitField name="ISEM18" description="Interrupt(N) semaphore n clear bit" start="18" size="1" />
+      <BitField name="ISEM19" description="Interrupt(N) semaphore n clear bit" start="19" size="1" />
+      <BitField name="ISEM20" description="Interrupt(N) semaphore n clear bit" start="20" size="1" />
+      <BitField name="ISEM21" description="Interrupt(N) semaphore n clear bit" start="21" size="1" />
+      <BitField name="ISEM22" description="Interrupt(N) semaphore n clear bit" start="22" size="1" />
+      <BitField name="ISEM23" description="Interrupt(N) semaphore n clear bit" start="23" size="1" />
+      <BitField name="ISEM24" description="Interrupt(N) semaphore n clear bit" start="24" size="1" />
+      <BitField name="ISEM25" description="Interrupt(N) semaphore n clear bit" start="25" size="1" />
+      <BitField name="ISEM26" description="Interrupt(N) semaphore n clear bit" start="26" size="1" />
+      <BitField name="ISEM27" description="Interrupt(N) semaphore n clear bit" start="27" size="1" />
+      <BitField name="ISEM28" description="Interrupt(N) semaphore n clear bit" start="28" size="1" />
+      <BitField name="ISEM29" description="Interrupt(N) semaphore n clear bit" start="29" size="1" />
+      <BitField name="ISEM30" description="Interrupt(N) semaphore n clear bit" start="30" size="1" />
+      <BitField name="ISEM31" description="Interrupt(N) semaphore n clear bit" start="31" size="1" />
+    </Register>
+    <Register name="HSEM_C1ISR" description="HSEM Interrupt status register" start="+0x108" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ISEM0" description="Interrupt(N) semaphore n status bit before enable (mask)" start="0" size="1" />
+      <BitField name="ISEM1" description="Interrupt(N) semaphore n status bit before enable (mask)" start="1" size="1" />
+      <BitField name="ISEM2" description="Interrupt(N) semaphore n status bit before enable (mask)" start="2" size="1" />
+      <BitField name="ISEM3" description="Interrupt(N) semaphore n status bit before enable (mask)" start="3" size="1" />
+      <BitField name="ISEM4" description="Interrupt(N) semaphore n status bit before enable (mask)" start="4" size="1" />
+      <BitField name="ISEM5" description="Interrupt(N) semaphore n status bit before enable (mask)" start="5" size="1" />
+      <BitField name="ISEM6" description="Interrupt(N) semaphore n status bit before enable (mask)" start="6" size="1" />
+      <BitField name="ISEM7" description="Interrupt(N) semaphore n status bit before enable (mask)" start="7" size="1" />
+      <BitField name="ISEM8" description="Interrupt(N) semaphore n status bit before enable (mask)" start="8" size="1" />
+      <BitField name="ISEM9" description="Interrupt(N) semaphore n status bit before enable (mask)" start="9" size="1" />
+      <BitField name="ISEM10" description="Interrupt(N) semaphore n status bit before enable (mask)" start="10" size="1" />
+      <BitField name="ISEM11" description="Interrupt(N) semaphore n status bit before enable (mask)" start="11" size="1" />
+      <BitField name="ISEM12" description="Interrupt(N) semaphore n status bit before enable (mask)" start="12" size="1" />
+      <BitField name="ISEM13" description="Interrupt(N) semaphore n status bit before enable (mask)" start="13" size="1" />
+      <BitField name="ISEM14" description="Interrupt(N) semaphore n status bit before enable (mask)" start="14" size="1" />
+      <BitField name="ISEM15" description="Interrupt(N) semaphore n status bit before enable (mask)" start="15" size="1" />
+      <BitField name="ISEM16" description="Interrupt(N) semaphore n status bit before enable (mask)" start="16" size="1" />
+      <BitField name="ISEM17" description="Interrupt(N) semaphore n status bit before enable (mask)" start="17" size="1" />
+      <BitField name="ISEM18" description="Interrupt(N) semaphore n status bit before enable (mask)" start="18" size="1" />
+      <BitField name="ISEM19" description="Interrupt(N) semaphore n status bit before enable (mask)" start="19" size="1" />
+      <BitField name="ISEM20" description="Interrupt(N) semaphore n status bit before enable (mask)" start="20" size="1" />
+      <BitField name="ISEM21" description="Interrupt(N) semaphore n status bit before enable (mask)" start="21" size="1" />
+      <BitField name="ISEM22" description="Interrupt(N) semaphore n status bit before enable (mask)" start="22" size="1" />
+      <BitField name="ISEM23" description="Interrupt(N) semaphore n status bit before enable (mask)" start="23" size="1" />
+      <BitField name="ISEM24" description="Interrupt(N) semaphore n status bit before enable (mask)" start="24" size="1" />
+      <BitField name="ISEM25" description="Interrupt(N) semaphore n status bit before enable (mask)" start="25" size="1" />
+      <BitField name="ISEM26" description="Interrupt(N) semaphore n status bit before enable (mask)" start="26" size="1" />
+      <BitField name="ISEM27" description="Interrupt(N) semaphore n status bit before enable (mask)" start="27" size="1" />
+      <BitField name="ISEM28" description="Interrupt(N) semaphore n status bit before enable (mask)" start="28" size="1" />
+      <BitField name="ISEM29" description="Interrupt(N) semaphore n status bit before enable (mask)" start="29" size="1" />
+      <BitField name="ISEM30" description="Interrupt(N) semaphore n status bit before enable (mask)" start="30" size="1" />
+      <BitField name="ISEM31" description="Interrupt(N) semaphore n status bit before enable (mask)" start="31" size="1" />
+    </Register>
+    <Register name="HSEM_C1MISR" description="HSEM Masked interrupt status register" start="+0x10C" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ISEM0" description="masked interrupt(N) semaphore n status bit after enable (mask)" start="0" size="1" />
+      <BitField name="ISEM1" description="masked interrupt(N) semaphore n status bit after enable (mask)" start="1" size="1" />
+      <BitField name="ISEM2" description="masked interrupt(N) semaphore n status bit after enable (mask)" start="2" size="1" />
+      <BitField name="ISEM3" description="masked interrupt(N) semaphore n status bit after enable (mask)" start="3" size="1" />
+      <BitField name="ISEM4" description="masked interrupt(N) semaphore n status bit after enable (mask)" start="4" size="1" />
+      <BitField name="ISEM5" description="masked interrupt(N) semaphore n status bit after enable (mask)" start="5" size="1" />
+      <BitField name="ISEM6" description="masked interrupt(N) semaphore n status bit after enable (mask)" start="6" size="1" />
+      <BitField name="ISEM7" description="masked interrupt(N) semaphore n status bit after enable (mask)" start="7" size="1" />
+      <BitField name="ISEM8" description="masked interrupt(N) semaphore n status bit after enable (mask)" start="8" size="1" />
+      <BitField name="ISEM9" description="masked interrupt(N) semaphore n status bit after enable (mask)" start="9" size="1" />
+      <BitField name="ISEM10" description="masked interrupt(N) semaphore n status bit after enable (mask)" start="10" size="1" />
+      <BitField name="ISEM11" description="masked interrupt(N) semaphore n status bit after enable (mask)" start="11" size="1" />
+      <BitField name="ISEM12" description="masked interrupt(N) semaphore n status bit after enable (mask)" start="12" size="1" />
+      <BitField name="ISEM13" description="masked interrupt(N) semaphore n status bit after enable (mask)" start="13" size="1" />
+      <BitField name="ISEM14" description="masked interrupt(N) semaphore n status bit after enable (mask)" start="14" size="1" />
+      <BitField name="ISEM15" description="masked interrupt(N) semaphore n status bit after enable (mask)" start="15" size="1" />
+      <BitField name="ISEM16" description="masked interrupt(N) semaphore n status bit after enable (mask)" start="16" size="1" />
+      <BitField name="ISEM17" description="masked interrupt(N) semaphore n status bit after enable (mask)" start="17" size="1" />
+      <BitField name="ISEM18" description="masked interrupt(N) semaphore n status bit after enable (mask)" start="18" size="1" />
+      <BitField name="ISEM19" description="masked interrupt(N) semaphore n status bit after enable (mask)" start="19" size="1" />
+      <BitField name="ISEM20" description="masked interrupt(N) semaphore n status bit after enable (mask)" start="20" size="1" />
+      <BitField name="ISEM21" description="masked interrupt(N) semaphore n status bit after enable (mask)" start="21" size="1" />
+      <BitField name="ISEM22" description="masked interrupt(N) semaphore n status bit after enable (mask)" start="22" size="1" />
+      <BitField name="ISEM23" description="masked interrupt(N) semaphore n status bit after enable (mask)" start="23" size="1" />
+      <BitField name="ISEM24" description="masked interrupt(N) semaphore n status bit after enable (mask)" start="24" size="1" />
+      <BitField name="ISEM25" description="masked interrupt(N) semaphore n status bit after enable (mask)" start="25" size="1" />
+      <BitField name="ISEM26" description="masked interrupt(N) semaphore n status bit after enable (mask)" start="26" size="1" />
+      <BitField name="ISEM27" description="masked interrupt(N) semaphore n status bit after enable (mask)" start="27" size="1" />
+      <BitField name="ISEM28" description="masked interrupt(N) semaphore n status bit after enable (mask)" start="28" size="1" />
+      <BitField name="ISEM29" description="masked interrupt(N) semaphore n status bit after enable (mask)" start="29" size="1" />
+      <BitField name="ISEM30" description="masked interrupt(N) semaphore n status bit after enable (mask)" start="30" size="1" />
+      <BitField name="ISEM31" description="masked interrupt(N) semaphore n status bit after enable (mask)" start="31" size="1" />
+    </Register>
+    <Register name="HSEM_CR" description="HSEM Clear register" start="+0x140" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="COREID" description="MasterID of semaphores to be cleared" start="8" size="4" />
+      <BitField name="KEY" description="Semaphore clear Key" start="16" size="16" />
+    </Register>
+    <Register name="HSEM_KEYR" description="HSEM Interrupt clear register" start="+0x144" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="KEY" description="Semaphore Clear Key" start="16" size="16" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="I2C1" description="I2C" start="0x40005400">
+    <Register name="CR1" description="Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed. The latency of the second write access can be up to 2 x PCLK1 + 6 x I2CCLK." start="+0x0" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PE" description="Peripheral enable Note: When PE=0, the I2C SCL and SDA lines are released. Internal state machines and status bits are put back to their reset value. When cleared, PE must be kept low for at least 3 APB clock cycles." start="0" size="1" />
+      <BitField name="TXIE" description="TX Interrupt enable" start="1" size="1" />
+      <BitField name="RXIE" description="RX Interrupt enable" start="2" size="1" />
+      <BitField name="ADDRIE" description="Address match Interrupt enable (slave only)" start="3" size="1" />
+      <BitField name="NACKIE" description="Not acknowledge received Interrupt enable" start="4" size="1" />
+      <BitField name="STOPIE" description="STOP detection Interrupt enable" start="5" size="1" />
+      <BitField name="TCIE" description="Transfer Complete interrupt enable Note: Any of these events will generate an interrupt: Transfer Complete (TC) Transfer Complete Reload (TCR)" start="6" size="1" />
+      <BitField name="ERRIE" description="Error interrupts enable Note: Any of these errors generate an interrupt: Arbitration Loss (ARLO) Bus Error detection (BERR) Overrun/Underrun (OVR) Timeout detection (TIMEOUT) PEC error detection (PECERR) Alert pin event detection (ALERT)" start="7" size="1" />
+      <BitField name="DNF" description="Digital noise filter These bits are used to configure the digital noise filter on SDA and SCL input. The digital filter will filter spikes with a length of up to DNF[3:0] * tI2CCLK ... Note: If the analog filter is also enabled, the digital filter is added to the analog filter. This filter can only be programmed when the I2C is disabled (PE = 0)." start="8" size="4" />
+      <BitField name="ANFOFF" description="Analog noise filter OFF Note: This bit can only be programmed when the I2C is disabled (PE = 0)." start="12" size="1" />
+      <BitField name="TXDMAEN" description="DMA transmission requests enable" start="14" size="1" />
+      <BitField name="RXDMAEN" description="DMA reception requests enable" start="15" size="1" />
+      <BitField name="SBC" description="Slave byte control This bit is used to enable hardware byte control in slave mode." start="16" size="1" />
+      <BitField name="NOSTRETCH" description="Clock stretching disable This bit is used to disable clock stretching in slave mode. It must be kept cleared in master mode. Note: This bit can only be programmed when the I2C is disabled (PE = 0)." start="17" size="1" />
+      <BitField name="WUPEN" description="Wakeup from Stop mode enable Note: If the Wakeup from Stop mode feature is not supported, this bit is reserved and forced by hardware to 0. Please refer to Section25.3: I2C implementation. Note: WUPEN can be set only when DNF = 0000" start="18" size="1" />
+      <BitField name="GCEN" description="General call enable" start="19" size="1" />
+      <BitField name="SMBHEN" description="SMBus Host address enable Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Please refer to Section25.3: I2C implementation." start="20" size="1" />
+      <BitField name="SMBDEN" description="SMBus Device Default address enable Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Please refer to Section25.3: I2C implementation." start="21" size="1" />
+      <BitField name="ALERTEN" description="SMBus alert enable Device mode (SMBHEN=0): Host mode (SMBHEN=1): Note: When ALERTEN=0, the SMBA pin can be used as a standard GPIO. If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Please refer to Section25.3: I2C implementation." start="22" size="1" />
+      <BitField name="PECEN" description="PEC enable Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Please refer to Section25.3: I2C implementation." start="23" size="1" />
+    </Register>
+    <Register name="CR2" description="Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed. The latency of the second write access can be up to 2 x PCLK1 + 6 x I2CCLK." start="+0x4" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SADD0" description="Slave address bit 0 (master mode) In 7-bit addressing mode (ADD10 = 0): This bit is dont care In 10-bit addressing mode (ADD10 = 1): This bit should be written with bit 0 of the slave address to be sent Note: Changing these bits when the START bit is set is not allowed." start="0" size="1" />
+      <BitField name="SADD1" description="Slave address bit 7:1 (master mode) In 7-bit addressing mode (ADD10 = 0): These bits should be written with the 7-bit slave address to be sent In 10-bit addressing mode (ADD10 = 1): These bits should be written with bits 7:1 of the slave address to be sent. Note: Changing these bits when the START bit is set is not allowed." start="1" size="1" />
+      <BitField name="SADD2" description="Slave address bit 7:1 (master mode) In 7-bit addressing mode (ADD10 = 0): These bits should be written with the 7-bit slave address to be sent In 10-bit addressing mode (ADD10 = 1): These bits should be written with bits 7:1 of the slave address to be sent. Note: Changing these bits when the START bit is set is not allowed." start="2" size="1" />
+      <BitField name="SADD3" description="Slave address bit 7:1 (master mode) In 7-bit addressing mode (ADD10 = 0): These bits should be written with the 7-bit slave address to be sent In 10-bit addressing mode (ADD10 = 1): These bits should be written with bits 7:1 of the slave address to be sent. Note: Changing these bits when the START bit is set is not allowed." start="3" size="1" />
+      <BitField name="SADD4" description="Slave address bit 7:1 (master mode) In 7-bit addressing mode (ADD10 = 0): These bits should be written with the 7-bit slave address to be sent In 10-bit addressing mode (ADD10 = 1): These bits should be written with bits 7:1 of the slave address to be sent. Note: Changing these bits when the START bit is set is not allowed." start="4" size="1" />
+      <BitField name="SADD5" description="Slave address bit 7:1 (master mode) In 7-bit addressing mode (ADD10 = 0): These bits should be written with the 7-bit slave address to be sent In 10-bit addressing mode (ADD10 = 1): These bits should be written with bits 7:1 of the slave address to be sent. Note: Changing these bits when the START bit is set is not allowed." start="5" size="1" />
+      <BitField name="SADD6" description="Slave address bit 7:1 (master mode) In 7-bit addressing mode (ADD10 = 0): These bits should be written with the 7-bit slave address to be sent In 10-bit addressing mode (ADD10 = 1): These bits should be written with bits 7:1 of the slave address to be sent. Note: Changing these bits when the START bit is set is not allowed." start="6" size="1" />
+      <BitField name="SADD7" description="Slave address bit 7:1 (master mode) In 7-bit addressing mode (ADD10 = 0): These bits should be written with the 7-bit slave address to be sent In 10-bit addressing mode (ADD10 = 1): These bits should be written with bits 7:1 of the slave address to be sent. Note: Changing these bits when the START bit is set is not allowed." start="7" size="1" />
+      <BitField name="SADD8" description="Slave address bit 9:8 (master mode) In 7-bit addressing mode (ADD10 = 0): These bits are dont care In 10-bit addressing mode (ADD10 = 1): These bits should be written with bits 9:8 of the slave address to be sent Note: Changing these bits when the START bit is set is not allowed." start="8" size="1" />
+      <BitField name="SADD9" description="Slave address bit 9:8 (master mode) In 7-bit addressing mode (ADD10 = 0): These bits are dont care In 10-bit addressing mode (ADD10 = 1): These bits should be written with bits 9:8 of the slave address to be sent Note: Changing these bits when the START bit is set is not allowed." start="9" size="1" />
+      <BitField name="RD_WRN" description="Transfer direction (master mode) Note: Changing this bit when the START bit is set is not allowed." start="10" size="1" />
+      <BitField name="ADD10" description="10-bit addressing mode (master mode) Note: Changing this bit when the START bit is set is not allowed." start="11" size="1" />
+      <BitField name="HEAD10R" description="10-bit address header only read direction (master receiver mode) Note: Changing this bit when the START bit is set is not allowed." start="12" size="1" />
+      <BitField name="START" description="Start generation This bit is set by software, and cleared by hardware after the Start followed by the address sequence is sent, by an arbitration loss, by a timeout error detection, or when PE = 0. It can also be cleared by software by writing 1 to the ADDRCF bit in the I2C_ICR register. If the I2C is already in master mode with AUTOEND = 0, setting this bit generates a Repeated Start condition when RELOAD=0, after the end of the NBYTES transfer. Otherwise setting this bit will generate a START condition once the bus is free. Note: Writing 0 to this bit has no effect. The START bit can be set even if the bus is BUSY or I2C is in slave mode. This bit has no effect when RELOAD is set." start="13" size="1" />
+      <BitField name="STOP" description="Stop generation (master mode) The bit is set by software, cleared by hardware when a Stop condition is detected, or when PE = 0. In Master Mode: Note: Writing 0 to this bit has no effect." start="14" size="1" />
+      <BitField name="NACK" description="NACK generation (slave mode) The bit is set by software, cleared by hardware when the NACK is sent, or when a STOP condition or an Address matched is received, or when PE=0. Note: Writing 0 to this bit has no effect. This bit is used in slave mode only: in master receiver mode, NACK is automatically generated after last byte preceding STOP or RESTART condition, whatever the NACK bit value. When an overrun occurs in slave receiver NOSTRETCH mode, a NACK is automatically generated whatever the NACK bit value. When hardware PEC checking is enabled (PECBYTE=1), the PEC acknowledge value does not depend on the NACK value." start="15" size="1" />
+      <BitField name="NBYTES" description="Number of bytes The number of bytes to be transmitted/received is programmed there. This field is dont care in slave mode with SBC=0. Note: Changing these bits when the START bit is set is not allowed." start="16" size="8" />
+      <BitField name="RELOAD" description="NBYTES reload mode This bit is set and cleared by software." start="24" size="1" />
+      <BitField name="AUTOEND" description="Automatic end mode (master mode) This bit is set and cleared by software. Note: This bit has no effect in slave mode or when the RELOAD bit is set." start="25" size="1" />
+      <BitField name="PECBYTE" description="Packet error checking byte This bit is set by software, and cleared by hardware when the PEC is transferred, or when a STOP condition or an Address matched is received, also when PE=0. Note: Writing 0 to this bit has no effect. This bit has no effect when RELOAD is set. This bit has no effect is slave mode when SBC=0. If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Please refer to Section25.3: I2C implementation." start="26" size="1" />
+    </Register>
+    <Register name="OAR1" description="Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed. The latency of the second write access can be up to 2 x PCLK1 + 6 x I2CCLK." start="+0x8" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OA1" description="Interface address 7-bit addressing mode: dont care 10-bit addressing mode: bits 9:8 of address Note: These bits can be written only when OA1EN=0. OA1[7:1]: Interface address Bits 7:1 of address Note: These bits can be written only when OA1EN=0. OA1[0]: Interface address 7-bit addressing mode: dont care 10-bit addressing mode: bit 0 of address Note: This bit can be written only when OA1EN=0." start="0" size="10" />
+      <BitField name="OA1MODE" description="Own Address 1 10-bit mode Note: This bit can be written only when OA1EN=0." start="10" size="1" />
+      <BitField name="OA1EN" description="Own Address 1 enable" start="15" size="1" />
+    </Register>
+    <Register name="OAR2" description="Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed. The latency of the second write access can be up to 2 x PCLK1 + 6 x I2CCLK." start="+0xC" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OA2" description="Interface address bits 7:1 of address Note: These bits can be written only when OA2EN=0." start="1" size="7" />
+      <BitField name="OA2MSK" description="Own Address 2 masks Note: These bits can be written only when OA2EN=0. As soon as OA2MSK is not equal to 0, the reserved I2C addresses (0b0000xxx and 0b1111xxx) are not acknowledged even if the comparison matches." start="8" size="3" />
+      <BitField name="OA2EN" description="Own Address 2 enable" start="15" size="1" />
+    </Register>
+    <Register name="TIMINGR" description="Access: No wait states" start="+0x10" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SCLL" description="SCL low period (master mode) This field is used to generate the SCL low period in master mode. tSCLL = (SCLL+1) x tPRESC Note: SCLL is also used to generate tBUF and tSU:STA timings." start="0" size="8" />
+      <BitField name="SCLH" description="SCL high period (master mode) This field is used to generate the SCL high period in master mode. tSCLH = (SCLH+1) x tPRESC Note: SCLH is also used to generate tSU:STO and tHD:STA timing." start="8" size="8" />
+      <BitField name="SDADEL" description="Data hold time This field is used to generate the delay tSDADEL between SCL falling edge and SDA edge. In master mode and in slave mode with NOSTRETCH = 0, the SCL line is stretched low during tSDADEL. tSDADEL= SDADEL x tPRESC Note: SDADEL is used to generate tHD:DAT timing." start="16" size="4" />
+      <BitField name="SCLDEL" description="Data setup time This field is used to generate a delay tSCLDEL between SDA edge and SCL rising edge. In master mode and in slave mode with NOSTRETCH = 0, the SCL line is stretched low during tSCLDEL. tSCLDEL = (SCLDEL+1) x tPRESC Note: tSCLDEL is used to generate tSU:DAT timing." start="20" size="4" />
+      <BitField name="PRESC" description="Timing prescaler This field is used to prescale I2CCLK in order to generate the clock period tPRESC used for data setup and hold counters (refer to I2C timings on page9) and for SCL high and low level counters (refer to I2C master initialization on page24). tPRESC = (PRESC+1) x tI2CCLK" start="28" size="4" />
+    </Register>
+    <Register name="TIMEOUTR" description="Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed. The latency of the second write access can be up to 2 x PCLK1 + 6 x I2CCLK." start="+0x14" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TIMEOUTA" description="Bus Timeout A This field is used to configure: The SCL low timeout condition tTIMEOUT when TIDLE=0 tTIMEOUT= (TIMEOUTA+1) x 2048 x tI2CCLK The bus idle condition (both SCL and SDA high) when TIDLE=1 tIDLE= (TIMEOUTA+1) x 4 x tI2CCLK Note: These bits can be written only when TIMOUTEN=0." start="0" size="12" />
+      <BitField name="TIDLE" description="Idle clock timeout detection Note: This bit can be written only when TIMOUTEN=0." start="12" size="1" />
+      <BitField name="TIMOUTEN" description="Clock timeout enable" start="15" size="1" />
+      <BitField name="TIMEOUTB" description="Bus timeout B This field is used to configure the cumulative clock extension timeout: In master mode, the master cumulative clock low extend time (tLOW:MEXT) is detected In slave mode, the slave cumulative clock low extend time (tLOW:SEXT) is detected tLOW:EXT= (TIMEOUTB+1) x 2048 x tI2CCLK Note: These bits can be written only when TEXTEN=0." start="16" size="12" />
+      <BitField name="TEXTEN" description="Extended clock timeout enable" start="31" size="1" />
+    </Register>
+    <Register name="ISR" description="Access: No wait states" start="+0x18" size="4" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField name="TXE" description="Transmit data register empty (transmitters) This bit is set by hardware when the I2C_TXDR register is empty. It is cleared when the next data to be sent is written in the I2C_TXDR register. This bit can be written to 1 by software in order to flush the transmit data register I2C_TXDR. Note: This bit is set by hardware when PE=0." start="0" size="1" access="Read/Write" />
+      <BitField name="TXIS" description="Transmit interrupt status (transmitters) This bit is set by hardware when the I2C_TXDR register is empty and the data to be transmitted must be written in the I2C_TXDR register. It is cleared when the next data to be sent is written in the I2C_TXDR register. This bit can be written to 1 by software when NOSTRETCH=1 only, in order to generate a TXIS event (interrupt if TXIE=1 or DMA request if TXDMAEN=1). Note: This bit is cleared by hardware when PE=0." start="1" size="1" access="Read/Write" />
+      <BitField name="RXNE" description="Receive data register not empty (receivers) This bit is set by hardware when the received data is copied into the I2C_RXDR register, and is ready to be read. It is cleared when I2C_RXDR is read. Note: This bit is cleared by hardware when PE=0." start="2" size="1" access="ReadOnly" />
+      <BitField name="ADDR" description="Address matched (slave mode) This bit is set by hardware as soon as the received slave address matched with one of the enabled slave addresses. It is cleared by software by setting ADDRCF bit. Note: This bit is cleared by hardware when PE=0." start="3" size="1" access="ReadOnly" />
+      <BitField name="NACKF" description="Not Acknowledge received flag This flag is set by hardware when a NACK is received after a byte transmission. It is cleared by software by setting the NACKCF bit. Note: This bit is cleared by hardware when PE=0." start="4" size="1" access="ReadOnly" />
+      <BitField name="STOPF" description="Stop detection flag This flag is set by hardware when a Stop condition is detected on the bus and the peripheral is involved in this transfer: either as a master, provided that the STOP condition is generated by the peripheral. or as a slave, provided that the peripheral has been addressed previously during this transfer. It is cleared by software by setting the STOPCF bit. Note: This bit is cleared by hardware when PE=0." start="5" size="1" access="ReadOnly" />
+      <BitField name="TC" description="Transfer Complete (master mode) This flag is set by hardware when RELOAD=0, AUTOEND=0 and NBYTES data have been transferred. It is cleared by software when START bit or STOP bit is set. Note: This bit is cleared by hardware when PE=0." start="6" size="1" access="ReadOnly" />
+      <BitField name="TCR" description="Transfer Complete Reload This flag is set by hardware when RELOAD=1 and NBYTES data have been transferred. It is cleared by software when NBYTES is written to a non-zero value. Note: This bit is cleared by hardware when PE=0. This flag is only for master mode, or for slave mode when the SBC bit is set." start="7" size="1" access="ReadOnly" />
+      <BitField name="BERR" description="Bus error This flag is set by hardware when a misplaced Start or Stop condition is detected whereas the peripheral is involved in the transfer. The flag is not set during the address phase in slave mode. It is cleared by software by setting BERRCF bit. Note: This bit is cleared by hardware when PE=0." start="8" size="1" access="ReadOnly" />
+      <BitField name="ARLO" description="Arbitration lost This flag is set by hardware in case of arbitration loss. It is cleared by software by setting the ARLOCF bit. Note: This bit is cleared by hardware when PE=0." start="9" size="1" access="ReadOnly" />
+      <BitField name="OVR" description="Overrun/Underrun (slave mode) This flag is set by hardware in slave mode with NOSTRETCH=1, when an overrun/underrun error occurs. It is cleared by software by setting the OVRCF bit. Note: This bit is cleared by hardware when PE=0." start="10" size="1" access="ReadOnly" />
+      <BitField name="PECERR" description="PEC Error in reception This flag is set by hardware when the received PEC does not match with the PEC register content. A NACK is automatically sent after the wrong PEC reception. It is cleared by software by setting the PECCF bit. Note: This bit is cleared by hardware when PE=0. If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Please refer to Section25.3: I2C implementation." start="11" size="1" access="ReadOnly" />
+      <BitField name="TIMEOUT" description="Timeout or tLOW detection flag This flag is set by hardware when a timeout or extended clock timeout occurred. It is cleared by software by setting the TIMEOUTCF bit. Note: This bit is cleared by hardware when PE=0. If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Please refer to Section25.3: I2C implementation." start="12" size="1" access="ReadOnly" />
+      <BitField name="ALERT" description="SMBus alert This flag is set by hardware when SMBHEN=1 (SMBus host configuration), ALERTEN=1 and a SMBALERT event (falling edge) is detected on SMBA pin. It is cleared by software by setting the ALERTCF bit. Note: This bit is cleared by hardware when PE=0. If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Please refer to Section25.3: I2C implementation." start="13" size="1" access="ReadOnly" />
+      <BitField name="BUSY" description="Bus busy This flag indicates that a communication is in progress on the bus. It is set by hardware when a START condition is detected. It is cleared by hardware when a Stop condition is detected, or when PE=0." start="15" size="1" access="ReadOnly" />
+      <BitField name="DIR" description="Transfer direction (Slave mode) This flag is updated when an address match event occurs (ADDR=1)." start="16" size="1" access="ReadOnly" />
+      <BitField name="ADDCODE" description="Address match code (Slave mode) These bits are updated with the received address when an address match event occurs (ADDR = 1). In the case of a 10-bit address, ADDCODE provides the 10-bit header followed by the 2 MSBs of the address." start="17" size="7" access="ReadOnly" />
+    </Register>
+    <Register name="ICR" description="Access: No wait states" start="+0x1C" size="4" access="WriteOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ADDRCF" description="Address matched flag clear Writing 1 to this bit clears the ADDR flag in the I2C_ISR register. Writing 1 to this bit also clears the START bit in the I2C_CR2 register." start="3" size="1" />
+      <BitField name="NACKCF" description="Not Acknowledge flag clear Writing 1 to this bit clears the ACKF flag in I2C_ISR register." start="4" size="1" />
+      <BitField name="STOPCF" description="Stop detection flag clear Writing 1 to this bit clears the STOPF flag in the I2C_ISR register." start="5" size="1" />
+      <BitField name="BERRCF" description="Bus error flag clear Writing 1 to this bit clears the BERRF flag in the I2C_ISR register." start="8" size="1" />
+      <BitField name="ARLOCF" description="Arbitration Lost flag clear Writing 1 to this bit clears the ARLO flag in the I2C_ISR register." start="9" size="1" />
+      <BitField name="OVRCF" description="Overrun/Underrun flag clear Writing 1 to this bit clears the OVR flag in the I2C_ISR register." start="10" size="1" />
+      <BitField name="PECCF" description="PEC Error flag clear Writing 1 to this bit clears the PECERR flag in the I2C_ISR register. Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Please refer to Section25.3: I2C implementation." start="11" size="1" />
+      <BitField name="TIMOUTCF" description="Timeout detection flag clear Writing 1 to this bit clears the TIMEOUT flag in the I2C_ISR register. Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Please refer to Section25.3: I2C implementation." start="12" size="1" />
+      <BitField name="ALERTCF" description="Alert flag clear Writing 1 to this bit clears the ALERT flag in the I2C_ISR register. Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Please refer to Section25.3: I2C implementation." start="13" size="1" />
+    </Register>
+    <Register name="PECR" description="Access: No wait states" start="+0x20" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PEC" description="Packet error checking register This field contains the internal PEC when PECEN=1. The PEC is cleared by hardware when PE=0." start="0" size="8" />
+    </Register>
+    <Register name="RXDR" description="Access: No wait states" start="+0x24" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RXDATA" description="8-bit receive data Data byte received from the I2C bus." start="0" size="8" />
+    </Register>
+    <Register name="TXDR" description="Access: No wait states" start="+0x28" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TXDATA" description="8-bit transmit data Data byte to be transmitted to the I2C bus. Note: These bits can be written only when TXE=1." start="0" size="8" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="I2C2" description="I2C" start="0x40005800">
+    <Register name="CR1" description="Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed. The latency of the second write access can be up to 2 x PCLK1 + 6 x I2CCLK." start="+0x0" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PE" description="Peripheral enable Note: When PE=0, the I2C SCL and SDA lines are released. Internal state machines and status bits are put back to their reset value. When cleared, PE must be kept low for at least 3 APB clock cycles." start="0" size="1" />
+      <BitField name="TXIE" description="TX Interrupt enable" start="1" size="1" />
+      <BitField name="RXIE" description="RX Interrupt enable" start="2" size="1" />
+      <BitField name="ADDRIE" description="Address match Interrupt enable (slave only)" start="3" size="1" />
+      <BitField name="NACKIE" description="Not acknowledge received Interrupt enable" start="4" size="1" />
+      <BitField name="STOPIE" description="STOP detection Interrupt enable" start="5" size="1" />
+      <BitField name="TCIE" description="Transfer Complete interrupt enable Note: Any of these events will generate an interrupt: Transfer Complete (TC) Transfer Complete Reload (TCR)" start="6" size="1" />
+      <BitField name="ERRIE" description="Error interrupts enable Note: Any of these errors generate an interrupt: Arbitration Loss (ARLO) Bus Error detection (BERR) Overrun/Underrun (OVR) Timeout detection (TIMEOUT) PEC error detection (PECERR) Alert pin event detection (ALERT)" start="7" size="1" />
+      <BitField name="DNF" description="Digital noise filter These bits are used to configure the digital noise filter on SDA and SCL input. The digital filter will filter spikes with a length of up to DNF[3:0] * tI2CCLK ... Note: If the analog filter is also enabled, the digital filter is added to the analog filter. This filter can only be programmed when the I2C is disabled (PE = 0)." start="8" size="4" />
+      <BitField name="ANFOFF" description="Analog noise filter OFF Note: This bit can only be programmed when the I2C is disabled (PE = 0)." start="12" size="1" />
+      <BitField name="TXDMAEN" description="DMA transmission requests enable" start="14" size="1" />
+      <BitField name="RXDMAEN" description="DMA reception requests enable" start="15" size="1" />
+      <BitField name="SBC" description="Slave byte control This bit is used to enable hardware byte control in slave mode." start="16" size="1" />
+      <BitField name="NOSTRETCH" description="Clock stretching disable This bit is used to disable clock stretching in slave mode. It must be kept cleared in master mode. Note: This bit can only be programmed when the I2C is disabled (PE = 0)." start="17" size="1" />
+      <BitField name="WUPEN" description="Wakeup from Stop mode enable Note: If the Wakeup from Stop mode feature is not supported, this bit is reserved and forced by hardware to 0. Please refer to Section25.3: I2C implementation. Note: WUPEN can be set only when DNF = 0000" start="18" size="1" />
+      <BitField name="GCEN" description="General call enable" start="19" size="1" />
+      <BitField name="SMBHEN" description="SMBus Host address enable Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Please refer to Section25.3: I2C implementation." start="20" size="1" />
+      <BitField name="SMBDEN" description="SMBus Device Default address enable Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Please refer to Section25.3: I2C implementation." start="21" size="1" />
+      <BitField name="ALERTEN" description="SMBus alert enable Device mode (SMBHEN=0): Host mode (SMBHEN=1): Note: When ALERTEN=0, the SMBA pin can be used as a standard GPIO. If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Please refer to Section25.3: I2C implementation." start="22" size="1" />
+      <BitField name="PECEN" description="PEC enable Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Please refer to Section25.3: I2C implementation." start="23" size="1" />
+    </Register>
+    <Register name="CR2" description="Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed. The latency of the second write access can be up to 2 x PCLK1 + 6 x I2CCLK." start="+0x4" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SADD0" description="Slave address bit 0 (master mode) In 7-bit addressing mode (ADD10 = 0): This bit is dont care In 10-bit addressing mode (ADD10 = 1): This bit should be written with bit 0 of the slave address to be sent Note: Changing these bits when the START bit is set is not allowed." start="0" size="1" />
+      <BitField name="SADD1" description="Slave address bit 7:1 (master mode) In 7-bit addressing mode (ADD10 = 0): These bits should be written with the 7-bit slave address to be sent In 10-bit addressing mode (ADD10 = 1): These bits should be written with bits 7:1 of the slave address to be sent. Note: Changing these bits when the START bit is set is not allowed." start="1" size="1" />
+      <BitField name="SADD2" description="Slave address bit 7:1 (master mode) In 7-bit addressing mode (ADD10 = 0): These bits should be written with the 7-bit slave address to be sent In 10-bit addressing mode (ADD10 = 1): These bits should be written with bits 7:1 of the slave address to be sent. Note: Changing these bits when the START bit is set is not allowed." start="2" size="1" />
+      <BitField name="SADD3" description="Slave address bit 7:1 (master mode) In 7-bit addressing mode (ADD10 = 0): These bits should be written with the 7-bit slave address to be sent In 10-bit addressing mode (ADD10 = 1): These bits should be written with bits 7:1 of the slave address to be sent. Note: Changing these bits when the START bit is set is not allowed." start="3" size="1" />
+      <BitField name="SADD4" description="Slave address bit 7:1 (master mode) In 7-bit addressing mode (ADD10 = 0): These bits should be written with the 7-bit slave address to be sent In 10-bit addressing mode (ADD10 = 1): These bits should be written with bits 7:1 of the slave address to be sent. Note: Changing these bits when the START bit is set is not allowed." start="4" size="1" />
+      <BitField name="SADD5" description="Slave address bit 7:1 (master mode) In 7-bit addressing mode (ADD10 = 0): These bits should be written with the 7-bit slave address to be sent In 10-bit addressing mode (ADD10 = 1): These bits should be written with bits 7:1 of the slave address to be sent. Note: Changing these bits when the START bit is set is not allowed." start="5" size="1" />
+      <BitField name="SADD6" description="Slave address bit 7:1 (master mode) In 7-bit addressing mode (ADD10 = 0): These bits should be written with the 7-bit slave address to be sent In 10-bit addressing mode (ADD10 = 1): These bits should be written with bits 7:1 of the slave address to be sent. Note: Changing these bits when the START bit is set is not allowed." start="6" size="1" />
+      <BitField name="SADD7" description="Slave address bit 7:1 (master mode) In 7-bit addressing mode (ADD10 = 0): These bits should be written with the 7-bit slave address to be sent In 10-bit addressing mode (ADD10 = 1): These bits should be written with bits 7:1 of the slave address to be sent. Note: Changing these bits when the START bit is set is not allowed." start="7" size="1" />
+      <BitField name="SADD8" description="Slave address bit 9:8 (master mode) In 7-bit addressing mode (ADD10 = 0): These bits are dont care In 10-bit addressing mode (ADD10 = 1): These bits should be written with bits 9:8 of the slave address to be sent Note: Changing these bits when the START bit is set is not allowed." start="8" size="1" />
+      <BitField name="SADD9" description="Slave address bit 9:8 (master mode) In 7-bit addressing mode (ADD10 = 0): These bits are dont care In 10-bit addressing mode (ADD10 = 1): These bits should be written with bits 9:8 of the slave address to be sent Note: Changing these bits when the START bit is set is not allowed." start="9" size="1" />
+      <BitField name="RD_WRN" description="Transfer direction (master mode) Note: Changing this bit when the START bit is set is not allowed." start="10" size="1" />
+      <BitField name="ADD10" description="10-bit addressing mode (master mode) Note: Changing this bit when the START bit is set is not allowed." start="11" size="1" />
+      <BitField name="HEAD10R" description="10-bit address header only read direction (master receiver mode) Note: Changing this bit when the START bit is set is not allowed." start="12" size="1" />
+      <BitField name="START" description="Start generation This bit is set by software, and cleared by hardware after the Start followed by the address sequence is sent, by an arbitration loss, by a timeout error detection, or when PE = 0. It can also be cleared by software by writing 1 to the ADDRCF bit in the I2C_ICR register. If the I2C is already in master mode with AUTOEND = 0, setting this bit generates a Repeated Start condition when RELOAD=0, after the end of the NBYTES transfer. Otherwise setting this bit will generate a START condition once the bus is free. Note: Writing 0 to this bit has no effect. The START bit can be set even if the bus is BUSY or I2C is in slave mode. This bit has no effect when RELOAD is set." start="13" size="1" />
+      <BitField name="STOP" description="Stop generation (master mode) The bit is set by software, cleared by hardware when a Stop condition is detected, or when PE = 0. In Master Mode: Note: Writing 0 to this bit has no effect." start="14" size="1" />
+      <BitField name="NACK" description="NACK generation (slave mode) The bit is set by software, cleared by hardware when the NACK is sent, or when a STOP condition or an Address matched is received, or when PE=0. Note: Writing 0 to this bit has no effect. This bit is used in slave mode only: in master receiver mode, NACK is automatically generated after last byte preceding STOP or RESTART condition, whatever the NACK bit value. When an overrun occurs in slave receiver NOSTRETCH mode, a NACK is automatically generated whatever the NACK bit value. When hardware PEC checking is enabled (PECBYTE=1), the PEC acknowledge value does not depend on the NACK value." start="15" size="1" />
+      <BitField name="NBYTES" description="Number of bytes The number of bytes to be transmitted/received is programmed there. This field is dont care in slave mode with SBC=0. Note: Changing these bits when the START bit is set is not allowed." start="16" size="8" />
+      <BitField name="RELOAD" description="NBYTES reload mode This bit is set and cleared by software." start="24" size="1" />
+      <BitField name="AUTOEND" description="Automatic end mode (master mode) This bit is set and cleared by software. Note: This bit has no effect in slave mode or when the RELOAD bit is set." start="25" size="1" />
+      <BitField name="PECBYTE" description="Packet error checking byte This bit is set by software, and cleared by hardware when the PEC is transferred, or when a STOP condition or an Address matched is received, also when PE=0. Note: Writing 0 to this bit has no effect. This bit has no effect when RELOAD is set. This bit has no effect is slave mode when SBC=0. If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Please refer to Section25.3: I2C implementation." start="26" size="1" />
+    </Register>
+    <Register name="OAR1" description="Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed. The latency of the second write access can be up to 2 x PCLK1 + 6 x I2CCLK." start="+0x8" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OA1" description="Interface address 7-bit addressing mode: dont care 10-bit addressing mode: bits 9:8 of address Note: These bits can be written only when OA1EN=0. OA1[7:1]: Interface address Bits 7:1 of address Note: These bits can be written only when OA1EN=0. OA1[0]: Interface address 7-bit addressing mode: dont care 10-bit addressing mode: bit 0 of address Note: This bit can be written only when OA1EN=0." start="0" size="10" />
+      <BitField name="OA1MODE" description="Own Address 1 10-bit mode Note: This bit can be written only when OA1EN=0." start="10" size="1" />
+      <BitField name="OA1EN" description="Own Address 1 enable" start="15" size="1" />
+    </Register>
+    <Register name="OAR2" description="Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed. The latency of the second write access can be up to 2 x PCLK1 + 6 x I2CCLK." start="+0xC" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OA2" description="Interface address bits 7:1 of address Note: These bits can be written only when OA2EN=0." start="1" size="7" />
+      <BitField name="OA2MSK" description="Own Address 2 masks Note: These bits can be written only when OA2EN=0. As soon as OA2MSK is not equal to 0, the reserved I2C addresses (0b0000xxx and 0b1111xxx) are not acknowledged even if the comparison matches." start="8" size="3" />
+      <BitField name="OA2EN" description="Own Address 2 enable" start="15" size="1" />
+    </Register>
+    <Register name="TIMINGR" description="Access: No wait states" start="+0x10" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SCLL" description="SCL low period (master mode) This field is used to generate the SCL low period in master mode. tSCLL = (SCLL+1) x tPRESC Note: SCLL is also used to generate tBUF and tSU:STA timings." start="0" size="8" />
+      <BitField name="SCLH" description="SCL high period (master mode) This field is used to generate the SCL high period in master mode. tSCLH = (SCLH+1) x tPRESC Note: SCLH is also used to generate tSU:STO and tHD:STA timing." start="8" size="8" />
+      <BitField name="SDADEL" description="Data hold time This field is used to generate the delay tSDADEL between SCL falling edge and SDA edge. In master mode and in slave mode with NOSTRETCH = 0, the SCL line is stretched low during tSDADEL. tSDADEL= SDADEL x tPRESC Note: SDADEL is used to generate tHD:DAT timing." start="16" size="4" />
+      <BitField name="SCLDEL" description="Data setup time This field is used to generate a delay tSCLDEL between SDA edge and SCL rising edge. In master mode and in slave mode with NOSTRETCH = 0, the SCL line is stretched low during tSCLDEL. tSCLDEL = (SCLDEL+1) x tPRESC Note: tSCLDEL is used to generate tSU:DAT timing." start="20" size="4" />
+      <BitField name="PRESC" description="Timing prescaler This field is used to prescale I2CCLK in order to generate the clock period tPRESC used for data setup and hold counters (refer to I2C timings on page9) and for SCL high and low level counters (refer to I2C master initialization on page24). tPRESC = (PRESC+1) x tI2CCLK" start="28" size="4" />
+    </Register>
+    <Register name="TIMEOUTR" description="Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed. The latency of the second write access can be up to 2 x PCLK1 + 6 x I2CCLK." start="+0x14" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TIMEOUTA" description="Bus Timeout A This field is used to configure: The SCL low timeout condition tTIMEOUT when TIDLE=0 tTIMEOUT= (TIMEOUTA+1) x 2048 x tI2CCLK The bus idle condition (both SCL and SDA high) when TIDLE=1 tIDLE= (TIMEOUTA+1) x 4 x tI2CCLK Note: These bits can be written only when TIMOUTEN=0." start="0" size="12" />
+      <BitField name="TIDLE" description="Idle clock timeout detection Note: This bit can be written only when TIMOUTEN=0." start="12" size="1" />
+      <BitField name="TIMOUTEN" description="Clock timeout enable" start="15" size="1" />
+      <BitField name="TIMEOUTB" description="Bus timeout B This field is used to configure the cumulative clock extension timeout: In master mode, the master cumulative clock low extend time (tLOW:MEXT) is detected In slave mode, the slave cumulative clock low extend time (tLOW:SEXT) is detected tLOW:EXT= (TIMEOUTB+1) x 2048 x tI2CCLK Note: These bits can be written only when TEXTEN=0." start="16" size="12" />
+      <BitField name="TEXTEN" description="Extended clock timeout enable" start="31" size="1" />
+    </Register>
+    <Register name="ISR" description="Access: No wait states" start="+0x18" size="4" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField name="TXE" description="Transmit data register empty (transmitters) This bit is set by hardware when the I2C_TXDR register is empty. It is cleared when the next data to be sent is written in the I2C_TXDR register. This bit can be written to 1 by software in order to flush the transmit data register I2C_TXDR. Note: This bit is set by hardware when PE=0." start="0" size="1" access="Read/Write" />
+      <BitField name="TXIS" description="Transmit interrupt status (transmitters) This bit is set by hardware when the I2C_TXDR register is empty and the data to be transmitted must be written in the I2C_TXDR register. It is cleared when the next data to be sent is written in the I2C_TXDR register. This bit can be written to 1 by software when NOSTRETCH=1 only, in order to generate a TXIS event (interrupt if TXIE=1 or DMA request if TXDMAEN=1). Note: This bit is cleared by hardware when PE=0." start="1" size="1" access="Read/Write" />
+      <BitField name="RXNE" description="Receive data register not empty (receivers) This bit is set by hardware when the received data is copied into the I2C_RXDR register, and is ready to be read. It is cleared when I2C_RXDR is read. Note: This bit is cleared by hardware when PE=0." start="2" size="1" access="ReadOnly" />
+      <BitField name="ADDR" description="Address matched (slave mode) This bit is set by hardware as soon as the received slave address matched with one of the enabled slave addresses. It is cleared by software by setting ADDRCF bit. Note: This bit is cleared by hardware when PE=0." start="3" size="1" access="ReadOnly" />
+      <BitField name="NACKF" description="Not Acknowledge received flag This flag is set by hardware when a NACK is received after a byte transmission. It is cleared by software by setting the NACKCF bit. Note: This bit is cleared by hardware when PE=0." start="4" size="1" access="ReadOnly" />
+      <BitField name="STOPF" description="Stop detection flag This flag is set by hardware when a Stop condition is detected on the bus and the peripheral is involved in this transfer: either as a master, provided that the STOP condition is generated by the peripheral. or as a slave, provided that the peripheral has been addressed previously during this transfer. It is cleared by software by setting the STOPCF bit. Note: This bit is cleared by hardware when PE=0." start="5" size="1" access="ReadOnly" />
+      <BitField name="TC" description="Transfer Complete (master mode) This flag is set by hardware when RELOAD=0, AUTOEND=0 and NBYTES data have been transferred. It is cleared by software when START bit or STOP bit is set. Note: This bit is cleared by hardware when PE=0." start="6" size="1" access="ReadOnly" />
+      <BitField name="TCR" description="Transfer Complete Reload This flag is set by hardware when RELOAD=1 and NBYTES data have been transferred. It is cleared by software when NBYTES is written to a non-zero value. Note: This bit is cleared by hardware when PE=0. This flag is only for master mode, or for slave mode when the SBC bit is set." start="7" size="1" access="ReadOnly" />
+      <BitField name="BERR" description="Bus error This flag is set by hardware when a misplaced Start or Stop condition is detected whereas the peripheral is involved in the transfer. The flag is not set during the address phase in slave mode. It is cleared by software by setting BERRCF bit. Note: This bit is cleared by hardware when PE=0." start="8" size="1" access="ReadOnly" />
+      <BitField name="ARLO" description="Arbitration lost This flag is set by hardware in case of arbitration loss. It is cleared by software by setting the ARLOCF bit. Note: This bit is cleared by hardware when PE=0." start="9" size="1" access="ReadOnly" />
+      <BitField name="OVR" description="Overrun/Underrun (slave mode) This flag is set by hardware in slave mode with NOSTRETCH=1, when an overrun/underrun error occurs. It is cleared by software by setting the OVRCF bit. Note: This bit is cleared by hardware when PE=0." start="10" size="1" access="ReadOnly" />
+      <BitField name="PECERR" description="PEC Error in reception This flag is set by hardware when the received PEC does not match with the PEC register content. A NACK is automatically sent after the wrong PEC reception. It is cleared by software by setting the PECCF bit. Note: This bit is cleared by hardware when PE=0. If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Please refer to Section25.3: I2C implementation." start="11" size="1" access="ReadOnly" />
+      <BitField name="TIMEOUT" description="Timeout or tLOW detection flag This flag is set by hardware when a timeout or extended clock timeout occurred. It is cleared by software by setting the TIMEOUTCF bit. Note: This bit is cleared by hardware when PE=0. If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Please refer to Section25.3: I2C implementation." start="12" size="1" access="ReadOnly" />
+      <BitField name="ALERT" description="SMBus alert This flag is set by hardware when SMBHEN=1 (SMBus host configuration), ALERTEN=1 and a SMBALERT event (falling edge) is detected on SMBA pin. It is cleared by software by setting the ALERTCF bit. Note: This bit is cleared by hardware when PE=0. If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Please refer to Section25.3: I2C implementation." start="13" size="1" access="ReadOnly" />
+      <BitField name="BUSY" description="Bus busy This flag indicates that a communication is in progress on the bus. It is set by hardware when a START condition is detected. It is cleared by hardware when a Stop condition is detected, or when PE=0." start="15" size="1" access="ReadOnly" />
+      <BitField name="DIR" description="Transfer direction (Slave mode) This flag is updated when an address match event occurs (ADDR=1)." start="16" size="1" access="ReadOnly" />
+      <BitField name="ADDCODE" description="Address match code (Slave mode) These bits are updated with the received address when an address match event occurs (ADDR = 1). In the case of a 10-bit address, ADDCODE provides the 10-bit header followed by the 2 MSBs of the address." start="17" size="7" access="ReadOnly" />
+    </Register>
+    <Register name="ICR" description="Access: No wait states" start="+0x1C" size="4" access="WriteOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ADDRCF" description="Address matched flag clear Writing 1 to this bit clears the ADDR flag in the I2C_ISR register. Writing 1 to this bit also clears the START bit in the I2C_CR2 register." start="3" size="1" />
+      <BitField name="NACKCF" description="Not Acknowledge flag clear Writing 1 to this bit clears the ACKF flag in I2C_ISR register." start="4" size="1" />
+      <BitField name="STOPCF" description="Stop detection flag clear Writing 1 to this bit clears the STOPF flag in the I2C_ISR register." start="5" size="1" />
+      <BitField name="BERRCF" description="Bus error flag clear Writing 1 to this bit clears the BERRF flag in the I2C_ISR register." start="8" size="1" />
+      <BitField name="ARLOCF" description="Arbitration Lost flag clear Writing 1 to this bit clears the ARLO flag in the I2C_ISR register." start="9" size="1" />
+      <BitField name="OVRCF" description="Overrun/Underrun flag clear Writing 1 to this bit clears the OVR flag in the I2C_ISR register." start="10" size="1" />
+      <BitField name="PECCF" description="PEC Error flag clear Writing 1 to this bit clears the PECERR flag in the I2C_ISR register. Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Please refer to Section25.3: I2C implementation." start="11" size="1" />
+      <BitField name="TIMOUTCF" description="Timeout detection flag clear Writing 1 to this bit clears the TIMEOUT flag in the I2C_ISR register. Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Please refer to Section25.3: I2C implementation." start="12" size="1" />
+      <BitField name="ALERTCF" description="Alert flag clear Writing 1 to this bit clears the ALERT flag in the I2C_ISR register. Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Please refer to Section25.3: I2C implementation." start="13" size="1" />
+    </Register>
+    <Register name="PECR" description="Access: No wait states" start="+0x20" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PEC" description="Packet error checking register This field contains the internal PEC when PECEN=1. The PEC is cleared by hardware when PE=0." start="0" size="8" />
+    </Register>
+    <Register name="RXDR" description="Access: No wait states" start="+0x24" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RXDATA" description="8-bit receive data Data byte received from the I2C bus." start="0" size="8" />
+    </Register>
+    <Register name="TXDR" description="Access: No wait states" start="+0x28" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TXDATA" description="8-bit transmit data Data byte to be transmitted to the I2C bus. Note: These bits can be written only when TXE=1." start="0" size="8" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="I2C3" description="I2C" start="0x40005C00">
+    <Register name="CR1" description="Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed. The latency of the second write access can be up to 2 x PCLK1 + 6 x I2CCLK." start="+0x0" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PE" description="Peripheral enable Note: When PE=0, the I2C SCL and SDA lines are released. Internal state machines and status bits are put back to their reset value. When cleared, PE must be kept low for at least 3 APB clock cycles." start="0" size="1" />
+      <BitField name="TXIE" description="TX Interrupt enable" start="1" size="1" />
+      <BitField name="RXIE" description="RX Interrupt enable" start="2" size="1" />
+      <BitField name="ADDRIE" description="Address match Interrupt enable (slave only)" start="3" size="1" />
+      <BitField name="NACKIE" description="Not acknowledge received Interrupt enable" start="4" size="1" />
+      <BitField name="STOPIE" description="STOP detection Interrupt enable" start="5" size="1" />
+      <BitField name="TCIE" description="Transfer Complete interrupt enable Note: Any of these events will generate an interrupt: Transfer Complete (TC) Transfer Complete Reload (TCR)" start="6" size="1" />
+      <BitField name="ERRIE" description="Error interrupts enable Note: Any of these errors generate an interrupt: Arbitration Loss (ARLO) Bus Error detection (BERR) Overrun/Underrun (OVR) Timeout detection (TIMEOUT) PEC error detection (PECERR) Alert pin event detection (ALERT)" start="7" size="1" />
+      <BitField name="DNF" description="Digital noise filter These bits are used to configure the digital noise filter on SDA and SCL input. The digital filter will filter spikes with a length of up to DNF[3:0] * tI2CCLK ... Note: If the analog filter is also enabled, the digital filter is added to the analog filter. This filter can only be programmed when the I2C is disabled (PE = 0)." start="8" size="4" />
+      <BitField name="ANFOFF" description="Analog noise filter OFF Note: This bit can only be programmed when the I2C is disabled (PE = 0)." start="12" size="1" />
+      <BitField name="TXDMAEN" description="DMA transmission requests enable" start="14" size="1" />
+      <BitField name="RXDMAEN" description="DMA reception requests enable" start="15" size="1" />
+      <BitField name="SBC" description="Slave byte control This bit is used to enable hardware byte control in slave mode." start="16" size="1" />
+      <BitField name="NOSTRETCH" description="Clock stretching disable This bit is used to disable clock stretching in slave mode. It must be kept cleared in master mode. Note: This bit can only be programmed when the I2C is disabled (PE = 0)." start="17" size="1" />
+      <BitField name="WUPEN" description="Wakeup from Stop mode enable Note: If the Wakeup from Stop mode feature is not supported, this bit is reserved and forced by hardware to 0. Please refer to Section25.3: I2C implementation. Note: WUPEN can be set only when DNF = 0000" start="18" size="1" />
+      <BitField name="GCEN" description="General call enable" start="19" size="1" />
+      <BitField name="SMBHEN" description="SMBus Host address enable Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Please refer to Section25.3: I2C implementation." start="20" size="1" />
+      <BitField name="SMBDEN" description="SMBus Device Default address enable Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Please refer to Section25.3: I2C implementation." start="21" size="1" />
+      <BitField name="ALERTEN" description="SMBus alert enable Device mode (SMBHEN=0): Host mode (SMBHEN=1): Note: When ALERTEN=0, the SMBA pin can be used as a standard GPIO. If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Please refer to Section25.3: I2C implementation." start="22" size="1" />
+      <BitField name="PECEN" description="PEC enable Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Please refer to Section25.3: I2C implementation." start="23" size="1" />
+    </Register>
+    <Register name="CR2" description="Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed. The latency of the second write access can be up to 2 x PCLK1 + 6 x I2CCLK." start="+0x4" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SADD0" description="Slave address bit 0 (master mode) In 7-bit addressing mode (ADD10 = 0): This bit is dont care In 10-bit addressing mode (ADD10 = 1): This bit should be written with bit 0 of the slave address to be sent Note: Changing these bits when the START bit is set is not allowed." start="0" size="1" />
+      <BitField name="SADD1" description="Slave address bit 7:1 (master mode) In 7-bit addressing mode (ADD10 = 0): These bits should be written with the 7-bit slave address to be sent In 10-bit addressing mode (ADD10 = 1): These bits should be written with bits 7:1 of the slave address to be sent. Note: Changing these bits when the START bit is set is not allowed." start="1" size="1" />
+      <BitField name="SADD2" description="Slave address bit 7:1 (master mode) In 7-bit addressing mode (ADD10 = 0): These bits should be written with the 7-bit slave address to be sent In 10-bit addressing mode (ADD10 = 1): These bits should be written with bits 7:1 of the slave address to be sent. Note: Changing these bits when the START bit is set is not allowed." start="2" size="1" />
+      <BitField name="SADD3" description="Slave address bit 7:1 (master mode) In 7-bit addressing mode (ADD10 = 0): These bits should be written with the 7-bit slave address to be sent In 10-bit addressing mode (ADD10 = 1): These bits should be written with bits 7:1 of the slave address to be sent. Note: Changing these bits when the START bit is set is not allowed." start="3" size="1" />
+      <BitField name="SADD4" description="Slave address bit 7:1 (master mode) In 7-bit addressing mode (ADD10 = 0): These bits should be written with the 7-bit slave address to be sent In 10-bit addressing mode (ADD10 = 1): These bits should be written with bits 7:1 of the slave address to be sent. Note: Changing these bits when the START bit is set is not allowed." start="4" size="1" />
+      <BitField name="SADD5" description="Slave address bit 7:1 (master mode) In 7-bit addressing mode (ADD10 = 0): These bits should be written with the 7-bit slave address to be sent In 10-bit addressing mode (ADD10 = 1): These bits should be written with bits 7:1 of the slave address to be sent. Note: Changing these bits when the START bit is set is not allowed." start="5" size="1" />
+      <BitField name="SADD6" description="Slave address bit 7:1 (master mode) In 7-bit addressing mode (ADD10 = 0): These bits should be written with the 7-bit slave address to be sent In 10-bit addressing mode (ADD10 = 1): These bits should be written with bits 7:1 of the slave address to be sent. Note: Changing these bits when the START bit is set is not allowed." start="6" size="1" />
+      <BitField name="SADD7" description="Slave address bit 7:1 (master mode) In 7-bit addressing mode (ADD10 = 0): These bits should be written with the 7-bit slave address to be sent In 10-bit addressing mode (ADD10 = 1): These bits should be written with bits 7:1 of the slave address to be sent. Note: Changing these bits when the START bit is set is not allowed." start="7" size="1" />
+      <BitField name="SADD8" description="Slave address bit 9:8 (master mode) In 7-bit addressing mode (ADD10 = 0): These bits are dont care In 10-bit addressing mode (ADD10 = 1): These bits should be written with bits 9:8 of the slave address to be sent Note: Changing these bits when the START bit is set is not allowed." start="8" size="1" />
+      <BitField name="SADD9" description="Slave address bit 9:8 (master mode) In 7-bit addressing mode (ADD10 = 0): These bits are dont care In 10-bit addressing mode (ADD10 = 1): These bits should be written with bits 9:8 of the slave address to be sent Note: Changing these bits when the START bit is set is not allowed." start="9" size="1" />
+      <BitField name="RD_WRN" description="Transfer direction (master mode) Note: Changing this bit when the START bit is set is not allowed." start="10" size="1" />
+      <BitField name="ADD10" description="10-bit addressing mode (master mode) Note: Changing this bit when the START bit is set is not allowed." start="11" size="1" />
+      <BitField name="HEAD10R" description="10-bit address header only read direction (master receiver mode) Note: Changing this bit when the START bit is set is not allowed." start="12" size="1" />
+      <BitField name="START" description="Start generation This bit is set by software, and cleared by hardware after the Start followed by the address sequence is sent, by an arbitration loss, by a timeout error detection, or when PE = 0. It can also be cleared by software by writing 1 to the ADDRCF bit in the I2C_ICR register. If the I2C is already in master mode with AUTOEND = 0, setting this bit generates a Repeated Start condition when RELOAD=0, after the end of the NBYTES transfer. Otherwise setting this bit will generate a START condition once the bus is free. Note: Writing 0 to this bit has no effect. The START bit can be set even if the bus is BUSY or I2C is in slave mode. This bit has no effect when RELOAD is set." start="13" size="1" />
+      <BitField name="STOP" description="Stop generation (master mode) The bit is set by software, cleared by hardware when a Stop condition is detected, or when PE = 0. In Master Mode: Note: Writing 0 to this bit has no effect." start="14" size="1" />
+      <BitField name="NACK" description="NACK generation (slave mode) The bit is set by software, cleared by hardware when the NACK is sent, or when a STOP condition or an Address matched is received, or when PE=0. Note: Writing 0 to this bit has no effect. This bit is used in slave mode only: in master receiver mode, NACK is automatically generated after last byte preceding STOP or RESTART condition, whatever the NACK bit value. When an overrun occurs in slave receiver NOSTRETCH mode, a NACK is automatically generated whatever the NACK bit value. When hardware PEC checking is enabled (PECBYTE=1), the PEC acknowledge value does not depend on the NACK value." start="15" size="1" />
+      <BitField name="NBYTES" description="Number of bytes The number of bytes to be transmitted/received is programmed there. This field is dont care in slave mode with SBC=0. Note: Changing these bits when the START bit is set is not allowed." start="16" size="8" />
+      <BitField name="RELOAD" description="NBYTES reload mode This bit is set and cleared by software." start="24" size="1" />
+      <BitField name="AUTOEND" description="Automatic end mode (master mode) This bit is set and cleared by software. Note: This bit has no effect in slave mode or when the RELOAD bit is set." start="25" size="1" />
+      <BitField name="PECBYTE" description="Packet error checking byte This bit is set by software, and cleared by hardware when the PEC is transferred, or when a STOP condition or an Address matched is received, also when PE=0. Note: Writing 0 to this bit has no effect. This bit has no effect when RELOAD is set. This bit has no effect is slave mode when SBC=0. If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Please refer to Section25.3: I2C implementation." start="26" size="1" />
+    </Register>
+    <Register name="OAR1" description="Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed. The latency of the second write access can be up to 2 x PCLK1 + 6 x I2CCLK." start="+0x8" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OA1" description="Interface address 7-bit addressing mode: dont care 10-bit addressing mode: bits 9:8 of address Note: These bits can be written only when OA1EN=0. OA1[7:1]: Interface address Bits 7:1 of address Note: These bits can be written only when OA1EN=0. OA1[0]: Interface address 7-bit addressing mode: dont care 10-bit addressing mode: bit 0 of address Note: This bit can be written only when OA1EN=0." start="0" size="10" />
+      <BitField name="OA1MODE" description="Own Address 1 10-bit mode Note: This bit can be written only when OA1EN=0." start="10" size="1" />
+      <BitField name="OA1EN" description="Own Address 1 enable" start="15" size="1" />
+    </Register>
+    <Register name="OAR2" description="Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed. The latency of the second write access can be up to 2 x PCLK1 + 6 x I2CCLK." start="+0xC" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OA2" description="Interface address bits 7:1 of address Note: These bits can be written only when OA2EN=0." start="1" size="7" />
+      <BitField name="OA2MSK" description="Own Address 2 masks Note: These bits can be written only when OA2EN=0. As soon as OA2MSK is not equal to 0, the reserved I2C addresses (0b0000xxx and 0b1111xxx) are not acknowledged even if the comparison matches." start="8" size="3" />
+      <BitField name="OA2EN" description="Own Address 2 enable" start="15" size="1" />
+    </Register>
+    <Register name="TIMINGR" description="Access: No wait states" start="+0x10" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SCLL" description="SCL low period (master mode) This field is used to generate the SCL low period in master mode. tSCLL = (SCLL+1) x tPRESC Note: SCLL is also used to generate tBUF and tSU:STA timings." start="0" size="8" />
+      <BitField name="SCLH" description="SCL high period (master mode) This field is used to generate the SCL high period in master mode. tSCLH = (SCLH+1) x tPRESC Note: SCLH is also used to generate tSU:STO and tHD:STA timing." start="8" size="8" />
+      <BitField name="SDADEL" description="Data hold time This field is used to generate the delay tSDADEL between SCL falling edge and SDA edge. In master mode and in slave mode with NOSTRETCH = 0, the SCL line is stretched low during tSDADEL. tSDADEL= SDADEL x tPRESC Note: SDADEL is used to generate tHD:DAT timing." start="16" size="4" />
+      <BitField name="SCLDEL" description="Data setup time This field is used to generate a delay tSCLDEL between SDA edge and SCL rising edge. In master mode and in slave mode with NOSTRETCH = 0, the SCL line is stretched low during tSCLDEL. tSCLDEL = (SCLDEL+1) x tPRESC Note: tSCLDEL is used to generate tSU:DAT timing." start="20" size="4" />
+      <BitField name="PRESC" description="Timing prescaler This field is used to prescale I2CCLK in order to generate the clock period tPRESC used for data setup and hold counters (refer to I2C timings on page9) and for SCL high and low level counters (refer to I2C master initialization on page24). tPRESC = (PRESC+1) x tI2CCLK" start="28" size="4" />
+    </Register>
+    <Register name="TIMEOUTR" description="Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed. The latency of the second write access can be up to 2 x PCLK1 + 6 x I2CCLK." start="+0x14" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TIMEOUTA" description="Bus Timeout A This field is used to configure: The SCL low timeout condition tTIMEOUT when TIDLE=0 tTIMEOUT= (TIMEOUTA+1) x 2048 x tI2CCLK The bus idle condition (both SCL and SDA high) when TIDLE=1 tIDLE= (TIMEOUTA+1) x 4 x tI2CCLK Note: These bits can be written only when TIMOUTEN=0." start="0" size="12" />
+      <BitField name="TIDLE" description="Idle clock timeout detection Note: This bit can be written only when TIMOUTEN=0." start="12" size="1" />
+      <BitField name="TIMOUTEN" description="Clock timeout enable" start="15" size="1" />
+      <BitField name="TIMEOUTB" description="Bus timeout B This field is used to configure the cumulative clock extension timeout: In master mode, the master cumulative clock low extend time (tLOW:MEXT) is detected In slave mode, the slave cumulative clock low extend time (tLOW:SEXT) is detected tLOW:EXT= (TIMEOUTB+1) x 2048 x tI2CCLK Note: These bits can be written only when TEXTEN=0." start="16" size="12" />
+      <BitField name="TEXTEN" description="Extended clock timeout enable" start="31" size="1" />
+    </Register>
+    <Register name="ISR" description="Access: No wait states" start="+0x18" size="4" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField name="TXE" description="Transmit data register empty (transmitters) This bit is set by hardware when the I2C_TXDR register is empty. It is cleared when the next data to be sent is written in the I2C_TXDR register. This bit can be written to 1 by software in order to flush the transmit data register I2C_TXDR. Note: This bit is set by hardware when PE=0." start="0" size="1" access="Read/Write" />
+      <BitField name="TXIS" description="Transmit interrupt status (transmitters) This bit is set by hardware when the I2C_TXDR register is empty and the data to be transmitted must be written in the I2C_TXDR register. It is cleared when the next data to be sent is written in the I2C_TXDR register. This bit can be written to 1 by software when NOSTRETCH=1 only, in order to generate a TXIS event (interrupt if TXIE=1 or DMA request if TXDMAEN=1). Note: This bit is cleared by hardware when PE=0." start="1" size="1" access="Read/Write" />
+      <BitField name="RXNE" description="Receive data register not empty (receivers) This bit is set by hardware when the received data is copied into the I2C_RXDR register, and is ready to be read. It is cleared when I2C_RXDR is read. Note: This bit is cleared by hardware when PE=0." start="2" size="1" access="ReadOnly" />
+      <BitField name="ADDR" description="Address matched (slave mode) This bit is set by hardware as soon as the received slave address matched with one of the enabled slave addresses. It is cleared by software by setting ADDRCF bit. Note: This bit is cleared by hardware when PE=0." start="3" size="1" access="ReadOnly" />
+      <BitField name="NACKF" description="Not Acknowledge received flag This flag is set by hardware when a NACK is received after a byte transmission. It is cleared by software by setting the NACKCF bit. Note: This bit is cleared by hardware when PE=0." start="4" size="1" access="ReadOnly" />
+      <BitField name="STOPF" description="Stop detection flag This flag is set by hardware when a Stop condition is detected on the bus and the peripheral is involved in this transfer: either as a master, provided that the STOP condition is generated by the peripheral. or as a slave, provided that the peripheral has been addressed previously during this transfer. It is cleared by software by setting the STOPCF bit. Note: This bit is cleared by hardware when PE=0." start="5" size="1" access="ReadOnly" />
+      <BitField name="TC" description="Transfer Complete (master mode) This flag is set by hardware when RELOAD=0, AUTOEND=0 and NBYTES data have been transferred. It is cleared by software when START bit or STOP bit is set. Note: This bit is cleared by hardware when PE=0." start="6" size="1" access="ReadOnly" />
+      <BitField name="TCR" description="Transfer Complete Reload This flag is set by hardware when RELOAD=1 and NBYTES data have been transferred. It is cleared by software when NBYTES is written to a non-zero value. Note: This bit is cleared by hardware when PE=0. This flag is only for master mode, or for slave mode when the SBC bit is set." start="7" size="1" access="ReadOnly" />
+      <BitField name="BERR" description="Bus error This flag is set by hardware when a misplaced Start or Stop condition is detected whereas the peripheral is involved in the transfer. The flag is not set during the address phase in slave mode. It is cleared by software by setting BERRCF bit. Note: This bit is cleared by hardware when PE=0." start="8" size="1" access="ReadOnly" />
+      <BitField name="ARLO" description="Arbitration lost This flag is set by hardware in case of arbitration loss. It is cleared by software by setting the ARLOCF bit. Note: This bit is cleared by hardware when PE=0." start="9" size="1" access="ReadOnly" />
+      <BitField name="OVR" description="Overrun/Underrun (slave mode) This flag is set by hardware in slave mode with NOSTRETCH=1, when an overrun/underrun error occurs. It is cleared by software by setting the OVRCF bit. Note: This bit is cleared by hardware when PE=0." start="10" size="1" access="ReadOnly" />
+      <BitField name="PECERR" description="PEC Error in reception This flag is set by hardware when the received PEC does not match with the PEC register content. A NACK is automatically sent after the wrong PEC reception. It is cleared by software by setting the PECCF bit. Note: This bit is cleared by hardware when PE=0. If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Please refer to Section25.3: I2C implementation." start="11" size="1" access="ReadOnly" />
+      <BitField name="TIMEOUT" description="Timeout or tLOW detection flag This flag is set by hardware when a timeout or extended clock timeout occurred. It is cleared by software by setting the TIMEOUTCF bit. Note: This bit is cleared by hardware when PE=0. If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Please refer to Section25.3: I2C implementation." start="12" size="1" access="ReadOnly" />
+      <BitField name="ALERT" description="SMBus alert This flag is set by hardware when SMBHEN=1 (SMBus host configuration), ALERTEN=1 and a SMBALERT event (falling edge) is detected on SMBA pin. It is cleared by software by setting the ALERTCF bit. Note: This bit is cleared by hardware when PE=0. If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Please refer to Section25.3: I2C implementation." start="13" size="1" access="ReadOnly" />
+      <BitField name="BUSY" description="Bus busy This flag indicates that a communication is in progress on the bus. It is set by hardware when a START condition is detected. It is cleared by hardware when a Stop condition is detected, or when PE=0." start="15" size="1" access="ReadOnly" />
+      <BitField name="DIR" description="Transfer direction (Slave mode) This flag is updated when an address match event occurs (ADDR=1)." start="16" size="1" access="ReadOnly" />
+      <BitField name="ADDCODE" description="Address match code (Slave mode) These bits are updated with the received address when an address match event occurs (ADDR = 1). In the case of a 10-bit address, ADDCODE provides the 10-bit header followed by the 2 MSBs of the address." start="17" size="7" access="ReadOnly" />
+    </Register>
+    <Register name="ICR" description="Access: No wait states" start="+0x1C" size="4" access="WriteOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ADDRCF" description="Address matched flag clear Writing 1 to this bit clears the ADDR flag in the I2C_ISR register. Writing 1 to this bit also clears the START bit in the I2C_CR2 register." start="3" size="1" />
+      <BitField name="NACKCF" description="Not Acknowledge flag clear Writing 1 to this bit clears the ACKF flag in I2C_ISR register." start="4" size="1" />
+      <BitField name="STOPCF" description="Stop detection flag clear Writing 1 to this bit clears the STOPF flag in the I2C_ISR register." start="5" size="1" />
+      <BitField name="BERRCF" description="Bus error flag clear Writing 1 to this bit clears the BERRF flag in the I2C_ISR register." start="8" size="1" />
+      <BitField name="ARLOCF" description="Arbitration Lost flag clear Writing 1 to this bit clears the ARLO flag in the I2C_ISR register." start="9" size="1" />
+      <BitField name="OVRCF" description="Overrun/Underrun flag clear Writing 1 to this bit clears the OVR flag in the I2C_ISR register." start="10" size="1" />
+      <BitField name="PECCF" description="PEC Error flag clear Writing 1 to this bit clears the PECERR flag in the I2C_ISR register. Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Please refer to Section25.3: I2C implementation." start="11" size="1" />
+      <BitField name="TIMOUTCF" description="Timeout detection flag clear Writing 1 to this bit clears the TIMEOUT flag in the I2C_ISR register. Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Please refer to Section25.3: I2C implementation." start="12" size="1" />
+      <BitField name="ALERTCF" description="Alert flag clear Writing 1 to this bit clears the ALERT flag in the I2C_ISR register. Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Please refer to Section25.3: I2C implementation." start="13" size="1" />
+    </Register>
+    <Register name="PECR" description="Access: No wait states" start="+0x20" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PEC" description="Packet error checking register This field contains the internal PEC when PECEN=1. The PEC is cleared by hardware when PE=0." start="0" size="8" />
+    </Register>
+    <Register name="RXDR" description="Access: No wait states" start="+0x24" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RXDATA" description="8-bit receive data Data byte received from the I2C bus." start="0" size="8" />
+    </Register>
+    <Register name="TXDR" description="Access: No wait states" start="+0x28" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TXDATA" description="8-bit transmit data Data byte to be transmitted to the I2C bus. Note: These bits can be written only when TXE=1." start="0" size="8" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="I2C4" description="I2C" start="0x58001C00">
+    <Register name="CR1" description="Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed. The latency of the second write access can be up to 2 x PCLK1 + 6 x I2CCLK." start="+0x0" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PE" description="Peripheral enable Note: When PE=0, the I2C SCL and SDA lines are released. Internal state machines and status bits are put back to their reset value. When cleared, PE must be kept low for at least 3 APB clock cycles." start="0" size="1" />
+      <BitField name="TXIE" description="TX Interrupt enable" start="1" size="1" />
+      <BitField name="RXIE" description="RX Interrupt enable" start="2" size="1" />
+      <BitField name="ADDRIE" description="Address match Interrupt enable (slave only)" start="3" size="1" />
+      <BitField name="NACKIE" description="Not acknowledge received Interrupt enable" start="4" size="1" />
+      <BitField name="STOPIE" description="STOP detection Interrupt enable" start="5" size="1" />
+      <BitField name="TCIE" description="Transfer Complete interrupt enable Note: Any of these events will generate an interrupt: Transfer Complete (TC) Transfer Complete Reload (TCR)" start="6" size="1" />
+      <BitField name="ERRIE" description="Error interrupts enable Note: Any of these errors generate an interrupt: Arbitration Loss (ARLO) Bus Error detection (BERR) Overrun/Underrun (OVR) Timeout detection (TIMEOUT) PEC error detection (PECERR) Alert pin event detection (ALERT)" start="7" size="1" />
+      <BitField name="DNF" description="Digital noise filter These bits are used to configure the digital noise filter on SDA and SCL input. The digital filter will filter spikes with a length of up to DNF[3:0] * tI2CCLK ... Note: If the analog filter is also enabled, the digital filter is added to the analog filter. This filter can only be programmed when the I2C is disabled (PE = 0)." start="8" size="4" />
+      <BitField name="ANFOFF" description="Analog noise filter OFF Note: This bit can only be programmed when the I2C is disabled (PE = 0)." start="12" size="1" />
+      <BitField name="TXDMAEN" description="DMA transmission requests enable" start="14" size="1" />
+      <BitField name="RXDMAEN" description="DMA reception requests enable" start="15" size="1" />
+      <BitField name="SBC" description="Slave byte control This bit is used to enable hardware byte control in slave mode." start="16" size="1" />
+      <BitField name="NOSTRETCH" description="Clock stretching disable This bit is used to disable clock stretching in slave mode. It must be kept cleared in master mode. Note: This bit can only be programmed when the I2C is disabled (PE = 0)." start="17" size="1" />
+      <BitField name="WUPEN" description="Wakeup from Stop mode enable Note: If the Wakeup from Stop mode feature is not supported, this bit is reserved and forced by hardware to 0. Please refer to Section25.3: I2C implementation. Note: WUPEN can be set only when DNF = 0000" start="18" size="1" />
+      <BitField name="GCEN" description="General call enable" start="19" size="1" />
+      <BitField name="SMBHEN" description="SMBus Host address enable Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Please refer to Section25.3: I2C implementation." start="20" size="1" />
+      <BitField name="SMBDEN" description="SMBus Device Default address enable Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Please refer to Section25.3: I2C implementation." start="21" size="1" />
+      <BitField name="ALERTEN" description="SMBus alert enable Device mode (SMBHEN=0): Host mode (SMBHEN=1): Note: When ALERTEN=0, the SMBA pin can be used as a standard GPIO. If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Please refer to Section25.3: I2C implementation." start="22" size="1" />
+      <BitField name="PECEN" description="PEC enable Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Please refer to Section25.3: I2C implementation." start="23" size="1" />
+    </Register>
+    <Register name="CR2" description="Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed. The latency of the second write access can be up to 2 x PCLK1 + 6 x I2CCLK." start="+0x4" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SADD0" description="Slave address bit 0 (master mode) In 7-bit addressing mode (ADD10 = 0): This bit is dont care In 10-bit addressing mode (ADD10 = 1): This bit should be written with bit 0 of the slave address to be sent Note: Changing these bits when the START bit is set is not allowed." start="0" size="1" />
+      <BitField name="SADD1" description="Slave address bit 7:1 (master mode) In 7-bit addressing mode (ADD10 = 0): These bits should be written with the 7-bit slave address to be sent In 10-bit addressing mode (ADD10 = 1): These bits should be written with bits 7:1 of the slave address to be sent. Note: Changing these bits when the START bit is set is not allowed." start="1" size="1" />
+      <BitField name="SADD2" description="Slave address bit 7:1 (master mode) In 7-bit addressing mode (ADD10 = 0): These bits should be written with the 7-bit slave address to be sent In 10-bit addressing mode (ADD10 = 1): These bits should be written with bits 7:1 of the slave address to be sent. Note: Changing these bits when the START bit is set is not allowed." start="2" size="1" />
+      <BitField name="SADD3" description="Slave address bit 7:1 (master mode) In 7-bit addressing mode (ADD10 = 0): These bits should be written with the 7-bit slave address to be sent In 10-bit addressing mode (ADD10 = 1): These bits should be written with bits 7:1 of the slave address to be sent. Note: Changing these bits when the START bit is set is not allowed." start="3" size="1" />
+      <BitField name="SADD4" description="Slave address bit 7:1 (master mode) In 7-bit addressing mode (ADD10 = 0): These bits should be written with the 7-bit slave address to be sent In 10-bit addressing mode (ADD10 = 1): These bits should be written with bits 7:1 of the slave address to be sent. Note: Changing these bits when the START bit is set is not allowed." start="4" size="1" />
+      <BitField name="SADD5" description="Slave address bit 7:1 (master mode) In 7-bit addressing mode (ADD10 = 0): These bits should be written with the 7-bit slave address to be sent In 10-bit addressing mode (ADD10 = 1): These bits should be written with bits 7:1 of the slave address to be sent. Note: Changing these bits when the START bit is set is not allowed." start="5" size="1" />
+      <BitField name="SADD6" description="Slave address bit 7:1 (master mode) In 7-bit addressing mode (ADD10 = 0): These bits should be written with the 7-bit slave address to be sent In 10-bit addressing mode (ADD10 = 1): These bits should be written with bits 7:1 of the slave address to be sent. Note: Changing these bits when the START bit is set is not allowed." start="6" size="1" />
+      <BitField name="SADD7" description="Slave address bit 7:1 (master mode) In 7-bit addressing mode (ADD10 = 0): These bits should be written with the 7-bit slave address to be sent In 10-bit addressing mode (ADD10 = 1): These bits should be written with bits 7:1 of the slave address to be sent. Note: Changing these bits when the START bit is set is not allowed." start="7" size="1" />
+      <BitField name="SADD8" description="Slave address bit 9:8 (master mode) In 7-bit addressing mode (ADD10 = 0): These bits are dont care In 10-bit addressing mode (ADD10 = 1): These bits should be written with bits 9:8 of the slave address to be sent Note: Changing these bits when the START bit is set is not allowed." start="8" size="1" />
+      <BitField name="SADD9" description="Slave address bit 9:8 (master mode) In 7-bit addressing mode (ADD10 = 0): These bits are dont care In 10-bit addressing mode (ADD10 = 1): These bits should be written with bits 9:8 of the slave address to be sent Note: Changing these bits when the START bit is set is not allowed." start="9" size="1" />
+      <BitField name="RD_WRN" description="Transfer direction (master mode) Note: Changing this bit when the START bit is set is not allowed." start="10" size="1" />
+      <BitField name="ADD10" description="10-bit addressing mode (master mode) Note: Changing this bit when the START bit is set is not allowed." start="11" size="1" />
+      <BitField name="HEAD10R" description="10-bit address header only read direction (master receiver mode) Note: Changing this bit when the START bit is set is not allowed." start="12" size="1" />
+      <BitField name="START" description="Start generation This bit is set by software, and cleared by hardware after the Start followed by the address sequence is sent, by an arbitration loss, by a timeout error detection, or when PE = 0. It can also be cleared by software by writing 1 to the ADDRCF bit in the I2C_ICR register. If the I2C is already in master mode with AUTOEND = 0, setting this bit generates a Repeated Start condition when RELOAD=0, after the end of the NBYTES transfer. Otherwise setting this bit will generate a START condition once the bus is free. Note: Writing 0 to this bit has no effect. The START bit can be set even if the bus is BUSY or I2C is in slave mode. This bit has no effect when RELOAD is set." start="13" size="1" />
+      <BitField name="STOP" description="Stop generation (master mode) The bit is set by software, cleared by hardware when a Stop condition is detected, or when PE = 0. In Master Mode: Note: Writing 0 to this bit has no effect." start="14" size="1" />
+      <BitField name="NACK" description="NACK generation (slave mode) The bit is set by software, cleared by hardware when the NACK is sent, or when a STOP condition or an Address matched is received, or when PE=0. Note: Writing 0 to this bit has no effect. This bit is used in slave mode only: in master receiver mode, NACK is automatically generated after last byte preceding STOP or RESTART condition, whatever the NACK bit value. When an overrun occurs in slave receiver NOSTRETCH mode, a NACK is automatically generated whatever the NACK bit value. When hardware PEC checking is enabled (PECBYTE=1), the PEC acknowledge value does not depend on the NACK value." start="15" size="1" />
+      <BitField name="NBYTES" description="Number of bytes The number of bytes to be transmitted/received is programmed there. This field is dont care in slave mode with SBC=0. Note: Changing these bits when the START bit is set is not allowed." start="16" size="8" />
+      <BitField name="RELOAD" description="NBYTES reload mode This bit is set and cleared by software." start="24" size="1" />
+      <BitField name="AUTOEND" description="Automatic end mode (master mode) This bit is set and cleared by software. Note: This bit has no effect in slave mode or when the RELOAD bit is set." start="25" size="1" />
+      <BitField name="PECBYTE" description="Packet error checking byte This bit is set by software, and cleared by hardware when the PEC is transferred, or when a STOP condition or an Address matched is received, also when PE=0. Note: Writing 0 to this bit has no effect. This bit has no effect when RELOAD is set. This bit has no effect is slave mode when SBC=0. If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Please refer to Section25.3: I2C implementation." start="26" size="1" />
+    </Register>
+    <Register name="OAR1" description="Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed. The latency of the second write access can be up to 2 x PCLK1 + 6 x I2CCLK." start="+0x8" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OA1" description="Interface address 7-bit addressing mode: dont care 10-bit addressing mode: bits 9:8 of address Note: These bits can be written only when OA1EN=0. OA1[7:1]: Interface address Bits 7:1 of address Note: These bits can be written only when OA1EN=0. OA1[0]: Interface address 7-bit addressing mode: dont care 10-bit addressing mode: bit 0 of address Note: This bit can be written only when OA1EN=0." start="0" size="10" />
+      <BitField name="OA1MODE" description="Own Address 1 10-bit mode Note: This bit can be written only when OA1EN=0." start="10" size="1" />
+      <BitField name="OA1EN" description="Own Address 1 enable" start="15" size="1" />
+    </Register>
+    <Register name="OAR2" description="Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed. The latency of the second write access can be up to 2 x PCLK1 + 6 x I2CCLK." start="+0xC" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OA2" description="Interface address bits 7:1 of address Note: These bits can be written only when OA2EN=0." start="1" size="7" />
+      <BitField name="OA2MSK" description="Own Address 2 masks Note: These bits can be written only when OA2EN=0. As soon as OA2MSK is not equal to 0, the reserved I2C addresses (0b0000xxx and 0b1111xxx) are not acknowledged even if the comparison matches." start="8" size="3" />
+      <BitField name="OA2EN" description="Own Address 2 enable" start="15" size="1" />
+    </Register>
+    <Register name="TIMINGR" description="Access: No wait states" start="+0x10" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SCLL" description="SCL low period (master mode) This field is used to generate the SCL low period in master mode. tSCLL = (SCLL+1) x tPRESC Note: SCLL is also used to generate tBUF and tSU:STA timings." start="0" size="8" />
+      <BitField name="SCLH" description="SCL high period (master mode) This field is used to generate the SCL high period in master mode. tSCLH = (SCLH+1) x tPRESC Note: SCLH is also used to generate tSU:STO and tHD:STA timing." start="8" size="8" />
+      <BitField name="SDADEL" description="Data hold time This field is used to generate the delay tSDADEL between SCL falling edge and SDA edge. In master mode and in slave mode with NOSTRETCH = 0, the SCL line is stretched low during tSDADEL. tSDADEL= SDADEL x tPRESC Note: SDADEL is used to generate tHD:DAT timing." start="16" size="4" />
+      <BitField name="SCLDEL" description="Data setup time This field is used to generate a delay tSCLDEL between SDA edge and SCL rising edge. In master mode and in slave mode with NOSTRETCH = 0, the SCL line is stretched low during tSCLDEL. tSCLDEL = (SCLDEL+1) x tPRESC Note: tSCLDEL is used to generate tSU:DAT timing." start="20" size="4" />
+      <BitField name="PRESC" description="Timing prescaler This field is used to prescale I2CCLK in order to generate the clock period tPRESC used for data setup and hold counters (refer to I2C timings on page9) and for SCL high and low level counters (refer to I2C master initialization on page24). tPRESC = (PRESC+1) x tI2CCLK" start="28" size="4" />
+    </Register>
+    <Register name="TIMEOUTR" description="Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed. The latency of the second write access can be up to 2 x PCLK1 + 6 x I2CCLK." start="+0x14" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TIMEOUTA" description="Bus Timeout A This field is used to configure: The SCL low timeout condition tTIMEOUT when TIDLE=0 tTIMEOUT= (TIMEOUTA+1) x 2048 x tI2CCLK The bus idle condition (both SCL and SDA high) when TIDLE=1 tIDLE= (TIMEOUTA+1) x 4 x tI2CCLK Note: These bits can be written only when TIMOUTEN=0." start="0" size="12" />
+      <BitField name="TIDLE" description="Idle clock timeout detection Note: This bit can be written only when TIMOUTEN=0." start="12" size="1" />
+      <BitField name="TIMOUTEN" description="Clock timeout enable" start="15" size="1" />
+      <BitField name="TIMEOUTB" description="Bus timeout B This field is used to configure the cumulative clock extension timeout: In master mode, the master cumulative clock low extend time (tLOW:MEXT) is detected In slave mode, the slave cumulative clock low extend time (tLOW:SEXT) is detected tLOW:EXT= (TIMEOUTB+1) x 2048 x tI2CCLK Note: These bits can be written only when TEXTEN=0." start="16" size="12" />
+      <BitField name="TEXTEN" description="Extended clock timeout enable" start="31" size="1" />
+    </Register>
+    <Register name="ISR" description="Access: No wait states" start="+0x18" size="4" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField name="TXE" description="Transmit data register empty (transmitters) This bit is set by hardware when the I2C_TXDR register is empty. It is cleared when the next data to be sent is written in the I2C_TXDR register. This bit can be written to 1 by software in order to flush the transmit data register I2C_TXDR. Note: This bit is set by hardware when PE=0." start="0" size="1" access="Read/Write" />
+      <BitField name="TXIS" description="Transmit interrupt status (transmitters) This bit is set by hardware when the I2C_TXDR register is empty and the data to be transmitted must be written in the I2C_TXDR register. It is cleared when the next data to be sent is written in the I2C_TXDR register. This bit can be written to 1 by software when NOSTRETCH=1 only, in order to generate a TXIS event (interrupt if TXIE=1 or DMA request if TXDMAEN=1). Note: This bit is cleared by hardware when PE=0." start="1" size="1" access="Read/Write" />
+      <BitField name="RXNE" description="Receive data register not empty (receivers) This bit is set by hardware when the received data is copied into the I2C_RXDR register, and is ready to be read. It is cleared when I2C_RXDR is read. Note: This bit is cleared by hardware when PE=0." start="2" size="1" access="ReadOnly" />
+      <BitField name="ADDR" description="Address matched (slave mode) This bit is set by hardware as soon as the received slave address matched with one of the enabled slave addresses. It is cleared by software by setting ADDRCF bit. Note: This bit is cleared by hardware when PE=0." start="3" size="1" access="ReadOnly" />
+      <BitField name="NACKF" description="Not Acknowledge received flag This flag is set by hardware when a NACK is received after a byte transmission. It is cleared by software by setting the NACKCF bit. Note: This bit is cleared by hardware when PE=0." start="4" size="1" access="ReadOnly" />
+      <BitField name="STOPF" description="Stop detection flag This flag is set by hardware when a Stop condition is detected on the bus and the peripheral is involved in this transfer: either as a master, provided that the STOP condition is generated by the peripheral. or as a slave, provided that the peripheral has been addressed previously during this transfer. It is cleared by software by setting the STOPCF bit. Note: This bit is cleared by hardware when PE=0." start="5" size="1" access="ReadOnly" />
+      <BitField name="TC" description="Transfer Complete (master mode) This flag is set by hardware when RELOAD=0, AUTOEND=0 and NBYTES data have been transferred. It is cleared by software when START bit or STOP bit is set. Note: This bit is cleared by hardware when PE=0." start="6" size="1" access="ReadOnly" />
+      <BitField name="TCR" description="Transfer Complete Reload This flag is set by hardware when RELOAD=1 and NBYTES data have been transferred. It is cleared by software when NBYTES is written to a non-zero value. Note: This bit is cleared by hardware when PE=0. This flag is only for master mode, or for slave mode when the SBC bit is set." start="7" size="1" access="ReadOnly" />
+      <BitField name="BERR" description="Bus error This flag is set by hardware when a misplaced Start or Stop condition is detected whereas the peripheral is involved in the transfer. The flag is not set during the address phase in slave mode. It is cleared by software by setting BERRCF bit. Note: This bit is cleared by hardware when PE=0." start="8" size="1" access="ReadOnly" />
+      <BitField name="ARLO" description="Arbitration lost This flag is set by hardware in case of arbitration loss. It is cleared by software by setting the ARLOCF bit. Note: This bit is cleared by hardware when PE=0." start="9" size="1" access="ReadOnly" />
+      <BitField name="OVR" description="Overrun/Underrun (slave mode) This flag is set by hardware in slave mode with NOSTRETCH=1, when an overrun/underrun error occurs. It is cleared by software by setting the OVRCF bit. Note: This bit is cleared by hardware when PE=0." start="10" size="1" access="ReadOnly" />
+      <BitField name="PECERR" description="PEC Error in reception This flag is set by hardware when the received PEC does not match with the PEC register content. A NACK is automatically sent after the wrong PEC reception. It is cleared by software by setting the PECCF bit. Note: This bit is cleared by hardware when PE=0. If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Please refer to Section25.3: I2C implementation." start="11" size="1" access="ReadOnly" />
+      <BitField name="TIMEOUT" description="Timeout or tLOW detection flag This flag is set by hardware when a timeout or extended clock timeout occurred. It is cleared by software by setting the TIMEOUTCF bit. Note: This bit is cleared by hardware when PE=0. If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Please refer to Section25.3: I2C implementation." start="12" size="1" access="ReadOnly" />
+      <BitField name="ALERT" description="SMBus alert This flag is set by hardware when SMBHEN=1 (SMBus host configuration), ALERTEN=1 and a SMBALERT event (falling edge) is detected on SMBA pin. It is cleared by software by setting the ALERTCF bit. Note: This bit is cleared by hardware when PE=0. If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Please refer to Section25.3: I2C implementation." start="13" size="1" access="ReadOnly" />
+      <BitField name="BUSY" description="Bus busy This flag indicates that a communication is in progress on the bus. It is set by hardware when a START condition is detected. It is cleared by hardware when a Stop condition is detected, or when PE=0." start="15" size="1" access="ReadOnly" />
+      <BitField name="DIR" description="Transfer direction (Slave mode) This flag is updated when an address match event occurs (ADDR=1)." start="16" size="1" access="ReadOnly" />
+      <BitField name="ADDCODE" description="Address match code (Slave mode) These bits are updated with the received address when an address match event occurs (ADDR = 1). In the case of a 10-bit address, ADDCODE provides the 10-bit header followed by the 2 MSBs of the address." start="17" size="7" access="ReadOnly" />
+    </Register>
+    <Register name="ICR" description="Access: No wait states" start="+0x1C" size="4" access="WriteOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ADDRCF" description="Address matched flag clear Writing 1 to this bit clears the ADDR flag in the I2C_ISR register. Writing 1 to this bit also clears the START bit in the I2C_CR2 register." start="3" size="1" />
+      <BitField name="NACKCF" description="Not Acknowledge flag clear Writing 1 to this bit clears the ACKF flag in I2C_ISR register." start="4" size="1" />
+      <BitField name="STOPCF" description="Stop detection flag clear Writing 1 to this bit clears the STOPF flag in the I2C_ISR register." start="5" size="1" />
+      <BitField name="BERRCF" description="Bus error flag clear Writing 1 to this bit clears the BERRF flag in the I2C_ISR register." start="8" size="1" />
+      <BitField name="ARLOCF" description="Arbitration Lost flag clear Writing 1 to this bit clears the ARLO flag in the I2C_ISR register." start="9" size="1" />
+      <BitField name="OVRCF" description="Overrun/Underrun flag clear Writing 1 to this bit clears the OVR flag in the I2C_ISR register." start="10" size="1" />
+      <BitField name="PECCF" description="PEC Error flag clear Writing 1 to this bit clears the PECERR flag in the I2C_ISR register. Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Please refer to Section25.3: I2C implementation." start="11" size="1" />
+      <BitField name="TIMOUTCF" description="Timeout detection flag clear Writing 1 to this bit clears the TIMEOUT flag in the I2C_ISR register. Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Please refer to Section25.3: I2C implementation." start="12" size="1" />
+      <BitField name="ALERTCF" description="Alert flag clear Writing 1 to this bit clears the ALERT flag in the I2C_ISR register. Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Please refer to Section25.3: I2C implementation." start="13" size="1" />
+    </Register>
+    <Register name="PECR" description="Access: No wait states" start="+0x20" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PEC" description="Packet error checking register This field contains the internal PEC when PECEN=1. The PEC is cleared by hardware when PE=0." start="0" size="8" />
+    </Register>
+    <Register name="RXDR" description="Access: No wait states" start="+0x24" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RXDATA" description="8-bit receive data Data byte received from the I2C bus." start="0" size="8" />
+    </Register>
+    <Register name="TXDR" description="Access: No wait states" start="+0x28" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TXDATA" description="8-bit transmit data Data byte to be transmitted to the I2C bus. Note: These bits can be written only when TXE=1." start="0" size="8" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="I2C5" description="I2C" start="0x40006400">
+    <Register name="CR1" description="Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed. The latency of the second write access can be up to 2 x PCLK1 + 6 x I2CCLK." start="+0x0" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PE" description="Peripheral enable Note: When PE=0, the I2C SCL and SDA lines are released. Internal state machines and status bits are put back to their reset value. When cleared, PE must be kept low for at least 3 APB clock cycles." start="0" size="1" />
+      <BitField name="TXIE" description="TX Interrupt enable" start="1" size="1" />
+      <BitField name="RXIE" description="RX Interrupt enable" start="2" size="1" />
+      <BitField name="ADDRIE" description="Address match Interrupt enable (slave only)" start="3" size="1" />
+      <BitField name="NACKIE" description="Not acknowledge received Interrupt enable" start="4" size="1" />
+      <BitField name="STOPIE" description="STOP detection Interrupt enable" start="5" size="1" />
+      <BitField name="TCIE" description="Transfer Complete interrupt enable Note: Any of these events will generate an interrupt: Transfer Complete (TC) Transfer Complete Reload (TCR)" start="6" size="1" />
+      <BitField name="ERRIE" description="Error interrupts enable Note: Any of these errors generate an interrupt: Arbitration Loss (ARLO) Bus Error detection (BERR) Overrun/Underrun (OVR) Timeout detection (TIMEOUT) PEC error detection (PECERR) Alert pin event detection (ALERT)" start="7" size="1" />
+      <BitField name="DNF" description="Digital noise filter These bits are used to configure the digital noise filter on SDA and SCL input. The digital filter will filter spikes with a length of up to DNF[3:0] * tI2CCLK ... Note: If the analog filter is also enabled, the digital filter is added to the analog filter. This filter can only be programmed when the I2C is disabled (PE = 0)." start="8" size="4" />
+      <BitField name="ANFOFF" description="Analog noise filter OFF Note: This bit can only be programmed when the I2C is disabled (PE = 0)." start="12" size="1" />
+      <BitField name="TXDMAEN" description="DMA transmission requests enable" start="14" size="1" />
+      <BitField name="RXDMAEN" description="DMA reception requests enable" start="15" size="1" />
+      <BitField name="SBC" description="Slave byte control This bit is used to enable hardware byte control in slave mode." start="16" size="1" />
+      <BitField name="NOSTRETCH" description="Clock stretching disable This bit is used to disable clock stretching in slave mode. It must be kept cleared in master mode. Note: This bit can only be programmed when the I2C is disabled (PE = 0)." start="17" size="1" />
+      <BitField name="WUPEN" description="Wakeup from Stop mode enable Note: If the Wakeup from Stop mode feature is not supported, this bit is reserved and forced by hardware to 0. Please refer to Section25.3: I2C implementation. Note: WUPEN can be set only when DNF = 0000" start="18" size="1" />
+      <BitField name="GCEN" description="General call enable" start="19" size="1" />
+      <BitField name="SMBHEN" description="SMBus Host address enable Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Please refer to Section25.3: I2C implementation." start="20" size="1" />
+      <BitField name="SMBDEN" description="SMBus Device Default address enable Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Please refer to Section25.3: I2C implementation." start="21" size="1" />
+      <BitField name="ALERTEN" description="SMBus alert enable Device mode (SMBHEN=0): Host mode (SMBHEN=1): Note: When ALERTEN=0, the SMBA pin can be used as a standard GPIO. If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Please refer to Section25.3: I2C implementation." start="22" size="1" />
+      <BitField name="PECEN" description="PEC enable Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Please refer to Section25.3: I2C implementation." start="23" size="1" />
+    </Register>
+    <Register name="CR2" description="Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed. The latency of the second write access can be up to 2 x PCLK1 + 6 x I2CCLK." start="+0x4" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SADD0" description="Slave address bit 0 (master mode) In 7-bit addressing mode (ADD10 = 0): This bit is dont care In 10-bit addressing mode (ADD10 = 1): This bit should be written with bit 0 of the slave address to be sent Note: Changing these bits when the START bit is set is not allowed." start="0" size="1" />
+      <BitField name="SADD1" description="Slave address bit 7:1 (master mode) In 7-bit addressing mode (ADD10 = 0): These bits should be written with the 7-bit slave address to be sent In 10-bit addressing mode (ADD10 = 1): These bits should be written with bits 7:1 of the slave address to be sent. Note: Changing these bits when the START bit is set is not allowed." start="1" size="1" />
+      <BitField name="SADD2" description="Slave address bit 7:1 (master mode) In 7-bit addressing mode (ADD10 = 0): These bits should be written with the 7-bit slave address to be sent In 10-bit addressing mode (ADD10 = 1): These bits should be written with bits 7:1 of the slave address to be sent. Note: Changing these bits when the START bit is set is not allowed." start="2" size="1" />
+      <BitField name="SADD3" description="Slave address bit 7:1 (master mode) In 7-bit addressing mode (ADD10 = 0): These bits should be written with the 7-bit slave address to be sent In 10-bit addressing mode (ADD10 = 1): These bits should be written with bits 7:1 of the slave address to be sent. Note: Changing these bits when the START bit is set is not allowed." start="3" size="1" />
+      <BitField name="SADD4" description="Slave address bit 7:1 (master mode) In 7-bit addressing mode (ADD10 = 0): These bits should be written with the 7-bit slave address to be sent In 10-bit addressing mode (ADD10 = 1): These bits should be written with bits 7:1 of the slave address to be sent. Note: Changing these bits when the START bit is set is not allowed." start="4" size="1" />
+      <BitField name="SADD5" description="Slave address bit 7:1 (master mode) In 7-bit addressing mode (ADD10 = 0): These bits should be written with the 7-bit slave address to be sent In 10-bit addressing mode (ADD10 = 1): These bits should be written with bits 7:1 of the slave address to be sent. Note: Changing these bits when the START bit is set is not allowed." start="5" size="1" />
+      <BitField name="SADD6" description="Slave address bit 7:1 (master mode) In 7-bit addressing mode (ADD10 = 0): These bits should be written with the 7-bit slave address to be sent In 10-bit addressing mode (ADD10 = 1): These bits should be written with bits 7:1 of the slave address to be sent. Note: Changing these bits when the START bit is set is not allowed." start="6" size="1" />
+      <BitField name="SADD7" description="Slave address bit 7:1 (master mode) In 7-bit addressing mode (ADD10 = 0): These bits should be written with the 7-bit slave address to be sent In 10-bit addressing mode (ADD10 = 1): These bits should be written with bits 7:1 of the slave address to be sent. Note: Changing these bits when the START bit is set is not allowed." start="7" size="1" />
+      <BitField name="SADD8" description="Slave address bit 9:8 (master mode) In 7-bit addressing mode (ADD10 = 0): These bits are dont care In 10-bit addressing mode (ADD10 = 1): These bits should be written with bits 9:8 of the slave address to be sent Note: Changing these bits when the START bit is set is not allowed." start="8" size="1" />
+      <BitField name="SADD9" description="Slave address bit 9:8 (master mode) In 7-bit addressing mode (ADD10 = 0): These bits are dont care In 10-bit addressing mode (ADD10 = 1): These bits should be written with bits 9:8 of the slave address to be sent Note: Changing these bits when the START bit is set is not allowed." start="9" size="1" />
+      <BitField name="RD_WRN" description="Transfer direction (master mode) Note: Changing this bit when the START bit is set is not allowed." start="10" size="1" />
+      <BitField name="ADD10" description="10-bit addressing mode (master mode) Note: Changing this bit when the START bit is set is not allowed." start="11" size="1" />
+      <BitField name="HEAD10R" description="10-bit address header only read direction (master receiver mode) Note: Changing this bit when the START bit is set is not allowed." start="12" size="1" />
+      <BitField name="START" description="Start generation This bit is set by software, and cleared by hardware after the Start followed by the address sequence is sent, by an arbitration loss, by a timeout error detection, or when PE = 0. It can also be cleared by software by writing 1 to the ADDRCF bit in the I2C_ICR register. If the I2C is already in master mode with AUTOEND = 0, setting this bit generates a Repeated Start condition when RELOAD=0, after the end of the NBYTES transfer. Otherwise setting this bit will generate a START condition once the bus is free. Note: Writing 0 to this bit has no effect. The START bit can be set even if the bus is BUSY or I2C is in slave mode. This bit has no effect when RELOAD is set." start="13" size="1" />
+      <BitField name="STOP" description="Stop generation (master mode) The bit is set by software, cleared by hardware when a Stop condition is detected, or when PE = 0. In Master Mode: Note: Writing 0 to this bit has no effect." start="14" size="1" />
+      <BitField name="NACK" description="NACK generation (slave mode) The bit is set by software, cleared by hardware when the NACK is sent, or when a STOP condition or an Address matched is received, or when PE=0. Note: Writing 0 to this bit has no effect. This bit is used in slave mode only: in master receiver mode, NACK is automatically generated after last byte preceding STOP or RESTART condition, whatever the NACK bit value. When an overrun occurs in slave receiver NOSTRETCH mode, a NACK is automatically generated whatever the NACK bit value. When hardware PEC checking is enabled (PECBYTE=1), the PEC acknowledge value does not depend on the NACK value." start="15" size="1" />
+      <BitField name="NBYTES" description="Number of bytes The number of bytes to be transmitted/received is programmed there. This field is dont care in slave mode with SBC=0. Note: Changing these bits when the START bit is set is not allowed." start="16" size="8" />
+      <BitField name="RELOAD" description="NBYTES reload mode This bit is set and cleared by software." start="24" size="1" />
+      <BitField name="AUTOEND" description="Automatic end mode (master mode) This bit is set and cleared by software. Note: This bit has no effect in slave mode or when the RELOAD bit is set." start="25" size="1" />
+      <BitField name="PECBYTE" description="Packet error checking byte This bit is set by software, and cleared by hardware when the PEC is transferred, or when a STOP condition or an Address matched is received, also when PE=0. Note: Writing 0 to this bit has no effect. This bit has no effect when RELOAD is set. This bit has no effect is slave mode when SBC=0. If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Please refer to Section25.3: I2C implementation." start="26" size="1" />
+    </Register>
+    <Register name="OAR1" description="Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed. The latency of the second write access can be up to 2 x PCLK1 + 6 x I2CCLK." start="+0x8" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OA1" description="Interface address 7-bit addressing mode: dont care 10-bit addressing mode: bits 9:8 of address Note: These bits can be written only when OA1EN=0. OA1[7:1]: Interface address Bits 7:1 of address Note: These bits can be written only when OA1EN=0. OA1[0]: Interface address 7-bit addressing mode: dont care 10-bit addressing mode: bit 0 of address Note: This bit can be written only when OA1EN=0." start="0" size="10" />
+      <BitField name="OA1MODE" description="Own Address 1 10-bit mode Note: This bit can be written only when OA1EN=0." start="10" size="1" />
+      <BitField name="OA1EN" description="Own Address 1 enable" start="15" size="1" />
+    </Register>
+    <Register name="OAR2" description="Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed. The latency of the second write access can be up to 2 x PCLK1 + 6 x I2CCLK." start="+0xC" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OA2" description="Interface address bits 7:1 of address Note: These bits can be written only when OA2EN=0." start="1" size="7" />
+      <BitField name="OA2MSK" description="Own Address 2 masks Note: These bits can be written only when OA2EN=0. As soon as OA2MSK is not equal to 0, the reserved I2C addresses (0b0000xxx and 0b1111xxx) are not acknowledged even if the comparison matches." start="8" size="3" />
+      <BitField name="OA2EN" description="Own Address 2 enable" start="15" size="1" />
+    </Register>
+    <Register name="TIMINGR" description="Access: No wait states" start="+0x10" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SCLL" description="SCL low period (master mode) This field is used to generate the SCL low period in master mode. tSCLL = (SCLL+1) x tPRESC Note: SCLL is also used to generate tBUF and tSU:STA timings." start="0" size="8" />
+      <BitField name="SCLH" description="SCL high period (master mode) This field is used to generate the SCL high period in master mode. tSCLH = (SCLH+1) x tPRESC Note: SCLH is also used to generate tSU:STO and tHD:STA timing." start="8" size="8" />
+      <BitField name="SDADEL" description="Data hold time This field is used to generate the delay tSDADEL between SCL falling edge and SDA edge. In master mode and in slave mode with NOSTRETCH = 0, the SCL line is stretched low during tSDADEL. tSDADEL= SDADEL x tPRESC Note: SDADEL is used to generate tHD:DAT timing." start="16" size="4" />
+      <BitField name="SCLDEL" description="Data setup time This field is used to generate a delay tSCLDEL between SDA edge and SCL rising edge. In master mode and in slave mode with NOSTRETCH = 0, the SCL line is stretched low during tSCLDEL. tSCLDEL = (SCLDEL+1) x tPRESC Note: tSCLDEL is used to generate tSU:DAT timing." start="20" size="4" />
+      <BitField name="PRESC" description="Timing prescaler This field is used to prescale I2CCLK in order to generate the clock period tPRESC used for data setup and hold counters (refer to I2C timings on page9) and for SCL high and low level counters (refer to I2C master initialization on page24). tPRESC = (PRESC+1) x tI2CCLK" start="28" size="4" />
+    </Register>
+    <Register name="TIMEOUTR" description="Access: No wait states, except if a write access occurs while a write access to this register is ongoing. In this case, wait states are inserted in the second write access until the previous one is completed. The latency of the second write access can be up to 2 x PCLK1 + 6 x I2CCLK." start="+0x14" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TIMEOUTA" description="Bus Timeout A This field is used to configure: The SCL low timeout condition tTIMEOUT when TIDLE=0 tTIMEOUT= (TIMEOUTA+1) x 2048 x tI2CCLK The bus idle condition (both SCL and SDA high) when TIDLE=1 tIDLE= (TIMEOUTA+1) x 4 x tI2CCLK Note: These bits can be written only when TIMOUTEN=0." start="0" size="12" />
+      <BitField name="TIDLE" description="Idle clock timeout detection Note: This bit can be written only when TIMOUTEN=0." start="12" size="1" />
+      <BitField name="TIMOUTEN" description="Clock timeout enable" start="15" size="1" />
+      <BitField name="TIMEOUTB" description="Bus timeout B This field is used to configure the cumulative clock extension timeout: In master mode, the master cumulative clock low extend time (tLOW:MEXT) is detected In slave mode, the slave cumulative clock low extend time (tLOW:SEXT) is detected tLOW:EXT= (TIMEOUTB+1) x 2048 x tI2CCLK Note: These bits can be written only when TEXTEN=0." start="16" size="12" />
+      <BitField name="TEXTEN" description="Extended clock timeout enable" start="31" size="1" />
+    </Register>
+    <Register name="ISR" description="Access: No wait states" start="+0x18" size="4" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField name="TXE" description="Transmit data register empty (transmitters) This bit is set by hardware when the I2C_TXDR register is empty. It is cleared when the next data to be sent is written in the I2C_TXDR register. This bit can be written to 1 by software in order to flush the transmit data register I2C_TXDR. Note: This bit is set by hardware when PE=0." start="0" size="1" access="Read/Write" />
+      <BitField name="TXIS" description="Transmit interrupt status (transmitters) This bit is set by hardware when the I2C_TXDR register is empty and the data to be transmitted must be written in the I2C_TXDR register. It is cleared when the next data to be sent is written in the I2C_TXDR register. This bit can be written to 1 by software when NOSTRETCH=1 only, in order to generate a TXIS event (interrupt if TXIE=1 or DMA request if TXDMAEN=1). Note: This bit is cleared by hardware when PE=0." start="1" size="1" access="Read/Write" />
+      <BitField name="RXNE" description="Receive data register not empty (receivers) This bit is set by hardware when the received data is copied into the I2C_RXDR register, and is ready to be read. It is cleared when I2C_RXDR is read. Note: This bit is cleared by hardware when PE=0." start="2" size="1" access="ReadOnly" />
+      <BitField name="ADDR" description="Address matched (slave mode) This bit is set by hardware as soon as the received slave address matched with one of the enabled slave addresses. It is cleared by software by setting ADDRCF bit. Note: This bit is cleared by hardware when PE=0." start="3" size="1" access="ReadOnly" />
+      <BitField name="NACKF" description="Not Acknowledge received flag This flag is set by hardware when a NACK is received after a byte transmission. It is cleared by software by setting the NACKCF bit. Note: This bit is cleared by hardware when PE=0." start="4" size="1" access="ReadOnly" />
+      <BitField name="STOPF" description="Stop detection flag This flag is set by hardware when a Stop condition is detected on the bus and the peripheral is involved in this transfer: either as a master, provided that the STOP condition is generated by the peripheral. or as a slave, provided that the peripheral has been addressed previously during this transfer. It is cleared by software by setting the STOPCF bit. Note: This bit is cleared by hardware when PE=0." start="5" size="1" access="ReadOnly" />
+      <BitField name="TC" description="Transfer Complete (master mode) This flag is set by hardware when RELOAD=0, AUTOEND=0 and NBYTES data have been transferred. It is cleared by software when START bit or STOP bit is set. Note: This bit is cleared by hardware when PE=0." start="6" size="1" access="ReadOnly" />
+      <BitField name="TCR" description="Transfer Complete Reload This flag is set by hardware when RELOAD=1 and NBYTES data have been transferred. It is cleared by software when NBYTES is written to a non-zero value. Note: This bit is cleared by hardware when PE=0. This flag is only for master mode, or for slave mode when the SBC bit is set." start="7" size="1" access="ReadOnly" />
+      <BitField name="BERR" description="Bus error This flag is set by hardware when a misplaced Start or Stop condition is detected whereas the peripheral is involved in the transfer. The flag is not set during the address phase in slave mode. It is cleared by software by setting BERRCF bit. Note: This bit is cleared by hardware when PE=0." start="8" size="1" access="ReadOnly" />
+      <BitField name="ARLO" description="Arbitration lost This flag is set by hardware in case of arbitration loss. It is cleared by software by setting the ARLOCF bit. Note: This bit is cleared by hardware when PE=0." start="9" size="1" access="ReadOnly" />
+      <BitField name="OVR" description="Overrun/Underrun (slave mode) This flag is set by hardware in slave mode with NOSTRETCH=1, when an overrun/underrun error occurs. It is cleared by software by setting the OVRCF bit. Note: This bit is cleared by hardware when PE=0." start="10" size="1" access="ReadOnly" />
+      <BitField name="PECERR" description="PEC Error in reception This flag is set by hardware when the received PEC does not match with the PEC register content. A NACK is automatically sent after the wrong PEC reception. It is cleared by software by setting the PECCF bit. Note: This bit is cleared by hardware when PE=0. If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Please refer to Section25.3: I2C implementation." start="11" size="1" access="ReadOnly" />
+      <BitField name="TIMEOUT" description="Timeout or tLOW detection flag This flag is set by hardware when a timeout or extended clock timeout occurred. It is cleared by software by setting the TIMEOUTCF bit. Note: This bit is cleared by hardware when PE=0. If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Please refer to Section25.3: I2C implementation." start="12" size="1" access="ReadOnly" />
+      <BitField name="ALERT" description="SMBus alert This flag is set by hardware when SMBHEN=1 (SMBus host configuration), ALERTEN=1 and a SMBALERT event (falling edge) is detected on SMBA pin. It is cleared by software by setting the ALERTCF bit. Note: This bit is cleared by hardware when PE=0. If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Please refer to Section25.3: I2C implementation." start="13" size="1" access="ReadOnly" />
+      <BitField name="BUSY" description="Bus busy This flag indicates that a communication is in progress on the bus. It is set by hardware when a START condition is detected. It is cleared by hardware when a Stop condition is detected, or when PE=0." start="15" size="1" access="ReadOnly" />
+      <BitField name="DIR" description="Transfer direction (Slave mode) This flag is updated when an address match event occurs (ADDR=1)." start="16" size="1" access="ReadOnly" />
+      <BitField name="ADDCODE" description="Address match code (Slave mode) These bits are updated with the received address when an address match event occurs (ADDR = 1). In the case of a 10-bit address, ADDCODE provides the 10-bit header followed by the 2 MSBs of the address." start="17" size="7" access="ReadOnly" />
+    </Register>
+    <Register name="ICR" description="Access: No wait states" start="+0x1C" size="4" access="WriteOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ADDRCF" description="Address matched flag clear Writing 1 to this bit clears the ADDR flag in the I2C_ISR register. Writing 1 to this bit also clears the START bit in the I2C_CR2 register." start="3" size="1" />
+      <BitField name="NACKCF" description="Not Acknowledge flag clear Writing 1 to this bit clears the ACKF flag in I2C_ISR register." start="4" size="1" />
+      <BitField name="STOPCF" description="Stop detection flag clear Writing 1 to this bit clears the STOPF flag in the I2C_ISR register." start="5" size="1" />
+      <BitField name="BERRCF" description="Bus error flag clear Writing 1 to this bit clears the BERRF flag in the I2C_ISR register." start="8" size="1" />
+      <BitField name="ARLOCF" description="Arbitration Lost flag clear Writing 1 to this bit clears the ARLO flag in the I2C_ISR register." start="9" size="1" />
+      <BitField name="OVRCF" description="Overrun/Underrun flag clear Writing 1 to this bit clears the OVR flag in the I2C_ISR register." start="10" size="1" />
+      <BitField name="PECCF" description="PEC Error flag clear Writing 1 to this bit clears the PECERR flag in the I2C_ISR register. Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Please refer to Section25.3: I2C implementation." start="11" size="1" />
+      <BitField name="TIMOUTCF" description="Timeout detection flag clear Writing 1 to this bit clears the TIMEOUT flag in the I2C_ISR register. Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Please refer to Section25.3: I2C implementation." start="12" size="1" />
+      <BitField name="ALERTCF" description="Alert flag clear Writing 1 to this bit clears the ALERT flag in the I2C_ISR register. Note: If the SMBus feature is not supported, this bit is reserved and forced by hardware to 0. Please refer to Section25.3: I2C implementation." start="13" size="1" />
+    </Register>
+    <Register name="PECR" description="Access: No wait states" start="+0x20" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PEC" description="Packet error checking register This field contains the internal PEC when PECEN=1. The PEC is cleared by hardware when PE=0." start="0" size="8" />
+    </Register>
+    <Register name="RXDR" description="Access: No wait states" start="+0x24" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RXDATA" description="8-bit receive data Data byte received from the I2C bus." start="0" size="8" />
+    </Register>
+    <Register name="TXDR" description="Access: No wait states" start="+0x28" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TXDATA" description="8-bit transmit data Data byte to be transmitted to the I2C bus. Note: These bits can be written only when TXE=1." start="0" size="8" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="IWDG1" description="IWDG" start="0x58004800">
+    <Register name="KR" description="Key register" start="+0x0" size="4" access="WriteOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="KEY" description="Key value (write only, read 0x0000) These bits must be written by software at regular intervals with the key value 0xAAAA, otherwise the watchdog generates a reset when the counter reaches 0. Writing the key value 0x5555 to enable access to the IWDG_PR, IWDG_RLR and IWDG_WINR registers (see Section23.3.6: Register access protection) Writing the key value CCCCh starts the watchdog (except if the hardware watchdog option is selected)" start="0" size="16" />
+    </Register>
+    <Register name="PR" description="Prescaler register" start="+0x4" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PR" description="Prescaler divider These bits are write access protected see Section23.3.6: Register access protection. They are written by software to select the prescaler divider feeding the counter clock. PVU bit of IWDG_SR must be reset in order to be able to change the prescaler divider. Note: Reading this register returns the prescaler value from the VDD voltage domain. This value may not be up to date/valid if a write operation to this register is ongoing. For this reason the value read from this register is valid only when the PVU bit in the IWDG_SR register is reset." start="0" size="3" />
+    </Register>
+    <Register name="RLR" description="Reload register" start="+0x8" size="4" access="Read/Write" reset_value="0x00000FFF" reset_mask="0xFFFFFFFF">
+      <BitField name="RL" description="Watchdog counter reload value These bits are write access protected see Section23.3.6. They are written by software to define the value to be loaded in the watchdog counter each time the value 0xAAAA is written in the IWDG_KR register. The watchdog counter counts down from this value. The timeout period is a function of this value and the clock prescaler. Refer to the datasheet for the timeout information. The RVU bit in the IWDG_SR register must be reset in order to be able to change the reload value. Note: Reading this register returns the reload value from the VDD voltage domain. This value may not be up to date/valid if a write operation to this register is ongoing on this register. For this reason the value read from this register is valid only when the RVU bit in the IWDG_SR register is reset." start="0" size="12" />
+    </Register>
+    <Register name="SR" description="Status register" start="+0xC" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PVU" description="Watchdog prescaler value update This bit is set by hardware to indicate that an update of the prescaler value is ongoing. It is reset by hardware when the prescaler update operation is completed in the VDD voltage domain (takes up to 5 RC 40 kHz cycles). Prescaler value can be updated only when PVU bit is reset." start="0" size="1" />
+      <BitField name="RVU" description="Watchdog counter reload value update This bit is set by hardware to indicate that an update of the reload value is ongoing. It is reset by hardware when the reload value update operation is completed in the VDD voltage domain (takes up to 5 RC 40 kHz cycles). Reload value can be updated only when RVU bit is reset." start="1" size="1" />
+      <BitField name="WVU" description="Watchdog counter window value update This bit is set by hardware to indicate that an update of the window value is ongoing. It is reset by hardware when the reload value update operation is completed in the VDD voltage domain (takes up to 5 RC 40 kHz cycles). Window value can be updated only when WVU bit is reset. This bit is generated only if generic window = 1" start="2" size="1" />
+    </Register>
+    <Register name="WINR" description="Window register" start="+0x10" size="4" access="Read/Write" reset_value="0x00000FFF" reset_mask="0xFFFFFFFF">
+      <BitField name="WIN" description="Watchdog counter window value These bits are write access protected see Section23.3.6. These bits contain the high limit of the window value to be compared to the downcounter. To prevent a reset, the downcounter must be reloaded when its value is lower than the window register value and greater than 0x0 The WVU bit in the IWDG_SR register must be reset in order to be able to change the reload value. Note: Reading this register returns the reload value from the VDD voltage domain. This value may not be valid if a write operation to this register is ongoing. For this reason the value read from this register is valid only when the WVU bit in the IWDG_SR register is reset." start="0" size="12" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="LPTIM1" description="Low power timer" start="0x40002400">
+    <Register name="ISR" description="Interrupt and Status Register" start="+0x0" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DOWN" description="Counter direction change up to down" start="6" size="1" />
+      <BitField name="UP" description="Counter direction change down to up" start="5" size="1" />
+      <BitField name="ARROK" description="Autoreload register update OK" start="4" size="1" />
+      <BitField name="CMPOK" description="Compare register update OK" start="3" size="1" />
+      <BitField name="EXTTRIG" description="External trigger edge event" start="2" size="1" />
+      <BitField name="ARRM" description="Autoreload match" start="1" size="1" />
+      <BitField name="CMPM" description="Compare match" start="0" size="1" />
+    </Register>
+    <Register name="ICR" description="Interrupt Clear Register" start="+0x4" size="4" access="WriteOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DOWNCF" description="Direction change to down Clear Flag" start="6" size="1" />
+      <BitField name="UPCF" description="Direction change to UP Clear Flag" start="5" size="1" />
+      <BitField name="ARROKCF" description="Autoreload register update OK Clear Flag" start="4" size="1" />
+      <BitField name="CMPOKCF" description="Compare register update OK Clear Flag" start="3" size="1" />
+      <BitField name="EXTTRIGCF" description="External trigger valid edge Clear Flag" start="2" size="1" />
+      <BitField name="ARRMCF" description="Autoreload match Clear Flag" start="1" size="1" />
+      <BitField name="CMPMCF" description="compare match Clear Flag" start="0" size="1" />
+    </Register>
+    <Register name="IER" description="Interrupt Enable Register" start="+0x8" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DOWNIE" description="Direction change to down Interrupt Enable" start="6" size="1" />
+      <BitField name="UPIE" description="Direction change to UP Interrupt Enable" start="5" size="1" />
+      <BitField name="ARROKIE" description="Autoreload register update OK Interrupt Enable" start="4" size="1" />
+      <BitField name="CMPOKIE" description="Compare register update OK Interrupt Enable" start="3" size="1" />
+      <BitField name="EXTTRIGIE" description="External trigger valid edge Interrupt Enable" start="2" size="1" />
+      <BitField name="ARRMIE" description="Autoreload match Interrupt Enable" start="1" size="1" />
+      <BitField name="CMPMIE" description="Compare match Interrupt Enable" start="0" size="1" />
+    </Register>
+    <Register name="CFGR" description="Configuration Register" start="+0xC" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ENC" description="Encoder mode enable" start="24" size="1" />
+      <BitField name="COUNTMODE" description="counter mode enabled" start="23" size="1" />
+      <BitField name="PRELOAD" description="Registers update mode" start="22" size="1" />
+      <BitField name="WAVPOL" description="Waveform shape polarity" start="21" size="1" />
+      <BitField name="WAVE" description="Waveform shape" start="20" size="1" />
+      <BitField name="TIMOUT" description="Timeout enable" start="19" size="1" />
+      <BitField name="TRIGEN" description="Trigger enable and polarity" start="17" size="2" />
+      <BitField name="TRIGSEL" description="Trigger selector" start="13" size="3" />
+      <BitField name="PRESC" description="Clock prescaler" start="9" size="3" />
+      <BitField name="TRGFLT" description="Configurable digital filter for trigger" start="6" size="2" />
+      <BitField name="CKFLT" description="Configurable digital filter for external clock" start="3" size="2" />
+      <BitField name="CKPOL" description="Clock Polarity" start="1" size="2" />
+      <BitField name="CKSEL" description="Clock selector" start="0" size="1" />
+    </Register>
+    <Register name="CR" description="Control Register" start="+0x10" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ENABLE" description="LPTIM Enable" start="0" size="1" />
+      <BitField name="SNGSTRT" description="LPTIM start in single mode" start="1" size="1" />
+      <BitField name="CNTSTRT" description="Timer start in continuous mode" start="2" size="1" />
+      <BitField name="COUNTRST" description="Counter reset" start="3" size="1" />
+      <BitField name="RSTARE" description="Reset after read enable" start="4" size="1" />
+    </Register>
+    <Register name="CMP" description="Compare Register" start="+0x14" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CMP" description="Compare value" start="0" size="16" />
+    </Register>
+    <Register name="ARR" description="Autoreload Register" start="+0x18" size="4" access="Read/Write" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField name="ARR" description="Auto reload value" start="0" size="16" />
+    </Register>
+    <Register name="CNT" description="Counter Register" start="+0x1C" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CNT" description="Counter value" start="0" size="16" />
+    </Register>
+    <Register name="CFGR2" description="LPTIM configuration register 2" start="+0x24" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IN1SEL" description="LPTIM Input 1 selection" start="0" size="2" />
+      <BitField name="IN2SEL" description="LPTIM Input 2 selection" start="4" size="2" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="LPTIM2" description="Low power timer" start="0x58002400">
+    <Register name="ISR" description="Interrupt and Status Register" start="+0x0" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DOWN" description="Counter direction change up to down" start="6" size="1" />
+      <BitField name="UP" description="Counter direction change down to up" start="5" size="1" />
+      <BitField name="ARROK" description="Autoreload register update OK" start="4" size="1" />
+      <BitField name="CMPOK" description="Compare register update OK" start="3" size="1" />
+      <BitField name="EXTTRIG" description="External trigger edge event" start="2" size="1" />
+      <BitField name="ARRM" description="Autoreload match" start="1" size="1" />
+      <BitField name="CMPM" description="Compare match" start="0" size="1" />
+    </Register>
+    <Register name="ICR" description="Interrupt Clear Register" start="+0x4" size="4" access="WriteOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DOWNCF" description="Direction change to down Clear Flag" start="6" size="1" />
+      <BitField name="UPCF" description="Direction change to UP Clear Flag" start="5" size="1" />
+      <BitField name="ARROKCF" description="Autoreload register update OK Clear Flag" start="4" size="1" />
+      <BitField name="CMPOKCF" description="Compare register update OK Clear Flag" start="3" size="1" />
+      <BitField name="EXTTRIGCF" description="External trigger valid edge Clear Flag" start="2" size="1" />
+      <BitField name="ARRMCF" description="Autoreload match Clear Flag" start="1" size="1" />
+      <BitField name="CMPMCF" description="compare match Clear Flag" start="0" size="1" />
+    </Register>
+    <Register name="IER" description="Interrupt Enable Register" start="+0x8" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DOWNIE" description="Direction change to down Interrupt Enable" start="6" size="1" />
+      <BitField name="UPIE" description="Direction change to UP Interrupt Enable" start="5" size="1" />
+      <BitField name="ARROKIE" description="Autoreload register update OK Interrupt Enable" start="4" size="1" />
+      <BitField name="CMPOKIE" description="Compare register update OK Interrupt Enable" start="3" size="1" />
+      <BitField name="EXTTRIGIE" description="External trigger valid edge Interrupt Enable" start="2" size="1" />
+      <BitField name="ARRMIE" description="Autoreload match Interrupt Enable" start="1" size="1" />
+      <BitField name="CMPMIE" description="Compare match Interrupt Enable" start="0" size="1" />
+    </Register>
+    <Register name="CFGR" description="Configuration Register" start="+0xC" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ENC" description="Encoder mode enable" start="24" size="1" />
+      <BitField name="COUNTMODE" description="counter mode enabled" start="23" size="1" />
+      <BitField name="PRELOAD" description="Registers update mode" start="22" size="1" />
+      <BitField name="WAVPOL" description="Waveform shape polarity" start="21" size="1" />
+      <BitField name="WAVE" description="Waveform shape" start="20" size="1" />
+      <BitField name="TIMOUT" description="Timeout enable" start="19" size="1" />
+      <BitField name="TRIGEN" description="Trigger enable and polarity" start="17" size="2" />
+      <BitField name="TRIGSEL" description="Trigger selector" start="13" size="3" />
+      <BitField name="PRESC" description="Clock prescaler" start="9" size="3" />
+      <BitField name="TRGFLT" description="Configurable digital filter for trigger" start="6" size="2" />
+      <BitField name="CKFLT" description="Configurable digital filter for external clock" start="3" size="2" />
+      <BitField name="CKPOL" description="Clock Polarity" start="1" size="2" />
+      <BitField name="CKSEL" description="Clock selector" start="0" size="1" />
+    </Register>
+    <Register name="CR" description="Control Register" start="+0x10" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ENABLE" description="LPTIM Enable" start="0" size="1" />
+      <BitField name="SNGSTRT" description="LPTIM start in single mode" start="1" size="1" />
+      <BitField name="CNTSTRT" description="Timer start in continuous mode" start="2" size="1" />
+      <BitField name="COUNTRST" description="Counter reset" start="3" size="1" />
+      <BitField name="RSTARE" description="Reset after read enable" start="4" size="1" />
+    </Register>
+    <Register name="CMP" description="Compare Register" start="+0x14" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CMP" description="Compare value" start="0" size="16" />
+    </Register>
+    <Register name="ARR" description="Autoreload Register" start="+0x18" size="4" access="Read/Write" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField name="ARR" description="Auto reload value" start="0" size="16" />
+    </Register>
+    <Register name="CNT" description="Counter Register" start="+0x1C" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CNT" description="Counter value" start="0" size="16" />
+    </Register>
+    <Register name="CFGR2" description="LPTIM configuration register 2" start="+0x24" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IN1SEL" description="LPTIM Input 1 selection" start="0" size="2" />
+      <BitField name="IN2SEL" description="LPTIM Input 2 selection" start="4" size="2" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="LPTIM3" description="Low power timer" start="0x58002800">
+    <Register name="ISR" description="Interrupt and Status Register" start="+0x0" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DOWN" description="Counter direction change up to down" start="6" size="1" />
+      <BitField name="UP" description="Counter direction change down to up" start="5" size="1" />
+      <BitField name="ARROK" description="Autoreload register update OK" start="4" size="1" />
+      <BitField name="CMPOK" description="Compare register update OK" start="3" size="1" />
+      <BitField name="EXTTRIG" description="External trigger edge event" start="2" size="1" />
+      <BitField name="ARRM" description="Autoreload match" start="1" size="1" />
+      <BitField name="CMPM" description="Compare match" start="0" size="1" />
+    </Register>
+    <Register name="ICR" description="Interrupt Clear Register" start="+0x4" size="4" access="WriteOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DOWNCF" description="Direction change to down Clear Flag" start="6" size="1" />
+      <BitField name="UPCF" description="Direction change to UP Clear Flag" start="5" size="1" />
+      <BitField name="ARROKCF" description="Autoreload register update OK Clear Flag" start="4" size="1" />
+      <BitField name="CMPOKCF" description="Compare register update OK Clear Flag" start="3" size="1" />
+      <BitField name="EXTTRIGCF" description="External trigger valid edge Clear Flag" start="2" size="1" />
+      <BitField name="ARRMCF" description="Autoreload match Clear Flag" start="1" size="1" />
+      <BitField name="CMPMCF" description="compare match Clear Flag" start="0" size="1" />
+    </Register>
+    <Register name="IER" description="Interrupt Enable Register" start="+0x8" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DOWNIE" description="Direction change to down Interrupt Enable" start="6" size="1" />
+      <BitField name="UPIE" description="Direction change to UP Interrupt Enable" start="5" size="1" />
+      <BitField name="ARROKIE" description="Autoreload register update OK Interrupt Enable" start="4" size="1" />
+      <BitField name="CMPOKIE" description="Compare register update OK Interrupt Enable" start="3" size="1" />
+      <BitField name="EXTTRIGIE" description="External trigger valid edge Interrupt Enable" start="2" size="1" />
+      <BitField name="ARRMIE" description="Autoreload match Interrupt Enable" start="1" size="1" />
+      <BitField name="CMPMIE" description="Compare match Interrupt Enable" start="0" size="1" />
+    </Register>
+    <Register name="CFGR" description="Configuration Register" start="+0xC" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ENC" description="Encoder mode enable" start="24" size="1" />
+      <BitField name="COUNTMODE" description="counter mode enabled" start="23" size="1" />
+      <BitField name="PRELOAD" description="Registers update mode" start="22" size="1" />
+      <BitField name="WAVPOL" description="Waveform shape polarity" start="21" size="1" />
+      <BitField name="WAVE" description="Waveform shape" start="20" size="1" />
+      <BitField name="TIMOUT" description="Timeout enable" start="19" size="1" />
+      <BitField name="TRIGEN" description="Trigger enable and polarity" start="17" size="2" />
+      <BitField name="TRIGSEL" description="Trigger selector" start="13" size="3" />
+      <BitField name="PRESC" description="Clock prescaler" start="9" size="3" />
+      <BitField name="TRGFLT" description="Configurable digital filter for trigger" start="6" size="2" />
+      <BitField name="CKFLT" description="Configurable digital filter for external clock" start="3" size="2" />
+      <BitField name="CKPOL" description="Clock Polarity" start="1" size="2" />
+      <BitField name="CKSEL" description="Clock selector" start="0" size="1" />
+    </Register>
+    <Register name="CR" description="Control Register" start="+0x10" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ENABLE" description="LPTIM Enable" start="0" size="1" />
+      <BitField name="SNGSTRT" description="LPTIM start in single mode" start="1" size="1" />
+      <BitField name="CNTSTRT" description="Timer start in continuous mode" start="2" size="1" />
+      <BitField name="COUNTRST" description="Counter reset" start="3" size="1" />
+      <BitField name="RSTARE" description="Reset after read enable" start="4" size="1" />
+    </Register>
+    <Register name="CMP" description="Compare Register" start="+0x14" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CMP" description="Compare value" start="0" size="16" />
+    </Register>
+    <Register name="ARR" description="Autoreload Register" start="+0x18" size="4" access="Read/Write" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField name="ARR" description="Auto reload value" start="0" size="16" />
+    </Register>
+    <Register name="CNT" description="Counter Register" start="+0x1C" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CNT" description="Counter value" start="0" size="16" />
+    </Register>
+    <Register name="CFGR2" description="LPTIM configuration register 2" start="+0x24" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IN1SEL" description="LPTIM Input 1 selection" start="0" size="2" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="LPTIM4" description="Low power timer" start="0x58002C00">
+    <Register name="ISR" description="Interrupt and Status Register" start="+0x0" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DOWN" description="Counter direction change up to down" start="6" size="1" />
+      <BitField name="UP" description="Counter direction change down to up" start="5" size="1" />
+      <BitField name="ARROK" description="Autoreload register update OK" start="4" size="1" />
+      <BitField name="CMPOK" description="Compare register update OK" start="3" size="1" />
+      <BitField name="EXTTRIG" description="External trigger edge event" start="2" size="1" />
+      <BitField name="ARRM" description="Autoreload match" start="1" size="1" />
+      <BitField name="CMPM" description="Compare match" start="0" size="1" />
+    </Register>
+    <Register name="ICR" description="Interrupt Clear Register" start="+0x4" size="4" access="WriteOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DOWNCF" description="Direction change to down Clear Flag" start="6" size="1" />
+      <BitField name="UPCF" description="Direction change to UP Clear Flag" start="5" size="1" />
+      <BitField name="ARROKCF" description="Autoreload register update OK Clear Flag" start="4" size="1" />
+      <BitField name="CMPOKCF" description="Compare register update OK Clear Flag" start="3" size="1" />
+      <BitField name="EXTTRIGCF" description="External trigger valid edge Clear Flag" start="2" size="1" />
+      <BitField name="ARRMCF" description="Autoreload match Clear Flag" start="1" size="1" />
+      <BitField name="CMPMCF" description="compare match Clear Flag" start="0" size="1" />
+    </Register>
+    <Register name="IER" description="Interrupt Enable Register" start="+0x8" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DOWNIE" description="Direction change to down Interrupt Enable" start="6" size="1" />
+      <BitField name="UPIE" description="Direction change to UP Interrupt Enable" start="5" size="1" />
+      <BitField name="ARROKIE" description="Autoreload register update OK Interrupt Enable" start="4" size="1" />
+      <BitField name="CMPOKIE" description="Compare register update OK Interrupt Enable" start="3" size="1" />
+      <BitField name="EXTTRIGIE" description="External trigger valid edge Interrupt Enable" start="2" size="1" />
+      <BitField name="ARRMIE" description="Autoreload match Interrupt Enable" start="1" size="1" />
+      <BitField name="CMPMIE" description="Compare match Interrupt Enable" start="0" size="1" />
+    </Register>
+    <Register name="CFGR" description="Configuration Register" start="+0xC" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ENC" description="Encoder mode enable" start="24" size="1" />
+      <BitField name="COUNTMODE" description="counter mode enabled" start="23" size="1" />
+      <BitField name="PRELOAD" description="Registers update mode" start="22" size="1" />
+      <BitField name="WAVPOL" description="Waveform shape polarity" start="21" size="1" />
+      <BitField name="WAVE" description="Waveform shape" start="20" size="1" />
+      <BitField name="TIMOUT" description="Timeout enable" start="19" size="1" />
+      <BitField name="TRIGEN" description="Trigger enable and polarity" start="17" size="2" />
+      <BitField name="TRIGSEL" description="Trigger selector" start="13" size="3" />
+      <BitField name="PRESC" description="Clock prescaler" start="9" size="3" />
+      <BitField name="TRGFLT" description="Configurable digital filter for trigger" start="6" size="2" />
+      <BitField name="CKFLT" description="Configurable digital filter for external clock" start="3" size="2" />
+      <BitField name="CKPOL" description="Clock Polarity" start="1" size="2" />
+      <BitField name="CKSEL" description="Clock selector" start="0" size="1" />
+    </Register>
+    <Register name="CR" description="Control Register" start="+0x10" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ENABLE" description="LPTIM Enable" start="0" size="1" />
+      <BitField name="SNGSTRT" description="LPTIM start in single mode" start="1" size="1" />
+      <BitField name="CNTSTRT" description="Timer start in continuous mode" start="2" size="1" />
+      <BitField name="COUNTRST" description="Counter reset" start="3" size="1" />
+      <BitField name="RSTARE" description="Reset after read enable" start="4" size="1" />
+    </Register>
+    <Register name="CMP" description="Compare Register" start="+0x14" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CMP" description="Compare value" start="0" size="16" />
+    </Register>
+    <Register name="ARR" description="Autoreload Register" start="+0x18" size="4" access="Read/Write" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField name="ARR" description="Auto reload value" start="0" size="16" />
+    </Register>
+    <Register name="CNT" description="Counter Register" start="+0x1C" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CNT" description="Counter value" start="0" size="16" />
+    </Register>
+    <Register name="CFGR2" description="LPTIM configuration register 2" start="+0x24" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IN1SEL" description="LPTIM Input 1 selection" start="0" size="2" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="LPTIM5" description="Low power timer" start="0x58003000">
+    <Register name="ISR" description="Interrupt and Status Register" start="+0x0" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DOWN" description="Counter direction change up to down" start="6" size="1" />
+      <BitField name="UP" description="Counter direction change down to up" start="5" size="1" />
+      <BitField name="ARROK" description="Autoreload register update OK" start="4" size="1" />
+      <BitField name="CMPOK" description="Compare register update OK" start="3" size="1" />
+      <BitField name="EXTTRIG" description="External trigger edge event" start="2" size="1" />
+      <BitField name="ARRM" description="Autoreload match" start="1" size="1" />
+      <BitField name="CMPM" description="Compare match" start="0" size="1" />
+    </Register>
+    <Register name="ICR" description="Interrupt Clear Register" start="+0x4" size="4" access="WriteOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DOWNCF" description="Direction change to down Clear Flag" start="6" size="1" />
+      <BitField name="UPCF" description="Direction change to UP Clear Flag" start="5" size="1" />
+      <BitField name="ARROKCF" description="Autoreload register update OK Clear Flag" start="4" size="1" />
+      <BitField name="CMPOKCF" description="Compare register update OK Clear Flag" start="3" size="1" />
+      <BitField name="EXTTRIGCF" description="External trigger valid edge Clear Flag" start="2" size="1" />
+      <BitField name="ARRMCF" description="Autoreload match Clear Flag" start="1" size="1" />
+      <BitField name="CMPMCF" description="compare match Clear Flag" start="0" size="1" />
+    </Register>
+    <Register name="IER" description="Interrupt Enable Register" start="+0x8" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DOWNIE" description="Direction change to down Interrupt Enable" start="6" size="1" />
+      <BitField name="UPIE" description="Direction change to UP Interrupt Enable" start="5" size="1" />
+      <BitField name="ARROKIE" description="Autoreload register update OK Interrupt Enable" start="4" size="1" />
+      <BitField name="CMPOKIE" description="Compare register update OK Interrupt Enable" start="3" size="1" />
+      <BitField name="EXTTRIGIE" description="External trigger valid edge Interrupt Enable" start="2" size="1" />
+      <BitField name="ARRMIE" description="Autoreload match Interrupt Enable" start="1" size="1" />
+      <BitField name="CMPMIE" description="Compare match Interrupt Enable" start="0" size="1" />
+    </Register>
+    <Register name="CFGR" description="Configuration Register" start="+0xC" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ENC" description="Encoder mode enable" start="24" size="1" />
+      <BitField name="COUNTMODE" description="counter mode enabled" start="23" size="1" />
+      <BitField name="PRELOAD" description="Registers update mode" start="22" size="1" />
+      <BitField name="WAVPOL" description="Waveform shape polarity" start="21" size="1" />
+      <BitField name="WAVE" description="Waveform shape" start="20" size="1" />
+      <BitField name="TIMOUT" description="Timeout enable" start="19" size="1" />
+      <BitField name="TRIGEN" description="Trigger enable and polarity" start="17" size="2" />
+      <BitField name="TRIGSEL" description="Trigger selector" start="13" size="3" />
+      <BitField name="PRESC" description="Clock prescaler" start="9" size="3" />
+      <BitField name="TRGFLT" description="Configurable digital filter for trigger" start="6" size="2" />
+      <BitField name="CKFLT" description="Configurable digital filter for external clock" start="3" size="2" />
+      <BitField name="CKPOL" description="Clock Polarity" start="1" size="2" />
+      <BitField name="CKSEL" description="Clock selector" start="0" size="1" />
+    </Register>
+    <Register name="CR" description="Control Register" start="+0x10" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ENABLE" description="LPTIM Enable" start="0" size="1" />
+      <BitField name="SNGSTRT" description="LPTIM start in single mode" start="1" size="1" />
+      <BitField name="CNTSTRT" description="Timer start in continuous mode" start="2" size="1" />
+      <BitField name="COUNTRST" description="Counter reset" start="3" size="1" />
+      <BitField name="RSTARE" description="Reset after read enable" start="4" size="1" />
+    </Register>
+    <Register name="CMP" description="Compare Register" start="+0x14" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CMP" description="Compare value" start="0" size="16" />
+    </Register>
+    <Register name="ARR" description="Autoreload Register" start="+0x18" size="4" access="Read/Write" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField name="ARR" description="Auto reload value" start="0" size="16" />
+    </Register>
+    <Register name="CNT" description="Counter Register" start="+0x1C" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CNT" description="Counter value" start="0" size="16" />
+    </Register>
+    <Register name="CFGR2" description="LPTIM configuration register 2" start="+0x24" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IN1SEL" description="LPTIM Input 1 selection" start="0" size="2" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="LPUART1" description="LPUART1" start="0x58000C00">
+    <Register name="CR1" description="Control register 1" start="+0x0" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="RXFFIE" description="RXFIFO Full interrupt enable" start="31" size="1" />
+      <BitField name="TXFEIE" description="TXFIFO empty interrupt enable" start="30" size="1" />
+      <BitField name="FIFOEN" description="FIFO mode enable" start="29" size="1" />
+      <BitField name="M1" description="Word length" start="28" size="1" />
+      <BitField name="DEAT" description="Driver Enable assertion time" start="21" size="5" />
+      <BitField name="DEDT" description="Driver Enable deassertion time" start="16" size="5" />
+      <BitField name="CMIE" description="Character match interrupt enable" start="14" size="1" />
+      <BitField name="MME" description="Mute mode enable" start="13" size="1" />
+      <BitField name="M0" description="Word length" start="12" size="1" />
+      <BitField name="WAKE" description="Receiver wakeup method" start="11" size="1" />
+      <BitField name="PCE" description="Parity control enable" start="10" size="1" />
+      <BitField name="PS" description="Parity selection" start="9" size="1" />
+      <BitField name="PEIE" description="PE interrupt enable" start="8" size="1" />
+      <BitField name="TXEIE" description="interrupt enable" start="7" size="1" />
+      <BitField name="TCIE" description="Transmission complete interrupt enable" start="6" size="1" />
+      <BitField name="RXNEIE" description="RXNE interrupt enable" start="5" size="1" />
+      <BitField name="IDLEIE" description="IDLE interrupt enable" start="4" size="1" />
+      <BitField name="TE" description="Transmitter enable" start="3" size="1" />
+      <BitField name="RE" description="Receiver enable" start="2" size="1" />
+      <BitField name="UESM" description="USART enable in Stop mode" start="1" size="1" />
+      <BitField name="UE" description="USART enable" start="0" size="1" />
+    </Register>
+    <Register name="CR2" description="Control register 2" start="+0x4" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="ADD" description="Address of the USART node" start="24" size="8" />
+      <BitField name="MSBFIRST" description="Most significant bit first" start="19" size="1" />
+      <BitField name="DATAINV" description="Binary data inversion" start="18" size="1" />
+      <BitField name="TXINV" description="TX pin active level inversion" start="17" size="1" />
+      <BitField name="RXINV" description="RX pin active level inversion" start="16" size="1" />
+      <BitField name="SWAP" description="Swap TX/RX pins" start="15" size="1" />
+      <BitField name="STOP" description="STOP bits" start="12" size="2" />
+      <BitField name="ADDM7" description="7-bit Address Detection/4-bit Address Detection" start="4" size="1" />
+    </Register>
+    <Register name="CR3" description="Control register 3" start="+0x8" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="TXFTCFG" description="TXFIFO threshold configuration" start="29" size="3" />
+      <BitField name="RXFTIE" description="RXFIFO threshold interrupt enable" start="28" size="1" />
+      <BitField name="RXFTCFG" description="Receive FIFO threshold configuration" start="25" size="3" />
+      <BitField name="TXFTIE" description="TXFIFO threshold interrupt enable" start="23" size="1" />
+      <BitField name="WUFIE" description="Wakeup from Stop mode interrupt enable" start="22" size="1" />
+      <BitField name="WUS" description="Wakeup from Stop mode interrupt flag selection" start="20" size="2" />
+      <BitField name="DEP" description="Driver enable polarity selection" start="15" size="1" />
+      <BitField name="DEM" description="Driver enable mode" start="14" size="1" />
+      <BitField name="DDRE" description="DMA Disable on Reception Error" start="13" size="1" />
+      <BitField name="OVRDIS" description="Overrun Disable" start="12" size="1" />
+      <BitField name="CTSIE" description="CTS interrupt enable" start="10" size="1" />
+      <BitField name="CTSE" description="CTS enable" start="9" size="1" />
+      <BitField name="RTSE" description="RTS enable" start="8" size="1" />
+      <BitField name="DMAT" description="DMA enable transmitter" start="7" size="1" />
+      <BitField name="DMAR" description="DMA enable receiver" start="6" size="1" />
+      <BitField name="HDSEL" description="Half-duplex selection" start="3" size="1" />
+      <BitField name="EIE" description="Error interrupt enable" start="0" size="1" />
+    </Register>
+    <Register name="BRR" description="Baud rate register" start="+0xC" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="BRR" description="BRR" start="0" size="20" />
+    </Register>
+    <Register name="GTPR" description="Guard time and prescaler register" start="+0x10" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="GT" description="Guard time value" start="8" size="8" />
+      <BitField name="PSC" description="Prescaler value" start="0" size="8" />
+    </Register>
+    <Register name="RTOR" description="Receiver timeout register" start="+0x14" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="BLEN" description="Block Length" start="24" size="8" />
+      <BitField name="RTO" description="Receiver timeout value" start="0" size="24" />
+    </Register>
+    <Register name="RQR" description="Request register" start="+0x18" size="4" access="WriteOnly" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="TXFRQ" description="Transmit data flush request" start="4" size="1" />
+      <BitField name="RXFRQ" description="Receive data flush request" start="3" size="1" />
+      <BitField name="MMRQ" description="Mute mode request" start="2" size="1" />
+      <BitField name="SBKRQ" description="Send break request" start="1" size="1" />
+      <BitField name="ABRRQ" description="Auto baud rate request" start="0" size="1" />
+    </Register>
+    <Register name="ISR" description="Interrupt &amp; status register" start="+0x1C" size="4" access="ReadOnly" reset_value="0x00C0" reset_mask="0xFFFFFFFF">
+      <BitField name="TXFT" description="TXFIFO threshold flag" start="27" size="1" />
+      <BitField name="RXFT" description="RXFIFO threshold flag" start="26" size="1" />
+      <BitField name="RXFF" description="RXFIFO Full" start="24" size="1" />
+      <BitField name="TXFE" description="TXFIFO Empty" start="23" size="1" />
+      <BitField name="REACK" description="REACK" start="22" size="1" />
+      <BitField name="TEACK" description="TEACK" start="21" size="1" />
+      <BitField name="WUF" description="WUF" start="20" size="1" />
+      <BitField name="RWU" description="RWU" start="19" size="1" />
+      <BitField name="SBKF" description="SBKF" start="18" size="1" />
+      <BitField name="CMF" description="CMF" start="17" size="1" />
+      <BitField name="BUSY" description="BUSY" start="16" size="1" />
+      <BitField name="CTS" description="CTS" start="10" size="1" />
+      <BitField name="CTSIF" description="CTSIF" start="9" size="1" />
+      <BitField name="TXE" description="TXE" start="7" size="1" />
+      <BitField name="TC" description="TC" start="6" size="1" />
+      <BitField name="RXNE" description="RXNE" start="5" size="1" />
+      <BitField name="IDLE" description="IDLE" start="4" size="1" />
+      <BitField name="ORE" description="ORE" start="3" size="1" />
+      <BitField name="NE" description="NE" start="2" size="1" />
+      <BitField name="FE" description="FE" start="1" size="1" />
+      <BitField name="PE" description="PE" start="0" size="1" />
+    </Register>
+    <Register name="ICR" description="Interrupt flag clear register" start="+0x20" size="4" access="WriteOnly" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="WUCF" description="Wakeup from Stop mode clear flag" start="20" size="1" />
+      <BitField name="CMCF" description="Character match clear flag" start="17" size="1" />
+      <BitField name="CTSCF" description="CTS clear flag" start="9" size="1" />
+      <BitField name="TCCF" description="Transmission complete clear flag" start="6" size="1" />
+      <BitField name="IDLECF" description="Idle line detected clear flag" start="4" size="1" />
+      <BitField name="ORECF" description="Overrun error clear flag" start="3" size="1" />
+      <BitField name="NCF" description="Noise detected clear flag" start="2" size="1" />
+      <BitField name="FECF" description="Framing error clear flag" start="1" size="1" />
+      <BitField name="PECF" description="Parity error clear flag" start="0" size="1" />
+    </Register>
+    <Register name="RDR" description="Receive data register" start="+0x24" size="4" access="ReadOnly" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="RDR" description="Receive data value" start="0" size="9" />
+    </Register>
+    <Register name="TDR" description="Transmit data register" start="+0x28" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="TDR" description="Transmit data value" start="0" size="9" />
+    </Register>
+    <Register name="PRESC" description="Prescaler register" start="+0x2C" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="PRESCALER" description="Clock prescaler" start="0" size="4" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="LTDC" description="LCD-TFT Controller" start="0x50001000">
+    <Register name="SSCR" description="Synchronization Size Configuration Register" start="+0x8" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HSW" description="Horizontal Synchronization Width (in units of pixel clock period)" start="16" size="10" />
+      <BitField name="VSH" description="Vertical Synchronization Height (in units of horizontal scan line)" start="0" size="11" />
+    </Register>
+    <Register name="BPCR" description="Back Porch Configuration Register" start="+0xC" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AHBP" description="Accumulated Horizontal back porch (in units of pixel clock period)" start="16" size="12" />
+      <BitField name="AVBP" description="Accumulated Vertical back porch (in units of horizontal scan line)" start="0" size="11" />
+    </Register>
+    <Register name="AWCR" description="Active Width Configuration Register" start="+0x10" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AAV" description="AAV" start="16" size="12" />
+      <BitField name="AAH" description="Accumulated Active Height (in units of horizontal scan line)" start="0" size="11" />
+    </Register>
+    <Register name="TWCR" description="Total Width Configuration Register" start="+0x14" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TOTALW" description="Total Width (in units of pixel clock period)" start="16" size="12" />
+      <BitField name="TOTALH" description="Total Height (in units of horizontal scan line)" start="0" size="11" />
+    </Register>
+    <Register name="GCR" description="Global Control Register" start="+0x18" size="4" reset_value="0x00002220" reset_mask="0xFFFFFFFF">
+      <BitField name="HSPOL" description="Horizontal Synchronization Polarity" start="31" size="1" access="Read/Write" />
+      <BitField name="VSPOL" description="Vertical Synchronization Polarity" start="30" size="1" access="Read/Write" />
+      <BitField name="DEPOL" description="Data Enable Polarity" start="29" size="1" access="Read/Write" />
+      <BitField name="PCPOL" description="Pixel Clock Polarity" start="28" size="1" access="Read/Write" />
+      <BitField name="DEN" description="Dither Enable" start="16" size="1" access="Read/Write" />
+      <BitField name="DRW" description="Dither Red Width" start="12" size="3" access="ReadOnly" />
+      <BitField name="DGW" description="Dither Green Width" start="8" size="3" access="ReadOnly" />
+      <BitField name="DBW" description="Dither Blue Width" start="4" size="3" access="ReadOnly" />
+      <BitField name="LTDCEN" description="LCD-TFT controller enable bit" start="0" size="1" access="Read/Write" />
+    </Register>
+    <Register name="SRCR" description="Shadow Reload Configuration Register" start="+0x24" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="VBR" description="Vertical Blanking Reload" start="1" size="1" />
+      <BitField name="IMR" description="Immediate Reload" start="0" size="1" />
+    </Register>
+    <Register name="BCCR" description="Background Color Configuration Register" start="+0x2C" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BCBLUE" description="Background Color Blue value" start="0" size="8" />
+      <BitField name="BCGREEN" description="Background Color Green value" start="8" size="8" />
+      <BitField name="BCRED" description="Background Color Red value" start="16" size="8" />
+    </Register>
+    <Register name="IER" description="Interrupt Enable Register" start="+0x34" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RRIE" description="Register Reload interrupt enable" start="3" size="1" />
+      <BitField name="TERRIE" description="Transfer Error Interrupt Enable" start="2" size="1" />
+      <BitField name="FUIE" description="FIFO Underrun Interrupt Enable" start="1" size="1" />
+      <BitField name="LIE" description="Line Interrupt Enable" start="0" size="1" />
+    </Register>
+    <Register name="ISR" description="Interrupt Status Register" start="+0x38" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RRIF" description="Register Reload Interrupt Flag" start="3" size="1" />
+      <BitField name="TERRIF" description="Transfer Error interrupt flag" start="2" size="1" />
+      <BitField name="FUIF" description="FIFO Underrun Interrupt flag" start="1" size="1" />
+      <BitField name="LIF" description="Line Interrupt flag" start="0" size="1" />
+    </Register>
+    <Register name="ICR" description="Interrupt Clear Register" start="+0x3C" size="4" access="WriteOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CRRIF" description="Clears Register Reload Interrupt Flag" start="3" size="1" />
+      <BitField name="CTERRIF" description="Clears the Transfer Error Interrupt Flag" start="2" size="1" />
+      <BitField name="CFUIF" description="Clears the FIFO Underrun Interrupt flag" start="1" size="1" />
+      <BitField name="CLIF" description="Clears the Line Interrupt Flag" start="0" size="1" />
+    </Register>
+    <Register name="LIPCR" description="Line Interrupt Position Configuration Register" start="+0x40" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LIPOS" description="Line Interrupt Position" start="0" size="11" />
+    </Register>
+    <Register name="CPSR" description="Current Position Status Register" start="+0x44" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CXPOS" description="Current X Position" start="16" size="16" />
+      <BitField name="CYPOS" description="Current Y Position" start="0" size="16" />
+    </Register>
+    <Register name="CDSR" description="Current Display Status Register" start="+0x48" size="4" access="ReadOnly" reset_value="0x0000000F" reset_mask="0xFFFFFFFF">
+      <BitField name="HSYNCS" description="Horizontal Synchronization display Status" start="3" size="1" />
+      <BitField name="VSYNCS" description="Vertical Synchronization display Status" start="2" size="1" />
+      <BitField name="HDES" description="Horizontal Data Enable display Status" start="1" size="1" />
+      <BitField name="VDES" description="Vertical Data Enable display Status" start="0" size="1" />
+    </Register>
+    <Register name="L1CR" description="Layerx Control Register" start="+0x84" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CLUTEN" description="Color Look-Up Table Enable" start="4" size="1" />
+      <BitField name="COLKEN" description="Color Keying Enable" start="1" size="1" />
+      <BitField name="LEN" description="Layer Enable" start="0" size="1" />
+    </Register>
+    <Register name="L1WHPCR" description="Layerx Window Horizontal Position Configuration Register" start="+0x88" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="WHSPPOS" description="Window Horizontal Stop Position" start="16" size="12" />
+      <BitField name="WHSTPOS" description="Window Horizontal Start Position" start="0" size="12" />
+    </Register>
+    <Register name="L1WVPCR" description="Layerx Window Vertical Position Configuration Register" start="+0x8C" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="WVSPPOS" description="Window Vertical Stop Position" start="16" size="11" />
+      <BitField name="WVSTPOS" description="Window Vertical Start Position" start="0" size="11" />
+    </Register>
+    <Register name="L1CKCR" description="Layerx Color Keying Configuration Register" start="+0x90" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CKRED" description="Color Key Red value" start="16" size="8" />
+      <BitField name="CKGREEN" description="Color Key Green value" start="8" size="8" />
+      <BitField name="CKBLUE" description="Color Key Blue value" start="0" size="8" />
+    </Register>
+    <Register name="L1PFCR" description="Layerx Pixel Format Configuration Register" start="+0x94" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PF" description="Pixel Format" start="0" size="3" />
+    </Register>
+    <Register name="L1CACR" description="Layerx Constant Alpha Configuration Register" start="+0x98" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CONSTA" description="Constant Alpha" start="0" size="8" />
+    </Register>
+    <Register name="L1DCCR" description="Layerx Default Color Configuration Register" start="+0x9C" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DCALPHA" description="Default Color Alpha" start="24" size="8" />
+      <BitField name="DCRED" description="Default Color Red" start="16" size="8" />
+      <BitField name="DCGREEN" description="Default Color Green" start="8" size="8" />
+      <BitField name="DCBLUE" description="Default Color Blue" start="0" size="8" />
+    </Register>
+    <Register name="L1BFCR" description="Layerx Blending Factors Configuration Register" start="+0xA0" size="4" access="Read/Write" reset_value="0x00000607" reset_mask="0xFFFFFFFF">
+      <BitField name="BF1" description="Blending Factor 1" start="8" size="3" />
+      <BitField name="BF2" description="Blending Factor 2" start="0" size="3" />
+    </Register>
+    <Register name="L1CFBAR" description="Layerx Color Frame Buffer Address Register" start="+0xAC" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CFBADD" description="Color Frame Buffer Start Address" start="0" size="32" />
+    </Register>
+    <Register name="L1CFBLR" description="Layerx Color Frame Buffer Length Register" start="+0xB0" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CFBP" description="Color Frame Buffer Pitch in bytes" start="16" size="13" />
+      <BitField name="CFBLL" description="Color Frame Buffer Line Length" start="0" size="13" />
+    </Register>
+    <Register name="L1CFBLNR" description="Layerx ColorFrame Buffer Line Number Register" start="+0xB4" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CFBLNBR" description="Frame Buffer Line Number" start="0" size="11" />
+    </Register>
+    <Register name="L1CLUTWR" description="Layerx CLUT Write Register" start="+0xC4" size="4" access="WriteOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CLUTADD" description="CLUT Address" start="24" size="8" />
+      <BitField name="RED" description="Red value" start="16" size="8" />
+      <BitField name="GREEN" description="Green value" start="8" size="8" />
+      <BitField name="BLUE" description="Blue value" start="0" size="8" />
+    </Register>
+    <Register name="L2CR" description="Layerx Control Register" start="+0x104" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CLUTEN" description="Color Look-Up Table Enable" start="4" size="1" />
+      <BitField name="COLKEN" description="Color Keying Enable" start="1" size="1" />
+      <BitField name="LEN" description="Layer Enable" start="0" size="1" />
+    </Register>
+    <Register name="L2WHPCR" description="Layerx Window Horizontal Position Configuration Register" start="+0x108" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="WHSPPOS" description="Window Horizontal Stop Position" start="16" size="12" />
+      <BitField name="WHSTPOS" description="Window Horizontal Start Position" start="0" size="12" />
+    </Register>
+    <Register name="L2WVPCR" description="Layerx Window Vertical Position Configuration Register" start="+0x10C" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="WVSPPOS" description="Window Vertical Stop Position" start="16" size="11" />
+      <BitField name="WVSTPOS" description="Window Vertical Start Position" start="0" size="11" />
+    </Register>
+    <Register name="L2CKCR" description="Layerx Color Keying Configuration Register" start="+0x110" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CKRED" description="Color Key Red value" start="16" size="8" />
+      <BitField name="CKGREEN" description="Color Key Green value" start="8" size="8" />
+      <BitField name="CKBLUE" description="Color Key Blue value" start="0" size="8" />
+    </Register>
+    <Register name="L2PFCR" description="Layerx Pixel Format Configuration Register" start="+0x114" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PF" description="Pixel Format" start="0" size="3" />
+    </Register>
+    <Register name="L2CACR" description="Layerx Constant Alpha Configuration Register" start="+0x118" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CONSTA" description="Constant Alpha" start="0" size="8" />
+    </Register>
+    <Register name="L2DCCR" description="Layerx Default Color Configuration Register" start="+0x11C" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DCALPHA" description="Default Color Alpha" start="24" size="8" />
+      <BitField name="DCRED" description="Default Color Red" start="16" size="8" />
+      <BitField name="DCGREEN" description="Default Color Green" start="8" size="8" />
+      <BitField name="DCBLUE" description="Default Color Blue" start="0" size="8" />
+    </Register>
+    <Register name="L2BFCR" description="Layerx Blending Factors Configuration Register" start="+0x120" size="4" access="Read/Write" reset_value="0x00000607" reset_mask="0xFFFFFFFF">
+      <BitField name="BF1" description="Blending Factor 1" start="8" size="3" />
+      <BitField name="BF2" description="Blending Factor 2" start="0" size="3" />
+    </Register>
+    <Register name="L2CFBAR" description="Layerx Color Frame Buffer Address Register" start="+0x12C" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CFBADD" description="Color Frame Buffer Start Address" start="0" size="32" />
+    </Register>
+    <Register name="L2CFBLR" description="Layerx Color Frame Buffer Length Register" start="+0x130" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CFBP" description="Color Frame Buffer Pitch in bytes" start="16" size="13" />
+      <BitField name="CFBLL" description="Color Frame Buffer Line Length" start="0" size="13" />
+    </Register>
+    <Register name="L2CFBLNR" description="Layerx ColorFrame Buffer Line Number Register" start="+0x134" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CFBLNBR" description="Frame Buffer Line Number" start="0" size="11" />
+    </Register>
+    <Register name="L2CLUTWR" description="Layerx CLUT Write Register" start="+0x144" size="4" access="WriteOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CLUTADD" description="CLUT Address" start="24" size="8" />
+      <BitField name="RED" description="Red value" start="16" size="8" />
+      <BitField name="GREEN" description="Green value" start="8" size="8" />
+      <BitField name="BLUE" description="Blue value" start="0" size="8" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="MDIOS" description="Management data input/output slave" start="0x40009400">
+    <Register name="MDIOS_CR" description="MDIOS configuration register" start="+0x0" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="Peripheral enable" start="0" size="1" />
+      <BitField name="WRIE" description="Register write interrupt enable" start="1" size="1" />
+      <BitField name="RDIE" description="Register Read Interrupt Enable" start="2" size="1" />
+      <BitField name="EIE" description="Error interrupt enable" start="3" size="1" />
+      <BitField name="DPC" description="Disable Preamble Check" start="7" size="1" />
+      <BitField name="PORT_ADDRESS" description="Slaves's address" start="8" size="5" />
+    </Register>
+    <Register name="MDIOS_WRFR" description="MDIOS write flag register" start="+0x4" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="WRF" description="Write flags for MDIO registers 0 to 31" start="0" size="32" />
+    </Register>
+    <Register name="MDIOS_CWRFR" description="MDIOS clear write flag register" start="+0x8" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CWRF" description="Clear the write flag" start="0" size="32" />
+    </Register>
+    <Register name="MDIOS_RDFR" description="MDIOS read flag register" start="+0xC" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RDF" description="Read flags for MDIO registers 0 to 31" start="0" size="32" />
+    </Register>
+    <Register name="MDIOS_CRDFR" description="MDIOS clear read flag register" start="+0x10" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CRDF" description="Clear the read flag" start="0" size="32" />
+    </Register>
+    <Register name="MDIOS_SR" description="MDIOS status register" start="+0x14" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PERF" description="Preamble error flag" start="0" size="1" />
+      <BitField name="SERF" description="Start error flag" start="1" size="1" />
+      <BitField name="TERF" description="Turnaround error flag" start="2" size="1" />
+    </Register>
+    <Register name="MDIOS_CLRFR" description="MDIOS clear flag register" start="+0x18" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CPERF" description="Clear the preamble error flag" start="0" size="1" />
+      <BitField name="CSERF" description="Clear the start error flag" start="1" size="1" />
+      <BitField name="CTERF" description="Clear the turnaround error flag" start="2" size="1" />
+    </Register>
+    <Register name="MDIOS_DINR0" description="MDIOS input data register 0" start="+0x1C" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DIN0" description="Input data received from MDIO Master during write frames" start="0" size="16" />
+    </Register>
+    <Register name="MDIOS_DINR1" description="MDIOS input data register 1" start="+0x20" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DIN1" description="Input data received from MDIO Master during write frames" start="0" size="16" />
+    </Register>
+    <Register name="MDIOS_DINR2" description="MDIOS input data register 2" start="+0x24" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DIN2" description="Input data received from MDIO Master during write frames" start="0" size="16" />
+    </Register>
+    <Register name="MDIOS_DINR3" description="MDIOS input data register 3" start="+0x28" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DIN3" description="Input data received from MDIO Master during write frames" start="0" size="16" />
+    </Register>
+    <Register name="MDIOS_DINR4" description="MDIOS input data register 4" start="+0x2C" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DIN4" description="Input data received from MDIO Master during write frames" start="0" size="16" />
+    </Register>
+    <Register name="MDIOS_DINR5" description="MDIOS input data register 5" start="+0x30" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DIN5" description="Input data received from MDIO Master during write frames" start="0" size="16" />
+    </Register>
+    <Register name="MDIOS_DINR6" description="MDIOS input data register 6" start="+0x34" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DIN6" description="Input data received from MDIO Master during write frames" start="0" size="16" />
+    </Register>
+    <Register name="MDIOS_DINR7" description="MDIOS input data register 7" start="+0x38" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DIN7" description="Input data received from MDIO Master during write frames" start="0" size="16" />
+    </Register>
+    <Register name="MDIOS_DINR8" description="MDIOS input data register 8" start="+0x3C" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DIN8" description="Input data received from MDIO Master during write frames" start="0" size="16" />
+    </Register>
+    <Register name="MDIOS_DINR9" description="MDIOS input data register 9" start="+0x40" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DIN9" description="Input data received from MDIO Master during write frames" start="0" size="16" />
+    </Register>
+    <Register name="MDIOS_DINR10" description="MDIOS input data register 10" start="+0x44" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DIN10" description="Input data received from MDIO Master during write frames" start="0" size="16" />
+    </Register>
+    <Register name="MDIOS_DINR11" description="MDIOS input data register 11" start="+0x48" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DIN11" description="Input data received from MDIO Master during write frames" start="0" size="16" />
+    </Register>
+    <Register name="MDIOS_DINR12" description="MDIOS input data register 12" start="+0x4C" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DIN12" description="Input data received from MDIO Master during write frames" start="0" size="16" />
+    </Register>
+    <Register name="MDIOS_DINR13" description="MDIOS input data register 13" start="+0x50" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DIN13" description="Input data received from MDIO Master during write frames" start="0" size="16" />
+    </Register>
+    <Register name="MDIOS_DINR14" description="MDIOS input data register 14" start="+0x54" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DIN14" description="Input data received from MDIO Master during write frames" start="0" size="16" />
+    </Register>
+    <Register name="MDIOS_DINR15" description="MDIOS input data register 15" start="+0x58" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DIN15" description="Input data received from MDIO Master during write frames" start="0" size="16" />
+    </Register>
+    <Register name="MDIOS_DINR16" description="MDIOS input data register 16" start="+0x5C" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DIN16" description="Input data received from MDIO Master during write frames" start="0" size="16" />
+    </Register>
+    <Register name="MDIOS_DINR17" description="MDIOS input data register 17" start="+0x60" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DIN17" description="Input data received from MDIO Master during write frames" start="0" size="16" />
+    </Register>
+    <Register name="MDIOS_DINR18" description="MDIOS input data register 18" start="+0x64" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DIN18" description="Input data received from MDIO Master during write frames" start="0" size="16" />
+    </Register>
+    <Register name="MDIOS_DINR19" description="MDIOS input data register 19" start="+0x68" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DIN19" description="Input data received from MDIO Master during write frames" start="0" size="16" />
+    </Register>
+    <Register name="MDIOS_DINR20" description="MDIOS input data register 20" start="+0x6C" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DIN20" description="Input data received from MDIO Master during write frames" start="0" size="16" />
+    </Register>
+    <Register name="MDIOS_DINR21" description="MDIOS input data register 21" start="+0x70" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DIN21" description="Input data received from MDIO Master during write frames" start="0" size="16" />
+    </Register>
+    <Register name="MDIOS_DINR22" description="MDIOS input data register 22" start="+0x74" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DIN22" description="Input data received from MDIO Master during write frames" start="0" size="16" />
+    </Register>
+    <Register name="MDIOS_DINR23" description="MDIOS input data register 23" start="+0x78" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DIN23" description="Input data received from MDIO Master during write frames" start="0" size="16" />
+    </Register>
+    <Register name="MDIOS_DINR24" description="MDIOS input data register 24" start="+0x7C" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DIN24" description="Input data received from MDIO Master during write frames" start="0" size="16" />
+    </Register>
+    <Register name="MDIOS_DINR25" description="MDIOS input data register 25" start="+0x80" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DIN25" description="Input data received from MDIO Master during write frames" start="0" size="16" />
+    </Register>
+    <Register name="MDIOS_DINR26" description="MDIOS input data register 26" start="+0x84" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DIN26" description="Input data received from MDIO Master during write frames" start="0" size="16" />
+    </Register>
+    <Register name="MDIOS_DINR27" description="MDIOS input data register 27" start="+0x88" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DIN27" description="Input data received from MDIO Master during write frames" start="0" size="16" />
+    </Register>
+    <Register name="MDIOS_DINR28" description="MDIOS input data register 28" start="+0x8C" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DIN28" description="Input data received from MDIO Master during write frames" start="0" size="16" />
+    </Register>
+    <Register name="MDIOS_DINR29" description="MDIOS input data register 29" start="+0x90" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DIN29" description="Input data received from MDIO Master during write frames" start="0" size="16" />
+    </Register>
+    <Register name="MDIOS_DINR30" description="MDIOS input data register 30" start="+0x94" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DIN30" description="Input data received from MDIO Master during write frames" start="0" size="16" />
+    </Register>
+    <Register name="MDIOS_DINR31" description="MDIOS input data register 31" start="+0x98" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DIN31" description="Input data received from MDIO Master during write frames" start="0" size="16" />
+    </Register>
+    <Register name="MDIOS_DOUTR0" description="MDIOS output data register 0" start="+0x9C" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DOUT0" description="Output data sent to MDIO Master during read frames" start="0" size="16" />
+    </Register>
+    <Register name="MDIOS_DOUTR1" description="MDIOS output data register 1" start="+0xA0" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DOUT1" description="Output data sent to MDIO Master during read frames" start="0" size="16" />
+    </Register>
+    <Register name="MDIOS_DOUTR2" description="MDIOS output data register 2" start="+0xA4" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DOUT2" description="Output data sent to MDIO Master during read frames" start="0" size="16" />
+    </Register>
+    <Register name="MDIOS_DOUTR3" description="MDIOS output data register 3" start="+0xA8" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DOUT3" description="Output data sent to MDIO Master during read frames" start="0" size="16" />
+    </Register>
+    <Register name="MDIOS_DOUTR4" description="MDIOS output data register 4" start="+0xAC" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DOUT4" description="Output data sent to MDIO Master during read frames" start="0" size="16" />
+    </Register>
+    <Register name="MDIOS_DOUTR5" description="MDIOS output data register 5" start="+0xB0" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DOUT5" description="Output data sent to MDIO Master during read frames" start="0" size="16" />
+    </Register>
+    <Register name="MDIOS_DOUTR6" description="MDIOS output data register 6" start="+0xB4" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DOUT6" description="Output data sent to MDIO Master during read frames" start="0" size="16" />
+    </Register>
+    <Register name="MDIOS_DOUTR7" description="MDIOS output data register 7" start="+0xB8" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DOUT7" description="Output data sent to MDIO Master during read frames" start="0" size="16" />
+    </Register>
+    <Register name="MDIOS_DOUTR8" description="MDIOS output data register 8" start="+0xBC" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DOUT8" description="Output data sent to MDIO Master during read frames" start="0" size="16" />
+    </Register>
+    <Register name="MDIOS_DOUTR9" description="MDIOS output data register 9" start="+0xC0" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DOUT9" description="Output data sent to MDIO Master during read frames" start="0" size="16" />
+    </Register>
+    <Register name="MDIOS_DOUTR10" description="MDIOS output data register 10" start="+0xC4" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DOUT10" description="Output data sent to MDIO Master during read frames" start="0" size="16" />
+    </Register>
+    <Register name="MDIOS_DOUTR11" description="MDIOS output data register 11" start="+0xC8" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DOUT11" description="Output data sent to MDIO Master during read frames" start="0" size="16" />
+    </Register>
+    <Register name="MDIOS_DOUTR12" description="MDIOS output data register 12" start="+0xCC" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DOUT12" description="Output data sent to MDIO Master during read frames" start="0" size="16" />
+    </Register>
+    <Register name="MDIOS_DOUTR13" description="MDIOS output data register 13" start="+0xD0" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DOUT13" description="Output data sent to MDIO Master during read frames" start="0" size="16" />
+    </Register>
+    <Register name="MDIOS_DOUTR14" description="MDIOS output data register 14" start="+0xD4" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DOUT14" description="Output data sent to MDIO Master during read frames" start="0" size="16" />
+    </Register>
+    <Register name="MDIOS_DOUTR15" description="MDIOS output data register 15" start="+0xD8" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DOUT15" description="Output data sent to MDIO Master during read frames" start="0" size="16" />
+    </Register>
+    <Register name="MDIOS_DOUTR16" description="MDIOS output data register 16" start="+0xDC" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DOUT16" description="Output data sent to MDIO Master during read frames" start="0" size="16" />
+    </Register>
+    <Register name="MDIOS_DOUTR17" description="MDIOS output data register 17" start="+0xE0" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DOUT17" description="Output data sent to MDIO Master during read frames" start="0" size="16" />
+    </Register>
+    <Register name="MDIOS_DOUTR18" description="MDIOS output data register 18" start="+0xE4" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DOUT18" description="Output data sent to MDIO Master during read frames" start="0" size="16" />
+    </Register>
+    <Register name="MDIOS_DOUTR19" description="MDIOS output data register 19" start="+0xE8" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DOUT19" description="Output data sent to MDIO Master during read frames" start="0" size="16" />
+    </Register>
+    <Register name="MDIOS_DOUTR20" description="MDIOS output data register 20" start="+0xEC" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DOUT20" description="Output data sent to MDIO Master during read frames" start="0" size="16" />
+    </Register>
+    <Register name="MDIOS_DOUTR21" description="MDIOS output data register 21" start="+0xF0" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DOUT21" description="Output data sent to MDIO Master during read frames" start="0" size="16" />
+    </Register>
+    <Register name="MDIOS_DOUTR22" description="MDIOS output data register 22" start="+0xF4" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DOUT22" description="Output data sent to MDIO Master during read frames" start="0" size="16" />
+    </Register>
+    <Register name="MDIOS_DOUTR23" description="MDIOS output data register 23" start="+0xF8" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DOUT23" description="Output data sent to MDIO Master during read frames" start="0" size="16" />
+    </Register>
+    <Register name="MDIOS_DOUTR24" description="MDIOS output data register 24" start="+0xFC" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DOUT24" description="Output data sent to MDIO Master during read frames" start="0" size="16" />
+    </Register>
+    <Register name="MDIOS_DOUTR25" description="MDIOS output data register 25" start="+0x100" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DOUT25" description="Output data sent to MDIO Master during read frames" start="0" size="16" />
+    </Register>
+    <Register name="MDIOS_DOUTR26" description="MDIOS output data register 26" start="+0x104" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DOUT26" description="Output data sent to MDIO Master during read frames" start="0" size="16" />
+    </Register>
+    <Register name="MDIOS_DOUTR27" description="MDIOS output data register 27" start="+0x108" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DOUT27" description="Output data sent to MDIO Master during read frames" start="0" size="16" />
+    </Register>
+    <Register name="MDIOS_DOUTR28" description="MDIOS output data register 28" start="+0x10C" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DOUT28" description="Output data sent to MDIO Master during read frames" start="0" size="16" />
+    </Register>
+    <Register name="MDIOS_DOUTR29" description="MDIOS output data register 29" start="+0x110" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DOUT29" description="Output data sent to MDIO Master during read frames" start="0" size="16" />
+    </Register>
+    <Register name="MDIOS_DOUTR30" description="MDIOS output data register 30" start="+0x114" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DOUT30" description="Output data sent to MDIO Master during read frames" start="0" size="16" />
+    </Register>
+    <Register name="MDIOS_DOUTR31" description="MDIOS output data register 31" start="+0x118" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DOUT31" description="Output data sent to MDIO Master during read frames" start="0" size="16" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="MDMA" description="MDMA" start="0x52000000">
+    <Register name="MDMA_GISR0" description="MDMA Global Interrupt/Status Register" start="+0x0" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="GIF0" description="Channel x global interrupt flag (x=...) This bit is set and reset by hardware. It is a logical OR of all the Channel x interrupt flags (CTCIFx, BTIFx, BRTIFx, TEIFx) which are enabled in the interrupt mask register (CTCIEx, BTIEx, BRTIEx, TEIEx)" start="0" size="1" />
+      <BitField name="GIF1" description="Channel x global interrupt flag (x=...) This bit is set and reset by hardware. It is a logical OR of all the Channel x interrupt flags (CTCIFx, BTIFx, BRTIFx, TEIFx) which are enabled in the interrupt mask register (CTCIEx, BTIEx, BRTIEx, TEIEx)" start="1" size="1" />
+      <BitField name="GIF2" description="Channel x global interrupt flag (x=...) This bit is set and reset by hardware. It is a logical OR of all the Channel x interrupt flags (CTCIFx, BTIFx, BRTIFx, TEIFx) which are enabled in the interrupt mask register (CTCIEx, BTIEx, BRTIEx, TEIEx)" start="2" size="1" />
+      <BitField name="GIF3" description="Channel x global interrupt flag (x=...) This bit is set and reset by hardware. It is a logical OR of all the Channel x interrupt flags (CTCIFx, BTIFx, BRTIFx, TEIFx) which are enabled in the interrupt mask register (CTCIEx, BTIEx, BRTIEx, TEIEx)" start="3" size="1" />
+      <BitField name="GIF4" description="Channel x global interrupt flag (x=...) This bit is set and reset by hardware. It is a logical OR of all the Channel x interrupt flags (CTCIFx, BTIFx, BRTIFx, TEIFx) which are enabled in the interrupt mask register (CTCIEx, BTIEx, BRTIEx, TEIEx)" start="4" size="1" />
+      <BitField name="GIF5" description="Channel x global interrupt flag (x=...) This bit is set and reset by hardware. It is a logical OR of all the Channel x interrupt flags (CTCIFx, BTIFx, BRTIFx, TEIFx) which are enabled in the interrupt mask register (CTCIEx, BTIEx, BRTIEx, TEIEx)" start="5" size="1" />
+      <BitField name="GIF6" description="Channel x global interrupt flag (x=...) This bit is set and reset by hardware. It is a logical OR of all the Channel x interrupt flags (CTCIFx, BTIFx, BRTIFx, TEIFx) which are enabled in the interrupt mask register (CTCIEx, BTIEx, BRTIEx, TEIEx)" start="6" size="1" />
+      <BitField name="GIF7" description="Channel x global interrupt flag (x=...) This bit is set and reset by hardware. It is a logical OR of all the Channel x interrupt flags (CTCIFx, BTIFx, BRTIFx, TEIFx) which are enabled in the interrupt mask register (CTCIEx, BTIEx, BRTIEx, TEIEx)" start="7" size="1" />
+      <BitField name="GIF8" description="Channel x global interrupt flag (x=...) This bit is set and reset by hardware. It is a logical OR of all the Channel x interrupt flags (CTCIFx, BTIFx, BRTIFx, TEIFx) which are enabled in the interrupt mask register (CTCIEx, BTIEx, BRTIEx, TEIEx)" start="8" size="1" />
+      <BitField name="GIF9" description="Channel x global interrupt flag (x=...) This bit is set and reset by hardware. It is a logical OR of all the Channel x interrupt flags (CTCIFx, BTIFx, BRTIFx, TEIFx) which are enabled in the interrupt mask register (CTCIEx, BTIEx, BRTIEx, TEIEx)" start="9" size="1" />
+      <BitField name="GIF10" description="Channel x global interrupt flag (x=...) This bit is set and reset by hardware. It is a logical OR of all the Channel x interrupt flags (CTCIFx, BTIFx, BRTIFx, TEIFx) which are enabled in the interrupt mask register (CTCIEx, BTIEx, BRTIEx, TEIEx)" start="10" size="1" />
+      <BitField name="GIF11" description="Channel x global interrupt flag (x=...) This bit is set and reset by hardware. It is a logical OR of all the Channel x interrupt flags (CTCIFx, BTIFx, BRTIFx, TEIFx) which are enabled in the interrupt mask register (CTCIEx, BTIEx, BRTIEx, TEIEx)" start="11" size="1" />
+      <BitField name="GIF12" description="Channel x global interrupt flag (x=...) This bit is set and reset by hardware. It is a logical OR of all the Channel x interrupt flags (CTCIFx, BTIFx, BRTIFx, TEIFx) which are enabled in the interrupt mask register (CTCIEx, BTIEx, BRTIEx, TEIEx)" start="12" size="1" />
+      <BitField name="GIF13" description="Channel x global interrupt flag (x=...) This bit is set and reset by hardware. It is a logical OR of all the Channel x interrupt flags (CTCIFx, BTIFx, BRTIFx, TEIFx) which are enabled in the interrupt mask register (CTCIEx, BTIEx, BRTIEx, TEIEx)" start="13" size="1" />
+      <BitField name="GIF14" description="Channel x global interrupt flag (x=...) This bit is set and reset by hardware. It is a logical OR of all the Channel x interrupt flags (CTCIFx, BTIFx, BRTIFx, TEIFx) which are enabled in the interrupt mask register (CTCIEx, BTIEx, BRTIEx, TEIEx)" start="14" size="1" />
+      <BitField name="GIF15" description="Channel x global interrupt flag (x=...) This bit is set and reset by hardware. It is a logical OR of all the Channel x interrupt flags (CTCIFx, BTIFx, BRTIFx, TEIFx) which are enabled in the interrupt mask register (CTCIEx, BTIEx, BRTIEx, TEIEx)" start="15" size="1" />
+    </Register>
+    <Register name="MDMA_C0ISR" description="MDMA channel x interrupt/status register" start="+0x40" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TEIF0" description="Channel x transfer error interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register." start="0" size="1" />
+      <BitField name="CTCIF0" description="Channel x Channel Transfer Complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register. CTC is set when the last block was transferred and the channel has been automatically disabled. CTC is also set when the channel is suspended, as a result of writing EN bit to 0." start="1" size="1" />
+      <BitField name="BRTIF0" description="Channel x block repeat transfer complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register." start="2" size="1" />
+      <BitField name="BTIF0" description="Channel x block transfer complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register." start="3" size="1" />
+      <BitField name="TCIF0" description="channel x buffer transfer complete" start="4" size="1" />
+      <BitField name="CRQA0" description="channel x request active flag" start="16" size="1" />
+    </Register>
+    <Register name="MDMA_C0IFCR" description="MDMA channel x interrupt flag clear register" start="+0x44" size="4" access="WriteOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CTEIF0" description="Channel x clear transfer error interrupt flag Writing a 1 into this bit clears TEIFx in the MDMA_ISRy register" start="0" size="1" />
+      <BitField name="CCTCIF0" description="Clear Channel transfer complete interrupt flag for channel x Writing a 1 into this bit clears CTCIFx in the MDMA_ISRy register" start="1" size="1" />
+      <BitField name="CBRTIF0" description="Channel x clear block repeat transfer complete interrupt flag Writing a 1 into this bit clears BRTIFx in the MDMA_ISRy register" start="2" size="1" />
+      <BitField name="CBTIF0" description="Channel x Clear block transfer complete interrupt flag Writing a 1 into this bit clears BTIFx in the MDMA_ISRy register" start="3" size="1" />
+      <BitField name="CLTCIF0" description="CLear buffer Transfer Complete Interrupt Flag for channel x Writing a 1 into this bit clears TCIFx in the MDMA_ISRy register" start="4" size="1" />
+    </Register>
+    <Register name="MDMA_C0ESR" description="MDMA Channel x error status register" start="+0x48" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TEA" description="Transfer Error Address These bits are set and cleared by HW, in case of an MDMA data transfer error. It is used in conjunction with TED. This field indicates the 7 LSBits of the address which generated a transfer/access error. It may be used by SW to retrieve the failing address, by adding this value (truncated to the buffer transfer length size) to the current SAR/DAR value. Note: The SAR/DAR current value doesnt reflect this last address due to the FIFO management system. The SAR/DAR are only updated at the end of a (buffer) transfer (of TLEN+1 bytes). Note: It is not set in case of a link data error." start="0" size="7" />
+      <BitField name="TED" description="Transfer Error Direction These bit is set and cleared by HW, in case of an MDMA data transfer error." start="7" size="1" />
+      <BitField name="TELD" description="Transfer Error Link Data These bit is set by HW, in case of a transfer error while reading the block link data structure. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register." start="8" size="1" />
+      <BitField name="TEMD" description="Transfer Error Mask Data These bit is set by HW, in case of a transfer error while writing the Mask Data. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register." start="9" size="1" />
+      <BitField name="ASE" description="Address/Size Error These bit is set by HW, when the programmed address is not aligned with the data size. TED will indicate whether the problem is on the source or destination. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register." start="10" size="1" />
+      <BitField name="BSE" description="Block Size Error These bit is set by HW, when the block size is not an integer multiple of the data size either for source or destination. TED will indicate whether the problem is on the source or destination. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register." start="11" size="1" />
+    </Register>
+    <Register name="MDMA_C0CR" description="This register is used to control the concerned channel." start="+0x4C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="channel enable" start="0" size="1" access="Read/Write" />
+      <BitField name="TEIE" description="Transfer error interrupt enable This bit is set and cleared by software." start="1" size="1" access="Read/Write" />
+      <BitField name="CTCIE" description="Channel Transfer Complete interrupt enable This bit is set and cleared by software." start="2" size="1" access="Read/Write" />
+      <BitField name="BRTIE" description="Block Repeat transfer interrupt enable This bit is set and cleared by software." start="3" size="1" access="Read/Write" />
+      <BitField name="BTIE" description="Block Transfer interrupt enable This bit is set and cleared by software." start="4" size="1" access="Read/Write" />
+      <BitField name="TCIE" description="buffer Transfer Complete interrupt enable This bit is set and cleared by software." start="5" size="1" access="Read/Write" />
+      <BitField name="PL" description="Priority level These bits are set and cleared by software. These bits are protected and can be written only if EN is 0." start="6" size="2" access="Read/Write" />
+      <BitField name="BEX" description="byte Endianness exchange" start="12" size="1" access="Read/Write" />
+      <BitField name="HEX" description="Half word Endianes exchange" start="13" size="1" access="Read/Write" />
+      <BitField name="WEX" description="Word Endianness exchange" start="14" size="1" access="Read/Write" />
+      <BitField name="SWRQ" description="SW ReQuest Writing a 1 into this bit sets the CRQAx in MDMA_ISRy register, activating the request on Channel x Note: Either the whole CxCR register or the 8-bit/16-bit register @ Address offset: 0x4E + 0x40 chn may be used for SWRQ activation. In case of a SW request, acknowledge is not generated (neither HW signal, nor CxMAR write access)." start="16" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="MDMA_C0TCR" description="This register is used to configure the concerned channel." start="+0x50" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SINC" description="Source increment mode These bits are set and cleared by software. These bits are protected and can be written only if EN is 0 Note: When source is AHB (SBUS=1), SINC = 00 is forbidden. In Linked List Mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00)." start="0" size="2" />
+      <BitField name="DINC" description="Destination increment mode These bits are set and cleared by software. These bits are protected and can be written only if EN is 0 Note: When destination is AHB (DBUS=1), DINC = 00 is forbidden." start="2" size="2" />
+      <BitField name="SSIZE" description="Source data size These bits are set and cleared by software. These bits are protected and can be written only if EN is 0 Note: If a value of 11 is programmed for the TCM access/AHB port, a transfer error will occur (TEIF bit set) If SINCOS &amp;lt; SSIZE and SINC &amp;#8800; 00, the result will be unpredictable. Note: SSIZE = 11 (double-word) is forbidden when source is TCM/AHB bus (SBUS=1)." start="4" size="2" />
+      <BitField name="DSIZE" description="Destination data size These bits are set and cleared by software. These bits are protected and can be written only if EN is 0. Note: If a value of 11 is programmed for the TCM access/AHB port, a transfer error will occur (TEIF bit set) If DINCOS &amp;lt; DSIZE and DINC &amp;#8800; 00, the result will be unpredictable. Note: DSIZE = 11 (double-word) is forbidden when destination is TCM/AHB bus (DBUS=1)." start="6" size="2" />
+      <BitField name="SINCOS" description="source increment offset size" start="8" size="2" />
+      <BitField name="DINCOS" description="Destination increment offset" start="10" size="2" />
+      <BitField name="SBURST" description="source burst transfer configuration" start="12" size="3" />
+      <BitField name="DBURST" description="Destination burst transfer configuration" start="15" size="3" />
+      <BitField name="TLEN" description="buffer transfer lengh" start="18" size="7" />
+      <BitField name="PKE" description="PacK Enable These bit is set and cleared by software. If the Source Size is smaller than the destination, it will be padded according to the PAM value. If the Source data size is larger than the destination one, it will be truncated. The alignment will be done according to the PAM[0] value. This bit is protected and can be written only if EN is 0" start="25" size="1" />
+      <BitField name="PAM" description="Padding/Alignement Mode These bits are set and cleared by software. Case 1: Source data size smaller than destination data size - 3 options are valid. Case 2: Source data size larger than destination data size. The remainder part is discarded. When PKE = 1 or DSIZE=SSIZE, these bits are ignored. These bits are protected and can be written only if EN is 0" start="26" size="2" />
+      <BitField name="TRGM" description="Trigger Mode These bits are set and cleared by software. Note: If TRGM is 11 for the current block, all the values loaded at the end of the current block through the linked list mechanism must keep the same value (TRGM=11) and the same SWRM value, otherwise the result is undefined. These bits are protected and can be written only if EN is 0." start="28" size="2" />
+      <BitField name="SWRM" description="SW Request Mode This bit is set and cleared by software. If a HW or SW request is currently active, the bit change will be delayed until the current transfer is completed. If the CxMAR contains a valid address, the CxMDR value will also be written @ CxMAR address. This bit is protected and can be written only if EN is 0." start="30" size="1" />
+      <BitField name="BWM" description="Bufferable Write Mode This bit is set and cleared by software. This bit is protected and can be written only if EN is 0. Note: All MDMA destination accesses are non-cacheable." start="31" size="1" />
+    </Register>
+    <Register name="MDMA_C0BNDTR" description="MDMA Channel x block number of data register" start="+0x54" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BNDT" description="block number of data to transfer" start="0" size="17" />
+      <BitField name="BRSUM" description="Block Repeat Source address Update Mode These bits are protected and can be written only if EN is 0." start="18" size="1" />
+      <BitField name="BRDUM" description="Block Repeat Destination address Update Mode These bits are protected and can be written only if EN is 0." start="19" size="1" />
+      <BitField name="BRC" description="Block Repeat Count This field contains the number of repetitions of the current block (0 to 4095). When the channel is enabled, this register is read-only, indicating the remaining number of blocks, excluding the current one. This register decrements after each complete block transfer. Once the last block transfer has completed, this register can either stay at zero or be reloaded automatically from memory (in Linked List mode - i.e. Link Address valid). These bits are protected and can be written only if EN is 0." start="20" size="12" />
+    </Register>
+    <Register name="MDMA_C0SAR" description="MDMA channel x source address register" start="+0x58" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SAR" description="source adr base" start="0" size="32" />
+    </Register>
+    <Register name="MDMA_C0DAR" description="MDMA channel x destination address register" start="+0x5C" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DAR" description="Destination adr base" start="0" size="32" />
+    </Register>
+    <Register name="MDMA_C0BRUR" description="MDMA channel x Block Repeat address Update register" start="+0x60" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SUV" description="source adresse update value" start="0" size="16" />
+      <BitField name="DUV" description="destination address update" start="16" size="16" />
+    </Register>
+    <Register name="MDMA_C0LAR" description="MDMA channel x Link Address register" start="+0x64" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LAR" description="Link address register" start="0" size="32" />
+    </Register>
+    <Register name="MDMA_C0TBR" description="MDMA channel x Trigger and Bus selection Register" start="+0x68" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TSEL" description="Trigger selection" start="0" size="6" />
+      <BitField name="SBUS" description="Source BUS select This bit is protected and can be written only if EN is 0." start="16" size="1" />
+      <BitField name="DBUS" description="Destination BUS slect This bit is protected and can be written only if EN is 0." start="17" size="1" />
+    </Register>
+    <Register name="MDMA_C0MAR" description="MDMA channel x Mask address register" start="+0x70" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MAR" description="Mask address" start="0" size="32" />
+    </Register>
+    <Register name="MDMA_C0MDR" description="MDMA channel x Mask Data register" start="+0x74" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MDR" description="Mask data" start="0" size="32" />
+    </Register>
+    <Register name="MDMA_C1ISR" description="MDMA channel x interrupt/status register" start="+0x80" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TEIF1" description="Channel x transfer error interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register." start="0" size="1" />
+      <BitField name="CTCIF1" description="Channel x Channel Transfer Complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register. CTC is set when the last block was transferred and the channel has been automatically disabled. CTC is also set when the channel is suspended, as a result of writing EN bit to 0." start="1" size="1" />
+      <BitField name="BRTIF1" description="Channel x block repeat transfer complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register." start="2" size="1" />
+      <BitField name="BTIF1" description="Channel x block transfer complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register." start="3" size="1" />
+      <BitField name="TCIF1" description="channel x buffer transfer complete" start="4" size="1" />
+      <BitField name="CRQA1" description="channel x request active flag" start="16" size="1" />
+    </Register>
+    <Register name="MDMA_C1IFCR" description="MDMA channel x interrupt flag clear register" start="+0x84" size="4" access="WriteOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CTEIF1" description="Channel x clear transfer error interrupt flag Writing a 1 into this bit clears TEIFx in the MDMA_ISRy register" start="0" size="1" />
+      <BitField name="CCTCIF1" description="Clear Channel transfer complete interrupt flag for channel x Writing a 1 into this bit clears CTCIFx in the MDMA_ISRy register" start="1" size="1" />
+      <BitField name="CBRTIF1" description="Channel x clear block repeat transfer complete interrupt flag Writing a 1 into this bit clears BRTIFx in the MDMA_ISRy register" start="2" size="1" />
+      <BitField name="CBTIF1" description="Channel x Clear block transfer complete interrupt flag Writing a 1 into this bit clears BTIFx in the MDMA_ISRy register" start="3" size="1" />
+      <BitField name="CLTCIF1" description="CLear buffer Transfer Complete Interrupt Flag for channel x Writing a 1 into this bit clears TCIFx in the MDMA_ISRy register" start="4" size="1" />
+    </Register>
+    <Register name="MDMA_C1ESR" description="MDMA Channel x error status register" start="+0x88" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TEA" description="Transfer Error Address These bits are set and cleared by HW, in case of an MDMA data transfer error. It is used in conjunction with TED. This field indicates the 7 LSBits of the address which generated a transfer/access error. It may be used by SW to retrieve the failing address, by adding this value (truncated to the buffer transfer length size) to the current SAR/DAR value. Note: The SAR/DAR current value doesnt reflect this last address due to the FIFO management system. The SAR/DAR are only updated at the end of a (buffer) transfer (of TLEN+1 bytes). Note: It is not set in case of a link data error." start="0" size="7" />
+      <BitField name="TED" description="Transfer Error Direction These bit is set and cleared by HW, in case of an MDMA data transfer error." start="7" size="1" />
+      <BitField name="TELD" description="Transfer Error Link Data These bit is set by HW, in case of a transfer error while reading the block link data structure. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register." start="8" size="1" />
+      <BitField name="TEMD" description="Transfer Error Mask Data These bit is set by HW, in case of a transfer error while writing the Mask Data. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register." start="9" size="1" />
+      <BitField name="ASE" description="Address/Size Error These bit is set by HW, when the programmed address is not aligned with the data size. TED will indicate whether the problem is on the source or destination. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register." start="10" size="1" />
+      <BitField name="BSE" description="Block Size Error These bit is set by HW, when the block size is not an integer multiple of the data size either for source or destination. TED will indicate whether the problem is on the source or destination. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register." start="11" size="1" />
+    </Register>
+    <Register name="MDMA_C1CR" description="This register is used to control the concerned channel." start="+0x8C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="channel enable" start="0" size="1" access="Read/Write" />
+      <BitField name="TEIE" description="Transfer error interrupt enable This bit is set and cleared by software." start="1" size="1" access="Read/Write" />
+      <BitField name="CTCIE" description="Channel Transfer Complete interrupt enable This bit is set and cleared by software." start="2" size="1" access="Read/Write" />
+      <BitField name="BRTIE" description="Block Repeat transfer interrupt enable This bit is set and cleared by software." start="3" size="1" access="Read/Write" />
+      <BitField name="BTIE" description="Block Transfer interrupt enable This bit is set and cleared by software." start="4" size="1" access="Read/Write" />
+      <BitField name="TCIE" description="buffer Transfer Complete interrupt enable This bit is set and cleared by software." start="5" size="1" access="Read/Write" />
+      <BitField name="PL" description="Priority level These bits are set and cleared by software. These bits are protected and can be written only if EN is 0." start="6" size="2" access="Read/Write" />
+      <BitField name="BEX" description="byte Endianness exchange" start="12" size="1" access="Read/Write" />
+      <BitField name="HEX" description="Half word Endianes exchange" start="13" size="1" access="Read/Write" />
+      <BitField name="WEX" description="Word Endianness exchange" start="14" size="1" access="Read/Write" />
+      <BitField name="SWRQ" description="SW ReQuest Writing a 1 into this bit sets the CRQAx in MDMA_ISRy register, activating the request on Channel x Note: Either the whole CxCR register or the 8-bit/16-bit register @ Address offset: 0x4E + 0x40 chn may be used for SWRQ activation. In case of a SW request, acknowledge is not generated (neither HW signal, nor CxMAR write access)." start="16" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="MDMA_C1TCR" description="This register is used to configure the concerned channel." start="+0x90" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SINC" description="Source increment mode These bits are set and cleared by software. These bits are protected and can be written only if EN is 0 Note: When source is AHB (SBUS=1), SINC = 00 is forbidden. In Linked List Mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00)." start="0" size="2" />
+      <BitField name="DINC" description="Destination increment mode These bits are set and cleared by software. These bits are protected and can be written only if EN is 0 Note: When destination is AHB (DBUS=1), DINC = 00 is forbidden." start="2" size="2" />
+      <BitField name="SSIZE" description="Source data size These bits are set and cleared by software. These bits are protected and can be written only if EN is 0 Note: If a value of 11 is programmed for the TCM access/AHB port, a transfer error will occur (TEIF bit set) If SINCOS &amp;lt; SSIZE and SINC &amp;#8800; 00, the result will be unpredictable. Note: SSIZE = 11 (double-word) is forbidden when source is TCM/AHB bus (SBUS=1)." start="4" size="2" />
+      <BitField name="DSIZE" description="Destination data size These bits are set and cleared by software. These bits are protected and can be written only if EN is 0. Note: If a value of 11 is programmed for the TCM access/AHB port, a transfer error will occur (TEIF bit set) If DINCOS &amp;lt; DSIZE and DINC &amp;#8800; 00, the result will be unpredictable. Note: DSIZE = 11 (double-word) is forbidden when destination is TCM/AHB bus (DBUS=1)." start="6" size="2" />
+      <BitField name="SINCOS" description="source increment offset size" start="8" size="2" />
+      <BitField name="DINCOS" description="Destination increment offset" start="10" size="2" />
+      <BitField name="SBURST" description="source burst transfer configuration" start="12" size="3" />
+      <BitField name="DBURST" description="Destination burst transfer configuration" start="15" size="3" />
+      <BitField name="TLEN" description="buffer transfer lengh" start="18" size="7" />
+      <BitField name="PKE" description="PacK Enable These bit is set and cleared by software. If the Source Size is smaller than the destination, it will be padded according to the PAM value. If the Source data size is larger than the destination one, it will be truncated. The alignment will be done according to the PAM[0] value. This bit is protected and can be written only if EN is 0" start="25" size="1" />
+      <BitField name="PAM" description="Padding/Alignement Mode These bits are set and cleared by software. Case 1: Source data size smaller than destination data size - 3 options are valid. Case 2: Source data size larger than destination data size. The remainder part is discarded. When PKE = 1 or DSIZE=SSIZE, these bits are ignored. These bits are protected and can be written only if EN is 0" start="26" size="2" />
+      <BitField name="TRGM" description="Trigger Mode These bits are set and cleared by software. Note: If TRGM is 11 for the current block, all the values loaded at the end of the current block through the linked list mechanism must keep the same value (TRGM=11) and the same SWRM value, otherwise the result is undefined. These bits are protected and can be written only if EN is 0." start="28" size="2" />
+      <BitField name="SWRM" description="SW Request Mode This bit is set and cleared by software. If a HW or SW request is currently active, the bit change will be delayed until the current transfer is completed. If the CxMAR contains a valid address, the CxMDR value will also be written @ CxMAR address. This bit is protected and can be written only if EN is 0." start="30" size="1" />
+      <BitField name="BWM" description="Bufferable Write Mode This bit is set and cleared by software. This bit is protected and can be written only if EN is 0. Note: All MDMA destination accesses are non-cacheable." start="31" size="1" />
+    </Register>
+    <Register name="MDMA_C1BNDTR" description="MDMA Channel x block number of data register" start="+0x94" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BNDT" description="block number of data to transfer" start="0" size="17" />
+      <BitField name="BRSUM" description="Block Repeat Source address Update Mode These bits are protected and can be written only if EN is 0." start="18" size="1" />
+      <BitField name="BRDUM" description="Block Repeat Destination address Update Mode These bits are protected and can be written only if EN is 0." start="19" size="1" />
+      <BitField name="BRC" description="Block Repeat Count This field contains the number of repetitions of the current block (0 to 4095). When the channel is enabled, this register is read-only, indicating the remaining number of blocks, excluding the current one. This register decrements after each complete block transfer. Once the last block transfer has completed, this register can either stay at zero or be reloaded automatically from memory (in Linked List mode - i.e. Link Address valid). These bits are protected and can be written only if EN is 0." start="20" size="12" />
+    </Register>
+    <Register name="MDMA_C1SAR" description="MDMA channel x source address register" start="+0x98" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SAR" description="source adr base" start="0" size="32" />
+    </Register>
+    <Register name="MDMA_C1DAR" description="MDMA channel x destination address register" start="+0x9C" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DAR" description="Destination adr base" start="0" size="32" />
+    </Register>
+    <Register name="MDMA_C1BRUR" description="MDMA channel x Block Repeat address Update register" start="+0xA0" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SUV" description="source adresse update value" start="0" size="16" />
+      <BitField name="DUV" description="destination address update" start="16" size="16" />
+    </Register>
+    <Register name="MDMA_C1LAR" description="MDMA channel x Link Address register" start="+0xA4" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LAR" description="Link address register" start="0" size="32" />
+    </Register>
+    <Register name="MDMA_C1TBR" description="MDMA channel x Trigger and Bus selection Register" start="+0xA8" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TSEL" description="Trigger selection" start="0" size="6" />
+      <BitField name="SBUS" description="Source BUS select This bit is protected and can be written only if EN is 0." start="16" size="1" />
+      <BitField name="DBUS" description="Destination BUS slect This bit is protected and can be written only if EN is 0." start="17" size="1" />
+    </Register>
+    <Register name="MDMA_C1MAR" description="MDMA channel x Mask address register" start="+0xB0" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MAR" description="Mask address" start="0" size="32" />
+    </Register>
+    <Register name="MDMA_C1MDR" description="MDMA channel x Mask Data register" start="+0xB4" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MDR" description="Mask data" start="0" size="32" />
+    </Register>
+    <Register name="MDMA_C2ISR" description="MDMA channel x interrupt/status register" start="+0xC0" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TEIF2" description="Channel x transfer error interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register." start="0" size="1" />
+      <BitField name="CTCIF2" description="Channel x Channel Transfer Complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register. CTC is set when the last block was transferred and the channel has been automatically disabled. CTC is also set when the channel is suspended, as a result of writing EN bit to 0." start="1" size="1" />
+      <BitField name="BRTIF2" description="Channel x block repeat transfer complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register." start="2" size="1" />
+      <BitField name="BTIF2" description="Channel x block transfer complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register." start="3" size="1" />
+      <BitField name="TCIF2" description="channel x buffer transfer complete" start="4" size="1" />
+      <BitField name="CRQA2" description="channel x request active flag" start="16" size="1" />
+    </Register>
+    <Register name="MDMA_C2IFCR" description="MDMA channel x interrupt flag clear register" start="+0xC4" size="4" access="WriteOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CTEIF2" description="Channel x clear transfer error interrupt flag Writing a 1 into this bit clears TEIFx in the MDMA_ISRy register" start="0" size="1" />
+      <BitField name="CCTCIF2" description="Clear Channel transfer complete interrupt flag for channel x Writing a 1 into this bit clears CTCIFx in the MDMA_ISRy register" start="1" size="1" />
+      <BitField name="CBRTIF2" description="Channel x clear block repeat transfer complete interrupt flag Writing a 1 into this bit clears BRTIFx in the MDMA_ISRy register" start="2" size="1" />
+      <BitField name="CBTIF2" description="Channel x Clear block transfer complete interrupt flag Writing a 1 into this bit clears BTIFx in the MDMA_ISRy register" start="3" size="1" />
+      <BitField name="CLTCIF2" description="CLear buffer Transfer Complete Interrupt Flag for channel x Writing a 1 into this bit clears TCIFx in the MDMA_ISRy register" start="4" size="1" />
+    </Register>
+    <Register name="MDMA_C2ESR" description="MDMA Channel x error status register" start="+0xC8" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TEA" description="Transfer Error Address These bits are set and cleared by HW, in case of an MDMA data transfer error. It is used in conjunction with TED. This field indicates the 7 LSBits of the address which generated a transfer/access error. It may be used by SW to retrieve the failing address, by adding this value (truncated to the buffer transfer length size) to the current SAR/DAR value. Note: The SAR/DAR current value doesnt reflect this last address due to the FIFO management system. The SAR/DAR are only updated at the end of a (buffer) transfer (of TLEN+1 bytes). Note: It is not set in case of a link data error." start="0" size="7" />
+      <BitField name="TED" description="Transfer Error Direction These bit is set and cleared by HW, in case of an MDMA data transfer error." start="7" size="1" />
+      <BitField name="TELD" description="Transfer Error Link Data These bit is set by HW, in case of a transfer error while reading the block link data structure. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register." start="8" size="1" />
+      <BitField name="TEMD" description="Transfer Error Mask Data These bit is set by HW, in case of a transfer error while writing the Mask Data. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register." start="9" size="1" />
+      <BitField name="ASE" description="Address/Size Error These bit is set by HW, when the programmed address is not aligned with the data size. TED will indicate whether the problem is on the source or destination. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register." start="10" size="1" />
+      <BitField name="BSE" description="Block Size Error These bit is set by HW, when the block size is not an integer multiple of the data size either for source or destination. TED will indicate whether the problem is on the source or destination. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register." start="11" size="1" />
+    </Register>
+    <Register name="MDMA_C2CR" description="This register is used to control the concerned channel." start="+0xCC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="channel enable" start="0" size="1" access="Read/Write" />
+      <BitField name="TEIE" description="Transfer error interrupt enable This bit is set and cleared by software." start="1" size="1" access="Read/Write" />
+      <BitField name="CTCIE" description="Channel Transfer Complete interrupt enable This bit is set and cleared by software." start="2" size="1" access="Read/Write" />
+      <BitField name="BRTIE" description="Block Repeat transfer interrupt enable This bit is set and cleared by software." start="3" size="1" access="Read/Write" />
+      <BitField name="BTIE" description="Block Transfer interrupt enable This bit is set and cleared by software." start="4" size="1" access="Read/Write" />
+      <BitField name="TCIE" description="buffer Transfer Complete interrupt enable This bit is set and cleared by software." start="5" size="1" access="Read/Write" />
+      <BitField name="PL" description="Priority level These bits are set and cleared by software. These bits are protected and can be written only if EN is 0." start="6" size="2" access="Read/Write" />
+      <BitField name="BEX" description="byte Endianness exchange" start="12" size="1" access="Read/Write" />
+      <BitField name="HEX" description="Half word Endianes exchange" start="13" size="1" access="Read/Write" />
+      <BitField name="WEX" description="Word Endianness exchange" start="14" size="1" access="Read/Write" />
+      <BitField name="SWRQ" description="SW ReQuest Writing a 1 into this bit sets the CRQAx in MDMA_ISRy register, activating the request on Channel x Note: Either the whole CxCR register or the 8-bit/16-bit register @ Address offset: 0x4E + 0x40 chn may be used for SWRQ activation. In case of a SW request, acknowledge is not generated (neither HW signal, nor CxMAR write access)." start="16" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="MDMA_C2TCR" description="This register is used to configure the concerned channel." start="+0xD0" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SINC" description="Source increment mode These bits are set and cleared by software. These bits are protected and can be written only if EN is 0 Note: When source is AHB (SBUS=1), SINC = 00 is forbidden. In Linked List Mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00)." start="0" size="2" />
+      <BitField name="DINC" description="Destination increment mode These bits are set and cleared by software. These bits are protected and can be written only if EN is 0 Note: When destination is AHB (DBUS=1), DINC = 00 is forbidden." start="2" size="2" />
+      <BitField name="SSIZE" description="Source data size These bits are set and cleared by software. These bits are protected and can be written only if EN is 0 Note: If a value of 11 is programmed for the TCM access/AHB port, a transfer error will occur (TEIF bit set) If SINCOS &amp;lt; SSIZE and SINC &amp;#8800; 00, the result will be unpredictable. Note: SSIZE = 11 (double-word) is forbidden when source is TCM/AHB bus (SBUS=1)." start="4" size="2" />
+      <BitField name="DSIZE" description="Destination data size These bits are set and cleared by software. These bits are protected and can be written only if EN is 0. Note: If a value of 11 is programmed for the TCM access/AHB port, a transfer error will occur (TEIF bit set) If DINCOS &amp;lt; DSIZE and DINC &amp;#8800; 00, the result will be unpredictable. Note: DSIZE = 11 (double-word) is forbidden when destination is TCM/AHB bus (DBUS=1)." start="6" size="2" />
+      <BitField name="SINCOS" description="source increment offset size" start="8" size="2" />
+      <BitField name="DINCOS" description="Destination increment offset" start="10" size="2" />
+      <BitField name="SBURST" description="source burst transfer configuration" start="12" size="3" />
+      <BitField name="DBURST" description="Destination burst transfer configuration" start="15" size="3" />
+      <BitField name="TLEN" description="buffer transfer lengh" start="18" size="7" />
+      <BitField name="PKE" description="PacK Enable These bit is set and cleared by software. If the Source Size is smaller than the destination, it will be padded according to the PAM value. If the Source data size is larger than the destination one, it will be truncated. The alignment will be done according to the PAM[0] value. This bit is protected and can be written only if EN is 0" start="25" size="1" />
+      <BitField name="PAM" description="Padding/Alignement Mode These bits are set and cleared by software. Case 1: Source data size smaller than destination data size - 3 options are valid. Case 2: Source data size larger than destination data size. The remainder part is discarded. When PKE = 1 or DSIZE=SSIZE, these bits are ignored. These bits are protected and can be written only if EN is 0" start="26" size="2" />
+      <BitField name="TRGM" description="Trigger Mode These bits are set and cleared by software. Note: If TRGM is 11 for the current block, all the values loaded at the end of the current block through the linked list mechanism must keep the same value (TRGM=11) and the same SWRM value, otherwise the result is undefined. These bits are protected and can be written only if EN is 0." start="28" size="2" />
+      <BitField name="SWRM" description="SW Request Mode This bit is set and cleared by software. If a HW or SW request is currently active, the bit change will be delayed until the current transfer is completed. If the CxMAR contains a valid address, the CxMDR value will also be written @ CxMAR address. This bit is protected and can be written only if EN is 0." start="30" size="1" />
+      <BitField name="BWM" description="Bufferable Write Mode This bit is set and cleared by software. This bit is protected and can be written only if EN is 0. Note: All MDMA destination accesses are non-cacheable." start="31" size="1" />
+    </Register>
+    <Register name="MDMA_C2BNDTR" description="MDMA Channel x block number of data register" start="+0xD4" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BNDT" description="block number of data to transfer" start="0" size="17" />
+      <BitField name="BRSUM" description="Block Repeat Source address Update Mode These bits are protected and can be written only if EN is 0." start="18" size="1" />
+      <BitField name="BRDUM" description="Block Repeat Destination address Update Mode These bits are protected and can be written only if EN is 0." start="19" size="1" />
+      <BitField name="BRC" description="Block Repeat Count This field contains the number of repetitions of the current block (0 to 4095). When the channel is enabled, this register is read-only, indicating the remaining number of blocks, excluding the current one. This register decrements after each complete block transfer. Once the last block transfer has completed, this register can either stay at zero or be reloaded automatically from memory (in Linked List mode - i.e. Link Address valid). These bits are protected and can be written only if EN is 0." start="20" size="12" />
+    </Register>
+    <Register name="MDMA_C2SAR" description="MDMA channel x source address register" start="+0xD8" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SAR" description="source adr base" start="0" size="32" />
+    </Register>
+    <Register name="MDMA_C2DAR" description="MDMA channel x destination address register" start="+0xDC" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DAR" description="Destination adr base" start="0" size="32" />
+    </Register>
+    <Register name="MDMA_C2BRUR" description="MDMA channel x Block Repeat address Update register" start="+0xE0" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SUV" description="source adresse update value" start="0" size="16" />
+      <BitField name="DUV" description="destination address update" start="16" size="16" />
+    </Register>
+    <Register name="MDMA_C2LAR" description="MDMA channel x Link Address register" start="+0xE4" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LAR" description="Link address register" start="0" size="32" />
+    </Register>
+    <Register name="MDMA_C2TBR" description="MDMA channel x Trigger and Bus selection Register" start="+0xE8" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TSEL" description="Trigger selection" start="0" size="6" />
+      <BitField name="SBUS" description="Source BUS select This bit is protected and can be written only if EN is 0." start="16" size="1" />
+      <BitField name="DBUS" description="Destination BUS slect This bit is protected and can be written only if EN is 0." start="17" size="1" />
+    </Register>
+    <Register name="MDMA_C2MAR" description="MDMA channel x Mask address register" start="+0xF0" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MAR" description="Mask address" start="0" size="32" />
+    </Register>
+    <Register name="MDMA_C2MDR" description="MDMA channel x Mask Data register" start="+0xF4" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MDR" description="Mask data" start="0" size="32" />
+    </Register>
+    <Register name="MDMA_C3ISR" description="MDMA channel x interrupt/status register" start="+0x100" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TEIF3" description="Channel x transfer error interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register." start="0" size="1" />
+      <BitField name="CTCIF3" description="Channel x Channel Transfer Complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register. CTC is set when the last block was transferred and the channel has been automatically disabled. CTC is also set when the channel is suspended, as a result of writing EN bit to 0." start="1" size="1" />
+      <BitField name="BRTIF3" description="Channel x block repeat transfer complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register." start="2" size="1" />
+      <BitField name="BTIF3" description="Channel x block transfer complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register." start="3" size="1" />
+      <BitField name="TCIF3" description="channel x buffer transfer complete" start="4" size="1" />
+      <BitField name="CRQA3" description="channel x request active flag" start="16" size="1" />
+    </Register>
+    <Register name="MDMA_C3IFCR" description="MDMA channel x interrupt flag clear register" start="+0x104" size="4" access="WriteOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CTEIF3" description="Channel x clear transfer error interrupt flag Writing a 1 into this bit clears TEIFx in the MDMA_ISRy register" start="0" size="1" />
+      <BitField name="CCTCIF3" description="Clear Channel transfer complete interrupt flag for channel x Writing a 1 into this bit clears CTCIFx in the MDMA_ISRy register" start="1" size="1" />
+      <BitField name="CBRTIF3" description="Channel x clear block repeat transfer complete interrupt flag Writing a 1 into this bit clears BRTIFx in the MDMA_ISRy register" start="2" size="1" />
+      <BitField name="CBTIF3" description="Channel x Clear block transfer complete interrupt flag Writing a 1 into this bit clears BTIFx in the MDMA_ISRy register" start="3" size="1" />
+      <BitField name="CLTCIF3" description="CLear buffer Transfer Complete Interrupt Flag for channel x Writing a 1 into this bit clears TCIFx in the MDMA_ISRy register" start="4" size="1" />
+    </Register>
+    <Register name="MDMA_C3ESR" description="MDMA Channel x error status register" start="+0x108" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TEA" description="Transfer Error Address These bits are set and cleared by HW, in case of an MDMA data transfer error. It is used in conjunction with TED. This field indicates the 7 LSBits of the address which generated a transfer/access error. It may be used by SW to retrieve the failing address, by adding this value (truncated to the buffer transfer length size) to the current SAR/DAR value. Note: The SAR/DAR current value doesnt reflect this last address due to the FIFO management system. The SAR/DAR are only updated at the end of a (buffer) transfer (of TLEN+1 bytes). Note: It is not set in case of a link data error." start="0" size="7" />
+      <BitField name="TED" description="Transfer Error Direction These bit is set and cleared by HW, in case of an MDMA data transfer error." start="7" size="1" />
+      <BitField name="TELD" description="Transfer Error Link Data These bit is set by HW, in case of a transfer error while reading the block link data structure. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register." start="8" size="1" />
+      <BitField name="TEMD" description="Transfer Error Mask Data These bit is set by HW, in case of a transfer error while writing the Mask Data. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register." start="9" size="1" />
+      <BitField name="ASE" description="Address/Size Error These bit is set by HW, when the programmed address is not aligned with the data size. TED will indicate whether the problem is on the source or destination. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register." start="10" size="1" />
+      <BitField name="BSE" description="Block Size Error These bit is set by HW, when the block size is not an integer multiple of the data size either for source or destination. TED will indicate whether the problem is on the source or destination. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register." start="11" size="1" />
+    </Register>
+    <Register name="MDMA_C3CR" description="This register is used to control the concerned channel." start="+0x10C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="channel enable" start="0" size="1" access="Read/Write" />
+      <BitField name="TEIE" description="Transfer error interrupt enable This bit is set and cleared by software." start="1" size="1" access="Read/Write" />
+      <BitField name="CTCIE" description="Channel Transfer Complete interrupt enable This bit is set and cleared by software." start="2" size="1" access="Read/Write" />
+      <BitField name="BRTIE" description="Block Repeat transfer interrupt enable This bit is set and cleared by software." start="3" size="1" access="Read/Write" />
+      <BitField name="BTIE" description="Block Transfer interrupt enable This bit is set and cleared by software." start="4" size="1" access="Read/Write" />
+      <BitField name="TCIE" description="buffer Transfer Complete interrupt enable This bit is set and cleared by software." start="5" size="1" access="Read/Write" />
+      <BitField name="PL" description="Priority level These bits are set and cleared by software. These bits are protected and can be written only if EN is 0." start="6" size="2" access="Read/Write" />
+      <BitField name="BEX" description="byte Endianness exchange" start="12" size="1" access="Read/Write" />
+      <BitField name="HEX" description="Half word Endianes exchange" start="13" size="1" access="Read/Write" />
+      <BitField name="WEX" description="Word Endianness exchange" start="14" size="1" access="Read/Write" />
+      <BitField name="SWRQ" description="SW ReQuest Writing a 1 into this bit sets the CRQAx in MDMA_ISRy register, activating the request on Channel x Note: Either the whole CxCR register or the 8-bit/16-bit register @ Address offset: 0x4E + 0x40 chn may be used for SWRQ activation. In case of a SW request, acknowledge is not generated (neither HW signal, nor CxMAR write access)." start="16" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="MDMA_C3TCR" description="This register is used to configure the concerned channel." start="+0x110" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SINC" description="Source increment mode These bits are set and cleared by software. These bits are protected and can be written only if EN is 0 Note: When source is AHB (SBUS=1), SINC = 00 is forbidden. In Linked List Mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00)." start="0" size="2" />
+      <BitField name="DINC" description="Destination increment mode These bits are set and cleared by software. These bits are protected and can be written only if EN is 0 Note: When destination is AHB (DBUS=1), DINC = 00 is forbidden." start="2" size="2" />
+      <BitField name="SSIZE" description="Source data size These bits are set and cleared by software. These bits are protected and can be written only if EN is 0 Note: If a value of 11 is programmed for the TCM access/AHB port, a transfer error will occur (TEIF bit set) If SINCOS &amp;lt; SSIZE and SINC &amp;#8800; 00, the result will be unpredictable. Note: SSIZE = 11 (double-word) is forbidden when source is TCM/AHB bus (SBUS=1)." start="4" size="2" />
+      <BitField name="DSIZE" description="Destination data size These bits are set and cleared by software. These bits are protected and can be written only if EN is 0. Note: If a value of 11 is programmed for the TCM access/AHB port, a transfer error will occur (TEIF bit set) If DINCOS &amp;lt; DSIZE and DINC &amp;#8800; 00, the result will be unpredictable. Note: DSIZE = 11 (double-word) is forbidden when destination is TCM/AHB bus (DBUS=1)." start="6" size="2" />
+      <BitField name="SINCOS" description="source increment offset size" start="8" size="2" />
+      <BitField name="DINCOS" description="Destination increment offset" start="10" size="2" />
+      <BitField name="SBURST" description="source burst transfer configuration" start="12" size="3" />
+      <BitField name="DBURST" description="Destination burst transfer configuration" start="15" size="3" />
+      <BitField name="TLEN" description="buffer transfer lengh" start="18" size="7" />
+      <BitField name="PKE" description="PacK Enable These bit is set and cleared by software. If the Source Size is smaller than the destination, it will be padded according to the PAM value. If the Source data size is larger than the destination one, it will be truncated. The alignment will be done according to the PAM[0] value. This bit is protected and can be written only if EN is 0" start="25" size="1" />
+      <BitField name="PAM" description="Padding/Alignement Mode These bits are set and cleared by software. Case 1: Source data size smaller than destination data size - 3 options are valid. Case 2: Source data size larger than destination data size. The remainder part is discarded. When PKE = 1 or DSIZE=SSIZE, these bits are ignored. These bits are protected and can be written only if EN is 0" start="26" size="2" />
+      <BitField name="TRGM" description="Trigger Mode These bits are set and cleared by software. Note: If TRGM is 11 for the current block, all the values loaded at the end of the current block through the linked list mechanism must keep the same value (TRGM=11) and the same SWRM value, otherwise the result is undefined. These bits are protected and can be written only if EN is 0." start="28" size="2" />
+      <BitField name="SWRM" description="SW Request Mode This bit is set and cleared by software. If a HW or SW request is currently active, the bit change will be delayed until the current transfer is completed. If the CxMAR contains a valid address, the CxMDR value will also be written @ CxMAR address. This bit is protected and can be written only if EN is 0." start="30" size="1" />
+      <BitField name="BWM" description="Bufferable Write Mode This bit is set and cleared by software. This bit is protected and can be written only if EN is 0. Note: All MDMA destination accesses are non-cacheable." start="31" size="1" />
+    </Register>
+    <Register name="MDMA_C3BNDTR" description="MDMA Channel x block number of data register" start="+0x114" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BNDT" description="block number of data to transfer" start="0" size="17" />
+      <BitField name="BRSUM" description="Block Repeat Source address Update Mode These bits are protected and can be written only if EN is 0." start="18" size="1" />
+      <BitField name="BRDUM" description="Block Repeat Destination address Update Mode These bits are protected and can be written only if EN is 0." start="19" size="1" />
+      <BitField name="BRC" description="Block Repeat Count This field contains the number of repetitions of the current block (0 to 4095). When the channel is enabled, this register is read-only, indicating the remaining number of blocks, excluding the current one. This register decrements after each complete block transfer. Once the last block transfer has completed, this register can either stay at zero or be reloaded automatically from memory (in Linked List mode - i.e. Link Address valid). These bits are protected and can be written only if EN is 0." start="20" size="12" />
+    </Register>
+    <Register name="MDMA_C3SAR" description="MDMA channel x source address register" start="+0x118" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SAR" description="source adr base" start="0" size="32" />
+    </Register>
+    <Register name="MDMA_C3DAR" description="MDMA channel x destination address register" start="+0x11C" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DAR" description="Destination adr base" start="0" size="32" />
+    </Register>
+    <Register name="MDMA_C3BRUR" description="MDMA channel x Block Repeat address Update register" start="+0x120" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SUV" description="source adresse update value" start="0" size="16" />
+      <BitField name="DUV" description="destination address update" start="16" size="16" />
+    </Register>
+    <Register name="MDMA_C3LAR" description="MDMA channel x Link Address register" start="+0x124" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LAR" description="Link address register" start="0" size="32" />
+    </Register>
+    <Register name="MDMA_C3TBR" description="MDMA channel x Trigger and Bus selection Register" start="+0x128" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TSEL" description="Trigger selection" start="0" size="6" />
+      <BitField name="SBUS" description="Source BUS select This bit is protected and can be written only if EN is 0." start="16" size="1" />
+      <BitField name="DBUS" description="Destination BUS slect This bit is protected and can be written only if EN is 0." start="17" size="1" />
+    </Register>
+    <Register name="MDMA_C3MAR" description="MDMA channel x Mask address register" start="+0x130" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MAR" description="Mask address" start="0" size="32" />
+    </Register>
+    <Register name="MDMA_C3MDR" description="MDMA channel x Mask Data register" start="+0x134" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MDR" description="Mask data" start="0" size="32" />
+    </Register>
+    <Register name="MDMA_C4ISR" description="MDMA channel x interrupt/status register" start="+0x140" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TEIF4" description="Channel x transfer error interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register." start="0" size="1" />
+      <BitField name="CTCIF4" description="Channel x Channel Transfer Complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register. CTC is set when the last block was transferred and the channel has been automatically disabled. CTC is also set when the channel is suspended, as a result of writing EN bit to 0." start="1" size="1" />
+      <BitField name="BRTIF4" description="Channel x block repeat transfer complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register." start="2" size="1" />
+      <BitField name="BTIF4" description="Channel x block transfer complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register." start="3" size="1" />
+      <BitField name="TCIF4" description="channel x buffer transfer complete" start="4" size="1" />
+      <BitField name="CRQA4" description="channel x request active flag" start="16" size="1" />
+    </Register>
+    <Register name="MDMA_C4IFCR" description="MDMA channel x interrupt flag clear register" start="+0x144" size="4" access="WriteOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CTEIF4" description="Channel x clear transfer error interrupt flag Writing a 1 into this bit clears TEIFx in the MDMA_ISRy register" start="0" size="1" />
+      <BitField name="CCTCIF4" description="Clear Channel transfer complete interrupt flag for channel x Writing a 1 into this bit clears CTCIFx in the MDMA_ISRy register" start="1" size="1" />
+      <BitField name="CBRTIF4" description="Channel x clear block repeat transfer complete interrupt flag Writing a 1 into this bit clears BRTIFx in the MDMA_ISRy register" start="2" size="1" />
+      <BitField name="CBTIF4" description="Channel x Clear block transfer complete interrupt flag Writing a 1 into this bit clears BTIFx in the MDMA_ISRy register" start="3" size="1" />
+      <BitField name="CLTCIF4" description="CLear buffer Transfer Complete Interrupt Flag for channel x Writing a 1 into this bit clears TCIFx in the MDMA_ISRy register" start="4" size="1" />
+    </Register>
+    <Register name="MDMA_C4ESR" description="MDMA Channel x error status register" start="+0x148" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TEA" description="Transfer Error Address These bits are set and cleared by HW, in case of an MDMA data transfer error. It is used in conjunction with TED. This field indicates the 7 LSBits of the address which generated a transfer/access error. It may be used by SW to retrieve the failing address, by adding this value (truncated to the buffer transfer length size) to the current SAR/DAR value. Note: The SAR/DAR current value doesnt reflect this last address due to the FIFO management system. The SAR/DAR are only updated at the end of a (buffer) transfer (of TLEN+1 bytes). Note: It is not set in case of a link data error." start="0" size="7" />
+      <BitField name="TED" description="Transfer Error Direction These bit is set and cleared by HW, in case of an MDMA data transfer error." start="7" size="1" />
+      <BitField name="TELD" description="Transfer Error Link Data These bit is set by HW, in case of a transfer error while reading the block link data structure. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register." start="8" size="1" />
+      <BitField name="TEMD" description="Transfer Error Mask Data These bit is set by HW, in case of a transfer error while writing the Mask Data. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register." start="9" size="1" />
+      <BitField name="ASE" description="Address/Size Error These bit is set by HW, when the programmed address is not aligned with the data size. TED will indicate whether the problem is on the source or destination. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register." start="10" size="1" />
+      <BitField name="BSE" description="Block Size Error These bit is set by HW, when the block size is not an integer multiple of the data size either for source or destination. TED will indicate whether the problem is on the source or destination. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register." start="11" size="1" />
+    </Register>
+    <Register name="MDMA_C4CR" description="This register is used to control the concerned channel." start="+0x14C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="channel enable" start="0" size="1" access="Read/Write" />
+      <BitField name="TEIE" description="Transfer error interrupt enable This bit is set and cleared by software." start="1" size="1" access="Read/Write" />
+      <BitField name="CTCIE" description="Channel Transfer Complete interrupt enable This bit is set and cleared by software." start="2" size="1" access="Read/Write" />
+      <BitField name="BRTIE" description="Block Repeat transfer interrupt enable This bit is set and cleared by software." start="3" size="1" access="Read/Write" />
+      <BitField name="BTIE" description="Block Transfer interrupt enable This bit is set and cleared by software." start="4" size="1" access="Read/Write" />
+      <BitField name="TCIE" description="buffer Transfer Complete interrupt enable This bit is set and cleared by software." start="5" size="1" access="Read/Write" />
+      <BitField name="PL" description="Priority level These bits are set and cleared by software. These bits are protected and can be written only if EN is 0." start="6" size="2" access="Read/Write" />
+      <BitField name="BEX" description="byte Endianness exchange" start="12" size="1" access="Read/Write" />
+      <BitField name="HEX" description="Half word Endianes exchange" start="13" size="1" access="Read/Write" />
+      <BitField name="WEX" description="Word Endianness exchange" start="14" size="1" access="Read/Write" />
+      <BitField name="SWRQ" description="SW ReQuest Writing a 1 into this bit sets the CRQAx in MDMA_ISRy register, activating the request on Channel x Note: Either the whole CxCR register or the 8-bit/16-bit register @ Address offset: 0x4E + 0x40 chn may be used for SWRQ activation. In case of a SW request, acknowledge is not generated (neither HW signal, nor CxMAR write access)." start="16" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="MDMA_C4TCR" description="This register is used to configure the concerned channel." start="+0x150" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SINC" description="Source increment mode These bits are set and cleared by software. These bits are protected and can be written only if EN is 0 Note: When source is AHB (SBUS=1), SINC = 00 is forbidden. In Linked List Mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00)." start="0" size="2" />
+      <BitField name="DINC" description="Destination increment mode These bits are set and cleared by software. These bits are protected and can be written only if EN is 0 Note: When destination is AHB (DBUS=1), DINC = 00 is forbidden." start="2" size="2" />
+      <BitField name="SSIZE" description="Source data size These bits are set and cleared by software. These bits are protected and can be written only if EN is 0 Note: If a value of 11 is programmed for the TCM access/AHB port, a transfer error will occur (TEIF bit set) If SINCOS &amp;lt; SSIZE and SINC &amp;#8800; 00, the result will be unpredictable. Note: SSIZE = 11 (double-word) is forbidden when source is TCM/AHB bus (SBUS=1)." start="4" size="2" />
+      <BitField name="DSIZE" description="Destination data size These bits are set and cleared by software. These bits are protected and can be written only if EN is 0. Note: If a value of 11 is programmed for the TCM access/AHB port, a transfer error will occur (TEIF bit set) If DINCOS &amp;lt; DSIZE and DINC &amp;#8800; 00, the result will be unpredictable. Note: DSIZE = 11 (double-word) is forbidden when destination is TCM/AHB bus (DBUS=1)." start="6" size="2" />
+      <BitField name="SINCOS" description="source increment offset size" start="8" size="2" />
+      <BitField name="DINCOS" description="Destination increment offset" start="10" size="2" />
+      <BitField name="SBURST" description="source burst transfer configuration" start="12" size="3" />
+      <BitField name="DBURST" description="Destination burst transfer configuration" start="15" size="3" />
+      <BitField name="TLEN" description="buffer transfer lengh" start="18" size="7" />
+      <BitField name="PKE" description="PacK Enable These bit is set and cleared by software. If the Source Size is smaller than the destination, it will be padded according to the PAM value. If the Source data size is larger than the destination one, it will be truncated. The alignment will be done according to the PAM[0] value. This bit is protected and can be written only if EN is 0" start="25" size="1" />
+      <BitField name="PAM" description="Padding/Alignement Mode These bits are set and cleared by software. Case 1: Source data size smaller than destination data size - 3 options are valid. Case 2: Source data size larger than destination data size. The remainder part is discarded. When PKE = 1 or DSIZE=SSIZE, these bits are ignored. These bits are protected and can be written only if EN is 0" start="26" size="2" />
+      <BitField name="TRGM" description="Trigger Mode These bits are set and cleared by software. Note: If TRGM is 11 for the current block, all the values loaded at the end of the current block through the linked list mechanism must keep the same value (TRGM=11) and the same SWRM value, otherwise the result is undefined. These bits are protected and can be written only if EN is 0." start="28" size="2" />
+      <BitField name="SWRM" description="SW Request Mode This bit is set and cleared by software. If a HW or SW request is currently active, the bit change will be delayed until the current transfer is completed. If the CxMAR contains a valid address, the CxMDR value will also be written @ CxMAR address. This bit is protected and can be written only if EN is 0." start="30" size="1" />
+      <BitField name="BWM" description="Bufferable Write Mode This bit is set and cleared by software. This bit is protected and can be written only if EN is 0. Note: All MDMA destination accesses are non-cacheable." start="31" size="1" />
+    </Register>
+    <Register name="MDMA_C4BNDTR" description="MDMA Channel x block number of data register" start="+0x154" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BNDT" description="block number of data to transfer" start="0" size="17" />
+      <BitField name="BRSUM" description="Block Repeat Source address Update Mode These bits are protected and can be written only if EN is 0." start="18" size="1" />
+      <BitField name="BRDUM" description="Block Repeat Destination address Update Mode These bits are protected and can be written only if EN is 0." start="19" size="1" />
+      <BitField name="BRC" description="Block Repeat Count This field contains the number of repetitions of the current block (0 to 4095). When the channel is enabled, this register is read-only, indicating the remaining number of blocks, excluding the current one. This register decrements after each complete block transfer. Once the last block transfer has completed, this register can either stay at zero or be reloaded automatically from memory (in Linked List mode - i.e. Link Address valid). These bits are protected and can be written only if EN is 0." start="20" size="12" />
+    </Register>
+    <Register name="MDMA_C4SAR" description="MDMA channel x source address register" start="+0x158" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SAR" description="source adr base" start="0" size="32" />
+    </Register>
+    <Register name="MDMA_C4DAR" description="MDMA channel x destination address register" start="+0x15C" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DAR" description="Destination adr base" start="0" size="32" />
+    </Register>
+    <Register name="MDMA_C4BRUR" description="MDMA channel x Block Repeat address Update register" start="+0x160" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SUV" description="source adresse update value" start="0" size="16" />
+      <BitField name="DUV" description="destination address update" start="16" size="16" />
+    </Register>
+    <Register name="MDMA_C4LAR" description="MDMA channel x Link Address register" start="+0x164" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LAR" description="Link address register" start="0" size="32" />
+    </Register>
+    <Register name="MDMA_C4TBR" description="MDMA channel x Trigger and Bus selection Register" start="+0x168" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TSEL" description="Trigger selection" start="0" size="6" />
+      <BitField name="SBUS" description="Source BUS select This bit is protected and can be written only if EN is 0." start="16" size="1" />
+      <BitField name="DBUS" description="Destination BUS slect This bit is protected and can be written only if EN is 0." start="17" size="1" />
+    </Register>
+    <Register name="MDMA_C4MAR" description="MDMA channel x Mask address register" start="+0x170" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MAR" description="Mask address" start="0" size="32" />
+    </Register>
+    <Register name="MDMA_C4MDR" description="MDMA channel x Mask Data register" start="+0x174" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MDR" description="Mask data" start="0" size="32" />
+    </Register>
+    <Register name="MDMA_C5ISR" description="MDMA channel x interrupt/status register" start="+0x180" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TEIF5" description="Channel x transfer error interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register." start="0" size="1" />
+      <BitField name="CTCIF5" description="Channel x Channel Transfer Complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register. CTC is set when the last block was transferred and the channel has been automatically disabled. CTC is also set when the channel is suspended, as a result of writing EN bit to 0." start="1" size="1" />
+      <BitField name="BRTIF5" description="Channel x block repeat transfer complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register." start="2" size="1" />
+      <BitField name="BTIF5" description="Channel x block transfer complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register." start="3" size="1" />
+      <BitField name="TCIF5" description="channel x buffer transfer complete" start="4" size="1" />
+      <BitField name="CRQA5" description="channel x request active flag" start="16" size="1" />
+    </Register>
+    <Register name="MDMA_C5IFCR" description="MDMA channel x interrupt flag clear register" start="+0x184" size="4" access="WriteOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CTEIF5" description="Channel x clear transfer error interrupt flag Writing a 1 into this bit clears TEIFx in the MDMA_ISRy register" start="0" size="1" />
+      <BitField name="CCTCIF5" description="Clear Channel transfer complete interrupt flag for channel x Writing a 1 into this bit clears CTCIFx in the MDMA_ISRy register" start="1" size="1" />
+      <BitField name="CBRTIF5" description="Channel x clear block repeat transfer complete interrupt flag Writing a 1 into this bit clears BRTIFx in the MDMA_ISRy register" start="2" size="1" />
+      <BitField name="CBTIF5" description="Channel x Clear block transfer complete interrupt flag Writing a 1 into this bit clears BTIFx in the MDMA_ISRy register" start="3" size="1" />
+      <BitField name="CLTCIF5" description="CLear buffer Transfer Complete Interrupt Flag for channel x Writing a 1 into this bit clears TCIFx in the MDMA_ISRy register" start="4" size="1" />
+    </Register>
+    <Register name="MDMA_C5ESR" description="MDMA Channel x error status register" start="+0x188" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TEA" description="Transfer Error Address These bits are set and cleared by HW, in case of an MDMA data transfer error. It is used in conjunction with TED. This field indicates the 7 LSBits of the address which generated a transfer/access error. It may be used by SW to retrieve the failing address, by adding this value (truncated to the buffer transfer length size) to the current SAR/DAR value. Note: The SAR/DAR current value doesnt reflect this last address due to the FIFO management system. The SAR/DAR are only updated at the end of a (buffer) transfer (of TLEN+1 bytes). Note: It is not set in case of a link data error." start="0" size="7" />
+      <BitField name="TED" description="Transfer Error Direction These bit is set and cleared by HW, in case of an MDMA data transfer error." start="7" size="1" />
+      <BitField name="TELD" description="Transfer Error Link Data These bit is set by HW, in case of a transfer error while reading the block link data structure. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register." start="8" size="1" />
+      <BitField name="TEMD" description="Transfer Error Mask Data These bit is set by HW, in case of a transfer error while writing the Mask Data. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register." start="9" size="1" />
+      <BitField name="ASE" description="Address/Size Error These bit is set by HW, when the programmed address is not aligned with the data size. TED will indicate whether the problem is on the source or destination. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register." start="10" size="1" />
+      <BitField name="BSE" description="Block Size Error These bit is set by HW, when the block size is not an integer multiple of the data size either for source or destination. TED will indicate whether the problem is on the source or destination. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register." start="11" size="1" />
+    </Register>
+    <Register name="MDMA_C5CR" description="This register is used to control the concerned channel." start="+0x18C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="channel enable" start="0" size="1" access="Read/Write" />
+      <BitField name="TEIE" description="Transfer error interrupt enable This bit is set and cleared by software." start="1" size="1" access="Read/Write" />
+      <BitField name="CTCIE" description="Channel Transfer Complete interrupt enable This bit is set and cleared by software." start="2" size="1" access="Read/Write" />
+      <BitField name="BRTIE" description="Block Repeat transfer interrupt enable This bit is set and cleared by software." start="3" size="1" access="Read/Write" />
+      <BitField name="BTIE" description="Block Transfer interrupt enable This bit is set and cleared by software." start="4" size="1" access="Read/Write" />
+      <BitField name="TCIE" description="buffer Transfer Complete interrupt enable This bit is set and cleared by software." start="5" size="1" access="Read/Write" />
+      <BitField name="PL" description="Priority level These bits are set and cleared by software. These bits are protected and can be written only if EN is 0." start="6" size="2" access="Read/Write" />
+      <BitField name="BEX" description="byte Endianness exchange" start="12" size="1" access="Read/Write" />
+      <BitField name="HEX" description="Half word Endianes exchange" start="13" size="1" access="Read/Write" />
+      <BitField name="WEX" description="Word Endianness exchange" start="14" size="1" access="Read/Write" />
+      <BitField name="SWRQ" description="SW ReQuest Writing a 1 into this bit sets the CRQAx in MDMA_ISRy register, activating the request on Channel x Note: Either the whole CxCR register or the 8-bit/16-bit register @ Address offset: 0x4E + 0x40 chn may be used for SWRQ activation. In case of a SW request, acknowledge is not generated (neither HW signal, nor CxMAR write access)." start="16" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="MDMA_C5TCR" description="This register is used to configure the concerned channel." start="+0x190" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SINC" description="Source increment mode These bits are set and cleared by software. These bits are protected and can be written only if EN is 0 Note: When source is AHB (SBUS=1), SINC = 00 is forbidden. In Linked List Mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00)." start="0" size="2" />
+      <BitField name="DINC" description="Destination increment mode These bits are set and cleared by software. These bits are protected and can be written only if EN is 0 Note: When destination is AHB (DBUS=1), DINC = 00 is forbidden." start="2" size="2" />
+      <BitField name="SSIZE" description="Source data size These bits are set and cleared by software. These bits are protected and can be written only if EN is 0 Note: If a value of 11 is programmed for the TCM access/AHB port, a transfer error will occur (TEIF bit set) If SINCOS &amp;lt; SSIZE and SINC &amp;#8800; 00, the result will be unpredictable. Note: SSIZE = 11 (double-word) is forbidden when source is TCM/AHB bus (SBUS=1)." start="4" size="2" />
+      <BitField name="DSIZE" description="Destination data size These bits are set and cleared by software. These bits are protected and can be written only if EN is 0. Note: If a value of 11 is programmed for the TCM access/AHB port, a transfer error will occur (TEIF bit set) If DINCOS &amp;lt; DSIZE and DINC &amp;#8800; 00, the result will be unpredictable. Note: DSIZE = 11 (double-word) is forbidden when destination is TCM/AHB bus (DBUS=1)." start="6" size="2" />
+      <BitField name="SINCOS" description="source increment offset size" start="8" size="2" />
+      <BitField name="DINCOS" description="Destination increment offset" start="10" size="2" />
+      <BitField name="SBURST" description="source burst transfer configuration" start="12" size="3" />
+      <BitField name="DBURST" description="Destination burst transfer configuration" start="15" size="3" />
+      <BitField name="TLEN" description="buffer transfer lengh" start="18" size="7" />
+      <BitField name="PKE" description="PacK Enable These bit is set and cleared by software. If the Source Size is smaller than the destination, it will be padded according to the PAM value. If the Source data size is larger than the destination one, it will be truncated. The alignment will be done according to the PAM[0] value. This bit is protected and can be written only if EN is 0" start="25" size="1" />
+      <BitField name="PAM" description="Padding/Alignement Mode These bits are set and cleared by software. Case 1: Source data size smaller than destination data size - 3 options are valid. Case 2: Source data size larger than destination data size. The remainder part is discarded. When PKE = 1 or DSIZE=SSIZE, these bits are ignored. These bits are protected and can be written only if EN is 0" start="26" size="2" />
+      <BitField name="TRGM" description="Trigger Mode These bits are set and cleared by software. Note: If TRGM is 11 for the current block, all the values loaded at the end of the current block through the linked list mechanism must keep the same value (TRGM=11) and the same SWRM value, otherwise the result is undefined. These bits are protected and can be written only if EN is 0." start="28" size="2" />
+      <BitField name="SWRM" description="SW Request Mode This bit is set and cleared by software. If a HW or SW request is currently active, the bit change will be delayed until the current transfer is completed. If the CxMAR contains a valid address, the CxMDR value will also be written @ CxMAR address. This bit is protected and can be written only if EN is 0." start="30" size="1" />
+      <BitField name="BWM" description="Bufferable Write Mode This bit is set and cleared by software. This bit is protected and can be written only if EN is 0. Note: All MDMA destination accesses are non-cacheable." start="31" size="1" />
+    </Register>
+    <Register name="MDMA_C5BNDTR" description="MDMA Channel x block number of data register" start="+0x194" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BNDT" description="block number of data to transfer" start="0" size="17" />
+      <BitField name="BRSUM" description="Block Repeat Source address Update Mode These bits are protected and can be written only if EN is 0." start="18" size="1" />
+      <BitField name="BRDUM" description="Block Repeat Destination address Update Mode These bits are protected and can be written only if EN is 0." start="19" size="1" />
+      <BitField name="BRC" description="Block Repeat Count This field contains the number of repetitions of the current block (0 to 4095). When the channel is enabled, this register is read-only, indicating the remaining number of blocks, excluding the current one. This register decrements after each complete block transfer. Once the last block transfer has completed, this register can either stay at zero or be reloaded automatically from memory (in Linked List mode - i.e. Link Address valid). These bits are protected and can be written only if EN is 0." start="20" size="12" />
+    </Register>
+    <Register name="MDMA_C5SAR" description="MDMA channel x source address register" start="+0x198" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SAR" description="source adr base" start="0" size="32" />
+    </Register>
+    <Register name="MDMA_C5DAR" description="MDMA channel x destination address register" start="+0x19C" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DAR" description="Destination adr base" start="0" size="32" />
+    </Register>
+    <Register name="MDMA_C5BRUR" description="MDMA channel x Block Repeat address Update register" start="+0x1A0" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SUV" description="source adresse update value" start="0" size="16" />
+      <BitField name="DUV" description="destination address update" start="16" size="16" />
+    </Register>
+    <Register name="MDMA_C5LAR" description="MDMA channel x Link Address register" start="+0x1A4" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LAR" description="Link address register" start="0" size="32" />
+    </Register>
+    <Register name="MDMA_C5TBR" description="MDMA channel x Trigger and Bus selection Register" start="+0x1A8" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TSEL" description="Trigger selection" start="0" size="6" />
+      <BitField name="SBUS" description="Source BUS select This bit is protected and can be written only if EN is 0." start="16" size="1" />
+      <BitField name="DBUS" description="Destination BUS slect This bit is protected and can be written only if EN is 0." start="17" size="1" />
+    </Register>
+    <Register name="MDMA_C5MAR" description="MDMA channel x Mask address register" start="+0x1B0" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MAR" description="Mask address" start="0" size="32" />
+    </Register>
+    <Register name="MDMA_C5MDR" description="MDMA channel x Mask Data register" start="+0x1B4" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MDR" description="Mask data" start="0" size="32" />
+    </Register>
+    <Register name="MDMA_C6ISR" description="MDMA channel x interrupt/status register" start="+0x1C0" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TEIF6" description="Channel x transfer error interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register." start="0" size="1" />
+      <BitField name="CTCIF6" description="Channel x Channel Transfer Complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register. CTC is set when the last block was transferred and the channel has been automatically disabled. CTC is also set when the channel is suspended, as a result of writing EN bit to 0." start="1" size="1" />
+      <BitField name="BRTIF6" description="Channel x block repeat transfer complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register." start="2" size="1" />
+      <BitField name="BTIF6" description="Channel x block transfer complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register." start="3" size="1" />
+      <BitField name="TCIF6" description="channel x buffer transfer complete" start="4" size="1" />
+      <BitField name="CRQA6" description="channel x request active flag" start="16" size="1" />
+    </Register>
+    <Register name="MDMA_C6IFCR" description="MDMA channel x interrupt flag clear register" start="+0x1C4" size="4" access="WriteOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CTEIF6" description="Channel x clear transfer error interrupt flag Writing a 1 into this bit clears TEIFx in the MDMA_ISRy register" start="0" size="1" />
+      <BitField name="CCTCIF6" description="Clear Channel transfer complete interrupt flag for channel x Writing a 1 into this bit clears CTCIFx in the MDMA_ISRy register" start="1" size="1" />
+      <BitField name="CBRTIF6" description="Channel x clear block repeat transfer complete interrupt flag Writing a 1 into this bit clears BRTIFx in the MDMA_ISRy register" start="2" size="1" />
+      <BitField name="CBTIF6" description="Channel x Clear block transfer complete interrupt flag Writing a 1 into this bit clears BTIFx in the MDMA_ISRy register" start="3" size="1" />
+      <BitField name="CLTCIF6" description="CLear buffer Transfer Complete Interrupt Flag for channel x Writing a 1 into this bit clears TCIFx in the MDMA_ISRy register" start="4" size="1" />
+    </Register>
+    <Register name="MDMA_C6ESR" description="MDMA Channel x error status register" start="+0x1C8" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TEA" description="Transfer Error Address These bits are set and cleared by HW, in case of an MDMA data transfer error. It is used in conjunction with TED. This field indicates the 7 LSBits of the address which generated a transfer/access error. It may be used by SW to retrieve the failing address, by adding this value (truncated to the buffer transfer length size) to the current SAR/DAR value. Note: The SAR/DAR current value doesnt reflect this last address due to the FIFO management system. The SAR/DAR are only updated at the end of a (buffer) transfer (of TLEN+1 bytes). Note: It is not set in case of a link data error." start="0" size="7" />
+      <BitField name="TED" description="Transfer Error Direction These bit is set and cleared by HW, in case of an MDMA data transfer error." start="7" size="1" />
+      <BitField name="TELD" description="Transfer Error Link Data These bit is set by HW, in case of a transfer error while reading the block link data structure. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register." start="8" size="1" />
+      <BitField name="TEMD" description="Transfer Error Mask Data These bit is set by HW, in case of a transfer error while writing the Mask Data. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register." start="9" size="1" />
+      <BitField name="ASE" description="Address/Size Error These bit is set by HW, when the programmed address is not aligned with the data size. TED will indicate whether the problem is on the source or destination. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register." start="10" size="1" />
+      <BitField name="BSE" description="Block Size Error These bit is set by HW, when the block size is not an integer multiple of the data size either for source or destination. TED will indicate whether the problem is on the source or destination. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register." start="11" size="1" />
+    </Register>
+    <Register name="MDMA_C6CR" description="This register is used to control the concerned channel." start="+0x1CC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="channel enable" start="0" size="1" access="Read/Write" />
+      <BitField name="TEIE" description="Transfer error interrupt enable This bit is set and cleared by software." start="1" size="1" access="Read/Write" />
+      <BitField name="CTCIE" description="Channel Transfer Complete interrupt enable This bit is set and cleared by software." start="2" size="1" access="Read/Write" />
+      <BitField name="BRTIE" description="Block Repeat transfer interrupt enable This bit is set and cleared by software." start="3" size="1" access="Read/Write" />
+      <BitField name="BTIE" description="Block Transfer interrupt enable This bit is set and cleared by software." start="4" size="1" access="Read/Write" />
+      <BitField name="TCIE" description="buffer Transfer Complete interrupt enable This bit is set and cleared by software." start="5" size="1" access="Read/Write" />
+      <BitField name="PL" description="Priority level These bits are set and cleared by software. These bits are protected and can be written only if EN is 0." start="6" size="2" access="Read/Write" />
+      <BitField name="BEX" description="byte Endianness exchange" start="12" size="1" access="Read/Write" />
+      <BitField name="HEX" description="Half word Endianes exchange" start="13" size="1" access="Read/Write" />
+      <BitField name="WEX" description="Word Endianness exchange" start="14" size="1" access="Read/Write" />
+      <BitField name="SWRQ" description="SW ReQuest Writing a 1 into this bit sets the CRQAx in MDMA_ISRy register, activating the request on Channel x Note: Either the whole CxCR register or the 8-bit/16-bit register @ Address offset: 0x4E + 0x40 chn may be used for SWRQ activation. In case of a SW request, acknowledge is not generated (neither HW signal, nor CxMAR write access)." start="16" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="MDMA_C6TCR" description="This register is used to configure the concerned channel." start="+0x1D0" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SINC" description="Source increment mode These bits are set and cleared by software. These bits are protected and can be written only if EN is 0 Note: When source is AHB (SBUS=1), SINC = 00 is forbidden. In Linked List Mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00)." start="0" size="2" />
+      <BitField name="DINC" description="Destination increment mode These bits are set and cleared by software. These bits are protected and can be written only if EN is 0 Note: When destination is AHB (DBUS=1), DINC = 00 is forbidden." start="2" size="2" />
+      <BitField name="SSIZE" description="Source data size These bits are set and cleared by software. These bits are protected and can be written only if EN is 0 Note: If a value of 11 is programmed for the TCM access/AHB port, a transfer error will occur (TEIF bit set) If SINCOS &amp;lt; SSIZE and SINC &amp;#8800; 00, the result will be unpredictable. Note: SSIZE = 11 (double-word) is forbidden when source is TCM/AHB bus (SBUS=1)." start="4" size="2" />
+      <BitField name="DSIZE" description="Destination data size These bits are set and cleared by software. These bits are protected and can be written only if EN is 0. Note: If a value of 11 is programmed for the TCM access/AHB port, a transfer error will occur (TEIF bit set) If DINCOS &amp;lt; DSIZE and DINC &amp;#8800; 00, the result will be unpredictable. Note: DSIZE = 11 (double-word) is forbidden when destination is TCM/AHB bus (DBUS=1)." start="6" size="2" />
+      <BitField name="SINCOS" description="source increment offset size" start="8" size="2" />
+      <BitField name="DINCOS" description="Destination increment offset" start="10" size="2" />
+      <BitField name="SBURST" description="source burst transfer configuration" start="12" size="3" />
+      <BitField name="DBURST" description="Destination burst transfer configuration" start="15" size="3" />
+      <BitField name="TLEN" description="buffer transfer lengh" start="18" size="7" />
+      <BitField name="PKE" description="PacK Enable These bit is set and cleared by software. If the Source Size is smaller than the destination, it will be padded according to the PAM value. If the Source data size is larger than the destination one, it will be truncated. The alignment will be done according to the PAM[0] value. This bit is protected and can be written only if EN is 0" start="25" size="1" />
+      <BitField name="PAM" description="Padding/Alignement Mode These bits are set and cleared by software. Case 1: Source data size smaller than destination data size - 3 options are valid. Case 2: Source data size larger than destination data size. The remainder part is discarded. When PKE = 1 or DSIZE=SSIZE, these bits are ignored. These bits are protected and can be written only if EN is 0" start="26" size="2" />
+      <BitField name="TRGM" description="Trigger Mode These bits are set and cleared by software. Note: If TRGM is 11 for the current block, all the values loaded at the end of the current block through the linked list mechanism must keep the same value (TRGM=11) and the same SWRM value, otherwise the result is undefined. These bits are protected and can be written only if EN is 0." start="28" size="2" />
+      <BitField name="SWRM" description="SW Request Mode This bit is set and cleared by software. If a HW or SW request is currently active, the bit change will be delayed until the current transfer is completed. If the CxMAR contains a valid address, the CxMDR value will also be written @ CxMAR address. This bit is protected and can be written only if EN is 0." start="30" size="1" />
+      <BitField name="BWM" description="Bufferable Write Mode This bit is set and cleared by software. This bit is protected and can be written only if EN is 0. Note: All MDMA destination accesses are non-cacheable." start="31" size="1" />
+    </Register>
+    <Register name="MDMA_C6BNDTR" description="MDMA Channel x block number of data register" start="+0x1D4" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BNDT" description="block number of data to transfer" start="0" size="17" />
+      <BitField name="BRSUM" description="Block Repeat Source address Update Mode These bits are protected and can be written only if EN is 0." start="18" size="1" />
+      <BitField name="BRDUM" description="Block Repeat Destination address Update Mode These bits are protected and can be written only if EN is 0." start="19" size="1" />
+      <BitField name="BRC" description="Block Repeat Count This field contains the number of repetitions of the current block (0 to 4095). When the channel is enabled, this register is read-only, indicating the remaining number of blocks, excluding the current one. This register decrements after each complete block transfer. Once the last block transfer has completed, this register can either stay at zero or be reloaded automatically from memory (in Linked List mode - i.e. Link Address valid). These bits are protected and can be written only if EN is 0" start="20" size="12" />
+    </Register>
+    <Register name="MDMA_C6SAR" description="MDMA channel x source address register" start="+0x1D8" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SAR" description="source adr base" start="0" size="32" />
+    </Register>
+    <Register name="MDMA_C6DAR" description="MDMA channel x destination address register" start="+0x1DC" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DAR" description="Destination adr base" start="0" size="32" />
+    </Register>
+    <Register name="MDMA_C6BRUR" description="MDMA channel x Block Repeat address Update register" start="+0x1E0" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SUV" description="source adresse update value" start="0" size="16" />
+      <BitField name="DUV" description="destination address update" start="16" size="16" />
+    </Register>
+    <Register name="MDMA_C6LAR" description="MDMA channel x Link Address register" start="+0x1E4" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LAR" description="Link address register" start="0" size="32" />
+    </Register>
+    <Register name="MDMA_C6TBR" description="MDMA channel x Trigger and Bus selection Register" start="+0x1E8" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TSEL" description="Trigger selection" start="0" size="6" />
+      <BitField name="SBUS" description="Source BUS select This bit is protected and can be written only if EN is 0." start="16" size="1" />
+      <BitField name="DBUS" description="Destination BUS slect This bit is protected and can be written only if EN is 0." start="17" size="1" />
+    </Register>
+    <Register name="MDMA_C6MAR" description="MDMA channel x Mask address register" start="+0x1F0" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MAR" description="Mask address" start="0" size="32" />
+    </Register>
+    <Register name="MDMA_C6MDR" description="MDMA channel x Mask Data register" start="+0x1F4" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MDR" description="Mask data" start="0" size="32" />
+    </Register>
+    <Register name="MDMA_C7ISR" description="MDMA channel x interrupt/status register" start="+0x200" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TEIF7" description="Channel x transfer error interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register." start="0" size="1" />
+      <BitField name="CTCIF7" description="Channel x Channel Transfer Complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register. CTC is set when the last block was transferred and the channel has been automatically disabled. CTC is also set when the channel is suspended, as a result of writing EN bit to 0." start="1" size="1" />
+      <BitField name="BRTIF7" description="Channel x block repeat transfer complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register." start="2" size="1" />
+      <BitField name="BTIF7" description="Channel x block transfer complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register." start="3" size="1" />
+      <BitField name="TCIF7" description="channel x buffer transfer complete" start="4" size="1" />
+      <BitField name="CRQA7" description="channel x request active flag" start="16" size="1" />
+    </Register>
+    <Register name="MDMA_C7IFCR" description="MDMA channel x interrupt flag clear register" start="+0x204" size="4" access="WriteOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CTEIF7" description="Channel x clear transfer error interrupt flag Writing a 1 into this bit clears TEIFx in the MDMA_ISRy register" start="0" size="1" />
+      <BitField name="CCTCIF7" description="Clear Channel transfer complete interrupt flag for channel x Writing a 1 into this bit clears CTCIFx in the MDMA_ISRy register" start="1" size="1" />
+      <BitField name="CBRTIF7" description="Channel x clear block repeat transfer complete interrupt flag Writing a 1 into this bit clears BRTIFx in the MDMA_ISRy register" start="2" size="1" />
+      <BitField name="CBTIF7" description="Channel x Clear block transfer complete interrupt flag Writing a 1 into this bit clears BTIFx in the MDMA_ISRy register" start="3" size="1" />
+      <BitField name="CLTCIF7" description="CLear buffer Transfer Complete Interrupt Flag for channel x Writing a 1 into this bit clears TCIFx in the MDMA_ISRy register" start="4" size="1" />
+    </Register>
+    <Register name="MDMA_C7ESR" description="MDMA Channel x error status register" start="+0x208" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TEA" description="Transfer Error Address These bits are set and cleared by HW, in case of an MDMA data transfer error. It is used in conjunction with TED. This field indicates the 7 LSBits of the address which generated a transfer/access error. It may be used by SW to retrieve the failing address, by adding this value (truncated to the buffer transfer length size) to the current SAR/DAR value. Note: The SAR/DAR current value doesnt reflect this last address due to the FIFO management system. The SAR/DAR are only updated at the end of a (buffer) transfer (of TLEN+1 bytes). Note: It is not set in case of a link data error." start="0" size="7" />
+      <BitField name="TED" description="Transfer Error Direction These bit is set and cleared by HW, in case of an MDMA data transfer error." start="7" size="1" />
+      <BitField name="TELD" description="Transfer Error Link Data These bit is set by HW, in case of a transfer error while reading the block link data structure. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register." start="8" size="1" />
+      <BitField name="TEMD" description="Transfer Error Mask Data These bit is set by HW, in case of a transfer error while writing the Mask Data. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register." start="9" size="1" />
+      <BitField name="ASE" description="Address/Size Error These bit is set by HW, when the programmed address is not aligned with the data size. TED will indicate whether the problem is on the source or destination. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register." start="10" size="1" />
+      <BitField name="BSE" description="Block Size Error These bit is set by HW, when the block size is not an integer multiple of the data size either for source or destination. TED will indicate whether the problem is on the source or destination. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register." start="11" size="1" />
+    </Register>
+    <Register name="MDMA_C7CR" description="This register is used to control the concerned channel." start="+0x20C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="channel enable" start="0" size="1" access="Read/Write" />
+      <BitField name="TEIE" description="Transfer error interrupt enable This bit is set and cleared by software." start="1" size="1" access="Read/Write" />
+      <BitField name="CTCIE" description="Channel Transfer Complete interrupt enable This bit is set and cleared by software." start="2" size="1" access="Read/Write" />
+      <BitField name="BRTIE" description="Block Repeat transfer interrupt enable This bit is set and cleared by software." start="3" size="1" access="Read/Write" />
+      <BitField name="BTIE" description="Block Transfer interrupt enable This bit is set and cleared by software." start="4" size="1" access="Read/Write" />
+      <BitField name="TCIE" description="buffer Transfer Complete interrupt enable This bit is set and cleared by software." start="5" size="1" access="Read/Write" />
+      <BitField name="PL" description="Priority level These bits are set and cleared by software. These bits are protected and can be written only if EN is 0." start="6" size="2" access="Read/Write" />
+      <BitField name="BEX" description="byte Endianness exchange" start="12" size="1" access="Read/Write" />
+      <BitField name="HEX" description="Half word Endianes exchange" start="13" size="1" access="Read/Write" />
+      <BitField name="WEX" description="Word Endianness exchange" start="14" size="1" access="Read/Write" />
+      <BitField name="SWRQ" description="SW ReQuest Writing a 1 into this bit sets the CRQAx in MDMA_ISRy register, activating the request on Channel x Note: Either the whole CxCR register or the 8-bit/16-bit register @ Address offset: 0x4E + 0x40 chn may be used for SWRQ activation. In case of a SW request, acknowledge is not generated (neither HW signal, nor CxMAR write access)." start="16" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="MDMA_C7TCR" description="This register is used to configure the concerned channel." start="+0x210" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SINC" description="Source increment mode These bits are set and cleared by software. These bits are protected and can be written only if EN is 0 Note: When source is AHB (SBUS=1), SINC = 00 is forbidden. In Linked List Mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00)." start="0" size="2" />
+      <BitField name="DINC" description="Destination increment mode These bits are set and cleared by software. These bits are protected and can be written only if EN is 0 Note: When destination is AHB (DBUS=1), DINC = 00 is forbidden." start="2" size="2" />
+      <BitField name="SSIZE" description="Source data size These bits are set and cleared by software. These bits are protected and can be written only if EN is 0 Note: If a value of 11 is programmed for the TCM access/AHB port, a transfer error will occur (TEIF bit set) If SINCOS &amp;lt; SSIZE and SINC &amp;#8800; 00, the result will be unpredictable. Note: SSIZE = 11 (double-word) is forbidden when source is TCM/AHB bus (SBUS=1)." start="4" size="2" />
+      <BitField name="DSIZE" description="Destination data size These bits are set and cleared by software. These bits are protected and can be written only if EN is 0. Note: If a value of 11 is programmed for the TCM access/AHB port, a transfer error will occur (TEIF bit set) If DINCOS &amp;lt; DSIZE and DINC &amp;#8800; 00, the result will be unpredictable. Note: DSIZE = 11 (double-word) is forbidden when destination is TCM/AHB bus (DBUS=1)." start="6" size="2" />
+      <BitField name="SINCOS" description="source increment offset size" start="8" size="2" />
+      <BitField name="DINCOS" description="Destination increment offset" start="10" size="2" />
+      <BitField name="SBURST" description="source burst transfer configuration" start="12" size="3" />
+      <BitField name="DBURST" description="Destination burst transfer configuration" start="15" size="3" />
+      <BitField name="TLEN" description="buffer transfer lengh" start="18" size="7" />
+      <BitField name="PKE" description="PacK Enable These bit is set and cleared by software. If the Source Size is smaller than the destination, it will be padded according to the PAM value. If the Source data size is larger than the destination one, it will be truncated. The alignment will be done according to the PAM[0] value. This bit is protected and can be written only if EN is 0" start="25" size="1" />
+      <BitField name="PAM" description="Padding/Alignement Mode These bits are set and cleared by software. Case 1: Source data size smaller than destination data size - 3 options are valid. Case 2: Source data size larger than destination data size. The remainder part is discarded. When PKE = 1 or DSIZE=SSIZE, these bits are ignored. These bits are protected and can be written only if EN is 0" start="26" size="2" />
+      <BitField name="TRGM" description="Trigger Mode These bits are set and cleared by software. Note: If TRGM is 11 for the current block, all the values loaded at the end of the current block through the linked list mechanism must keep the same value (TRGM=11) and the same SWRM value, otherwise the result is undefined. These bits are protected and can be written only if EN is 0." start="28" size="2" />
+      <BitField name="SWRM" description="SW Request Mode This bit is set and cleared by software. If a HW or SW request is currently active, the bit change will be delayed until the current transfer is completed. If the CxMAR contains a valid address, the CxMDR value will also be written @ CxMAR address. This bit is protected and can be written only if EN is 0." start="30" size="1" />
+      <BitField name="BWM" description="Bufferable Write Mode This bit is set and cleared by software. This bit is protected and can be written only if EN is 0. Note: All MDMA destination accesses are non-cacheable." start="31" size="1" />
+    </Register>
+    <Register name="MDMA_C7BNDTR" description="MDMA Channel x block number of data register" start="+0x214" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BNDT" description="block number of data to transfer" start="0" size="17" />
+      <BitField name="BRSUM" description="Block Repeat Source address Update Mode These bits are protected and can be written only if EN is 0." start="18" size="1" />
+      <BitField name="BRDUM" description="Block Repeat Destination address Update Mode These bits are protected and can be written only if EN is 0." start="19" size="1" />
+      <BitField name="BRC" description="Block Repeat Count This field contains the number of repetitions of the current block (0 to 4095). When the channel is enabled, this register is read-only, indicating the remaining number of blocks, excluding the current one. This register decrements after each complete block transfer. Once the last block transfer has completed, this register can either stay at zero or be reloaded automatically from memory (in Linked List mode - i.e. Link Address valid). These bits are protected and can be written only if EN is 0." start="20" size="12" />
+    </Register>
+    <Register name="MDMA_C7SAR" description="MDMA channel x source address register" start="+0x218" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SAR" description="source adr base" start="0" size="32" />
+    </Register>
+    <Register name="MDMA_C7DAR" description="MDMA channel x destination address register" start="+0x21C" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DAR" description="Destination adr base" start="0" size="32" />
+    </Register>
+    <Register name="MDMA_C7BRUR" description="MDMA channel x Block Repeat address Update register" start="+0x220" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SUV" description="source adresse update value" start="0" size="16" />
+      <BitField name="DUV" description="destination address update" start="16" size="16" />
+    </Register>
+    <Register name="MDMA_C7LAR" description="MDMA channel x Link Address register" start="+0x224" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LAR" description="Link address register" start="0" size="32" />
+    </Register>
+    <Register name="MDMA_C7TBR" description="MDMA channel x Trigger and Bus selection Register" start="+0x228" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TSEL" description="Trigger selection" start="0" size="6" />
+      <BitField name="SBUS" description="Source BUS select This bit is protected and can be written only if EN is 0." start="16" size="1" />
+      <BitField name="DBUS" description="Destination BUS slect This bit is protected and can be written only if EN is 0." start="17" size="1" />
+    </Register>
+    <Register name="MDMA_C7MAR" description="MDMA channel x Mask address register" start="+0x230" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MAR" description="Mask address" start="0" size="32" />
+    </Register>
+    <Register name="MDMA_C7MDR" description="MDMA channel x Mask Data register" start="+0x234" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MDR" description="Mask data" start="0" size="32" />
+    </Register>
+    <Register name="MDMA_C8ISR" description="MDMA channel x interrupt/status register" start="+0x240" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TEIF8" description="Channel x transfer error interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register." start="0" size="1" />
+      <BitField name="CTCIF8" description="Channel x Channel Transfer Complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register. CTC is set when the last block was transferred and the channel has been automatically disabled. CTC is also set when the channel is suspended, as a result of writing EN bit to 0." start="1" size="1" />
+      <BitField name="BRTIF8" description="Channel x block repeat transfer complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register." start="2" size="1" />
+      <BitField name="BTIF8" description="Channel x block transfer complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register." start="3" size="1" />
+      <BitField name="TCIF8" description="channel x buffer transfer complete" start="4" size="1" />
+      <BitField name="CRQA8" description="channel x request active flag" start="16" size="1" />
+    </Register>
+    <Register name="MDMA_C8IFCR" description="MDMA channel x interrupt flag clear register" start="+0x244" size="4" access="WriteOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CTEIF8" description="Channel x clear transfer error interrupt flag Writing a 1 into this bit clears TEIFx in the MDMA_ISRy register" start="0" size="1" />
+      <BitField name="CCTCIF8" description="Clear Channel transfer complete interrupt flag for channel x Writing a 1 into this bit clears CTCIFx in the MDMA_ISRy register" start="1" size="1" />
+      <BitField name="CBRTIF8" description="Channel x clear block repeat transfer complete interrupt flag Writing a 1 into this bit clears BRTIFx in the MDMA_ISRy register" start="2" size="1" />
+      <BitField name="CBTIF8" description="Channel x Clear block transfer complete interrupt flag Writing a 1 into this bit clears BTIFx in the MDMA_ISRy register" start="3" size="1" />
+      <BitField name="CLTCIF8" description="CLear buffer Transfer Complete Interrupt Flag for channel x Writing a 1 into this bit clears TCIFx in the MDMA_ISRy register" start="4" size="1" />
+    </Register>
+    <Register name="MDMA_C8ESR" description="MDMA Channel x error status register" start="+0x248" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TEA" description="Transfer Error Address These bits are set and cleared by HW, in case of an MDMA data transfer error. It is used in conjunction with TED. This field indicates the 7 LSBits of the address which generated a transfer/access error. It may be used by SW to retrieve the failing address, by adding this value (truncated to the buffer transfer length size) to the current SAR/DAR value. Note: The SAR/DAR current value doesnt reflect this last address due to the FIFO management system. The SAR/DAR are only updated at the end of a (buffer) transfer (of TLEN+1 bytes). Note: It is not set in case of a link data error." start="0" size="7" />
+      <BitField name="TED" description="Transfer Error Direction These bit is set and cleared by HW, in case of an MDMA data transfer error." start="7" size="1" />
+      <BitField name="TELD" description="Transfer Error Link Data These bit is set by HW, in case of a transfer error while reading the block link data structure. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register." start="8" size="1" />
+      <BitField name="TEMD" description="Transfer Error Mask Data These bit is set by HW, in case of a transfer error while writing the Mask Data. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register." start="9" size="1" />
+      <BitField name="ASE" description="Address/Size Error These bit is set by HW, when the programmed address is not aligned with the data size. TED will indicate whether the problem is on the source or destination. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register." start="10" size="1" />
+      <BitField name="BSE" description="Block Size Error These bit is set by HW, when the block size is not an integer multiple of the data size either for source or destination. TED will indicate whether the problem is on the source or destination. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register." start="11" size="1" />
+    </Register>
+    <Register name="MDMA_C8CR" description="This register is used to control the concerned channel." start="+0x24C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="channel enable" start="0" size="1" access="Read/Write" />
+      <BitField name="TEIE" description="Transfer error interrupt enable This bit is set and cleared by software." start="1" size="1" access="Read/Write" />
+      <BitField name="CTCIE" description="Channel Transfer Complete interrupt enable This bit is set and cleared by software." start="2" size="1" access="Read/Write" />
+      <BitField name="BRTIE" description="Block Repeat transfer interrupt enable This bit is set and cleared by software." start="3" size="1" access="Read/Write" />
+      <BitField name="BTIE" description="Block Transfer interrupt enable This bit is set and cleared by software." start="4" size="1" access="Read/Write" />
+      <BitField name="TCIE" description="buffer Transfer Complete interrupt enable This bit is set and cleared by software." start="5" size="1" access="Read/Write" />
+      <BitField name="PL" description="Priority level These bits are set and cleared by software. These bits are protected and can be written only if EN is 0." start="6" size="2" access="Read/Write" />
+      <BitField name="BEX" description="byte Endianness exchange" start="12" size="1" access="Read/Write" />
+      <BitField name="HEX" description="Half word Endianes exchange" start="13" size="1" access="Read/Write" />
+      <BitField name="WEX" description="Word Endianness exchange" start="14" size="1" access="Read/Write" />
+      <BitField name="SWRQ" description="SW ReQuest Writing a 1 into this bit sets the CRQAx in MDMA_ISRy register, activating the request on Channel x Note: Either the whole CxCR register or the 8-bit/16-bit register @ Address offset: 0x4E + 0x40 chn may be used for SWRQ activation. In case of a SW request, acknowledge is not generated (neither HW signal, nor CxMAR write access)." start="16" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="MDMA_C8TCR" description="This register is used to configure the concerned channel." start="+0x250" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SINC" description="Source increment mode These bits are set and cleared by software. These bits are protected and can be written only if EN is 0 Note: When source is AHB (SBUS=1), SINC = 00 is forbidden. In Linked List Mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00)." start="0" size="2" />
+      <BitField name="DINC" description="Destination increment mode These bits are set and cleared by software. These bits are protected and can be written only if EN is 0 Note: When destination is AHB (DBUS=1), DINC = 00 is forbidden." start="2" size="2" />
+      <BitField name="SSIZE" description="Source data size These bits are set and cleared by software. These bits are protected and can be written only if EN is 0 Note: If a value of 11 is programmed for the TCM access/AHB port, a transfer error will occur (TEIF bit set) If SINCOS &amp;lt; SSIZE and SINC &amp;#8800; 00, the result will be unpredictable. Note: SSIZE = 11 (double-word) is forbidden when source is TCM/AHB bus (SBUS=1)." start="4" size="2" />
+      <BitField name="DSIZE" description="Destination data size These bits are set and cleared by software. These bits are protected and can be written only if EN is 0. Note: If a value of 11 is programmed for the TCM access/AHB port, a transfer error will occur (TEIF bit set) If DINCOS &amp;lt; DSIZE and DINC &amp;#8800; 00, the result will be unpredictable. Note: DSIZE = 11 (double-word) is forbidden when destination is TCM/AHB bus (DBUS=1)." start="6" size="2" />
+      <BitField name="SINCOS" description="source increment offset size" start="8" size="2" />
+      <BitField name="DINCOS" description="Destination increment offset" start="10" size="2" />
+      <BitField name="SBURST" description="source burst transfer configuration" start="12" size="3" />
+      <BitField name="DBURST" description="Destination burst transfer configuration" start="15" size="3" />
+      <BitField name="TLEN" description="buffer transfer lengh" start="18" size="7" />
+      <BitField name="PKE" description="PacK Enable These bit is set and cleared by software. If the Source Size is smaller than the destination, it will be padded according to the PAM value. If the Source data size is larger than the destination one, it will be truncated. The alignment will be done according to the PAM[0] value. This bit is protected and can be written only if EN is 0" start="25" size="1" />
+      <BitField name="PAM" description="Padding/Alignement Mode These bits are set and cleared by software. Case 1: Source data size smaller than destination data size - 3 options are valid. Case 2: Source data size larger than destination data size. The remainder part is discarded. When PKE = 1 or DSIZE=SSIZE, these bits are ignored. These bits are protected and can be written only if EN is 0" start="26" size="2" />
+      <BitField name="TRGM" description="Trigger Mode These bits are set and cleared by software. Note: If TRGM is 11 for the current block, all the values loaded at the end of the current block through the linked list mechanism must keep the same value (TRGM=11) and the same SWRM value, otherwise the result is undefined. These bits are protected and can be written only if EN is 0." start="28" size="2" />
+      <BitField name="SWRM" description="SW Request Mode This bit is set and cleared by software. If a HW or SW request is currently active, the bit change will be delayed until the current transfer is completed. If the CxMAR contains a valid address, the CxMDR value will also be written @ CxMAR address. This bit is protected and can be written only if EN is 0." start="30" size="1" />
+      <BitField name="BWM" description="Bufferable Write Mode This bit is set and cleared by software. This bit is protected and can be written only if EN is 0. Note: All MDMA destination accesses are non-cacheable." start="31" size="1" />
+    </Register>
+    <Register name="MDMA_C8BNDTR" description="MDMA Channel x block number of data register" start="+0x254" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BNDT" description="block number of data to transfer" start="0" size="17" />
+      <BitField name="BRSUM" description="Block Repeat Source address Update Mode These bits are protected and can be written only if EN is 0." start="18" size="1" />
+      <BitField name="BRDUM" description="Block Repeat Destination address Update Mode These bits are protected and can be written only if EN is 0." start="19" size="1" />
+      <BitField name="BRC" description="Block Repeat Count This field contains the number of repetitions of the current block (0 to 4095). When the channel is enabled, this register is read-only, indicating the remaining number of blocks, excluding the current one. This register decrements after each complete block transfer. Once the last block transfer has completed, this register can either stay at zero or be reloaded automatically from memory (in Linked List mode - i.e. Link Address valid). These bits are protected and can be written only if EN is 0." start="20" size="12" />
+    </Register>
+    <Register name="MDMA_C8SAR" description="MDMA channel x source address register" start="+0x258" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SAR" description="source adr base" start="0" size="32" />
+    </Register>
+    <Register name="MDMA_C8DAR" description="MDMA channel x destination address register" start="+0x25C" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DAR" description="Destination adr base" start="0" size="32" />
+    </Register>
+    <Register name="MDMA_C8BRUR" description="MDMA channel x Block Repeat address Update register" start="+0x260" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SUV" description="source adresse update value" start="0" size="16" />
+      <BitField name="DUV" description="destination address update" start="16" size="16" />
+    </Register>
+    <Register name="MDMA_C8LAR" description="MDMA channel x Link Address register" start="+0x264" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LAR" description="Link address register" start="0" size="32" />
+    </Register>
+    <Register name="MDMA_C8TBR" description="MDMA channel x Trigger and Bus selection Register" start="+0x268" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TSEL" description="Trigger selection" start="0" size="6" />
+      <BitField name="SBUS" description="Source BUS select This bit is protected and can be written only if EN is 0." start="16" size="1" />
+      <BitField name="DBUS" description="Destination BUS slect This bit is protected and can be written only if EN is 0." start="17" size="1" />
+    </Register>
+    <Register name="MDMA_C8MAR" description="MDMA channel x Mask address register" start="+0x270" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MAR" description="Mask address" start="0" size="32" />
+    </Register>
+    <Register name="MDMA_C8MDR" description="MDMA channel x Mask Data register" start="+0x274" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MDR" description="Mask data" start="0" size="32" />
+    </Register>
+    <Register name="MDMA_C9ISR" description="MDMA channel x interrupt/status register" start="+0x280" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TEIF9" description="Channel x transfer error interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register." start="0" size="1" />
+      <BitField name="CTCIF9" description="Channel x Channel Transfer Complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register. CTC is set when the last block was transferred and the channel has been automatically disabled. CTC is also set when the channel is suspended, as a result of writing EN bit to 0." start="1" size="1" />
+      <BitField name="BRTIF9" description="Channel x block repeat transfer complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register." start="2" size="1" />
+      <BitField name="BTIF9" description="Channel x block transfer complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register." start="3" size="1" />
+      <BitField name="TCIF9" description="channel x buffer transfer complete" start="4" size="1" />
+      <BitField name="CRQA9" description="channel x request active flag" start="16" size="1" />
+    </Register>
+    <Register name="MDMA_C9IFCR" description="MDMA channel x interrupt flag clear register" start="+0x284" size="4" access="WriteOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CTEIF9" description="Channel x clear transfer error interrupt flag Writing a 1 into this bit clears TEIFx in the MDMA_ISRy register" start="0" size="1" />
+      <BitField name="CCTCIF9" description="Clear Channel transfer complete interrupt flag for channel x Writing a 1 into this bit clears CTCIFx in the MDMA_ISRy register" start="1" size="1" />
+      <BitField name="CBRTIF9" description="Channel x clear block repeat transfer complete interrupt flag Writing a 1 into this bit clears BRTIFx in the MDMA_ISRy register" start="2" size="1" />
+      <BitField name="CBTIF9" description="Channel x Clear block transfer complete interrupt flag Writing a 1 into this bit clears BTIFx in the MDMA_ISRy register" start="3" size="1" />
+      <BitField name="CLTCIF9" description="CLear buffer Transfer Complete Interrupt Flag for channel x Writing a 1 into this bit clears TCIFx in the MDMA_ISRy register" start="4" size="1" />
+    </Register>
+    <Register name="MDMA_C9ESR" description="MDMA Channel x error status register" start="+0x288" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TEA" description="Transfer Error Address These bits are set and cleared by HW, in case of an MDMA data transfer error. It is used in conjunction with TED. This field indicates the 7 LSBits of the address which generated a transfer/access error. It may be used by SW to retrieve the failing address, by adding this value (truncated to the buffer transfer length size) to the current SAR/DAR value. Note: The SAR/DAR current value doesnt reflect this last address due to the FIFO management system. The SAR/DAR are only updated at the end of a (buffer) transfer (of TLEN+1 bytes). Note: It is not set in case of a link data error." start="0" size="7" />
+      <BitField name="TED" description="Transfer Error Direction These bit is set and cleared by HW, in case of an MDMA data transfer error." start="7" size="1" />
+      <BitField name="TELD" description="Transfer Error Link Data These bit is set by HW, in case of a transfer error while reading the block link data structure. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register." start="8" size="1" />
+      <BitField name="TEMD" description="Transfer Error Mask Data These bit is set by HW, in case of a transfer error while writing the Mask Data. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register." start="9" size="1" />
+      <BitField name="ASE" description="Address/Size Error These bit is set by HW, when the programmed address is not aligned with the data size. TED will indicate whether the problem is on the source or destination. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register." start="10" size="1" />
+      <BitField name="BSE" description="Block Size Error These bit is set by HW, when the block size is not an integer multiple of the data size either for source or destination. TED will indicate whether the problem is on the source or destination. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register." start="11" size="1" />
+    </Register>
+    <Register name="MDMA_C9CR" description="This register is used to control the concerned channel." start="+0x28C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="channel enable" start="0" size="1" access="Read/Write" />
+      <BitField name="TEIE" description="Transfer error interrupt enable This bit is set and cleared by software." start="1" size="1" access="Read/Write" />
+      <BitField name="CTCIE" description="Channel Transfer Complete interrupt enable This bit is set and cleared by software." start="2" size="1" access="Read/Write" />
+      <BitField name="BRTIE" description="Block Repeat transfer interrupt enable This bit is set and cleared by software." start="3" size="1" access="Read/Write" />
+      <BitField name="BTIE" description="Block Transfer interrupt enable This bit is set and cleared by software." start="4" size="1" access="Read/Write" />
+      <BitField name="TCIE" description="buffer Transfer Complete interrupt enable This bit is set and cleared by software." start="5" size="1" access="Read/Write" />
+      <BitField name="PL" description="Priority level These bits are set and cleared by software. These bits are protected and can be written only if EN is 0." start="6" size="2" access="Read/Write" />
+      <BitField name="BEX" description="byte Endianness exchange" start="12" size="1" access="Read/Write" />
+      <BitField name="HEX" description="Half word Endianes exchange" start="13" size="1" access="Read/Write" />
+      <BitField name="WEX" description="Word Endianness exchange" start="14" size="1" access="Read/Write" />
+      <BitField name="SWRQ" description="SW ReQuest Writing a 1 into this bit sets the CRQAx in MDMA_ISRy register, activating the request on Channel x Note: Either the whole CxCR register or the 8-bit/16-bit register @ Address offset: 0x4E + 0x40 chn may be used for SWRQ activation. In case of a SW request, acknowledge is not generated (neither HW signal, nor CxMAR write access)." start="16" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="MDMA_C9TCR" description="This register is used to configure the concerned channel." start="+0x290" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SINC" description="Source increment mode These bits are set and cleared by software. These bits are protected and can be written only if EN is 0 Note: When source is AHB (SBUS=1), SINC = 00 is forbidden. In Linked List Mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00)." start="0" size="2" />
+      <BitField name="DINC" description="Destination increment mode These bits are set and cleared by software. These bits are protected and can be written only if EN is 0 Note: When destination is AHB (DBUS=1), DINC = 00 is forbidden." start="2" size="2" />
+      <BitField name="SSIZE" description="Source data size These bits are set and cleared by software. These bits are protected and can be written only if EN is 0 Note: If a value of 11 is programmed for the TCM access/AHB port, a transfer error will occur (TEIF bit set) If SINCOS &amp;lt; SSIZE and SINC &amp;#8800; 00, the result will be unpredictable. Note: SSIZE = 11 (double-word) is forbidden when source is TCM/AHB bus (SBUS=1)." start="4" size="2" />
+      <BitField name="DSIZE" description="Destination data size These bits are set and cleared by software. These bits are protected and can be written only if EN is 0. Note: If a value of 11 is programmed for the TCM access/AHB port, a transfer error will occur (TEIF bit set) If DINCOS &amp;lt; DSIZE and DINC &amp;#8800; 00, the result will be unpredictable. Note: DSIZE = 11 (double-word) is forbidden when destination is TCM/AHB bus (DBUS=1)." start="6" size="2" />
+      <BitField name="SINCOS" description="source increment offset size" start="8" size="2" />
+      <BitField name="DINCOS" description="Destination increment offset" start="10" size="2" />
+      <BitField name="SBURST" description="source burst transfer configuration" start="12" size="3" />
+      <BitField name="DBURST" description="Destination burst transfer configuration" start="15" size="3" />
+      <BitField name="TLEN" description="buffer transfer lengh" start="18" size="7" />
+      <BitField name="PKE" description="PacK Enable These bit is set and cleared by software. If the Source Size is smaller than the destination, it will be padded according to the PAM value. If the Source data size is larger than the destination one, it will be truncated. The alignment will be done according to the PAM[0] value. This bit is protected and can be written only if EN is 0" start="25" size="1" />
+      <BitField name="PAM" description="Padding/Alignement Mode These bits are set and cleared by software. Case 1: Source data size smaller than destination data size - 3 options are valid. Case 2: Source data size larger than destination data size. The remainder part is discarded. When PKE = 1 or DSIZE=SSIZE, these bits are ignored. These bits are protected and can be written only if EN is 0" start="26" size="2" />
+      <BitField name="TRGM" description="Trigger Mode These bits are set and cleared by software. Note: If TRGM is 11 for the current block, all the values loaded at the end of the current block through the linked list mechanism must keep the same value (TRGM=11) and the same SWRM value, otherwise the result is undefined. These bits are protected and can be written only if EN is 0." start="28" size="2" />
+      <BitField name="SWRM" description="SW Request Mode This bit is set and cleared by software. If a HW or SW request is currently active, the bit change will be delayed until the current transfer is completed. If the CxMAR contains a valid address, the CxMDR value will also be written @ CxMAR address. This bit is protected and can be written only if EN is 0." start="30" size="1" />
+      <BitField name="BWM" description="Bufferable Write Mode This bit is set and cleared by software. This bit is protected and can be written only if EN is 0. Note: All MDMA destination accesses are non-cacheable." start="31" size="1" />
+    </Register>
+    <Register name="MDMA_C9BNDTR" description="MDMA Channel x block number of data register" start="+0x294" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BNDT" description="block number of data to transfer" start="0" size="17" />
+      <BitField name="BRSUM" description="Block Repeat Source address Update Mode These bits are protected and can be written only if EN is 0." start="18" size="1" />
+      <BitField name="BRDUM" description="Block Repeat Destination address Update Mode These bits are protected and can be written only if EN is 0." start="19" size="1" />
+      <BitField name="BRC" description="Block Repeat Count This field contains the number of repetitions of the current block (0 to 4095). When the channel is enabled, this register is read-only, indicating the remaining number of blocks, excluding the current one. This register decrements after each complete block transfer. Once the last block transfer has completed, this register can either stay at zero or be reloaded automatically from memory (in Linked List mode - i.e. Link Address valid). These bits are protected and can be written only if EN is 0." start="20" size="12" />
+    </Register>
+    <Register name="MDMA_C9SAR" description="MDMA channel x source address register" start="+0x298" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SAR" description="source adr base" start="0" size="32" />
+    </Register>
+    <Register name="MDMA_C9DAR" description="MDMA channel x destination address register" start="+0x29C" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DAR" description="Destination adr base" start="0" size="32" />
+    </Register>
+    <Register name="MDMA_C9BRUR" description="MDMA channel x Block Repeat address Update register" start="+0x2A0" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SUV" description="source adresse update value" start="0" size="16" />
+      <BitField name="DUV" description="destination address update" start="16" size="16" />
+    </Register>
+    <Register name="MDMA_C9LAR" description="MDMA channel x Link Address register" start="+0x2A4" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LAR" description="Link address register" start="0" size="32" />
+    </Register>
+    <Register name="MDMA_C9TBR" description="MDMA channel x Trigger and Bus selection Register" start="+0x2A8" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TSEL" description="Trigger selection" start="0" size="6" />
+      <BitField name="SBUS" description="Source BUS select This bit is protected and can be written only if EN is 0." start="16" size="1" />
+      <BitField name="DBUS" description="Destination BUS slect This bit is protected and can be written only if EN is 0." start="17" size="1" />
+    </Register>
+    <Register name="MDMA_C9MAR" description="MDMA channel x Mask address register" start="+0x2B0" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MAR" description="Mask address" start="0" size="32" />
+    </Register>
+    <Register name="MDMA_C9MDR" description="MDMA channel x Mask Data register" start="+0x2B4" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MDR" description="Mask data" start="0" size="32" />
+    </Register>
+    <Register name="MDMA_C10ISR" description="MDMA channel x interrupt/status register" start="+0x2C0" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TEIF10" description="Channel x transfer error interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register." start="0" size="1" />
+      <BitField name="CTCIF10" description="Channel x Channel Transfer Complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register. CTC is set when the last block was transferred and the channel has been automatically disabled. CTC is also set when the channel is suspended, as a result of writing EN bit to 0." start="1" size="1" />
+      <BitField name="BRTIF10" description="Channel x block repeat transfer complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register." start="2" size="1" />
+      <BitField name="BTIF10" description="Channel x block transfer complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register." start="3" size="1" />
+      <BitField name="TCIF10" description="channel x buffer transfer complete" start="4" size="1" />
+      <BitField name="CRQA10" description="channel x request active flag" start="16" size="1" />
+    </Register>
+    <Register name="MDMA_C10IFCR" description="MDMA channel x interrupt flag clear register" start="+0x2C4" size="4" access="WriteOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CTEIF10" description="Channel x clear transfer error interrupt flag Writing a 1 into this bit clears TEIFx in the MDMA_ISRy register" start="0" size="1" />
+      <BitField name="CCTCIF10" description="Clear Channel transfer complete interrupt flag for channel x Writing a 1 into this bit clears CTCIFx in the MDMA_ISRy register" start="1" size="1" />
+      <BitField name="CBRTIF10" description="Channel x clear block repeat transfer complete interrupt flag Writing a 1 into this bit clears BRTIFx in the MDMA_ISRy register" start="2" size="1" />
+      <BitField name="CBTIF10" description="Channel x Clear block transfer complete interrupt flag Writing a 1 into this bit clears BTIFx in the MDMA_ISRy register" start="3" size="1" />
+      <BitField name="CLTCIF10" description="CLear buffer Transfer Complete Interrupt Flag for channel x Writing a 1 into this bit clears TCIFx in the MDMA_ISRy register" start="4" size="1" />
+    </Register>
+    <Register name="MDMA_C10ESR" description="MDMA Channel x error status register" start="+0x2C8" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TEA" description="Transfer Error Address These bits are set and cleared by HW, in case of an MDMA data transfer error. It is used in conjunction with TED. This field indicates the 7 LSBits of the address which generated a transfer/access error. It may be used by SW to retrieve the failing address, by adding this value (truncated to the buffer transfer length size) to the current SAR/DAR value. Note: The SAR/DAR current value doesnt reflect this last address due to the FIFO management system. The SAR/DAR are only updated at the end of a (buffer) transfer (of TLEN+1 bytes). Note: It is not set in case of a link data error." start="0" size="7" />
+      <BitField name="TED" description="Transfer Error Direction These bit is set and cleared by HW, in case of an MDMA data transfer error." start="7" size="1" />
+      <BitField name="TELD" description="Transfer Error Link Data These bit is set by HW, in case of a transfer error while reading the block link data structure. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register." start="8" size="1" />
+      <BitField name="TEMD" description="Transfer Error Mask Data These bit is set by HW, in case of a transfer error while writing the Mask Data. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register." start="9" size="1" />
+      <BitField name="ASE" description="Address/Size Error These bit is set by HW, when the programmed address is not aligned with the data size. TED will indicate whether the problem is on the source or destination. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register." start="10" size="1" />
+      <BitField name="BSE" description="Block Size Error These bit is set by HW, when the block size is not an integer multiple of the data size either for source or destination. TED will indicate whether the problem is on the source or destination. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register." start="11" size="1" />
+    </Register>
+    <Register name="MDMA_C10CR" description="This register is used to control the concerned channel." start="+0x2CC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="channel enable" start="0" size="1" access="Read/Write" />
+      <BitField name="TEIE" description="Transfer error interrupt enable This bit is set and cleared by software." start="1" size="1" access="Read/Write" />
+      <BitField name="CTCIE" description="Channel Transfer Complete interrupt enable This bit is set and cleared by software." start="2" size="1" access="Read/Write" />
+      <BitField name="BRTIE" description="Block Repeat transfer interrupt enable This bit is set and cleared by software." start="3" size="1" access="Read/Write" />
+      <BitField name="BTIE" description="Block Transfer interrupt enable This bit is set and cleared by software." start="4" size="1" access="Read/Write" />
+      <BitField name="TCIE" description="buffer Transfer Complete interrupt enable This bit is set and cleared by software." start="5" size="1" access="Read/Write" />
+      <BitField name="PL" description="Priority level These bits are set and cleared by software. These bits are protected and can be written only if EN is 0." start="6" size="2" access="Read/Write" />
+      <BitField name="BEX" description="byte Endianness exchange" start="12" size="1" access="Read/Write" />
+      <BitField name="HEX" description="Half word Endianes exchange" start="13" size="1" access="Read/Write" />
+      <BitField name="WEX" description="Word Endianness exchange" start="14" size="1" access="Read/Write" />
+      <BitField name="SWRQ" description="SW ReQuest Writing a 1 into this bit sets the CRQAx in MDMA_ISRy register, activating the request on Channel x Note: Either the whole CxCR register or the 8-bit/16-bit register @ Address offset: 0x4E + 0x40 chn may be used for SWRQ activation. In case of a SW request, acknowledge is not generated (neither HW signal, nor CxMAR write access)." start="16" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="MDMA_C10TCR" description="This register is used to configure the concerned channel." start="+0x2D0" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SINC" description="Source increment mode These bits are set and cleared by software. These bits are protected and can be written only if EN is 0 Note: When source is AHB (SBUS=1), SINC = 00 is forbidden. In Linked List Mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00)." start="0" size="2" />
+      <BitField name="DINC" description="Destination increment mode These bits are set and cleared by software. These bits are protected and can be written only if EN is 0 Note: When destination is AHB (DBUS=1), DINC = 00 is forbidden." start="2" size="2" />
+      <BitField name="SSIZE" description="Source data size These bits are set and cleared by software. These bits are protected and can be written only if EN is 0 Note: If a value of 11 is programmed for the TCM access/AHB port, a transfer error will occur (TEIF bit set) If SINCOS &amp;lt; SSIZE and SINC &amp;#8800; 00, the result will be unpredictable. Note: SSIZE = 11 (double-word) is forbidden when source is TCM/AHB bus (SBUS=1)." start="4" size="2" />
+      <BitField name="DSIZE" description="Destination data size These bits are set and cleared by software. These bits are protected and can be written only if EN is 0. Note: If a value of 11 is programmed for the TCM access/AHB port, a transfer error will occur (TEIF bit set) If DINCOS &amp;lt; DSIZE and DINC &amp;#8800; 00, the result will be unpredictable. Note: DSIZE = 11 (double-word) is forbidden when destination is TCM/AHB bus (DBUS=1)." start="6" size="2" />
+      <BitField name="SINCOS" description="source increment offset size" start="8" size="2" />
+      <BitField name="DINCOS" description="Destination increment offset" start="10" size="2" />
+      <BitField name="SBURST" description="source burst transfer configuration" start="12" size="3" />
+      <BitField name="DBURST" description="Destination burst transfer configuration" start="15" size="3" />
+      <BitField name="TLEN" description="buffer transfer lengh" start="18" size="7" />
+      <BitField name="PKE" description="PacK Enable These bit is set and cleared by software. If the Source Size is smaller than the destination, it will be padded according to the PAM value. If the Source data size is larger than the destination one, it will be truncated. The alignment will be done according to the PAM[0] value. This bit is protected and can be written only if EN is 0" start="25" size="1" />
+      <BitField name="PAM" description="Padding/Alignement Mode These bits are set and cleared by software. Case 1: Source data size smaller than destination data size - 3 options are valid. Case 2: Source data size larger than destination data size. The remainder part is discarded. When PKE = 1 or DSIZE=SSIZE, these bits are ignored. These bits are protected and can be written only if EN is 0" start="26" size="2" />
+      <BitField name="TRGM" description="Trigger Mode These bits are set and cleared by software. Note: If TRGM is 11 for the current block, all the values loaded at the end of the current block through the linked list mechanism must keep the same value (TRGM=11) and the same SWRM value, otherwise the result is undefined. These bits are protected and can be written only if EN is 0." start="28" size="2" />
+      <BitField name="SWRM" description="SW Request Mode This bit is set and cleared by software. If a HW or SW request is currently active, the bit change will be delayed until the current transfer is completed. If the CxMAR contains a valid address, the CxMDR value will also be written @ CxMAR address. This bit is protected and can be written only if EN is 0." start="30" size="1" />
+      <BitField name="BWM" description="Bufferable Write Mode This bit is set and cleared by software. This bit is protected and can be written only if EN is 0. Note: All MDMA destination accesses are non-cacheable." start="31" size="1" />
+    </Register>
+    <Register name="MDMA_C10BNDTR" description="MDMA Channel x block number of data register" start="+0x2D4" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BNDT" description="block number of data to transfer" start="0" size="17" />
+      <BitField name="BRSUM" description="Block Repeat Source address Update Mode These bits are protected and can be written only if EN is 0." start="18" size="1" />
+      <BitField name="BRDUM" description="Block Repeat Destination address Update Mode These bits are protected and can be written only if EN is 0." start="19" size="1" />
+      <BitField name="BRC" description="Block Repeat Count This field contains the number of repetitions of the current block (0 to 4095). When the channel is enabled, this register is read-only, indicating the remaining number of blocks, excluding the current one. This register decrements after each complete block transfer. Once the last block transfer has completed, this register can either stay at zero or be reloaded automatically from memory (in Linked List mode - i.e. Link Address valid). These bits are protected and can be written only if EN is 0." start="20" size="12" />
+    </Register>
+    <Register name="MDMA_C10SAR" description="MDMA channel x source address register" start="+0x2D8" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SAR" description="source adr base" start="0" size="32" />
+    </Register>
+    <Register name="MDMA_C10DAR" description="MDMA channel x destination address register" start="+0x2DC" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DAR" description="Destination adr base" start="0" size="32" />
+    </Register>
+    <Register name="MDMA_C10BRUR" description="MDMA channel x Block Repeat address Update register" start="+0x2E0" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SUV" description="source adresse update value" start="0" size="16" />
+      <BitField name="DUV" description="destination address update" start="16" size="16" />
+    </Register>
+    <Register name="MDMA_C10LAR" description="MDMA channel x Link Address register" start="+0x2E4" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LAR" description="Link address register" start="0" size="32" />
+    </Register>
+    <Register name="MDMA_C10TBR" description="MDMA channel x Trigger and Bus selection Register" start="+0x2E8" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TSEL" description="Trigger selection" start="0" size="6" />
+      <BitField name="SBUS" description="Source BUS select This bit is protected and can be written only if EN is 0." start="16" size="1" />
+      <BitField name="DBUS" description="Destination BUS slect This bit is protected and can be written only if EN is 0." start="17" size="1" />
+    </Register>
+    <Register name="MDMA_C10MAR" description="MDMA channel x Mask address register" start="+0x2F0" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MAR" description="Mask address" start="0" size="32" />
+    </Register>
+    <Register name="MDMA_C10MDR" description="MDMA channel x Mask Data register" start="+0x2F4" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MDR" description="Mask data" start="0" size="32" />
+    </Register>
+    <Register name="MDMA_C11ISR" description="MDMA channel x interrupt/status register" start="+0x300" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TEIF11" description="Channel x transfer error interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register." start="0" size="1" />
+      <BitField name="CTCIF11" description="Channel x Channel Transfer Complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register. CTC is set when the last block was transferred and the channel has been automatically disabled. CTC is also set when the channel is suspended, as a result of writing EN bit to 0." start="1" size="1" />
+      <BitField name="BRTIF11" description="Channel x block repeat transfer complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register." start="2" size="1" />
+      <BitField name="BTIF11" description="Channel x block transfer complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register." start="3" size="1" />
+      <BitField name="TCIF11" description="channel x buffer transfer complete" start="4" size="1" />
+      <BitField name="CRQA11" description="channel x request active flag" start="16" size="1" />
+    </Register>
+    <Register name="MDMA_C11IFCR" description="MDMA channel x interrupt flag clear register" start="+0x304" size="4" access="WriteOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CTEIF11" description="Channel x clear transfer error interrupt flag Writing a 1 into this bit clears TEIFx in the MDMA_ISRy register" start="0" size="1" />
+      <BitField name="CCTCIF11" description="Clear Channel transfer complete interrupt flag for channel x Writing a 1 into this bit clears CTCIFx in the MDMA_ISRy register" start="1" size="1" />
+      <BitField name="CBRTIF11" description="Channel x clear block repeat transfer complete interrupt flag Writing a 1 into this bit clears BRTIFx in the MDMA_ISRy register" start="2" size="1" />
+      <BitField name="CBTIF11" description="Channel x Clear block transfer complete interrupt flag Writing a 1 into this bit clears BTIFx in the MDMA_ISRy register" start="3" size="1" />
+      <BitField name="CLTCIF11" description="CLear buffer Transfer Complete Interrupt Flag for channel x Writing a 1 into this bit clears TCIFx in the MDMA_ISRy register" start="4" size="1" />
+    </Register>
+    <Register name="MDMA_C11ESR" description="MDMA Channel x error status register" start="+0x308" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TEA" description="Transfer Error Address These bits are set and cleared by HW, in case of an MDMA data transfer error. It is used in conjunction with TED. This field indicates the 7 LSBits of the address which generated a transfer/access error. It may be used by SW to retrieve the failing address, by adding this value (truncated to the buffer transfer length size) to the current SAR/DAR value. Note: The SAR/DAR current value doesnt reflect this last address due to the FIFO management system. The SAR/DAR are only updated at the end of a (buffer) transfer (of TLEN+1 bytes). Note: It is not set in case of a link data error." start="0" size="7" />
+      <BitField name="TED" description="Transfer Error Direction These bit is set and cleared by HW, in case of an MDMA data transfer error." start="7" size="1" />
+      <BitField name="TELD" description="Transfer Error Link Data These bit is set by HW, in case of a transfer error while reading the block link data structure. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register." start="8" size="1" />
+      <BitField name="TEMD" description="Transfer Error Mask Data These bit is set by HW, in case of a transfer error while writing the Mask Data. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register." start="9" size="1" />
+      <BitField name="ASE" description="Address/Size Error These bit is set by HW, when the programmed address is not aligned with the data size. TED will indicate whether the problem is on the source or destination. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register." start="10" size="1" />
+      <BitField name="BSE" description="Block Size Error These bit is set by HW, when the block size is not an integer multiple of the data size either for source or destination. TED will indicate whether the problem is on the source or destination. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register." start="11" size="1" />
+    </Register>
+    <Register name="MDMA_C11CR" description="This register is used to control the concerned channel." start="+0x30C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="channel enable" start="0" size="1" access="Read/Write" />
+      <BitField name="TEIE" description="Transfer error interrupt enable This bit is set and cleared by software." start="1" size="1" access="Read/Write" />
+      <BitField name="CTCIE" description="Channel Transfer Complete interrupt enable This bit is set and cleared by software." start="2" size="1" access="Read/Write" />
+      <BitField name="BRTIE" description="Block Repeat transfer interrupt enable This bit is set and cleared by software." start="3" size="1" access="Read/Write" />
+      <BitField name="BTIE" description="Block Transfer interrupt enable This bit is set and cleared by software." start="4" size="1" access="Read/Write" />
+      <BitField name="TCIE" description="buffer Transfer Complete interrupt enable This bit is set and cleared by software." start="5" size="1" access="Read/Write" />
+      <BitField name="PL" description="Priority level These bits are set and cleared by software. These bits are protected and can be written only if EN is 0." start="6" size="2" access="Read/Write" />
+      <BitField name="BEX" description="byte Endianness exchange" start="12" size="1" access="Read/Write" />
+      <BitField name="HEX" description="Half word Endianes exchange" start="13" size="1" access="Read/Write" />
+      <BitField name="WEX" description="Word Endianness exchange" start="14" size="1" access="Read/Write" />
+      <BitField name="SWRQ" description="SW ReQuest Writing a 1 into this bit sets the CRQAx in MDMA_ISRy register, activating the request on Channel x Note: Either the whole CxCR register or the 8-bit/16-bit register @ Address offset: 0x4E + 0x40 chn may be used for SWRQ activation. In case of a SW request, acknowledge is not generated (neither HW signal, nor CxMAR write access)." start="16" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="MDMA_C11TCR" description="This register is used to configure the concerned channel." start="+0x310" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SINC" description="Source increment mode These bits are set and cleared by software. These bits are protected and can be written only if EN is 0 Note: When source is AHB (SBUS=1), SINC = 00 is forbidden. In Linked List Mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00)." start="0" size="2" />
+      <BitField name="DINC" description="Destination increment mode These bits are set and cleared by software. These bits are protected and can be written only if EN is 0 Note: When destination is AHB (DBUS=1), DINC = 00 is forbidden." start="2" size="2" />
+      <BitField name="SSIZE" description="Source data size These bits are set and cleared by software. These bits are protected and can be written only if EN is 0 Note: If a value of 11 is programmed for the TCM access/AHB port, a transfer error will occur (TEIF bit set) If SINCOS &amp;lt; SSIZE and SINC &amp;#8800; 00, the result will be unpredictable. Note: SSIZE = 11 (double-word) is forbidden when source is TCM/AHB bus (SBUS=1)." start="4" size="2" />
+      <BitField name="DSIZE" description="Destination data size These bits are set and cleared by software. These bits are protected and can be written only if EN is 0. Note: If a value of 11 is programmed for the TCM access/AHB port, a transfer error will occur (TEIF bit set) If DINCOS &amp;lt; DSIZE and DINC &amp;#8800; 00, the result will be unpredictable. Note: DSIZE = 11 (double-word) is forbidden when destination is TCM/AHB bus (DBUS=1)." start="6" size="2" />
+      <BitField name="SINCOS" description="source increment offset size" start="8" size="2" />
+      <BitField name="DINCOS" description="Destination increment offset" start="10" size="2" />
+      <BitField name="SBURST" description="source burst transfer configuration" start="12" size="3" />
+      <BitField name="DBURST" description="Destination burst transfer configuration" start="15" size="3" />
+      <BitField name="TLEN" description="buffer transfer lengh" start="18" size="7" />
+      <BitField name="PKE" description="PacK Enable These bit is set and cleared by software. If the Source Size is smaller than the destination, it will be padded according to the PAM value. If the Source data size is larger than the destination one, it will be truncated. The alignment will be done according to the PAM[0] value. This bit is protected and can be written only if EN is 0" start="25" size="1" />
+      <BitField name="PAM" description="Padding/Alignement Mode These bits are set and cleared by software. Case 1: Source data size smaller than destination data size - 3 options are valid. Case 2: Source data size larger than destination data size. The remainder part is discarded. When PKE = 1 or DSIZE=SSIZE, these bits are ignored. These bits are protected and can be written only if EN is 0" start="26" size="2" />
+      <BitField name="TRGM" description="Trigger Mode These bits are set and cleared by software. Note: If TRGM is 11 for the current block, all the values loaded at the end of the current block through the linked list mechanism must keep the same value (TRGM=11) and the same SWRM value, otherwise the result is undefined. These bits are protected and can be written only if EN is 0." start="28" size="2" />
+      <BitField name="SWRM" description="SW Request Mode This bit is set and cleared by software. If a HW or SW request is currently active, the bit change will be delayed until the current transfer is completed. If the CxMAR contains a valid address, the CxMDR value will also be written @ CxMAR address. This bit is protected and can be written only if EN is 0." start="30" size="1" />
+      <BitField name="BWM" description="Bufferable Write Mode This bit is set and cleared by software. This bit is protected and can be written only if EN is 0. Note: All MDMA destination accesses are non-cacheable." start="31" size="1" />
+    </Register>
+    <Register name="MDMA_C11BNDTR" description="MDMA Channel x block number of data register" start="+0x314" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BNDT" description="block number of data to transfer" start="0" size="17" />
+      <BitField name="BRSUM" description="Block Repeat Source address Update Mode These bits are protected and can be written only if EN is 0." start="18" size="1" />
+      <BitField name="BRDUM" description="Block Repeat Destination address Update Mode These bits are protected and can be written only if EN is 0." start="19" size="1" />
+      <BitField name="BRC" description="Block Repeat Count This field contains the number of repetitions of the current block (0 to 4095). When the channel is enabled, this register is read-only, indicating the remaining number of blocks, excluding the current one. This register decrements after each complete block transfer. Once the last block transfer has completed, this register can either stay at zero or be reloaded automatically from memory (in Linked List mode - i.e. Link Address valid). These bits are protected and can be written only if EN is 0." start="20" size="12" />
+    </Register>
+    <Register name="MDMA_C11SAR" description="MDMA channel x source address register" start="+0x318" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SAR" description="source adr base" start="0" size="32" />
+    </Register>
+    <Register name="MDMA_C11DAR" description="MDMA channel x destination address register" start="+0x31C" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DAR" description="Destination adr base" start="0" size="32" />
+    </Register>
+    <Register name="MDMA_C11BRUR" description="MDMA channel x Block Repeat address Update register" start="+0x320" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SUV" description="source adresse update value" start="0" size="16" />
+      <BitField name="DUV" description="destination address update" start="16" size="16" />
+    </Register>
+    <Register name="MDMA_C11LAR" description="MDMA channel x Link Address register" start="+0x324" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LAR" description="Link address register" start="0" size="32" />
+    </Register>
+    <Register name="MDMA_C11TBR" description="MDMA channel x Trigger and Bus selection Register" start="+0x328" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TSEL" description="Trigger selection" start="0" size="6" />
+      <BitField name="SBUS" description="Source BUS select This bit is protected and can be written only if EN is 0." start="16" size="1" />
+      <BitField name="DBUS" description="Destination BUS slect This bit is protected and can be written only if EN is 0." start="17" size="1" />
+    </Register>
+    <Register name="MDMA_C11MAR" description="MDMA channel x Mask address register" start="+0x330" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MAR" description="Mask address" start="0" size="32" />
+    </Register>
+    <Register name="MDMA_C11MDR" description="MDMA channel x Mask Data register" start="+0x334" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MDR" description="Mask data" start="0" size="32" />
+    </Register>
+    <Register name="MDMA_C12ISR" description="MDMA channel x interrupt/status register" start="+0x340" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TEIF12" description="Channel x transfer error interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register." start="0" size="1" />
+      <BitField name="CTCIF12" description="Channel x Channel Transfer Complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register. CTC is set when the last block was transferred and the channel has been automatically disabled. CTC is also set when the channel is suspended, as a result of writing EN bit to 0." start="1" size="1" />
+      <BitField name="BRTIF12" description="Channel x block repeat transfer complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register." start="2" size="1" />
+      <BitField name="BTIF12" description="Channel x block transfer complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register." start="3" size="1" />
+      <BitField name="TCIF12" description="channel x buffer transfer complete" start="4" size="1" />
+      <BitField name="CRQA12" description="channel x request active flag" start="16" size="1" />
+    </Register>
+    <Register name="MDMA_C12IFCR" description="MDMA channel x interrupt flag clear register" start="+0x344" size="4" access="WriteOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CTEIF12" description="Channel x clear transfer error interrupt flag Writing a 1 into this bit clears TEIFx in the MDMA_ISRy register" start="0" size="1" />
+      <BitField name="CCTCIF12" description="Clear Channel transfer complete interrupt flag for channel x Writing a 1 into this bit clears CTCIFx in the MDMA_ISRy register" start="1" size="1" />
+      <BitField name="CBRTIF12" description="Channel x clear block repeat transfer complete interrupt flag Writing a 1 into this bit clears BRTIFx in the MDMA_ISRy register" start="2" size="1" />
+      <BitField name="CBTIF12" description="Channel x Clear block transfer complete interrupt flag Writing a 1 into this bit clears BTIFx in the MDMA_ISRy register" start="3" size="1" />
+      <BitField name="CLTCIF12" description="CLear buffer Transfer Complete Interrupt Flag for channel x Writing a 1 into this bit clears TCIFx in the MDMA_ISRy register" start="4" size="1" />
+    </Register>
+    <Register name="MDMA_C12ESR" description="MDMA Channel x error status register" start="+0x348" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TEA" description="Transfer Error Address These bits are set and cleared by HW, in case of an MDMA data transfer error. It is used in conjunction with TED. This field indicates the 7 LSBits of the address which generated a transfer/access error. It may be used by SW to retrieve the failing address, by adding this value (truncated to the buffer transfer length size) to the current SAR/DAR value. Note: The SAR/DAR current value doesnt reflect this last address due to the FIFO management system. The SAR/DAR are only updated at the end of a (buffer) transfer (of TLEN+1 bytes). Note: It is not set in case of a link data error." start="0" size="7" />
+      <BitField name="TED" description="Transfer Error Direction These bit is set and cleared by HW, in case of an MDMA data transfer error." start="7" size="1" />
+      <BitField name="TELD" description="Transfer Error Link Data These bit is set by HW, in case of a transfer error while reading the block link data structure. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register." start="8" size="1" />
+      <BitField name="TEMD" description="Transfer Error Mask Data These bit is set by HW, in case of a transfer error while writing the Mask Data. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register." start="9" size="1" />
+      <BitField name="ASE" description="Address/Size Error These bit is set by HW, when the programmed address is not aligned with the data size. TED will indicate whether the problem is on the source or destination. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register." start="10" size="1" />
+      <BitField name="BSE" description="Block Size Error These bit is set by HW, when the block size is not an integer multiple of the data size either for source or destination. TED will indicate whether the problem is on the source or destination. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register." start="11" size="1" />
+    </Register>
+    <Register name="MDMA_C12CR" description="This register is used to control the concerned channel." start="+0x34C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="channel enable" start="0" size="1" access="Read/Write" />
+      <BitField name="TEIE" description="Transfer error interrupt enable This bit is set and cleared by software." start="1" size="1" access="Read/Write" />
+      <BitField name="CTCIE" description="Channel Transfer Complete interrupt enable This bit is set and cleared by software." start="2" size="1" access="Read/Write" />
+      <BitField name="BRTIE" description="Block Repeat transfer interrupt enable This bit is set and cleared by software." start="3" size="1" access="Read/Write" />
+      <BitField name="BTIE" description="Block Transfer interrupt enable This bit is set and cleared by software." start="4" size="1" access="Read/Write" />
+      <BitField name="TCIE" description="buffer Transfer Complete interrupt enable This bit is set and cleared by software." start="5" size="1" access="Read/Write" />
+      <BitField name="PL" description="Priority level These bits are set and cleared by software. These bits are protected and can be written only if EN is 0." start="6" size="2" access="Read/Write" />
+      <BitField name="BEX" description="byte Endianness exchange" start="12" size="1" access="Read/Write" />
+      <BitField name="HEX" description="Half word Endianes exchange" start="13" size="1" access="Read/Write" />
+      <BitField name="WEX" description="Word Endianness exchange" start="14" size="1" access="Read/Write" />
+      <BitField name="SWRQ" description="SW ReQuest Writing a 1 into this bit sets the CRQAx in MDMA_ISRy register, activating the request on Channel x Note: Either the whole CxCR register or the 8-bit/16-bit register @ Address offset: 0x4E + 0x40 chn may be used for SWRQ activation. In case of a SW request, acknowledge is not generated (neither HW signal, nor CxMAR write access)." start="16" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="MDMA_C12TCR" description="This register is used to configure the concerned channel." start="+0x350" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SINC" description="Source increment mode These bits are set and cleared by software. These bits are protected and can be written only if EN is 0 Note: When source is AHB (SBUS=1), SINC = 00 is forbidden. In Linked List Mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00)." start="0" size="2" />
+      <BitField name="DINC" description="Destination increment mode These bits are set and cleared by software. These bits are protected and can be written only if EN is 0 Note: When destination is AHB (DBUS=1), DINC = 00 is forbidden." start="2" size="2" />
+      <BitField name="SSIZE" description="Source data size These bits are set and cleared by software. These bits are protected and can be written only if EN is 0 Note: If a value of 11 is programmed for the TCM access/AHB port, a transfer error will occur (TEIF bit set) If SINCOS &amp;lt; SSIZE and SINC &amp;#8800; 00, the result will be unpredictable. Note: SSIZE = 11 (double-word) is forbidden when source is TCM/AHB bus (SBUS=1)." start="4" size="2" />
+      <BitField name="DSIZE" description="Destination data size These bits are set and cleared by software. These bits are protected and can be written only if EN is 0. Note: If a value of 11 is programmed for the TCM access/AHB port, a transfer error will occur (TEIF bit set) If DINCOS &amp;lt; DSIZE and DINC &amp;#8800; 00, the result will be unpredictable. Note: DSIZE = 11 (double-word) is forbidden when destination is TCM/AHB bus (DBUS=1)." start="6" size="2" />
+      <BitField name="SINCOS" description="source increment offset size" start="8" size="2" />
+      <BitField name="DINCOS" description="Destination increment offset" start="10" size="2" />
+      <BitField name="SBURST" description="source burst transfer configuration" start="12" size="3" />
+      <BitField name="DBURST" description="Destination burst transfer configuration" start="15" size="3" />
+      <BitField name="TLEN" description="buffer transfer lengh" start="18" size="7" />
+      <BitField name="PKE" description="PacK Enable These bit is set and cleared by software. If the Source Size is smaller than the destination, it will be padded according to the PAM value. If the Source data size is larger than the destination one, it will be truncated. The alignment will be done according to the PAM[0] value. This bit is protected and can be written only if EN is 0" start="25" size="1" />
+      <BitField name="PAM" description="Padding/Alignement Mode These bits are set and cleared by software. Case 1: Source data size smaller than destination data size - 3 options are valid. Case 2: Source data size larger than destination data size. The remainder part is discarded. When PKE = 1 or DSIZE=SSIZE, these bits are ignored. These bits are protected and can be written only if EN is 0" start="26" size="2" />
+      <BitField name="TRGM" description="Trigger Mode These bits are set and cleared by software. Note: If TRGM is 11 for the current block, all the values loaded at the end of the current block through the linked list mechanism must keep the same value (TRGM=11) and the same SWRM value, otherwise the result is undefined. These bits are protected and can be written only if EN is 0." start="28" size="2" />
+      <BitField name="SWRM" description="SW Request Mode This bit is set and cleared by software. If a HW or SW request is currently active, the bit change will be delayed until the current transfer is completed. If the CxMAR contains a valid address, the CxMDR value will also be written @ CxMAR address. This bit is protected and can be written only if EN is 0." start="30" size="1" />
+      <BitField name="BWM" description="Bufferable Write Mode This bit is set and cleared by software. This bit is protected and can be written only if EN is 0. Note: All MDMA destination accesses are non-cacheable." start="31" size="1" />
+    </Register>
+    <Register name="MDMA_C12BNDTR" description="MDMA Channel x block number of data register" start="+0x354" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BNDT" description="block number of data to transfer" start="0" size="17" />
+      <BitField name="BRSUM" description="Block Repeat Source address Update Mode These bits are protected and can be written only if EN is 0." start="18" size="1" />
+      <BitField name="BRDUM" description="Block Repeat Destination address Update Mode These bits are protected and can be written only if EN is 0." start="19" size="1" />
+      <BitField name="BRC" description="Block Repeat Count This field contains the number of repetitions of the current block (0 to 4095). When the channel is enabled, this register is read-only, indicating the remaining number of blocks, excluding the current one. This register decrements after each complete block transfer. Once the last block transfer has completed, this register can either stay at zero or be reloaded automatically from memory (in Linked List mode - i.e. Link Address valid). These bits are protected and can be written only if EN is 0." start="20" size="12" />
+    </Register>
+    <Register name="MDMA_C12SAR" description="MDMA channel x source address register" start="+0x358" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SAR" description="source adr base" start="0" size="32" />
+    </Register>
+    <Register name="MDMA_C12DAR" description="MDMA channel x destination address register" start="+0x35C" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DAR" description="Destination adr base" start="0" size="32" />
+    </Register>
+    <Register name="MDMA_C12BRUR" description="MDMA channel x Block Repeat address Update register" start="+0x360" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SUV" description="source adresse update value" start="0" size="16" />
+      <BitField name="DUV" description="destination address update" start="16" size="16" />
+    </Register>
+    <Register name="MDMA_C12LAR" description="MDMA channel x Link Address register" start="+0x364" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LAR" description="Link address register" start="0" size="32" />
+    </Register>
+    <Register name="MDMA_C12TBR" description="MDMA channel x Trigger and Bus selection Register" start="+0x368" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TSEL" description="Trigger selection" start="0" size="6" />
+      <BitField name="SBUS" description="Source BUS select This bit is protected and can be written only if EN is 0." start="16" size="1" />
+      <BitField name="DBUS" description="Destination BUS slect This bit is protected and can be written only if EN is 0." start="17" size="1" />
+    </Register>
+    <Register name="MDMA_C12MAR" description="MDMA channel x Mask address register" start="+0x370" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MAR" description="Mask address" start="0" size="32" />
+    </Register>
+    <Register name="MDMA_C12MDR" description="MDMA channel x Mask Data register" start="+0x374" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MDR" description="Mask data" start="0" size="32" />
+    </Register>
+    <Register name="MDMA_C13ISR" description="MDMA channel x interrupt/status register" start="+0x380" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TEIF13" description="Channel x transfer error interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register." start="0" size="1" />
+      <BitField name="CTCIF13" description="Channel x Channel Transfer Complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register. CTC is set when the last block was transferred and the channel has been automatically disabled. CTC is also set when the channel is suspended, as a result of writing EN bit to 0." start="1" size="1" />
+      <BitField name="BRTIF13" description="Channel x block repeat transfer complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register." start="2" size="1" />
+      <BitField name="BTIF13" description="Channel x block transfer complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register." start="3" size="1" />
+      <BitField name="TCIF13" description="channel x buffer transfer complete" start="4" size="1" />
+      <BitField name="CRQA13" description="channel x request active flag" start="16" size="1" />
+    </Register>
+    <Register name="MDMA_C13IFCR" description="MDMA channel x interrupt flag clear register" start="+0x384" size="4" access="WriteOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CTEIF13" description="Channel x clear transfer error interrupt flag Writing a 1 into this bit clears TEIFx in the MDMA_ISRy register" start="0" size="1" />
+      <BitField name="CCTCIF13" description="Clear Channel transfer complete interrupt flag for channel x Writing a 1 into this bit clears CTCIFx in the MDMA_ISRy register" start="1" size="1" />
+      <BitField name="CBRTIF13" description="Channel x clear block repeat transfer complete interrupt flag Writing a 1 into this bit clears BRTIFx in the MDMA_ISRy register" start="2" size="1" />
+      <BitField name="CBTIF13" description="Channel x Clear block transfer complete interrupt flag Writing a 1 into this bit clears BTIFx in the MDMA_ISRy register" start="3" size="1" />
+      <BitField name="CLTCIF13" description="CLear buffer Transfer Complete Interrupt Flag for channel x Writing a 1 into this bit clears TCIFx in the MDMA_ISRy register" start="4" size="1" />
+    </Register>
+    <Register name="MDMA_C13ESR" description="MDMA Channel x error status register" start="+0x388" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TEA" description="Transfer Error Address These bits are set and cleared by HW, in case of an MDMA data transfer error. It is used in conjunction with TED. This field indicates the 7 LSBits of the address which generated a transfer/access error. It may be used by SW to retrieve the failing address, by adding this value (truncated to the buffer transfer length size) to the current SAR/DAR value. Note: The SAR/DAR current value doesnt reflect this last address due to the FIFO management system. The SAR/DAR are only updated at the end of a (buffer) transfer (of TLEN+1 bytes). Note: It is not set in case of a link data error." start="0" size="7" />
+      <BitField name="TED" description="Transfer Error Direction These bit is set and cleared by HW, in case of an MDMA data transfer error." start="7" size="1" />
+      <BitField name="TELD" description="Transfer Error Link Data These bit is set by HW, in case of a transfer error while reading the block link data structure. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register." start="8" size="1" />
+      <BitField name="TEMD" description="Transfer Error Mask Data These bit is set by HW, in case of a transfer error while writing the Mask Data. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register." start="9" size="1" />
+      <BitField name="ASE" description="Address/Size Error These bit is set by HW, when the programmed address is not aligned with the data size. TED will indicate whether the problem is on the source or destination. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register." start="10" size="1" />
+      <BitField name="BSE" description="Block Size Error These bit is set by HW, when the block size is not an integer multiple of the data size either for source or destination. TED will indicate whether the problem is on the source or destination. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register." start="11" size="1" />
+    </Register>
+    <Register name="MDMA_C13CR" description="This register is used to control the concerned channel." start="+0x38C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="channel enable" start="0" size="1" access="Read/Write" />
+      <BitField name="TEIE" description="Transfer error interrupt enable This bit is set and cleared by software." start="1" size="1" access="Read/Write" />
+      <BitField name="CTCIE" description="Channel Transfer Complete interrupt enable This bit is set and cleared by software." start="2" size="1" access="Read/Write" />
+      <BitField name="BRTIE" description="Block Repeat transfer interrupt enable This bit is set and cleared by software." start="3" size="1" access="Read/Write" />
+      <BitField name="BTIE" description="Block Transfer interrupt enable This bit is set and cleared by software." start="4" size="1" access="Read/Write" />
+      <BitField name="TCIE" description="buffer Transfer Complete interrupt enable This bit is set and cleared by software." start="5" size="1" access="Read/Write" />
+      <BitField name="PL" description="Priority level These bits are set and cleared by software. These bits are protected and can be written only if EN is 0." start="6" size="2" access="Read/Write" />
+      <BitField name="BEX" description="byte Endianness exchange" start="12" size="1" access="Read/Write" />
+      <BitField name="HEX" description="Half word Endianes exchange" start="13" size="1" access="Read/Write" />
+      <BitField name="WEX" description="Word Endianness exchange" start="14" size="1" access="Read/Write" />
+      <BitField name="SWRQ" description="SW ReQuest Writing a 1 into this bit sets the CRQAx in MDMA_ISRy register, activating the request on Channel x Note: Either the whole CxCR register or the 8-bit/16-bit register @ Address offset: 0x4E + 0x40 chn may be used for SWRQ activation. In case of a SW request, acknowledge is not generated (neither HW signal, nor CxMAR write access)." start="16" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="MDMA_C13TCR" description="This register is used to configure the concerned channel." start="+0x390" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SINC" description="Source increment mode These bits are set and cleared by software. These bits are protected and can be written only if EN is 0 Note: When source is AHB (SBUS=1), SINC = 00 is forbidden. In Linked List Mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00)." start="0" size="2" />
+      <BitField name="DINC" description="Destination increment mode These bits are set and cleared by software. These bits are protected and can be written only if EN is 0 Note: When destination is AHB (DBUS=1), DINC = 00 is forbidden." start="2" size="2" />
+      <BitField name="SSIZE" description="Source data size These bits are set and cleared by software. These bits are protected and can be written only if EN is 0 Note: If a value of 11 is programmed for the TCM access/AHB port, a transfer error will occur (TEIF bit set) If SINCOS &amp;lt; SSIZE and SINC &amp;#8800; 00, the result will be unpredictable. Note: SSIZE = 11 (double-word) is forbidden when source is TCM/AHB bus (SBUS=1)." start="4" size="2" />
+      <BitField name="DSIZE" description="Destination data size These bits are set and cleared by software. These bits are protected and can be written only if EN is 0. Note: If a value of 11 is programmed for the TCM access/AHB port, a transfer error will occur (TEIF bit set) If DINCOS &amp;lt; DSIZE and DINC &amp;#8800; 00, the result will be unpredictable. Note: DSIZE = 11 (double-word) is forbidden when destination is TCM/AHB bus (DBUS=1)." start="6" size="2" />
+      <BitField name="SINCOS" description="source increment offset size" start="8" size="2" />
+      <BitField name="DINCOS" description="Destination increment offset" start="10" size="2" />
+      <BitField name="SBURST" description="source burst transfer configuration" start="12" size="3" />
+      <BitField name="DBURST" description="Destination burst transfer configuration" start="15" size="3" />
+      <BitField name="TLEN" description="buffer transfer lengh" start="18" size="7" />
+      <BitField name="PKE" description="PacK Enable These bit is set and cleared by software. If the Source Size is smaller than the destination, it will be padded according to the PAM value. If the Source data size is larger than the destination one, it will be truncated. The alignment will be done according to the PAM[0] value. This bit is protected and can be written only if EN is 0" start="25" size="1" />
+      <BitField name="PAM" description="Padding/Alignement Mode These bits are set and cleared by software. Case 1: Source data size smaller than destination data size - 3 options are valid. Case 2: Source data size larger than destination data size. The remainder part is discarded. When PKE = 1 or DSIZE=SSIZE, these bits are ignored. These bits are protected and can be written only if EN is 0" start="26" size="2" />
+      <BitField name="TRGM" description="Trigger Mode These bits are set and cleared by software. Note: If TRGM is 11 for the current block, all the values loaded at the end of the current block through the linked list mechanism must keep the same value (TRGM=11) and the same SWRM value, otherwise the result is undefined. These bits are protected and can be written only if EN is 0." start="28" size="2" />
+      <BitField name="SWRM" description="SW Request Mode This bit is set and cleared by software. If a HW or SW request is currently active, the bit change will be delayed until the current transfer is completed. If the CxMAR contains a valid address, the CxMDR value will also be written @ CxMAR address. This bit is protected and can be written only if EN is 0." start="30" size="1" />
+      <BitField name="BWM" description="Bufferable Write Mode This bit is set and cleared by software. This bit is protected and can be written only if EN is 0. Note: All MDMA destination accesses are non-cacheable." start="31" size="1" />
+    </Register>
+    <Register name="MDMA_C13BNDTR" description="MDMA Channel x block number of data register" start="+0x394" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BNDT" description="block number of data to transfer" start="0" size="17" />
+      <BitField name="BRSUM" description="Block Repeat Source address Update Mode These bits are protected and can be written only if EN is 0." start="18" size="1" />
+      <BitField name="BRDUM" description="Block Repeat Destination address Update Mode These bits are protected and can be written only if EN is 0." start="19" size="1" />
+      <BitField name="BRC" description="Block Repeat Count This field contains the number of repetitions of the current block (0 to 4095). When the channel is enabled, this register is read-only, indicating the remaining number of blocks, excluding the current one. This register decrements after each complete block transfer. Once the last block transfer has completed, this register can either stay at zero or be reloaded automatically from memory (in Linked List mode - i.e. Link Address valid). These bits are protected and can be written only if EN is 0." start="20" size="12" />
+    </Register>
+    <Register name="MDMA_C13SAR" description="MDMA channel x source address register" start="+0x398" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SAR" description="source adr base" start="0" size="32" />
+    </Register>
+    <Register name="MDMA_C13DAR" description="MDMA channel x destination address register" start="+0x39C" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DAR" description="Destination adr base" start="0" size="32" />
+    </Register>
+    <Register name="MDMA_C13BRUR" description="MDMA channel x Block Repeat address Update register" start="+0x3A0" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SUV" description="source adresse update value" start="0" size="16" />
+      <BitField name="DUV" description="destination address update" start="16" size="16" />
+    </Register>
+    <Register name="MDMA_C13LAR" description="MDMA channel x Link Address register" start="+0x3A4" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LAR" description="Link address register" start="0" size="32" />
+    </Register>
+    <Register name="MDMA_C13TBR" description="MDMA channel x Trigger and Bus selection Register" start="+0x3A8" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TSEL" description="Trigger selection" start="0" size="6" />
+      <BitField name="SBUS" description="Source BUS select This bit is protected and can be written only if EN is 0." start="16" size="1" />
+      <BitField name="DBUS" description="Destination BUS slect This bit is protected and can be written only if EN is 0." start="17" size="1" />
+    </Register>
+    <Register name="MDMA_C13MAR" description="MDMA channel x Mask address register" start="+0x3B0" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MAR" description="Mask address" start="0" size="32" />
+    </Register>
+    <Register name="MDMA_C13MDR" description="MDMA channel x Mask Data register" start="+0x3B4" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MDR" description="Mask data" start="0" size="32" />
+    </Register>
+    <Register name="MDMA_C14ISR" description="MDMA channel x interrupt/status register" start="+0x3C0" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TEIF14" description="Channel x transfer error interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register." start="0" size="1" />
+      <BitField name="CTCIF14" description="Channel x Channel Transfer Complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register. CTC is set when the last block was transferred and the channel has been automatically disabled. CTC is also set when the channel is suspended, as a result of writing EN bit to 0." start="1" size="1" />
+      <BitField name="BRTIF14" description="Channel x block repeat transfer complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register." start="2" size="1" />
+      <BitField name="BTIF14" description="Channel x block transfer complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register." start="3" size="1" />
+      <BitField name="TCIF14" description="channel x buffer transfer complete" start="4" size="1" />
+      <BitField name="CRQA14" description="channel x request active flag" start="16" size="1" />
+    </Register>
+    <Register name="MDMA_C14IFCR" description="MDMA channel x interrupt flag clear register" start="+0x3C4" size="4" access="WriteOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CTEIF14" description="Channel x clear transfer error interrupt flag Writing a 1 into this bit clears TEIFx in the MDMA_ISRy register" start="0" size="1" />
+      <BitField name="CCTCIF14" description="Clear Channel transfer complete interrupt flag for channel x Writing a 1 into this bit clears CTCIFx in the MDMA_ISRy register" start="1" size="1" />
+      <BitField name="CBRTIF14" description="Channel x clear block repeat transfer complete interrupt flag Writing a 1 into this bit clears BRTIFx in the MDMA_ISRy register" start="2" size="1" />
+      <BitField name="CBTIF14" description="Channel x Clear block transfer complete interrupt flag Writing a 1 into this bit clears BTIFx in the MDMA_ISRy register" start="3" size="1" />
+      <BitField name="CLTCIF14" description="CLear buffer Transfer Complete Interrupt Flag for channel x Writing a 1 into this bit clears TCIFx in the MDMA_ISRy register" start="4" size="1" />
+    </Register>
+    <Register name="MDMA_C14ESR" description="MDMA Channel x error status register" start="+0x3C8" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TEA" description="Transfer Error Address These bits are set and cleared by HW, in case of an MDMA data transfer error. It is used in conjunction with TED. This field indicates the 7 LSBits of the address which generated a transfer/access error. It may be used by SW to retrieve the failing address, by adding this value (truncated to the buffer transfer length size) to the current SAR/DAR value. Note: The SAR/DAR current value doesnt reflect this last address due to the FIFO management system. The SAR/DAR are only updated at the end of a (buffer) transfer (of TLEN+1 bytes). Note: It is not set in case of a link data error." start="0" size="7" />
+      <BitField name="TED" description="Transfer Error Direction These bit is set and cleared by HW, in case of an MDMA data transfer error." start="7" size="1" />
+      <BitField name="TELD" description="Transfer Error Link Data These bit is set by HW, in case of a transfer error while reading the block link data structure. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register." start="8" size="1" />
+      <BitField name="TEMD" description="Transfer Error Mask Data These bit is set by HW, in case of a transfer error while writing the Mask Data. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register." start="9" size="1" />
+      <BitField name="ASE" description="Address/Size Error These bit is set by HW, when the programmed address is not aligned with the data size. TED will indicate whether the problem is on the source or destination. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register." start="10" size="1" />
+      <BitField name="BSE" description="Block Size Error These bit is set by HW, when the block size is not an integer multiple of the data size either for source or destination. TED will indicate whether the problem is on the source or destination. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register." start="11" size="1" />
+    </Register>
+    <Register name="MDMA_C14CR" description="This register is used to control the concerned channel." start="+0x3CC" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="channel enable" start="0" size="1" access="Read/Write" />
+      <BitField name="TEIE" description="Transfer error interrupt enable This bit is set and cleared by software." start="1" size="1" access="Read/Write" />
+      <BitField name="CTCIE" description="Channel Transfer Complete interrupt enable This bit is set and cleared by software." start="2" size="1" access="Read/Write" />
+      <BitField name="BRTIE" description="Block Repeat transfer interrupt enable This bit is set and cleared by software." start="3" size="1" access="Read/Write" />
+      <BitField name="BTIE" description="Block Transfer interrupt enable This bit is set and cleared by software." start="4" size="1" access="Read/Write" />
+      <BitField name="TCIE" description="buffer Transfer Complete interrupt enable This bit is set and cleared by software." start="5" size="1" access="Read/Write" />
+      <BitField name="PL" description="Priority level These bits are set and cleared by software. These bits are protected and can be written only if EN is 0." start="6" size="2" access="Read/Write" />
+      <BitField name="BEX" description="byte Endianness exchange" start="12" size="1" access="Read/Write" />
+      <BitField name="HEX" description="Half word Endianes exchange" start="13" size="1" access="Read/Write" />
+      <BitField name="WEX" description="Word Endianness exchange" start="14" size="1" access="Read/Write" />
+      <BitField name="SWRQ" description="SW ReQuest Writing a 1 into this bit sets the CRQAx in MDMA_ISRy register, activating the request on Channel x Note: Either the whole CxCR register or the 8-bit/16-bit register @ Address offset: 0x4E + 0x40 chn may be used for SWRQ activation. In case of a SW request, acknowledge is not generated (neither HW signal, nor CxMAR write access)." start="16" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="MDMA_C14TCR" description="This register is used to configure the concerned channel." start="+0x3D0" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SINC" description="Source increment mode These bits are set and cleared by software. These bits are protected and can be written only if EN is 0 Note: When source is AHB (SBUS=1), SINC = 00 is forbidden. In Linked List Mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00)." start="0" size="2" />
+      <BitField name="DINC" description="Destination increment mode These bits are set and cleared by software. These bits are protected and can be written only if EN is 0 Note: When destination is AHB (DBUS=1), DINC = 00 is forbidden." start="2" size="2" />
+      <BitField name="SSIZE" description="Source data size These bits are set and cleared by software. These bits are protected and can be written only if EN is 0 Note: If a value of 11 is programmed for the TCM access/AHB port, a transfer error will occur (TEIF bit set) If SINCOS &amp;lt; SSIZE and SINC &amp;#8800; 00, the result will be unpredictable. Note: SSIZE = 11 (double-word) is forbidden when source is TCM/AHB bus (SBUS=1)." start="4" size="2" />
+      <BitField name="DSIZE" description="Destination data size These bits are set and cleared by software. These bits are protected and can be written only if EN is 0. Note: If a value of 11 is programmed for the TCM access/AHB port, a transfer error will occur (TEIF bit set) If DINCOS &amp;lt; DSIZE and DINC &amp;#8800; 00, the result will be unpredictable. Note: DSIZE = 11 (double-word) is forbidden when destination is TCM/AHB bus (DBUS=1)." start="6" size="2" />
+      <BitField name="SINCOS" description="source increment offset size" start="8" size="2" />
+      <BitField name="DINCOS" description="Destination increment offset" start="10" size="2" />
+      <BitField name="SBURST" description="source burst transfer configuration" start="12" size="3" />
+      <BitField name="DBURST" description="Destination burst transfer configuration" start="15" size="3" />
+      <BitField name="TLEN" description="buffer transfer lengh" start="18" size="7" />
+      <BitField name="PKE" description="PacK Enable These bit is set and cleared by software. If the Source Size is smaller than the destination, it will be padded according to the PAM value. If the Source data size is larger than the destination one, it will be truncated. The alignment will be done according to the PAM[0] value. This bit is protected and can be written only if EN is 0" start="25" size="1" />
+      <BitField name="PAM" description="Padding/Alignement Mode These bits are set and cleared by software. Case 1: Source data size smaller than destination data size - 3 options are valid. Case 2: Source data size larger than destination data size. The remainder part is discarded. When PKE = 1 or DSIZE=SSIZE, these bits are ignored. These bits are protected and can be written only if EN is 0" start="26" size="2" />
+      <BitField name="TRGM" description="Trigger Mode These bits are set and cleared by software. Note: If TRGM is 11 for the current block, all the values loaded at the end of the current block through the linked list mechanism must keep the same value (TRGM=11) and the same SWRM value, otherwise the result is undefined. These bits are protected and can be written only if EN is 0." start="28" size="2" />
+      <BitField name="SWRM" description="SW Request Mode This bit is set and cleared by software. If a HW or SW request is currently active, the bit change will be delayed until the current transfer is completed. If the CxMAR contains a valid address, the CxMDR value will also be written @ CxMAR address. This bit is protected and can be written only if EN is 0." start="30" size="1" />
+      <BitField name="BWM" description="Bufferable Write Mode This bit is set and cleared by software. This bit is protected and can be written only if EN is 0. Note: All MDMA destination accesses are non-cacheable." start="31" size="1" />
+    </Register>
+    <Register name="MDMA_C14BNDTR" description="MDMA Channel x block number of data register" start="+0x3D4" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BNDT" description="block number of data to transfer" start="0" size="17" />
+      <BitField name="BRSUM" description="Block Repeat Source address Update Mode These bits are protected and can be written only if EN is 0." start="18" size="1" />
+      <BitField name="BRDUM" description="Block Repeat Destination address Update Mode These bits are protected and can be written only if EN is 0." start="19" size="1" />
+      <BitField name="BRC" description="Block Repeat Count This field contains the number of repetitions of the current block (0 to 4095). When the channel is enabled, this register is read-only, indicating the remaining number of blocks, excluding the current one. This register decrements after each complete block transfer. Once the last block transfer has completed, this register can either stay at zero or be reloaded automatically from memory (in Linked List mode - i.e. Link Address valid). These bits are protected and can be written only if EN is 0." start="20" size="12" />
+    </Register>
+    <Register name="MDMA_C14SAR" description="MDMA channel x source address register" start="+0x3D8" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SAR" description="source adr base" start="0" size="32" />
+    </Register>
+    <Register name="MDMA_C14DAR" description="MDMA channel x destination address register" start="+0x3DC" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DAR" description="Destination adr base" start="0" size="32" />
+    </Register>
+    <Register name="MDMA_C14BRUR" description="MDMA channel x Block Repeat address Update register" start="+0x3E0" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SUV" description="source adresse update value" start="0" size="16" />
+      <BitField name="DUV" description="destination address update" start="16" size="16" />
+    </Register>
+    <Register name="MDMA_C14LAR" description="MDMA channel x Link Address register" start="+0x3E4" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LAR" description="Link address register" start="0" size="32" />
+    </Register>
+    <Register name="MDMA_C14TBR" description="MDMA channel x Trigger and Bus selection Register" start="+0x3E8" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TSEL" description="Trigger selection" start="0" size="6" />
+      <BitField name="SBUS" description="Source BUS select This bit is protected and can be written only if EN is 0." start="16" size="1" />
+      <BitField name="DBUS" description="Destination BUS slect This bit is protected and can be written only if EN is 0." start="17" size="1" />
+    </Register>
+    <Register name="MDMA_C14MAR" description="MDMA channel x Mask address register" start="+0x3F0" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MAR" description="Mask address" start="0" size="32" />
+    </Register>
+    <Register name="MDMA_C14MDR" description="MDMA channel x Mask Data register" start="+0x3F4" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MDR" description="Mask data" start="0" size="32" />
+    </Register>
+    <Register name="MDMA_C15ISR" description="MDMA channel x interrupt/status register" start="+0x400" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TEIF15" description="Channel x transfer error interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register." start="0" size="1" />
+      <BitField name="CTCIF15" description="Channel x Channel Transfer Complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register. CTC is set when the last block was transferred and the channel has been automatically disabled. CTC is also set when the channel is suspended, as a result of writing EN bit to 0." start="1" size="1" />
+      <BitField name="BRTIF15" description="Channel x block repeat transfer complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register." start="2" size="1" />
+      <BitField name="BTIF15" description="Channel x block transfer complete interrupt flag This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCRy register." start="3" size="1" />
+      <BitField name="TCIF15" description="channel x buffer transfer complete" start="4" size="1" />
+      <BitField name="CRQA15" description="channel x request active flag" start="16" size="1" />
+    </Register>
+    <Register name="MDMA_C15IFCR" description="MDMA channel x interrupt flag clear register" start="+0x404" size="4" access="WriteOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CTEIF15" description="Channel x clear transfer error interrupt flag Writing a 1 into this bit clears TEIFx in the MDMA_ISRy register" start="0" size="1" />
+      <BitField name="CCTCIF15" description="Clear Channel transfer complete interrupt flag for channel x Writing a 1 into this bit clears CTCIFx in the MDMA_ISRy register" start="1" size="1" />
+      <BitField name="CBRTIF15" description="Channel x clear block repeat transfer complete interrupt flag Writing a 1 into this bit clears BRTIFx in the MDMA_ISRy register" start="2" size="1" />
+      <BitField name="CBTIF15" description="Channel x Clear block transfer complete interrupt flag Writing a 1 into this bit clears BTIFx in the MDMA_ISRy register" start="3" size="1" />
+      <BitField name="CLTCIF15" description="CLear buffer Transfer Complete Interrupt Flag for channel x Writing a 1 into this bit clears TCIFx in the MDMA_ISRy register" start="4" size="1" />
+    </Register>
+    <Register name="MDMA_C15ESR" description="MDMA Channel x error status register" start="+0x408" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TEA" description="Transfer Error Address These bits are set and cleared by HW, in case of an MDMA data transfer error. It is used in conjunction with TED. This field indicates the 7 LSBits of the address which generated a transfer/access error. It may be used by SW to retrieve the failing address, by adding this value (truncated to the buffer transfer length size) to the current SAR/DAR value. Note: The SAR/DAR current value doesnt reflect this last address due to the FIFO management system. The SAR/DAR are only updated at the end of a (buffer) transfer (of TLEN+1 bytes). Note: It is not set in case of a link data error." start="0" size="7" />
+      <BitField name="TED" description="Transfer Error Direction These bit is set and cleared by HW, in case of an MDMA data transfer error." start="7" size="1" />
+      <BitField name="TELD" description="Transfer Error Link Data These bit is set by HW, in case of a transfer error while reading the block link data structure. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register." start="8" size="1" />
+      <BitField name="TEMD" description="Transfer Error Mask Data These bit is set by HW, in case of a transfer error while writing the Mask Data. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register." start="9" size="1" />
+      <BitField name="ASE" description="Address/Size Error These bit is set by HW, when the programmed address is not aligned with the data size. TED will indicate whether the problem is on the source or destination. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register." start="10" size="1" />
+      <BitField name="BSE" description="Block Size Error These bit is set by HW, when the block size is not an integer multiple of the data size either for source or destination. TED will indicate whether the problem is on the source or destination. It is cleared by software writing 1 to the CTEIFx bit in the DMA_IFCRy register." start="11" size="1" />
+    </Register>
+    <Register name="MDMA_C15CR" description="This register is used to control the concerned channel." start="+0x40C" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="channel enable" start="0" size="1" access="Read/Write" />
+      <BitField name="TEIE" description="Transfer error interrupt enable This bit is set and cleared by software." start="1" size="1" access="Read/Write" />
+      <BitField name="CTCIE" description="Channel Transfer Complete interrupt enable This bit is set and cleared by software." start="2" size="1" access="Read/Write" />
+      <BitField name="BRTIE" description="Block Repeat transfer interrupt enable This bit is set and cleared by software." start="3" size="1" access="Read/Write" />
+      <BitField name="BTIE" description="Block Transfer interrupt enable This bit is set and cleared by software." start="4" size="1" access="Read/Write" />
+      <BitField name="TCIE" description="buffer Transfer Complete interrupt enable This bit is set and cleared by software." start="5" size="1" access="Read/Write" />
+      <BitField name="PL" description="Priority level These bits are set and cleared by software. These bits are protected and can be written only if EN is 0." start="6" size="2" access="Read/Write" />
+      <BitField name="BEX" description="byte Endianness exchange" start="12" size="1" access="Read/Write" />
+      <BitField name="HEX" description="Half word Endianes exchange" start="13" size="1" access="Read/Write" />
+      <BitField name="WEX" description="Word Endianness exchange" start="14" size="1" access="Read/Write" />
+      <BitField name="SWRQ" description="SW ReQuest Writing a 1 into this bit sets the CRQAx in MDMA_ISRy register, activating the request on Channel x Note: Either the whole CxCR register or the 8-bit/16-bit register @ Address offset: 0x4E + 0x40 chn may be used for SWRQ activation. In case of a SW request, acknowledge is not generated (neither HW signal, nor CxMAR write access)." start="16" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="MDMA_C15TCR" description="This register is used to configure the concerned channel." start="+0x410" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SINC" description="Source increment mode These bits are set and cleared by software. These bits are protected and can be written only if EN is 0 Note: When source is AHB (SBUS=1), SINC = 00 is forbidden. In Linked List Mode, at the end of a block (single or last block in repeated block transfer mode), this register will be loaded from memory (from address given by current LAR[31:0] + 0x00)." start="0" size="2" />
+      <BitField name="DINC" description="Destination increment mode These bits are set and cleared by software. These bits are protected and can be written only if EN is 0 Note: When destination is AHB (DBUS=1), DINC = 00 is forbidden." start="2" size="2" />
+      <BitField name="SSIZE" description="Source data size These bits are set and cleared by software. These bits are protected and can be written only if EN is 0 Note: If a value of 11 is programmed for the TCM access/AHB port, a transfer error will occur (TEIF bit set) If SINCOS &amp;lt; SSIZE and SINC &amp;#8800; 00, the result will be unpredictable. Note: SSIZE = 11 (double-word) is forbidden when source is TCM/AHB bus (SBUS=1)." start="4" size="2" />
+      <BitField name="DSIZE" description="Destination data size These bits are set and cleared by software. These bits are protected and can be written only if EN is 0. Note: If a value of 11 is programmed for the TCM access/AHB port, a transfer error will occur (TEIF bit set) If DINCOS &amp;lt; DSIZE and DINC &amp;#8800; 00, the result will be unpredictable. Note: DSIZE = 11 (double-word) is forbidden when destination is TCM/AHB bus (DBUS=1)." start="6" size="2" />
+      <BitField name="SINCOS" description="source increment offset size" start="8" size="2" />
+      <BitField name="DINCOS" description="Destination increment offset" start="10" size="2" />
+      <BitField name="SBURST" description="source burst transfer configuration" start="12" size="3" />
+      <BitField name="DBURST" description="Destination burst transfer configuration" start="15" size="3" />
+      <BitField name="TLEN" description="buffer transfer lengh" start="18" size="7" />
+      <BitField name="PKE" description="PacK Enable These bit is set and cleared by software. If the Source Size is smaller than the destination, it will be padded according to the PAM value. If the Source data size is larger than the destination one, it will be truncated. The alignment will be done according to the PAM[0] value. This bit is protected and can be written only if EN is 0" start="25" size="1" />
+      <BitField name="PAM" description="Padding/Alignement Mode These bits are set and cleared by software. Case 1: Source data size smaller than destination data size - 3 options are valid. Case 2: Source data size larger than destination data size. The remainder part is discarded. When PKE = 1 or DSIZE=SSIZE, these bits are ignored. These bits are protected and can be written only if EN is 0" start="26" size="2" />
+      <BitField name="TRGM" description="Trigger Mode These bits are set and cleared by software. Note: If TRGM is 11 for the current block, all the values loaded at the end of the current block through the linked list mechanism must keep the same value (TRGM=11) and the same SWRM value, otherwise the result is undefined. These bits are protected and can be written only if EN is 0." start="28" size="2" />
+      <BitField name="SWRM" description="SW Request Mode This bit is set and cleared by software. If a HW or SW request is currently active, the bit change will be delayed until the current transfer is completed. If the CxMAR contains a valid address, the CxMDR value will also be written @ CxMAR address. This bit is protected and can be written only if EN is 0." start="30" size="1" />
+      <BitField name="BWM" description="Bufferable Write Mode This bit is set and cleared by software. This bit is protected and can be written only if EN is 0. Note: All MDMA destination accesses are non-cacheable." start="31" size="1" />
+    </Register>
+    <Register name="MDMA_C15BNDTR" description="MDMA Channel x block number of data register" start="+0x414" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BNDT" description="block number of data to transfer" start="0" size="17" />
+      <BitField name="BRSUM" description="Block Repeat Source address Update Mode These bits are protected and can be written only if EN is 0." start="18" size="1" />
+      <BitField name="BRDUM" description="Block Repeat Destination address Update Mode These bits are protected and can be written only if EN is 0." start="19" size="1" />
+      <BitField name="BRC" description="Block Repeat Count This field contains the number of repetitions of the current block (0 to 4095). When the channel is enabled, this register is read-only, indicating the remaining number of blocks, excluding the current one. This register decrements after each complete block transfer. Once the last block transfer has completed, this register can either stay at zero or be reloaded automatically from memory (in Linked List mode - i.e. Link Address valid). These bits are protected and can be written only if EN is 0." start="20" size="12" />
+    </Register>
+    <Register name="MDMA_C15SAR" description="MDMA channel x source address register" start="+0x418" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SAR" description="source adr base" start="0" size="32" />
+    </Register>
+    <Register name="MDMA_C15DAR" description="MDMA channel x destination address register" start="+0x41C" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DAR" description="Destination adr base" start="0" size="32" />
+    </Register>
+    <Register name="MDMA_C15BRUR" description="MDMA channel x Block Repeat address Update register" start="+0x420" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SUV" description="source adresse update value" start="0" size="16" />
+      <BitField name="DUV" description="destination address update" start="16" size="16" />
+    </Register>
+    <Register name="MDMA_C15LAR" description="MDMA channel x Link Address register" start="+0x424" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LAR" description="Link address register" start="0" size="32" />
+    </Register>
+    <Register name="MDMA_C15TBR" description="MDMA channel x Trigger and Bus selection Register" start="+0x428" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TSEL" description="Trigger selection" start="0" size="6" />
+      <BitField name="SBUS" description="Source BUS select This bit is protected and can be written only if EN is 0." start="16" size="1" />
+      <BitField name="DBUS" description="Destination BUS slect This bit is protected and can be written only if EN is 0." start="17" size="1" />
+    </Register>
+    <Register name="MDMA_C15MAR" description="MDMA channel x Mask address register" start="+0x430" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MAR" description="Mask address" start="0" size="32" />
+    </Register>
+    <Register name="MDMA_C15MDR" description="MDMA channel x Mask Data register" start="+0x434" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MDR" description="Mask data" start="0" size="32" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="MPU" description="Memory protection unit" start="0xE000ED90">
+    <Register name="MPU_TYPER" description="MPU type register" start="+0x0" size="4" access="ReadOnly" reset_value="0X00000800" reset_mask="0xFFFFFFFF">
+      <BitField name="SEPARATE" description="Separate flag" start="0" size="1" />
+      <BitField name="DREGION" description="Number of MPU data regions" start="8" size="8" />
+      <BitField name="IREGION" description="Number of MPU instruction regions" start="16" size="8" />
+    </Register>
+    <Register name="MPU_CTRL" description="MPU control register" start="+0x4" size="4" access="Read/Write" reset_value="0X00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ENABLE" description="Enables the MPU" start="0" size="1" />
+      <BitField name="HFNMIENA" description="Enables the operation of MPU during hard fault" start="1" size="1" />
+      <BitField name="PRIVDEFENA" description="Enable priviliged software access to default memory map" start="2" size="1" />
+    </Register>
+    <Register name="MPU_RNR" description="MPU region number register" start="+0x8" size="4" access="Read/Write" reset_value="0X00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="REGION" description="MPU region" start="0" size="8" />
+    </Register>
+    <Register name="MPU_RBAR" description="MPU region base address register" start="+0xC" size="4" access="Read/Write" reset_value="0X00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="REGION" description="MPU region field" start="0" size="4" />
+      <BitField name="VALID" description="MPU region number valid" start="4" size="1" />
+      <BitField name="ADDR" description="Region base address field" start="5" size="27" />
+    </Register>
+    <Register name="MPU_RASR" description="MPU region attribute and size register" start="+0x10" size="4" access="Read/Write" reset_value="0X00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ENABLE" description="Region enable bit." start="0" size="1" />
+      <BitField name="SIZE" description="Size of the MPU protection region" start="1" size="5" />
+      <BitField name="SRD" description="Subregion disable bits" start="8" size="8" />
+      <BitField name="B" description="memory attribute" start="16" size="1" />
+      <BitField name="C" description="memory attribute" start="17" size="1" />
+      <BitField name="S" description="Shareable memory attribute" start="18" size="1" />
+      <BitField name="TEX" description="memory attribute" start="19" size="3" />
+      <BitField name="AP" description="Access permission" start="24" size="3" />
+      <BitField name="XN" description="Instruction access disable bit" start="28" size="1" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="NVIC" description="Nested Vectored Interrupt Controller" start="0xE000E100">
+    <Register name="ISER0" description="Interrupt Set-Enable Register" start="+0x0" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SETENA" description="SETENA" start="0" size="32" />
+    </Register>
+    <Register name="ISER1" description="Interrupt Set-Enable Register" start="+0x4" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SETENA" description="SETENA" start="0" size="32" />
+    </Register>
+    <Register name="ISER2" description="Interrupt Set-Enable Register" start="+0x8" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SETENA" description="SETENA" start="0" size="32" />
+    </Register>
+    <Register name="ICER0" description="Interrupt Clear-Enable Register" start="+0x80" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CLRENA" description="CLRENA" start="0" size="32" />
+    </Register>
+    <Register name="ICER1" description="Interrupt Clear-Enable Register" start="+0x84" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CLRENA" description="CLRENA" start="0" size="32" />
+    </Register>
+    <Register name="ICER2" description="Interrupt Clear-Enable Register" start="+0x88" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CLRENA" description="CLRENA" start="0" size="32" />
+    </Register>
+    <Register name="ISPR0" description="Interrupt Set-Pending Register" start="+0x100" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SETPEND" description="SETPEND" start="0" size="32" />
+    </Register>
+    <Register name="ISPR1" description="Interrupt Set-Pending Register" start="+0x104" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SETPEND" description="SETPEND" start="0" size="32" />
+    </Register>
+    <Register name="ISPR2" description="Interrupt Set-Pending Register" start="+0x108" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SETPEND" description="SETPEND" start="0" size="32" />
+    </Register>
+    <Register name="ICPR0" description="Interrupt Clear-Pending Register" start="+0x180" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CLRPEND" description="CLRPEND" start="0" size="32" />
+    </Register>
+    <Register name="ICPR1" description="Interrupt Clear-Pending Register" start="+0x184" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CLRPEND" description="CLRPEND" start="0" size="32" />
+    </Register>
+    <Register name="ICPR2" description="Interrupt Clear-Pending Register" start="+0x188" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CLRPEND" description="CLRPEND" start="0" size="32" />
+    </Register>
+    <Register name="IABR0" description="Interrupt Active Bit Register" start="+0x200" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ACTIVE" description="ACTIVE" start="0" size="32" />
+    </Register>
+    <Register name="IABR1" description="Interrupt Active Bit Register" start="+0x204" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ACTIVE" description="ACTIVE" start="0" size="32" />
+    </Register>
+    <Register name="IABR2" description="Interrupt Active Bit Register" start="+0x208" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ACTIVE" description="ACTIVE" start="0" size="32" />
+    </Register>
+    <Register name="IPR0" description="Interrupt Priority Register" start="+0x300" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IPR_N0" description="IPR_N0" start="0" size="8" />
+      <BitField name="IPR_N1" description="IPR_N1" start="8" size="8" />
+      <BitField name="IPR_N2" description="IPR_N2" start="16" size="8" />
+      <BitField name="IPR_N3" description="IPR_N3" start="24" size="8" />
+    </Register>
+    <Register name="IPR1" description="Interrupt Priority Register" start="+0x304" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IPR_N0" description="IPR_N0" start="0" size="8" />
+      <BitField name="IPR_N1" description="IPR_N1" start="8" size="8" />
+      <BitField name="IPR_N2" description="IPR_N2" start="16" size="8" />
+      <BitField name="IPR_N3" description="IPR_N3" start="24" size="8" />
+    </Register>
+    <Register name="IPR2" description="Interrupt Priority Register" start="+0x308" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IPR_N0" description="IPR_N0" start="0" size="8" />
+      <BitField name="IPR_N1" description="IPR_N1" start="8" size="8" />
+      <BitField name="IPR_N2" description="IPR_N2" start="16" size="8" />
+      <BitField name="IPR_N3" description="IPR_N3" start="24" size="8" />
+    </Register>
+    <Register name="IPR3" description="Interrupt Priority Register" start="+0x30C" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IPR_N0" description="IPR_N0" start="0" size="8" />
+      <BitField name="IPR_N1" description="IPR_N1" start="8" size="8" />
+      <BitField name="IPR_N2" description="IPR_N2" start="16" size="8" />
+      <BitField name="IPR_N3" description="IPR_N3" start="24" size="8" />
+    </Register>
+    <Register name="IPR4" description="Interrupt Priority Register" start="+0x310" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IPR_N0" description="IPR_N0" start="0" size="8" />
+      <BitField name="IPR_N1" description="IPR_N1" start="8" size="8" />
+      <BitField name="IPR_N2" description="IPR_N2" start="16" size="8" />
+      <BitField name="IPR_N3" description="IPR_N3" start="24" size="8" />
+    </Register>
+    <Register name="IPR5" description="Interrupt Priority Register" start="+0x314" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IPR_N0" description="IPR_N0" start="0" size="8" />
+      <BitField name="IPR_N1" description="IPR_N1" start="8" size="8" />
+      <BitField name="IPR_N2" description="IPR_N2" start="16" size="8" />
+      <BitField name="IPR_N3" description="IPR_N3" start="24" size="8" />
+    </Register>
+    <Register name="IPR6" description="Interrupt Priority Register" start="+0x318" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IPR_N0" description="IPR_N0" start="0" size="8" />
+      <BitField name="IPR_N1" description="IPR_N1" start="8" size="8" />
+      <BitField name="IPR_N2" description="IPR_N2" start="16" size="8" />
+      <BitField name="IPR_N3" description="IPR_N3" start="24" size="8" />
+    </Register>
+    <Register name="IPR7" description="Interrupt Priority Register" start="+0x31C" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IPR_N0" description="IPR_N0" start="0" size="8" />
+      <BitField name="IPR_N1" description="IPR_N1" start="8" size="8" />
+      <BitField name="IPR_N2" description="IPR_N2" start="16" size="8" />
+      <BitField name="IPR_N3" description="IPR_N3" start="24" size="8" />
+    </Register>
+    <Register name="IPR8" description="Interrupt Priority Register" start="+0x320" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IPR_N0" description="IPR_N0" start="0" size="8" />
+      <BitField name="IPR_N1" description="IPR_N1" start="8" size="8" />
+      <BitField name="IPR_N2" description="IPR_N2" start="16" size="8" />
+      <BitField name="IPR_N3" description="IPR_N3" start="24" size="8" />
+    </Register>
+    <Register name="IPR9" description="Interrupt Priority Register" start="+0x324" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IPR_N0" description="IPR_N0" start="0" size="8" />
+      <BitField name="IPR_N1" description="IPR_N1" start="8" size="8" />
+      <BitField name="IPR_N2" description="IPR_N2" start="16" size="8" />
+      <BitField name="IPR_N3" description="IPR_N3" start="24" size="8" />
+    </Register>
+    <Register name="IPR10" description="Interrupt Priority Register" start="+0x328" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IPR_N0" description="IPR_N0" start="0" size="8" />
+      <BitField name="IPR_N1" description="IPR_N1" start="8" size="8" />
+      <BitField name="IPR_N2" description="IPR_N2" start="16" size="8" />
+      <BitField name="IPR_N3" description="IPR_N3" start="24" size="8" />
+    </Register>
+    <Register name="IPR11" description="Interrupt Priority Register" start="+0x32C" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IPR_N0" description="IPR_N0" start="0" size="8" />
+      <BitField name="IPR_N1" description="IPR_N1" start="8" size="8" />
+      <BitField name="IPR_N2" description="IPR_N2" start="16" size="8" />
+      <BitField name="IPR_N3" description="IPR_N3" start="24" size="8" />
+    </Register>
+    <Register name="IPR12" description="Interrupt Priority Register" start="+0x330" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IPR_N0" description="IPR_N0" start="0" size="8" />
+      <BitField name="IPR_N1" description="IPR_N1" start="8" size="8" />
+      <BitField name="IPR_N2" description="IPR_N2" start="16" size="8" />
+      <BitField name="IPR_N3" description="IPR_N3" start="24" size="8" />
+    </Register>
+    <Register name="IPR13" description="Interrupt Priority Register" start="+0x334" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IPR_N0" description="IPR_N0" start="0" size="8" />
+      <BitField name="IPR_N1" description="IPR_N1" start="8" size="8" />
+      <BitField name="IPR_N2" description="IPR_N2" start="16" size="8" />
+      <BitField name="IPR_N3" description="IPR_N3" start="24" size="8" />
+    </Register>
+    <Register name="IPR14" description="Interrupt Priority Register" start="+0x338" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IPR_N0" description="IPR_N0" start="0" size="8" />
+      <BitField name="IPR_N1" description="IPR_N1" start="8" size="8" />
+      <BitField name="IPR_N2" description="IPR_N2" start="16" size="8" />
+      <BitField name="IPR_N3" description="IPR_N3" start="24" size="8" />
+    </Register>
+    <Register name="IPR15" description="Interrupt Priority Register" start="+0x33C" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IPR_N0" description="IPR_N0" start="0" size="8" />
+      <BitField name="IPR_N1" description="IPR_N1" start="8" size="8" />
+      <BitField name="IPR_N2" description="IPR_N2" start="16" size="8" />
+      <BitField name="IPR_N3" description="IPR_N3" start="24" size="8" />
+    </Register>
+    <Register name="IPR16" description="Interrupt Priority Register" start="+0x340" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IPR_N0" description="IPR_N0" start="0" size="8" />
+      <BitField name="IPR_N1" description="IPR_N1" start="8" size="8" />
+      <BitField name="IPR_N2" description="IPR_N2" start="16" size="8" />
+      <BitField name="IPR_N3" description="IPR_N3" start="24" size="8" />
+    </Register>
+    <Register name="IPR17" description="Interrupt Priority Register" start="+0x344" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IPR_N0" description="IPR_N0" start="0" size="8" />
+      <BitField name="IPR_N1" description="IPR_N1" start="8" size="8" />
+      <BitField name="IPR_N2" description="IPR_N2" start="16" size="8" />
+      <BitField name="IPR_N3" description="IPR_N3" start="24" size="8" />
+    </Register>
+    <Register name="IPR18" description="Interrupt Priority Register" start="+0x348" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IPR_N0" description="IPR_N0" start="0" size="8" />
+      <BitField name="IPR_N1" description="IPR_N1" start="8" size="8" />
+      <BitField name="IPR_N2" description="IPR_N2" start="16" size="8" />
+      <BitField name="IPR_N3" description="IPR_N3" start="24" size="8" />
+    </Register>
+    <Register name="IPR19" description="Interrupt Priority Register" start="+0x34C" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IPR_N0" description="IPR_N0" start="0" size="8" />
+      <BitField name="IPR_N1" description="IPR_N1" start="8" size="8" />
+      <BitField name="IPR_N2" description="IPR_N2" start="16" size="8" />
+      <BitField name="IPR_N3" description="IPR_N3" start="24" size="8" />
+    </Register>
+    <Register name="IPR20" description="Interrupt Priority Register" start="+0x350" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IPR_N0" description="IPR_N0" start="0" size="8" />
+      <BitField name="IPR_N1" description="IPR_N1" start="8" size="8" />
+      <BitField name="IPR_N2" description="IPR_N2" start="16" size="8" />
+      <BitField name="IPR_N3" description="IPR_N3" start="24" size="8" />
+    </Register>
+    <Register name="IPR21" description="Interrupt Priority Register" start="+0x354" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IPR_N0" description="IPR_N0" start="0" size="8" />
+      <BitField name="IPR_N1" description="IPR_N1" start="8" size="8" />
+      <BitField name="IPR_N2" description="IPR_N2" start="16" size="8" />
+      <BitField name="IPR_N3" description="IPR_N3" start="24" size="8" />
+    </Register>
+    <Register name="IPR22" description="Interrupt Priority Register" start="+0x358" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IPR_N0" description="IPR_N0" start="0" size="8" />
+      <BitField name="IPR_N1" description="IPR_N1" start="8" size="8" />
+      <BitField name="IPR_N2" description="IPR_N2" start="16" size="8" />
+      <BitField name="IPR_N3" description="IPR_N3" start="24" size="8" />
+    </Register>
+    <Register name="IPR23" description="Interrupt Priority Register" start="+0x35C" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IPR_N0" description="IPR_N0" start="0" size="8" />
+      <BitField name="IPR_N1" description="IPR_N1" start="8" size="8" />
+      <BitField name="IPR_N2" description="IPR_N2" start="16" size="8" />
+      <BitField name="IPR_N3" description="IPR_N3" start="24" size="8" />
+    </Register>
+    <Register name="IPR24" description="Interrupt Priority Register" start="+0x360" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IPR_N0" description="IPR_N0" start="0" size="8" />
+      <BitField name="IPR_N1" description="IPR_N1" start="8" size="8" />
+      <BitField name="IPR_N2" description="IPR_N2" start="16" size="8" />
+      <BitField name="IPR_N3" description="IPR_N3" start="24" size="8" />
+    </Register>
+    <Register name="IPR25" description="Interrupt Priority Register" start="+0x364" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IPR_N0" description="IPR_N0" start="0" size="8" />
+      <BitField name="IPR_N1" description="IPR_N1" start="8" size="8" />
+      <BitField name="IPR_N2" description="IPR_N2" start="16" size="8" />
+      <BitField name="IPR_N3" description="IPR_N3" start="24" size="8" />
+    </Register>
+    <Register name="IPR26" description="Interrupt Priority Register" start="+0x368" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IPR_N0" description="IPR_N0" start="0" size="8" />
+      <BitField name="IPR_N1" description="IPR_N1" start="8" size="8" />
+      <BitField name="IPR_N2" description="IPR_N2" start="16" size="8" />
+      <BitField name="IPR_N3" description="IPR_N3" start="24" size="8" />
+    </Register>
+    <Register name="IPR27" description="Interrupt Priority Register" start="+0x36C" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IPR_N0" description="IPR_N0" start="0" size="8" />
+      <BitField name="IPR_N1" description="IPR_N1" start="8" size="8" />
+      <BitField name="IPR_N2" description="IPR_N2" start="16" size="8" />
+      <BitField name="IPR_N3" description="IPR_N3" start="24" size="8" />
+    </Register>
+    <Register name="IPR28" description="Interrupt Priority Register" start="+0x370" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IPR_N0" description="IPR_N0" start="0" size="8" />
+      <BitField name="IPR_N1" description="IPR_N1" start="8" size="8" />
+      <BitField name="IPR_N2" description="IPR_N2" start="16" size="8" />
+      <BitField name="IPR_N3" description="IPR_N3" start="24" size="8" />
+    </Register>
+    <Register name="IPR29" description="Interrupt Priority Register" start="+0x374" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IPR_N0" description="IPR_N0" start="0" size="8" />
+      <BitField name="IPR_N1" description="IPR_N1" start="8" size="8" />
+      <BitField name="IPR_N2" description="IPR_N2" start="16" size="8" />
+      <BitField name="IPR_N3" description="IPR_N3" start="24" size="8" />
+    </Register>
+    <Register name="IPR30" description="Interrupt Priority Register" start="+0x378" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IPR_N0" description="IPR_N0" start="0" size="8" />
+      <BitField name="IPR_N1" description="IPR_N1" start="8" size="8" />
+      <BitField name="IPR_N2" description="IPR_N2" start="16" size="8" />
+      <BitField name="IPR_N3" description="IPR_N3" start="24" size="8" />
+    </Register>
+    <Register name="IPR31" description="Interrupt Priority Register" start="+0x37C" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IPR_N0" description="IPR_N0" start="0" size="8" />
+      <BitField name="IPR_N1" description="IPR_N1" start="8" size="8" />
+      <BitField name="IPR_N2" description="IPR_N2" start="16" size="8" />
+      <BitField name="IPR_N3" description="IPR_N3" start="24" size="8" />
+    </Register>
+    <Register name="IPR32" description="Interrupt Priority Register" start="+0x380" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IPR_N0" description="IPR_N0" start="0" size="8" />
+      <BitField name="IPR_N1" description="IPR_N1" start="8" size="8" />
+      <BitField name="IPR_N2" description="IPR_N2" start="16" size="8" />
+      <BitField name="IPR_N3" description="IPR_N3" start="24" size="8" />
+    </Register>
+    <Register name="IPR33" description="Interrupt Priority Register" start="+0x384" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IPR_N0" description="IPR_N0" start="0" size="8" />
+      <BitField name="IPR_N1" description="IPR_N1" start="8" size="8" />
+      <BitField name="IPR_N2" description="IPR_N2" start="16" size="8" />
+      <BitField name="IPR_N3" description="IPR_N3" start="24" size="8" />
+    </Register>
+    <Register name="IPR34" description="Interrupt Priority Register" start="+0x388" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IPR_N0" description="IPR_N0" start="0" size="8" />
+      <BitField name="IPR_N1" description="IPR_N1" start="8" size="8" />
+      <BitField name="IPR_N2" description="IPR_N2" start="16" size="8" />
+      <BitField name="IPR_N3" description="IPR_N3" start="24" size="8" />
+    </Register>
+    <Register name="IPR35" description="Interrupt Priority Register" start="+0x38C" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IPR_N0" description="IPR_N0" start="0" size="8" />
+      <BitField name="IPR_N1" description="IPR_N1" start="8" size="8" />
+      <BitField name="IPR_N2" description="IPR_N2" start="16" size="8" />
+      <BitField name="IPR_N3" description="IPR_N3" start="24" size="8" />
+    </Register>
+    <Register name="IPR36" description="Interrupt Priority Register" start="+0x390" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IPR_N0" description="IPR_N0" start="0" size="8" />
+      <BitField name="IPR_N1" description="IPR_N1" start="8" size="8" />
+      <BitField name="IPR_N2" description="IPR_N2" start="16" size="8" />
+      <BitField name="IPR_N3" description="IPR_N3" start="24" size="8" />
+    </Register>
+    <Register name="IPR37" description="Interrupt Priority Register" start="+0x394" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IPR_N0" description="IPR_N0" start="0" size="8" />
+      <BitField name="IPR_N1" description="IPR_N1" start="8" size="8" />
+      <BitField name="IPR_N2" description="IPR_N2" start="16" size="8" />
+      <BitField name="IPR_N3" description="IPR_N3" start="24" size="8" />
+    </Register>
+    <Register name="IPR38" description="Interrupt Priority Register" start="+0x398" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IPR_N0" description="IPR_N0" start="0" size="8" />
+      <BitField name="IPR_N1" description="IPR_N1" start="8" size="8" />
+      <BitField name="IPR_N2" description="IPR_N2" start="16" size="8" />
+      <BitField name="IPR_N3" description="IPR_N3" start="24" size="8" />
+    </Register>
+    <Register name="ISER3" description="Interrupt Set-Enable Register" start="+0xC" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
+    <Register name="ICER3" description="Interrupt Clear-Enable Register" start="+0x8C" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
+    <Register name="ISPR3" description="Interrupt Set-Pending Register" start="+0x10C" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
+    <Register name="ICPR3" description="Interrupt Clear-Pending Register" start="+0x1C0" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
+    <Register name="IABR3" description="Interrupt Active Bit Register" start="+0x20C" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF" />
+  </RegisterGroup>
+  <RegisterGroup name="NVIC_STIR" description="Nested vectored interrupt controller" start="0xE000EF00">
+    <Register name="STIR" description="Software trigger interrupt register" start="+0x0" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="INTID" description="Software generated interrupt ID" start="0" size="9" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="OCTOSPI1" description="OctoSPI" start="0x52005000">
+    <Register name="CR" description="control register" start="+0x0" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FMODE" description="Functional mode" start="28" size="2" />
+      <BitField name="PMM" description="Polling match mode" start="23" size="1" />
+      <BitField name="APMS" description="Automatic poll mode stop" start="22" size="1" />
+      <BitField name="TOIE" description="TimeOut interrupt enable" start="20" size="1" />
+      <BitField name="SMIE" description="Status match interrupt enable" start="19" size="1" />
+      <BitField name="FTIE" description="FIFO threshold interrupt enable" start="18" size="1" />
+      <BitField name="TCIE" description="Transfer complete interrupt enable" start="17" size="1" />
+      <BitField name="TEIE" description="Transfer error interrupt enable" start="16" size="1" />
+      <BitField name="FTHRES" description="IFO threshold level" start="8" size="5" />
+      <BitField name="FSEL" description="FLASH memory selection" start="7" size="1" />
+      <BitField name="DQM" description="Dual-quad mode" start="6" size="1" />
+      <BitField name="TCEN" description="Timeout counter enable" start="3" size="1" />
+      <BitField name="DMAEN" description="DMA enable" start="2" size="1" />
+      <BitField name="ABORT" description="Abort request" start="1" size="1" />
+      <BitField name="EN" description="Enable" start="0" size="1" />
+    </Register>
+    <Register name="DCR1" description="device configuration register" start="+0x8" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CKMODE" description="Mode 0 / mode 3" start="0" size="1" />
+      <BitField name="FRCK" description="Free running clock" start="1" size="1" />
+      <BitField name="CSHT" description="Chip-select high time" start="8" size="3" />
+      <BitField name="DEVSIZE" description="Device size" start="16" size="5" />
+      <BitField name="MTYP" description="Memory type" start="24" size="2" />
+    </Register>
+    <Register name="DCR2" description="device configuration register 2" start="+0xC" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PRESCALER" description="Clock prescaler" start="0" size="8" />
+      <BitField name="WRAPSIZE" description="Wrap size" start="16" size="3" />
+    </Register>
+    <Register name="DCR3" description="device configuration register 3" start="+0x10" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MAXTRAN" description="Maximum transfer" start="0" size="8" />
+      <BitField name="CSBOUND" description="CS boundary" start="16" size="5" />
+    </Register>
+    <Register name="DCR4" description="DCR4" start="+0x14" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="REFRESH" description="Refresh rate" start="0" size="16" />
+    </Register>
+    <Register name="SR" description="status register" start="+0x20" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CTEF" description="Clear transfer error flag" start="0" size="1" />
+      <BitField name="CTCF" description="Clear transfer complete flag" start="1" size="1" />
+      <BitField name="CSMF" description="Clear status match flag" start="3" size="1" />
+      <BitField name="CTOF" description="Clear timeout flag" start="4" size="1" />
+      <BitField name="FTF" description="FIFO threshold flag" start="2" size="1" />
+      <BitField name="BUSY" description="Busy" start="5" size="1" />
+      <BitField name="FLEVEL" description="FIFO level" start="8" size="6" />
+    </Register>
+    <Register name="FCR" description="flag clear register" start="+0x24" size="4" access="WriteOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CTEF" description="Clear transfer error flag" start="0" size="1" />
+      <BitField name="CTCF" description="Clear transfer complete flag" start="1" size="1" />
+      <BitField name="CSMF" description="Clear status match flag" start="3" size="1" />
+      <BitField name="CTOF" description="Clear timeout flag" start="4" size="1" />
+    </Register>
+    <Register name="DLR" description="data length register" start="+0x40" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DL" description="Data length" start="0" size="32" />
+    </Register>
+    <Register name="AR" description="address register" start="+0x48" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ADRESS" description="Adress" start="0" size="32" />
+    </Register>
+    <Register name="DR" description="data register" start="+0x50" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DATA" description="Data" start="0" size="32" />
+    </Register>
+    <Register name="PSMKR" description="polling status mask register" start="+0x80" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MASK" description="Status mask" start="0" size="32" />
+    </Register>
+    <Register name="PSMAR" description="polling status match register" start="+0x88" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MATCH" description="Match" start="0" size="32" />
+    </Register>
+    <Register name="CCR" description="polling interval register" start="+0x100" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IMODE" description="Instruction mode" start="0" size="3" />
+      <BitField name="IDTR" description="Instruction double transfer rate" start="3" size="1" />
+      <BitField name="ISIZE" description="Instruction size" start="4" size="2" />
+      <BitField name="ADMODE" description="Address mode" start="8" size="3" />
+      <BitField name="ADDTR" description="Address double transfer rate" start="11" size="1" />
+      <BitField name="ADSIZE" description="Address size" start="12" size="2" />
+      <BitField name="ABMODE" description="Alternate byte mode" start="16" size="3" />
+      <BitField name="ABDTR" description="Alternate bytes double transfer rate" start="19" size="1" />
+      <BitField name="ABSIZE" description="Alternate bytes size" start="20" size="2" />
+      <BitField name="DMODE" description="Data mode" start="24" size="3" />
+      <BitField name="DDTR" description="Alternate bytes double transfer rate" start="27" size="1" />
+      <BitField name="DQSE" description="DQS enable" start="29" size="1" />
+      <BitField name="SIOO" description="Send instruction only once mode" start="31" size="1" />
+    </Register>
+    <Register name="TCR" description="communication configuration register" start="+0x108" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DCYC" description="Number of dummy cycles" start="0" size="5" />
+      <BitField name="DHQC" description="Delay hold quarter cycle" start="28" size="1" />
+      <BitField name="SSHIFT" description="Sample shift" start="30" size="1" />
+    </Register>
+    <Register name="IR" description="timing configuration register" start="+0x110" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="INSTRUCTION" description="INSTRUCTION" start="0" size="32" />
+    </Register>
+    <Register name="ABR" description="instruction register" start="+0x120" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ALTERNATE" description="Alternate bytes" start="0" size="32" />
+    </Register>
+    <Register name="LPTR" description="alternate bytes register" start="+0x130" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TIMEOUT" description="Timeout period" start="0" size="16" />
+    </Register>
+    <Register name="WPCCR" description="low-power timeout register" start="+0x140" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IMODE" description="Instruction mode" start="0" size="3" />
+      <BitField name="IDTR" description="Instruction double transfer rate" start="3" size="1" />
+      <BitField name="ISIZE" description="Instruction size" start="4" size="2" />
+      <BitField name="ADMODE" description="Address mode" start="8" size="3" />
+      <BitField name="ADDTR" description="Address double transfer rate" start="11" size="1" />
+      <BitField name="ADSIZE" description="Address size" start="12" size="2" />
+      <BitField name="ABMODE" description="Alternate byte mode" start="16" size="3" />
+      <BitField name="ABDTR" description="Alternate bytes double transfer rate" start="19" size="1" />
+      <BitField name="ABSIZE" description="Alternate bytes size" start="20" size="2" />
+      <BitField name="DMODE" description="Data mode" start="24" size="3" />
+      <BitField name="DDTR" description="alternate bytes double transfer rate" start="27" size="1" />
+      <BitField name="DQSE" description="DQS enable" start="29" size="1" />
+    </Register>
+    <Register name="WPTCR" description="wrap timing configuration register" start="+0x148" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DCYC" description="Number of dummy cycles" start="0" size="5" />
+      <BitField name="DHQC" description="Delay hold quarter cycle" start="28" size="1" />
+      <BitField name="SSHIFT" description="Sample shift" start="30" size="1" />
+    </Register>
+    <Register name="WPIR" description="wrap instruction register" start="+0x150" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="INSTRUCTION" description="INSTRUCTION" start="0" size="32" />
+    </Register>
+    <Register name="WPABR" description="wrap alternate bytes register" start="+0x160" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ALTERNATE" description="Alternate bytes" start="0" size="32" />
+    </Register>
+    <Register name="WCCR" description="write communication configuration register" start="+0x180" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IMODE" description="Instruction mode" start="0" size="2" />
+      <BitField name="IDTR" description="Instruction double transfer rate" start="2" size="1" />
+      <BitField name="ISIZE" description="Instruction size" start="3" size="1" />
+      <BitField name="ADMODE" description="Address mode" start="8" size="3" />
+      <BitField name="ADDTR" description="Address double transfer rate" start="11" size="1" />
+      <BitField name="ADSIZE" description="Address size" start="12" size="2" />
+      <BitField name="ABMODE" description="Alternate-byte mode" start="16" size="3" />
+      <BitField name="ABDTR" description="Alternate bytes double transfer rate" start="19" size="1" />
+      <BitField name="ABSIZE" description="Alternate bytes size" start="20" size="2" />
+      <BitField name="DMODE" description="Data mode" start="24" size="3" />
+      <BitField name="DDTR" description="DDTR" start="27" size="1" />
+      <BitField name="DQSE" description="DQSE" start="29" size="1" />
+    </Register>
+    <Register name="WTCR" description="write timing configuration register" start="+0x188" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DCYC" description="DCYC" start="0" size="5" />
+    </Register>
+    <Register name="WABR" description="write alternate bytes register" start="+0x1A0" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ALTERNATE" description="Alternate bytes" start="0" size="32" />
+    </Register>
+    <Register name="HLCR" description="HyperBusTM latency configuration register" start="+0x200" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LM" description="Latency mode" start="0" size="1" />
+      <BitField name="WZL" description="Write zero latency" start="1" size="1" />
+      <BitField name="TACC" description="Access time" start="8" size="8" />
+      <BitField name="TRWR" description="Read write recovery time" start="16" size="8" />
+    </Register>
+    <Register name="PIR" description="OCTOSPI polling interval register" start="+0x90" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="INTERVAL" description="Polling interval" start="0" size="16" />
+    </Register>
+    <Register name="WIR" description="instruction register" start="+0x190" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="INSTRUCTION" description="INSTRUCTION" start="0" size="32" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="OCTOSPI2" description="OctoSPI" start="0x5200A000">
+    <Register name="CR" description="control register" start="+0x0" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FMODE" description="Functional mode" start="28" size="2" />
+      <BitField name="PMM" description="Polling match mode" start="23" size="1" />
+      <BitField name="APMS" description="Automatic poll mode stop" start="22" size="1" />
+      <BitField name="TOIE" description="TimeOut interrupt enable" start="20" size="1" />
+      <BitField name="SMIE" description="Status match interrupt enable" start="19" size="1" />
+      <BitField name="FTIE" description="FIFO threshold interrupt enable" start="18" size="1" />
+      <BitField name="TCIE" description="Transfer complete interrupt enable" start="17" size="1" />
+      <BitField name="TEIE" description="Transfer error interrupt enable" start="16" size="1" />
+      <BitField name="FTHRES" description="IFO threshold level" start="8" size="5" />
+      <BitField name="FSEL" description="FLASH memory selection" start="7" size="1" />
+      <BitField name="DQM" description="Dual-quad mode" start="6" size="1" />
+      <BitField name="TCEN" description="Timeout counter enable" start="3" size="1" />
+      <BitField name="DMAEN" description="DMA enable" start="2" size="1" />
+      <BitField name="ABORT" description="Abort request" start="1" size="1" />
+      <BitField name="EN" description="Enable" start="0" size="1" />
+    </Register>
+    <Register name="DCR1" description="device configuration register" start="+0x8" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CKMODE" description="Mode 0 / mode 3" start="0" size="1" />
+      <BitField name="FRCK" description="Free running clock" start="1" size="1" />
+      <BitField name="CSHT" description="Chip-select high time" start="8" size="3" />
+      <BitField name="DEVSIZE" description="Device size" start="16" size="5" />
+      <BitField name="MTYP" description="Memory type" start="24" size="2" />
+    </Register>
+    <Register name="DCR2" description="device configuration register 2" start="+0xC" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PRESCALER" description="Clock prescaler" start="0" size="8" />
+      <BitField name="WRAPSIZE" description="Wrap size" start="16" size="3" />
+    </Register>
+    <Register name="DCR3" description="device configuration register 3" start="+0x10" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MAXTRAN" description="Maximum transfer" start="0" size="8" />
+      <BitField name="CSBOUND" description="CS boundary" start="16" size="5" />
+    </Register>
+    <Register name="DCR4" description="DCR4" start="+0x14" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="REFRESH" description="Refresh rate" start="0" size="16" />
+    </Register>
+    <Register name="SR" description="status register" start="+0x20" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CTEF" description="Clear transfer error flag" start="0" size="1" />
+      <BitField name="CTCF" description="Clear transfer complete flag" start="1" size="1" />
+      <BitField name="CSMF" description="Clear status match flag" start="3" size="1" />
+      <BitField name="CTOF" description="Clear timeout flag" start="4" size="1" />
+      <BitField name="FTF" description="FIFO threshold flag" start="2" size="1" />
+      <BitField name="BUSY" description="Busy" start="5" size="1" />
+      <BitField name="FLEVEL" description="FIFO level" start="8" size="6" />
+    </Register>
+    <Register name="FCR" description="flag clear register" start="+0x24" size="4" access="WriteOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CTEF" description="Clear transfer error flag" start="0" size="1" />
+      <BitField name="CTCF" description="Clear transfer complete flag" start="1" size="1" />
+      <BitField name="CSMF" description="Clear status match flag" start="3" size="1" />
+      <BitField name="CTOF" description="Clear timeout flag" start="4" size="1" />
+    </Register>
+    <Register name="DLR" description="data length register" start="+0x40" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DL" description="Data length" start="0" size="32" />
+    </Register>
+    <Register name="AR" description="address register" start="+0x48" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ADRESS" description="Adress" start="0" size="32" />
+    </Register>
+    <Register name="DR" description="data register" start="+0x50" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DATA" description="Data" start="0" size="32" />
+    </Register>
+    <Register name="PSMKR" description="polling status mask register" start="+0x80" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MASK" description="Status mask" start="0" size="32" />
+    </Register>
+    <Register name="PSMAR" description="polling status match register" start="+0x88" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MATCH" description="Match" start="0" size="32" />
+    </Register>
+    <Register name="CCR" description="polling interval register" start="+0x100" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IMODE" description="Instruction mode" start="0" size="3" />
+      <BitField name="IDTR" description="Instruction double transfer rate" start="3" size="1" />
+      <BitField name="ISIZE" description="Instruction size" start="4" size="2" />
+      <BitField name="ADMODE" description="Address mode" start="8" size="3" />
+      <BitField name="ADDTR" description="Address double transfer rate" start="11" size="1" />
+      <BitField name="ADSIZE" description="Address size" start="12" size="2" />
+      <BitField name="ABMODE" description="Alternate byte mode" start="16" size="3" />
+      <BitField name="ABDTR" description="Alternate bytes double transfer rate" start="19" size="1" />
+      <BitField name="ABSIZE" description="Alternate bytes size" start="20" size="2" />
+      <BitField name="DMODE" description="Data mode" start="24" size="3" />
+      <BitField name="DDTR" description="Alternate bytes double transfer rate" start="27" size="1" />
+      <BitField name="DQSE" description="DQS enable" start="29" size="1" />
+      <BitField name="SIOO" description="Send instruction only once mode" start="31" size="1" />
+    </Register>
+    <Register name="TCR" description="communication configuration register" start="+0x108" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DCYC" description="Number of dummy cycles" start="0" size="5" />
+      <BitField name="DHQC" description="Delay hold quarter cycle" start="28" size="1" />
+      <BitField name="SSHIFT" description="Sample shift" start="30" size="1" />
+    </Register>
+    <Register name="IR" description="timing configuration register" start="+0x110" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="INSTRUCTION" description="INSTRUCTION" start="0" size="32" />
+    </Register>
+    <Register name="ABR" description="instruction register" start="+0x120" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ALTERNATE" description="Alternate bytes" start="0" size="32" />
+    </Register>
+    <Register name="LPTR" description="alternate bytes register" start="+0x130" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TIMEOUT" description="Timeout period" start="0" size="16" />
+    </Register>
+    <Register name="WPCCR" description="low-power timeout register" start="+0x140" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IMODE" description="Instruction mode" start="0" size="3" />
+      <BitField name="IDTR" description="Instruction double transfer rate" start="3" size="1" />
+      <BitField name="ISIZE" description="Instruction size" start="4" size="2" />
+      <BitField name="ADMODE" description="Address mode" start="8" size="3" />
+      <BitField name="ADDTR" description="Address double transfer rate" start="11" size="1" />
+      <BitField name="ADSIZE" description="Address size" start="12" size="2" />
+      <BitField name="ABMODE" description="Alternate byte mode" start="16" size="3" />
+      <BitField name="ABDTR" description="Alternate bytes double transfer rate" start="19" size="1" />
+      <BitField name="ABSIZE" description="Alternate bytes size" start="20" size="2" />
+      <BitField name="DMODE" description="Data mode" start="24" size="3" />
+      <BitField name="DDTR" description="alternate bytes double transfer rate" start="27" size="1" />
+      <BitField name="DQSE" description="DQS enable" start="29" size="1" />
+    </Register>
+    <Register name="WPTCR" description="wrap timing configuration register" start="+0x148" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DCYC" description="Number of dummy cycles" start="0" size="5" />
+      <BitField name="DHQC" description="Delay hold quarter cycle" start="28" size="1" />
+      <BitField name="SSHIFT" description="Sample shift" start="30" size="1" />
+    </Register>
+    <Register name="WPIR" description="wrap instruction register" start="+0x150" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="INSTRUCTION" description="INSTRUCTION" start="0" size="32" />
+    </Register>
+    <Register name="WPABR" description="wrap alternate bytes register" start="+0x160" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ALTERNATE" description="Alternate bytes" start="0" size="32" />
+    </Register>
+    <Register name="WCCR" description="write communication configuration register" start="+0x180" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IMODE" description="Instruction mode" start="0" size="2" />
+      <BitField name="IDTR" description="Instruction double transfer rate" start="2" size="1" />
+      <BitField name="ISIZE" description="Instruction size" start="3" size="1" />
+      <BitField name="ADMODE" description="Address mode" start="8" size="3" />
+      <BitField name="ADDTR" description="Address double transfer rate" start="11" size="1" />
+      <BitField name="ADSIZE" description="Address size" start="12" size="2" />
+      <BitField name="ABMODE" description="Alternate-byte mode" start="16" size="3" />
+      <BitField name="ABDTR" description="Alternate bytes double transfer rate" start="19" size="1" />
+      <BitField name="ABSIZE" description="Alternate bytes size" start="20" size="2" />
+      <BitField name="DMODE" description="Data mode" start="24" size="3" />
+      <BitField name="DDTR" description="DDTR" start="27" size="1" />
+      <BitField name="DQSE" description="DQSE" start="29" size="1" />
+    </Register>
+    <Register name="WTCR" description="write timing configuration register" start="+0x188" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DCYC" description="DCYC" start="0" size="5" />
+    </Register>
+    <Register name="WABR" description="write alternate bytes register" start="+0x1A0" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ALTERNATE" description="Alternate bytes" start="0" size="32" />
+    </Register>
+    <Register name="HLCR" description="HyperBusTM latency configuration register" start="+0x200" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LM" description="Latency mode" start="0" size="1" />
+      <BitField name="WZL" description="Write zero latency" start="1" size="1" />
+      <BitField name="TACC" description="Access time" start="8" size="8" />
+      <BitField name="TRWR" description="Read write recovery time" start="16" size="8" />
+    </Register>
+    <Register name="PIR" description="OCTOSPI polling interval register" start="+0x90" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="INTERVAL" description="Polling interval" start="0" size="16" />
+    </Register>
+    <Register name="WIR" description="instruction register" start="+0x190" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="INSTRUCTION" description="INSTRUCTION" start="0" size="32" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="OPAMP" description="Operational amplifiers" start="0x40009000">
+    <Register name="OPAMP1_CSR" description="OPAMP1 control/status register" start="+0x0" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OPAEN" description="Operational amplifier Enable" start="0" size="1" />
+      <BitField name="FORCE_VP" description="Force internal reference on VP (reserved for test" start="1" size="1" />
+      <BitField name="VP_SEL" description="Operational amplifier PGA mode" start="2" size="2" />
+      <BitField name="VM_SEL" description="Inverting input selection" start="5" size="2" />
+      <BitField name="OPAHSM" description="Operational amplifier high-speed mode" start="8" size="1" />
+      <BitField name="CALON" description="Calibration mode enabled" start="11" size="1" />
+      <BitField name="CALSEL" description="Calibration selection" start="12" size="2" />
+      <BitField name="PGA_GAIN" description="allows to switch from AOP offset trimmed values to AOP offset" start="14" size="4" />
+      <BitField name="USERTRIM" description="User trimming enable" start="18" size="1" />
+      <BitField name="TSTREF" description="OPAMP calibration reference voltage output control (reserved for test)" start="29" size="1" />
+      <BitField name="CALOUT" description="Operational amplifier calibration output" start="30" size="1" />
+    </Register>
+    <Register name="OPAMP1_OTR" description="OPAMP1 offset trimming register in normal mode" start="+0x4" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TRIMOFFSETN" description="Trim for NMOS differential pairs" start="0" size="5" />
+      <BitField name="TRIMOFFSETP" description="Trim for PMOS differential pairs" start="8" size="5" />
+    </Register>
+    <Register name="OPAMP1_HSOTR" description="OPAMP1 offset trimming register in low-power mode" start="+0x8" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TRIMLPOFFSETN" description="Trim for NMOS differential pairs" start="0" size="5" />
+      <BitField name="TRIMLPOFFSETP" description="Trim for PMOS differential pairs" start="8" size="5" />
+    </Register>
+    <Register name="OPAMP2_CSR" description="OPAMP2 control/status register" start="+0x10" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OPAEN" description="Operational amplifier Enable" start="0" size="1" />
+      <BitField name="FORCE_VP" description="Force internal reference on VP (reserved for test)" start="1" size="1" />
+      <BitField name="VM_SEL" description="Inverting input selection" start="5" size="2" />
+      <BitField name="OPAHSM" description="Operational amplifier high-speed mode" start="8" size="1" />
+      <BitField name="CALON" description="Calibration mode enabled" start="11" size="1" />
+      <BitField name="CALSEL" description="Calibration selection" start="12" size="2" />
+      <BitField name="PGA_GAIN" description="Operational amplifier Programmable amplifier gain value" start="14" size="4" />
+      <BitField name="USERTRIM" description="User trimming enable" start="18" size="1" />
+      <BitField name="TSTREF" description="OPAMP calibration reference voltage output control (reserved for test)" start="29" size="1" />
+      <BitField name="CALOUT" description="Operational amplifier calibration output" start="30" size="1" />
+    </Register>
+    <Register name="OPAMP2_OTR" description="OPAMP2 offset trimming register in normal mode" start="+0x14" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TRIMOFFSETN" description="Trim for NMOS differential pairs" start="0" size="5" />
+      <BitField name="TRIMOFFSETP" description="Trim for PMOS differential pairs" start="8" size="5" />
+    </Register>
+    <Register name="OPAMP2_HSOTR" description="OPAMP2 offset trimming register in low-power mode" start="+0x18" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TRIMLPOFFSETN" description="Trim for NMOS differential pairs" start="0" size="5" />
+      <BitField name="TRIMLPOFFSETP" description="Trim for PMOS differential pairs" start="8" size="5" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="OTG1_HS_DEVICE" description="USB 1 on the go high speed" start="0x40040800">
+    <Register name="OTG_HS_DCFG" description="OTG_HS device configuration register" start="+0x0" size="4" access="Read/Write" reset_value="0x02200000" reset_mask="0xFFFFFFFF">
+      <BitField name="DSPD" description="Device speed" start="0" size="2" />
+      <BitField name="NZLSOHSK" description="Nonzero-length status OUT handshake" start="2" size="1" />
+      <BitField name="DAD" description="Device address" start="4" size="7" />
+      <BitField name="PFIVL" description="Periodic (micro)frame interval" start="11" size="2" />
+      <BitField name="PERSCHIVL" description="Periodic scheduling interval" start="24" size="2" />
+    </Register>
+    <Register name="OTG_HS_DCTL" description="OTG_HS device control register" start="+0x4" size="4" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="RWUSIG" description="Remote wakeup signaling" start="0" size="1" access="Read/Write" />
+      <BitField name="SDIS" description="Soft disconnect" start="1" size="1" access="Read/Write" />
+      <BitField name="GINSTS" description="Global IN NAK status" start="2" size="1" access="ReadOnly" />
+      <BitField name="GONSTS" description="Global OUT NAK status" start="3" size="1" access="ReadOnly" />
+      <BitField name="TCTL" description="Test control" start="4" size="3" access="Read/Write" />
+      <BitField name="SGINAK" description="Set global IN NAK" start="7" size="1" access="WriteOnly" />
+      <BitField name="CGINAK" description="Clear global IN NAK" start="8" size="1" access="WriteOnly" />
+      <BitField name="SGONAK" description="Set global OUT NAK" start="9" size="1" access="WriteOnly" />
+      <BitField name="CGONAK" description="Clear global OUT NAK" start="10" size="1" access="WriteOnly" />
+      <BitField name="POPRGDNE" description="Power-on programming done" start="11" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HS_DSTS" description="OTG_HS device status register" start="+0x8" size="4" access="ReadOnly" reset_value="0x00000010" reset_mask="0xFFFFFFFF">
+      <BitField name="SUSPSTS" description="Suspend status" start="0" size="1" />
+      <BitField name="ENUMSPD" description="Enumerated speed" start="1" size="2" />
+      <BitField name="EERR" description="Erratic error" start="3" size="1" />
+      <BitField name="FNSOF" description="Frame number of the received SOF" start="8" size="14" />
+    </Register>
+    <Register name="OTG_HS_DIEPMSK" description="OTG_HS device IN endpoint common interrupt mask register" start="+0x10" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRCM" description="Transfer completed interrupt mask" start="0" size="1" />
+      <BitField name="EPDM" description="Endpoint disabled interrupt mask" start="1" size="1" />
+      <BitField name="TOM" description="Timeout condition mask (nonisochronous endpoints)" start="3" size="1" />
+      <BitField name="ITTXFEMSK" description="IN token received when TxFIFO empty mask" start="4" size="1" />
+      <BitField name="INEPNMM" description="IN token received with EP mismatch mask" start="5" size="1" />
+      <BitField name="INEPNEM" description="IN endpoint NAK effective mask" start="6" size="1" />
+      <BitField name="TXFURM" description="FIFO underrun mask" start="8" size="1" />
+      <BitField name="BIM" description="BNA interrupt mask" start="9" size="1" />
+    </Register>
+    <Register name="OTG_HS_DOEPMSK" description="OTG_HS device OUT endpoint common interrupt mask register" start="+0x14" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRCM" description="Transfer completed interrupt mask" start="0" size="1" />
+      <BitField name="EPDM" description="Endpoint disabled interrupt mask" start="1" size="1" />
+      <BitField name="STUPM" description="SETUP phase done mask" start="3" size="1" />
+      <BitField name="OTEPDM" description="OUT token received when endpoint disabled mask" start="4" size="1" />
+      <BitField name="B2BSTUP" description="Back-to-back SETUP packets received mask" start="6" size="1" />
+      <BitField name="OPEM" description="OUT packet error mask" start="8" size="1" />
+      <BitField name="BOIM" description="BNA interrupt mask" start="9" size="1" />
+    </Register>
+    <Register name="OTG_HS_DAINT" description="OTG_HS device all endpoints interrupt register" start="+0x18" size="4" access="ReadOnly" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="IEPINT" description="IN endpoint interrupt bits" start="0" size="16" />
+      <BitField name="OEPINT" description="OUT endpoint interrupt bits" start="16" size="16" />
+    </Register>
+    <Register name="OTG_HS_DAINTMSK" description="OTG_HS all endpoints interrupt mask register" start="+0x1C" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="IEPM" description="IN EP interrupt mask bits" start="0" size="16" />
+      <BitField name="OEPM" description="OUT EP interrupt mask bits" start="16" size="16" />
+    </Register>
+    <Register name="OTG_HS_DVBUSDIS" description="OTG_HS device VBUS discharge time register" start="+0x28" size="4" access="Read/Write" reset_value="0x000017D7" reset_mask="0xFFFFFFFF">
+      <BitField name="VBUSDT" description="Device VBUS discharge time" start="0" size="16" />
+    </Register>
+    <Register name="OTG_HS_DVBUSPULSE" description="OTG_HS device VBUS pulsing time register" start="+0x2C" size="4" access="Read/Write" reset_value="0x000005B8" reset_mask="0xFFFFFFFF">
+      <BitField name="DVBUSP" description="Device VBUS pulsing time" start="0" size="12" />
+    </Register>
+    <Register name="OTG_HS_DTHRCTL" description="OTG_HS Device threshold control register" start="+0x30" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="NONISOTHREN" description="Nonisochronous IN endpoints threshold enable" start="0" size="1" />
+      <BitField name="ISOTHREN" description="ISO IN endpoint threshold enable" start="1" size="1" />
+      <BitField name="TXTHRLEN" description="Transmit threshold length" start="2" size="9" />
+      <BitField name="RXTHREN" description="Receive threshold enable" start="16" size="1" />
+      <BitField name="RXTHRLEN" description="Receive threshold length" start="17" size="9" />
+      <BitField name="ARPEN" description="Arbiter parking enable" start="27" size="1" />
+    </Register>
+    <Register name="OTG_HS_DIEPEMPMSK" description="OTG_HS device IN endpoint FIFO empty interrupt mask register" start="+0x34" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="INEPTXFEM" description="IN EP Tx FIFO empty interrupt mask bits" start="0" size="16" />
+    </Register>
+    <Register name="OTG_HS_DEACHINT" description="OTG_HS device each endpoint interrupt register" start="+0x38" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="IEP1INT" description="IN endpoint 1interrupt bit" start="1" size="1" />
+      <BitField name="OEP1INT" description="OUT endpoint 1 interrupt bit" start="17" size="1" />
+    </Register>
+    <Register name="OTG_HS_DEACHINTMSK" description="OTG_HS device each endpoint interrupt register mask" start="+0x3C" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="IEP1INTM" description="IN Endpoint 1 interrupt mask bit" start="1" size="1" />
+      <BitField name="OEP1INTM" description="OUT Endpoint 1 interrupt mask bit" start="17" size="1" />
+    </Register>
+    <Register name="OTG_HS_DIEPCTL0" description="OTG device endpoint-0 control register" start="+0x100" size="4" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="USBAEP" description="USB active endpoint" start="15" size="1" access="Read/Write" />
+      <BitField name="EONUM_DPID" description="Even/odd frame" start="16" size="1" access="ReadOnly" />
+      <BitField name="NAKSTS" description="NAK status" start="17" size="1" access="ReadOnly" />
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write" />
+      <BitField name="Stall" description="STALL handshake" start="21" size="1" access="Read/Write" />
+      <BitField name="TXFNUM" description="TxFIFO number" start="22" size="4" access="Read/Write" />
+      <BitField name="CNAK" description="Clear NAK" start="26" size="1" access="WriteOnly" />
+      <BitField name="SNAK" description="Set NAK" start="27" size="1" access="WriteOnly" />
+      <BitField name="SD0PID_SEVNFRM" description="Set DATA0 PID" start="28" size="1" access="WriteOnly" />
+      <BitField name="SODDFRM" description="Set odd frame" start="29" size="1" access="WriteOnly" />
+      <BitField name="EPDIS" description="Endpoint disable" start="30" size="1" access="Read/Write" />
+      <BitField name="EPENA" description="Endpoint enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HS_DIEPCTL1" description="OTG device endpoint-1 control register" start="+0x120" size="4" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="USBAEP" description="USB active endpoint" start="15" size="1" access="Read/Write" />
+      <BitField name="EONUM_DPID" description="Even/odd frame" start="16" size="1" access="ReadOnly" />
+      <BitField name="NAKSTS" description="NAK status" start="17" size="1" access="ReadOnly" />
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write" />
+      <BitField name="Stall" description="STALL handshake" start="21" size="1" access="Read/Write" />
+      <BitField name="TXFNUM" description="TxFIFO number" start="22" size="4" access="Read/Write" />
+      <BitField name="CNAK" description="Clear NAK" start="26" size="1" access="WriteOnly" />
+      <BitField name="SNAK" description="Set NAK" start="27" size="1" access="WriteOnly" />
+      <BitField name="SD0PID_SEVNFRM" description="Set DATA0 PID" start="28" size="1" access="WriteOnly" />
+      <BitField name="SODDFRM" description="Set odd frame" start="29" size="1" access="WriteOnly" />
+      <BitField name="EPDIS" description="Endpoint disable" start="30" size="1" access="Read/Write" />
+      <BitField name="EPENA" description="Endpoint enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HS_DIEPCTL2" description="OTG device endpoint-2 control register" start="+0x140" size="4" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="USBAEP" description="USB active endpoint" start="15" size="1" access="Read/Write" />
+      <BitField name="EONUM_DPID" description="Even/odd frame" start="16" size="1" access="ReadOnly" />
+      <BitField name="NAKSTS" description="NAK status" start="17" size="1" access="ReadOnly" />
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write" />
+      <BitField name="Stall" description="STALL handshake" start="21" size="1" access="Read/Write" />
+      <BitField name="TXFNUM" description="TxFIFO number" start="22" size="4" access="Read/Write" />
+      <BitField name="CNAK" description="Clear NAK" start="26" size="1" access="WriteOnly" />
+      <BitField name="SNAK" description="Set NAK" start="27" size="1" access="WriteOnly" />
+      <BitField name="SD0PID_SEVNFRM" description="Set DATA0 PID" start="28" size="1" access="WriteOnly" />
+      <BitField name="SODDFRM" description="Set odd frame" start="29" size="1" access="WriteOnly" />
+      <BitField name="EPDIS" description="Endpoint disable" start="30" size="1" access="Read/Write" />
+      <BitField name="EPENA" description="Endpoint enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HS_DIEPCTL3" description="OTG device endpoint-3 control register" start="+0x160" size="4" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="USBAEP" description="USB active endpoint" start="15" size="1" access="Read/Write" />
+      <BitField name="EONUM_DPID" description="Even/odd frame" start="16" size="1" access="ReadOnly" />
+      <BitField name="NAKSTS" description="NAK status" start="17" size="1" access="ReadOnly" />
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write" />
+      <BitField name="Stall" description="STALL handshake" start="21" size="1" access="Read/Write" />
+      <BitField name="TXFNUM" description="TxFIFO number" start="22" size="4" access="Read/Write" />
+      <BitField name="CNAK" description="Clear NAK" start="26" size="1" access="WriteOnly" />
+      <BitField name="SNAK" description="Set NAK" start="27" size="1" access="WriteOnly" />
+      <BitField name="SD0PID_SEVNFRM" description="Set DATA0 PID" start="28" size="1" access="WriteOnly" />
+      <BitField name="SODDFRM" description="Set odd frame" start="29" size="1" access="WriteOnly" />
+      <BitField name="EPDIS" description="Endpoint disable" start="30" size="1" access="Read/Write" />
+      <BitField name="EPENA" description="Endpoint enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HS_DIEPCTL4" description="OTG device endpoint-4 control register" start="+0x180" size="4" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="USBAEP" description="USB active endpoint" start="15" size="1" access="Read/Write" />
+      <BitField name="EONUM_DPID" description="Even/odd frame" start="16" size="1" access="ReadOnly" />
+      <BitField name="NAKSTS" description="NAK status" start="17" size="1" access="ReadOnly" />
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write" />
+      <BitField name="Stall" description="STALL handshake" start="21" size="1" access="Read/Write" />
+      <BitField name="TXFNUM" description="TxFIFO number" start="22" size="4" access="Read/Write" />
+      <BitField name="CNAK" description="Clear NAK" start="26" size="1" access="WriteOnly" />
+      <BitField name="SNAK" description="Set NAK" start="27" size="1" access="WriteOnly" />
+      <BitField name="SD0PID_SEVNFRM" description="Set DATA0 PID" start="28" size="1" access="WriteOnly" />
+      <BitField name="SODDFRM" description="Set odd frame" start="29" size="1" access="WriteOnly" />
+      <BitField name="EPDIS" description="Endpoint disable" start="30" size="1" access="Read/Write" />
+      <BitField name="EPENA" description="Endpoint enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HS_DIEPCTL5" description="OTG device endpoint-5 control register" start="+0x1A0" size="4" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="USBAEP" description="USB active endpoint" start="15" size="1" access="Read/Write" />
+      <BitField name="EONUM_DPID" description="Even/odd frame" start="16" size="1" access="ReadOnly" />
+      <BitField name="NAKSTS" description="NAK status" start="17" size="1" access="ReadOnly" />
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write" />
+      <BitField name="Stall" description="STALL handshake" start="21" size="1" access="Read/Write" />
+      <BitField name="TXFNUM" description="TxFIFO number" start="22" size="4" access="Read/Write" />
+      <BitField name="CNAK" description="Clear NAK" start="26" size="1" access="WriteOnly" />
+      <BitField name="SNAK" description="Set NAK" start="27" size="1" access="WriteOnly" />
+      <BitField name="SD0PID_SEVNFRM" description="Set DATA0 PID" start="28" size="1" access="WriteOnly" />
+      <BitField name="SODDFRM" description="Set odd frame" start="29" size="1" access="WriteOnly" />
+      <BitField name="EPDIS" description="Endpoint disable" start="30" size="1" access="Read/Write" />
+      <BitField name="EPENA" description="Endpoint enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HS_DIEPCTL6" description="OTG device endpoint-6 control register" start="+0x1C0" size="4" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="USBAEP" description="USB active endpoint" start="15" size="1" access="Read/Write" />
+      <BitField name="EONUM_DPID" description="Even/odd frame" start="16" size="1" access="ReadOnly" />
+      <BitField name="NAKSTS" description="NAK status" start="17" size="1" access="ReadOnly" />
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write" />
+      <BitField name="Stall" description="STALL handshake" start="21" size="1" access="Read/Write" />
+      <BitField name="TXFNUM" description="TxFIFO number" start="22" size="4" access="Read/Write" />
+      <BitField name="CNAK" description="Clear NAK" start="26" size="1" access="WriteOnly" />
+      <BitField name="SNAK" description="Set NAK" start="27" size="1" access="WriteOnly" />
+      <BitField name="SD0PID_SEVNFRM" description="Set DATA0 PID" start="28" size="1" access="WriteOnly" />
+      <BitField name="SODDFRM" description="Set odd frame" start="29" size="1" access="WriteOnly" />
+      <BitField name="EPDIS" description="Endpoint disable" start="30" size="1" access="Read/Write" />
+      <BitField name="EPENA" description="Endpoint enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HS_DIEPCTL7" description="OTG device endpoint-7 control register" start="+0x1E0" size="4" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="USBAEP" description="USB active endpoint" start="15" size="1" access="Read/Write" />
+      <BitField name="EONUM_DPID" description="Even/odd frame" start="16" size="1" access="ReadOnly" />
+      <BitField name="NAKSTS" description="NAK status" start="17" size="1" access="ReadOnly" />
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write" />
+      <BitField name="Stall" description="STALL handshake" start="21" size="1" access="Read/Write" />
+      <BitField name="TXFNUM" description="TxFIFO number" start="22" size="4" access="Read/Write" />
+      <BitField name="CNAK" description="Clear NAK" start="26" size="1" access="WriteOnly" />
+      <BitField name="SNAK" description="Set NAK" start="27" size="1" access="WriteOnly" />
+      <BitField name="SD0PID_SEVNFRM" description="Set DATA0 PID" start="28" size="1" access="WriteOnly" />
+      <BitField name="SODDFRM" description="Set odd frame" start="29" size="1" access="WriteOnly" />
+      <BitField name="EPDIS" description="Endpoint disable" start="30" size="1" access="Read/Write" />
+      <BitField name="EPENA" description="Endpoint enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HS_DIEPINT0" description="OTG device endpoint-0 interrupt register" start="+0x108" size="4" reset_value="0x00000080" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRC" description="Transfer completed interrupt" start="0" size="1" access="Read/Write" />
+      <BitField name="EPDISD" description="Endpoint disabled interrupt" start="1" size="1" access="Read/Write" />
+      <BitField name="TOC" description="Timeout condition" start="3" size="1" access="Read/Write" />
+      <BitField name="ITTXFE" description="IN token received when TxFIFO is empty" start="4" size="1" access="Read/Write" />
+      <BitField name="INEPNE" description="IN endpoint NAK effective" start="6" size="1" access="Read/Write" />
+      <BitField name="TXFE" description="Transmit FIFO empty" start="7" size="1" access="ReadOnly" />
+      <BitField name="TXFIFOUDRN" description="Transmit Fifo Underrun" start="8" size="1" access="Read/Write" />
+      <BitField name="BNA" description="Buffer not available interrupt" start="9" size="1" access="Read/Write" />
+      <BitField name="PKTDRPSTS" description="Packet dropped status" start="11" size="1" access="Read/Write" />
+      <BitField name="BERR" description="Babble error interrupt" start="12" size="1" access="Read/Write" />
+      <BitField name="NAK" description="NAK interrupt" start="13" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HS_DIEPINT1" description="OTG device endpoint-1 interrupt register" start="+0x128" size="4" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRC" description="Transfer completed interrupt" start="0" size="1" access="Read/Write" />
+      <BitField name="EPDISD" description="Endpoint disabled interrupt" start="1" size="1" access="Read/Write" />
+      <BitField name="TOC" description="Timeout condition" start="3" size="1" access="Read/Write" />
+      <BitField name="ITTXFE" description="IN token received when TxFIFO is empty" start="4" size="1" access="Read/Write" />
+      <BitField name="INEPNE" description="IN endpoint NAK effective" start="6" size="1" access="Read/Write" />
+      <BitField name="TXFE" description="Transmit FIFO empty" start="7" size="1" access="ReadOnly" />
+      <BitField name="TXFIFOUDRN" description="Transmit Fifo Underrun" start="8" size="1" access="Read/Write" />
+      <BitField name="BNA" description="Buffer not available interrupt" start="9" size="1" access="Read/Write" />
+      <BitField name="PKTDRPSTS" description="Packet dropped status" start="11" size="1" access="Read/Write" />
+      <BitField name="BERR" description="Babble error interrupt" start="12" size="1" access="Read/Write" />
+      <BitField name="NAK" description="NAK interrupt" start="13" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HS_DIEPINT2" description="OTG device endpoint-2 interrupt register" start="+0x148" size="4" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRC" description="Transfer completed interrupt" start="0" size="1" access="Read/Write" />
+      <BitField name="EPDISD" description="Endpoint disabled interrupt" start="1" size="1" access="Read/Write" />
+      <BitField name="TOC" description="Timeout condition" start="3" size="1" access="Read/Write" />
+      <BitField name="ITTXFE" description="IN token received when TxFIFO is empty" start="4" size="1" access="Read/Write" />
+      <BitField name="INEPNE" description="IN endpoint NAK effective" start="6" size="1" access="Read/Write" />
+      <BitField name="TXFE" description="Transmit FIFO empty" start="7" size="1" access="ReadOnly" />
+      <BitField name="TXFIFOUDRN" description="Transmit Fifo Underrun" start="8" size="1" access="Read/Write" />
+      <BitField name="BNA" description="Buffer not available interrupt" start="9" size="1" access="Read/Write" />
+      <BitField name="PKTDRPSTS" description="Packet dropped status" start="11" size="1" access="Read/Write" />
+      <BitField name="BERR" description="Babble error interrupt" start="12" size="1" access="Read/Write" />
+      <BitField name="NAK" description="NAK interrupt" start="13" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HS_DIEPINT3" description="OTG device endpoint-3 interrupt register" start="+0x168" size="4" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRC" description="Transfer completed interrupt" start="0" size="1" access="Read/Write" />
+      <BitField name="EPDISD" description="Endpoint disabled interrupt" start="1" size="1" access="Read/Write" />
+      <BitField name="TOC" description="Timeout condition" start="3" size="1" access="Read/Write" />
+      <BitField name="ITTXFE" description="IN token received when TxFIFO is empty" start="4" size="1" access="Read/Write" />
+      <BitField name="INEPNE" description="IN endpoint NAK effective" start="6" size="1" access="Read/Write" />
+      <BitField name="TXFE" description="Transmit FIFO empty" start="7" size="1" access="ReadOnly" />
+      <BitField name="TXFIFOUDRN" description="Transmit Fifo Underrun" start="8" size="1" access="Read/Write" />
+      <BitField name="BNA" description="Buffer not available interrupt" start="9" size="1" access="Read/Write" />
+      <BitField name="PKTDRPSTS" description="Packet dropped status" start="11" size="1" access="Read/Write" />
+      <BitField name="BERR" description="Babble error interrupt" start="12" size="1" access="Read/Write" />
+      <BitField name="NAK" description="NAK interrupt" start="13" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HS_DIEPINT4" description="OTG device endpoint-4 interrupt register" start="+0x188" size="4" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRC" description="Transfer completed interrupt" start="0" size="1" access="Read/Write" />
+      <BitField name="EPDISD" description="Endpoint disabled interrupt" start="1" size="1" access="Read/Write" />
+      <BitField name="TOC" description="Timeout condition" start="3" size="1" access="Read/Write" />
+      <BitField name="ITTXFE" description="IN token received when TxFIFO is empty" start="4" size="1" access="Read/Write" />
+      <BitField name="INEPNE" description="IN endpoint NAK effective" start="6" size="1" access="Read/Write" />
+      <BitField name="TXFE" description="Transmit FIFO empty" start="7" size="1" access="ReadOnly" />
+      <BitField name="TXFIFOUDRN" description="Transmit Fifo Underrun" start="8" size="1" access="Read/Write" />
+      <BitField name="BNA" description="Buffer not available interrupt" start="9" size="1" access="Read/Write" />
+      <BitField name="PKTDRPSTS" description="Packet dropped status" start="11" size="1" access="Read/Write" />
+      <BitField name="BERR" description="Babble error interrupt" start="12" size="1" access="Read/Write" />
+      <BitField name="NAK" description="NAK interrupt" start="13" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HS_DIEPINT5" description="OTG device endpoint-5 interrupt register" start="+0x1A8" size="4" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRC" description="Transfer completed interrupt" start="0" size="1" access="Read/Write" />
+      <BitField name="EPDISD" description="Endpoint disabled interrupt" start="1" size="1" access="Read/Write" />
+      <BitField name="TOC" description="Timeout condition" start="3" size="1" access="Read/Write" />
+      <BitField name="ITTXFE" description="IN token received when TxFIFO is empty" start="4" size="1" access="Read/Write" />
+      <BitField name="INEPNE" description="IN endpoint NAK effective" start="6" size="1" access="Read/Write" />
+      <BitField name="TXFE" description="Transmit FIFO empty" start="7" size="1" access="ReadOnly" />
+      <BitField name="TXFIFOUDRN" description="Transmit Fifo Underrun" start="8" size="1" access="Read/Write" />
+      <BitField name="BNA" description="Buffer not available interrupt" start="9" size="1" access="Read/Write" />
+      <BitField name="PKTDRPSTS" description="Packet dropped status" start="11" size="1" access="Read/Write" />
+      <BitField name="BERR" description="Babble error interrupt" start="12" size="1" access="Read/Write" />
+      <BitField name="NAK" description="NAK interrupt" start="13" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HS_DIEPINT6" description="OTG device endpoint-6 interrupt register" start="+0x1C8" size="4" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRC" description="Transfer completed interrupt" start="0" size="1" access="Read/Write" />
+      <BitField name="EPDISD" description="Endpoint disabled interrupt" start="1" size="1" access="Read/Write" />
+      <BitField name="TOC" description="Timeout condition" start="3" size="1" access="Read/Write" />
+      <BitField name="ITTXFE" description="IN token received when TxFIFO is empty" start="4" size="1" access="Read/Write" />
+      <BitField name="INEPNE" description="IN endpoint NAK effective" start="6" size="1" access="Read/Write" />
+      <BitField name="TXFE" description="Transmit FIFO empty" start="7" size="1" access="ReadOnly" />
+      <BitField name="TXFIFOUDRN" description="Transmit Fifo Underrun" start="8" size="1" access="Read/Write" />
+      <BitField name="BNA" description="Buffer not available interrupt" start="9" size="1" access="Read/Write" />
+      <BitField name="PKTDRPSTS" description="Packet dropped status" start="11" size="1" access="Read/Write" />
+      <BitField name="BERR" description="Babble error interrupt" start="12" size="1" access="Read/Write" />
+      <BitField name="NAK" description="NAK interrupt" start="13" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HS_DIEPINT7" description="OTG device endpoint-7 interrupt register" start="+0x1E8" size="4" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRC" description="Transfer completed interrupt" start="0" size="1" access="Read/Write" />
+      <BitField name="EPDISD" description="Endpoint disabled interrupt" start="1" size="1" access="Read/Write" />
+      <BitField name="TOC" description="Timeout condition" start="3" size="1" access="Read/Write" />
+      <BitField name="ITTXFE" description="IN token received when TxFIFO is empty" start="4" size="1" access="Read/Write" />
+      <BitField name="INEPNE" description="IN endpoint NAK effective" start="6" size="1" access="Read/Write" />
+      <BitField name="TXFE" description="Transmit FIFO empty" start="7" size="1" access="ReadOnly" />
+      <BitField name="TXFIFOUDRN" description="Transmit Fifo Underrun" start="8" size="1" access="Read/Write" />
+      <BitField name="BNA" description="Buffer not available interrupt" start="9" size="1" access="Read/Write" />
+      <BitField name="PKTDRPSTS" description="Packet dropped status" start="11" size="1" access="Read/Write" />
+      <BitField name="BERR" description="Babble error interrupt" start="12" size="1" access="Read/Write" />
+      <BitField name="NAK" description="NAK interrupt" start="13" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HS_DIEPTSIZ0" description="OTG_HS device IN endpoint 0 transfer size register" start="+0x110" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRSIZ" description="Transfer size" start="0" size="7" />
+      <BitField name="PKTCNT" description="Packet count" start="19" size="2" />
+    </Register>
+    <Register name="OTG_HS_DIEPDMA1" description="OTG_HS device endpoint-1 DMA address register" start="+0x114" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAADDR" description="DMA address" start="0" size="32" />
+    </Register>
+    <Register name="OTG_HS_DIEPDMA2" description="OTG_HS device endpoint-2 DMA address register" start="+0x134" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAADDR" description="DMA address" start="0" size="32" />
+    </Register>
+    <Register name="OTG_HS_DIEPDMA3" description="OTG_HS device endpoint-3 DMA address register" start="+0x154" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAADDR" description="DMA address" start="0" size="32" />
+    </Register>
+    <Register name="OTG_HS_DIEPDMA4" description="OTG_HS device endpoint-4 DMA address register" start="+0x174" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAADDR" description="DMA address" start="0" size="32" />
+    </Register>
+    <Register name="OTG_HS_DIEPDMA5" description="OTG_HS device endpoint-5 DMA address register" start="+0x194" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAADDR" description="DMA address" start="0" size="32" />
+    </Register>
+    <Register name="OTG_HS_DTXFSTS0" description="OTG_HS device IN endpoint transmit FIFO status register" start="+0x118" size="4" access="ReadOnly" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="INEPTFSAV" description="IN endpoint TxFIFO space avail" start="0" size="16" />
+    </Register>
+    <Register name="OTG_HS_DTXFSTS1" description="OTG_HS device IN endpoint transmit FIFO status register" start="+0x138" size="4" access="ReadOnly" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="INEPTFSAV" description="IN endpoint TxFIFO space avail" start="0" size="16" />
+    </Register>
+    <Register name="OTG_HS_DTXFSTS2" description="OTG_HS device IN endpoint transmit FIFO status register" start="+0x158" size="4" access="ReadOnly" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="INEPTFSAV" description="IN endpoint TxFIFO space avail" start="0" size="16" />
+    </Register>
+    <Register name="OTG_HS_DTXFSTS3" description="OTG_HS device IN endpoint transmit FIFO status register" start="+0x178" size="4" access="ReadOnly" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="INEPTFSAV" description="IN endpoint TxFIFO space avail" start="0" size="16" />
+    </Register>
+    <Register name="OTG_HS_DTXFSTS4" description="OTG_HS device IN endpoint transmit FIFO status register" start="+0x198" size="4" access="ReadOnly" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="INEPTFSAV" description="IN endpoint TxFIFO space avail" start="0" size="16" />
+    </Register>
+    <Register name="OTG_HS_DTXFSTS5" description="OTG_HS device IN endpoint transmit FIFO status register" start="+0x1B8" size="4" access="ReadOnly" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="INEPTFSAV" description="IN endpoint TxFIFO space avail" start="0" size="16" />
+    </Register>
+    <Register name="OTG_HS_DIEPTSIZ1" description="OTG_HS device endpoint transfer size register" start="+0x130" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRSIZ" description="Transfer size" start="0" size="19" />
+      <BitField name="PKTCNT" description="Packet count" start="19" size="10" />
+      <BitField name="MCNT" description="Multi count" start="29" size="2" />
+    </Register>
+    <Register name="OTG_HS_DIEPTSIZ2" description="OTG_HS device endpoint transfer size register" start="+0x150" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRSIZ" description="Transfer size" start="0" size="19" />
+      <BitField name="PKTCNT" description="Packet count" start="19" size="10" />
+      <BitField name="MCNT" description="Multi count" start="29" size="2" />
+    </Register>
+    <Register name="OTG_HS_DIEPTSIZ3" description="OTG_HS device endpoint transfer size register" start="+0x170" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRSIZ" description="Transfer size" start="0" size="19" />
+      <BitField name="PKTCNT" description="Packet count" start="19" size="10" />
+      <BitField name="MCNT" description="Multi count" start="29" size="2" />
+    </Register>
+    <Register name="OTG_HS_DIEPTSIZ4" description="OTG_HS device endpoint transfer size register" start="+0x190" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRSIZ" description="Transfer size" start="0" size="19" />
+      <BitField name="PKTCNT" description="Packet count" start="19" size="10" />
+      <BitField name="MCNT" description="Multi count" start="29" size="2" />
+    </Register>
+    <Register name="OTG_HS_DIEPTSIZ5" description="OTG_HS device endpoint transfer size register" start="+0x1B0" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRSIZ" description="Transfer size" start="0" size="19" />
+      <BitField name="PKTCNT" description="Packet count" start="19" size="10" />
+      <BitField name="MCNT" description="Multi count" start="29" size="2" />
+    </Register>
+    <Register name="OTG_HS_DOEPCTL0" description="OTG_HS device control OUT endpoint 0 control register" start="+0x300" size="4" reset_value="0x00008000" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="2" access="ReadOnly" />
+      <BitField name="USBAEP" description="USB active endpoint" start="15" size="1" access="ReadOnly" />
+      <BitField name="NAKSTS" description="NAK status" start="17" size="1" access="ReadOnly" />
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="ReadOnly" />
+      <BitField name="SNPM" description="Snoop mode" start="20" size="1" access="Read/Write" />
+      <BitField name="Stall" description="STALL handshake" start="21" size="1" access="Read/Write" />
+      <BitField name="CNAK" description="Clear NAK" start="26" size="1" access="WriteOnly" />
+      <BitField name="SNAK" description="Set NAK" start="27" size="1" access="WriteOnly" />
+      <BitField name="EPDIS" description="Endpoint disable" start="30" size="1" access="ReadOnly" />
+      <BitField name="EPENA" description="Endpoint enable" start="31" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="OTG_HS_DOEPCTL1" description="OTG device endpoint-1 control register" start="+0x320" size="4" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="USBAEP" description="USB active endpoint" start="15" size="1" access="Read/Write" />
+      <BitField name="EONUM_DPID" description="Even odd frame/Endpoint data PID" start="16" size="1" access="ReadOnly" />
+      <BitField name="NAKSTS" description="NAK status" start="17" size="1" access="ReadOnly" />
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write" />
+      <BitField name="SNPM" description="Snoop mode" start="20" size="1" access="Read/Write" />
+      <BitField name="Stall" description="STALL handshake" start="21" size="1" access="Read/Write" />
+      <BitField name="CNAK" description="Clear NAK" start="26" size="1" access="WriteOnly" />
+      <BitField name="SNAK" description="Set NAK" start="27" size="1" access="WriteOnly" />
+      <BitField name="SD0PID_SEVNFRM" description="Set DATA0 PID/Set even frame" start="28" size="1" access="WriteOnly" />
+      <BitField name="SODDFRM" description="Set odd frame" start="29" size="1" access="WriteOnly" />
+      <BitField name="EPDIS" description="Endpoint disable" start="30" size="1" access="Read/Write" />
+      <BitField name="EPENA" description="Endpoint enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HS_DOEPCTL2" description="OTG device endpoint-2 control register" start="+0x340" size="4" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="USBAEP" description="USB active endpoint" start="15" size="1" access="Read/Write" />
+      <BitField name="EONUM_DPID" description="Even odd frame/Endpoint data PID" start="16" size="1" access="ReadOnly" />
+      <BitField name="NAKSTS" description="NAK status" start="17" size="1" access="ReadOnly" />
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write" />
+      <BitField name="SNPM" description="Snoop mode" start="20" size="1" access="Read/Write" />
+      <BitField name="Stall" description="STALL handshake" start="21" size="1" access="Read/Write" />
+      <BitField name="CNAK" description="Clear NAK" start="26" size="1" access="WriteOnly" />
+      <BitField name="SNAK" description="Set NAK" start="27" size="1" access="WriteOnly" />
+      <BitField name="SD0PID_SEVNFRM" description="Set DATA0 PID/Set even frame" start="28" size="1" access="WriteOnly" />
+      <BitField name="SODDFRM" description="Set odd frame" start="29" size="1" access="WriteOnly" />
+      <BitField name="EPDIS" description="Endpoint disable" start="30" size="1" access="Read/Write" />
+      <BitField name="EPENA" description="Endpoint enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HS_DOEPCTL3" description="OTG device endpoint-3 control register" start="+0x360" size="4" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="USBAEP" description="USB active endpoint" start="15" size="1" access="Read/Write" />
+      <BitField name="EONUM_DPID" description="Even odd frame/Endpoint data PID" start="16" size="1" access="ReadOnly" />
+      <BitField name="NAKSTS" description="NAK status" start="17" size="1" access="ReadOnly" />
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write" />
+      <BitField name="SNPM" description="Snoop mode" start="20" size="1" access="Read/Write" />
+      <BitField name="Stall" description="STALL handshake" start="21" size="1" access="Read/Write" />
+      <BitField name="CNAK" description="Clear NAK" start="26" size="1" access="WriteOnly" />
+      <BitField name="SNAK" description="Set NAK" start="27" size="1" access="WriteOnly" />
+      <BitField name="SD0PID_SEVNFRM" description="Set DATA0 PID/Set even frame" start="28" size="1" access="WriteOnly" />
+      <BitField name="SODDFRM" description="Set odd frame" start="29" size="1" access="WriteOnly" />
+      <BitField name="EPDIS" description="Endpoint disable" start="30" size="1" access="Read/Write" />
+      <BitField name="EPENA" description="Endpoint enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HS_DOEPINT0" description="OTG_HS device endpoint-0 interrupt register" start="+0x308" size="4" access="Read/Write" reset_value="0x00000080" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRC" description="Transfer completed interrupt" start="0" size="1" />
+      <BitField name="EPDISD" description="Endpoint disabled interrupt" start="1" size="1" />
+      <BitField name="STUP" description="SETUP phase done" start="3" size="1" />
+      <BitField name="OTEPDIS" description="OUT token received when endpoint disabled" start="4" size="1" />
+      <BitField name="B2BSTUP" description="Back-to-back SETUP packets received" start="6" size="1" />
+      <BitField name="NYET" description="NYET interrupt" start="14" size="1" />
+    </Register>
+    <Register name="OTG_HS_DOEPINT1" description="OTG_HS device endpoint-1 interrupt register" start="+0x328" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRC" description="Transfer completed interrupt" start="0" size="1" />
+      <BitField name="EPDISD" description="Endpoint disabled interrupt" start="1" size="1" />
+      <BitField name="STUP" description="SETUP phase done" start="3" size="1" />
+      <BitField name="OTEPDIS" description="OUT token received when endpoint disabled" start="4" size="1" />
+      <BitField name="B2BSTUP" description="Back-to-back SETUP packets received" start="6" size="1" />
+      <BitField name="NYET" description="NYET interrupt" start="14" size="1" />
+    </Register>
+    <Register name="OTG_HS_DOEPINT2" description="OTG_HS device endpoint-2 interrupt register" start="+0x348" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRC" description="Transfer completed interrupt" start="0" size="1" />
+      <BitField name="EPDISD" description="Endpoint disabled interrupt" start="1" size="1" />
+      <BitField name="STUP" description="SETUP phase done" start="3" size="1" />
+      <BitField name="OTEPDIS" description="OUT token received when endpoint disabled" start="4" size="1" />
+      <BitField name="B2BSTUP" description="Back-to-back SETUP packets received" start="6" size="1" />
+      <BitField name="NYET" description="NYET interrupt" start="14" size="1" />
+    </Register>
+    <Register name="OTG_HS_DOEPINT3" description="OTG_HS device endpoint-3 interrupt register" start="+0x368" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRC" description="Transfer completed interrupt" start="0" size="1" />
+      <BitField name="EPDISD" description="Endpoint disabled interrupt" start="1" size="1" />
+      <BitField name="STUP" description="SETUP phase done" start="3" size="1" />
+      <BitField name="OTEPDIS" description="OUT token received when endpoint disabled" start="4" size="1" />
+      <BitField name="B2BSTUP" description="Back-to-back SETUP packets received" start="6" size="1" />
+      <BitField name="NYET" description="NYET interrupt" start="14" size="1" />
+    </Register>
+    <Register name="OTG_HS_DOEPINT4" description="OTG_HS device endpoint-4 interrupt register" start="+0x388" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRC" description="Transfer completed interrupt" start="0" size="1" />
+      <BitField name="EPDISD" description="Endpoint disabled interrupt" start="1" size="1" />
+      <BitField name="STUP" description="SETUP phase done" start="3" size="1" />
+      <BitField name="OTEPDIS" description="OUT token received when endpoint disabled" start="4" size="1" />
+      <BitField name="B2BSTUP" description="Back-to-back SETUP packets received" start="6" size="1" />
+      <BitField name="NYET" description="NYET interrupt" start="14" size="1" />
+    </Register>
+    <Register name="OTG_HS_DOEPINT5" description="OTG_HS device endpoint-5 interrupt register" start="+0x3A8" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRC" description="Transfer completed interrupt" start="0" size="1" />
+      <BitField name="EPDISD" description="Endpoint disabled interrupt" start="1" size="1" />
+      <BitField name="STUP" description="SETUP phase done" start="3" size="1" />
+      <BitField name="OTEPDIS" description="OUT token received when endpoint disabled" start="4" size="1" />
+      <BitField name="B2BSTUP" description="Back-to-back SETUP packets received" start="6" size="1" />
+      <BitField name="NYET" description="NYET interrupt" start="14" size="1" />
+    </Register>
+    <Register name="OTG_HS_DOEPINT6" description="OTG_HS device endpoint-6 interrupt register" start="+0x3C8" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRC" description="Transfer completed interrupt" start="0" size="1" />
+      <BitField name="EPDISD" description="Endpoint disabled interrupt" start="1" size="1" />
+      <BitField name="STUP" description="SETUP phase done" start="3" size="1" />
+      <BitField name="OTEPDIS" description="OUT token received when endpoint disabled" start="4" size="1" />
+      <BitField name="B2BSTUP" description="Back-to-back SETUP packets received" start="6" size="1" />
+      <BitField name="NYET" description="NYET interrupt" start="14" size="1" />
+    </Register>
+    <Register name="OTG_HS_DOEPINT7" description="OTG_HS device endpoint-7 interrupt register" start="+0x3E8" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRC" description="Transfer completed interrupt" start="0" size="1" />
+      <BitField name="EPDISD" description="Endpoint disabled interrupt" start="1" size="1" />
+      <BitField name="STUP" description="SETUP phase done" start="3" size="1" />
+      <BitField name="OTEPDIS" description="OUT token received when endpoint disabled" start="4" size="1" />
+      <BitField name="B2BSTUP" description="Back-to-back SETUP packets received" start="6" size="1" />
+      <BitField name="NYET" description="NYET interrupt" start="14" size="1" />
+    </Register>
+    <Register name="OTG_HS_DOEPTSIZ0" description="OTG_HS device endpoint-0 transfer size register" start="+0x310" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRSIZ" description="Transfer size" start="0" size="7" />
+      <BitField name="PKTCNT" description="Packet count" start="19" size="1" />
+      <BitField name="STUPCNT" description="SETUP packet count" start="29" size="2" />
+    </Register>
+    <Register name="OTG_HS_DOEPTSIZ1" description="OTG_HS device endpoint-1 transfer size register" start="+0x330" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRSIZ" description="Transfer size" start="0" size="19" />
+      <BitField name="PKTCNT" description="Packet count" start="19" size="10" />
+      <BitField name="RXDPID_STUPCNT" description="Received data PID/SETUP packet count" start="29" size="2" />
+    </Register>
+    <Register name="OTG_HS_DOEPTSIZ2" description="OTG_HS device endpoint-2 transfer size register" start="+0x350" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRSIZ" description="Transfer size" start="0" size="19" />
+      <BitField name="PKTCNT" description="Packet count" start="19" size="10" />
+      <BitField name="RXDPID_STUPCNT" description="Received data PID/SETUP packet count" start="29" size="2" />
+    </Register>
+    <Register name="OTG_HS_DOEPTSIZ3" description="OTG_HS device endpoint-3 transfer size register" start="+0x370" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRSIZ" description="Transfer size" start="0" size="19" />
+      <BitField name="PKTCNT" description="Packet count" start="19" size="10" />
+      <BitField name="RXDPID_STUPCNT" description="Received data PID/SETUP packet count" start="29" size="2" />
+    </Register>
+    <Register name="OTG_HS_DOEPTSIZ4" description="OTG_HS device endpoint-4 transfer size register" start="+0x390" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRSIZ" description="Transfer size" start="0" size="19" />
+      <BitField name="PKTCNT" description="Packet count" start="19" size="10" />
+      <BitField name="RXDPID_STUPCNT" description="Received data PID/SETUP packet count" start="29" size="2" />
+    </Register>
+    <Register name="OTG_HS_DIEPTSIZ6" description="OTG_HS device endpoint transfer size register" start="+0x1A0" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRSIZ" description="Transfer size" start="0" size="19" />
+      <BitField name="PKTCNT" description="Packet count" start="19" size="10" />
+      <BitField name="MCNT" description="Multi count" start="29" size="2" />
+    </Register>
+    <Register name="OTG_HS_DTXFSTS6" description="OTG_HS device IN endpoint transmit FIFO status register" start="+0x1A4" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="INEPTFSAV" description="IN endpoint TxFIFO space avail" start="0" size="16" />
+    </Register>
+    <Register name="OTG_HS_DIEPTSIZ7" description="OTG_HS device endpoint transfer size register" start="+0x1A8" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRSIZ" description="Transfer size" start="0" size="19" />
+      <BitField name="PKTCNT" description="Packet count" start="19" size="10" />
+      <BitField name="MCNT" description="Multi count" start="29" size="2" />
+    </Register>
+    <Register name="OTG_HS_DTXFSTS7" description="OTG_HS device IN endpoint transmit FIFO status register" start="+0x1AC" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="INEPTFSAV" description="IN endpoint TxFIFO space avail" start="0" size="16" />
+    </Register>
+    <Register name="OTG_HS_DOEPCTL4" description="OTG device endpoint-4 control register" start="+0x380" size="4" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="USBAEP" description="USB active endpoint" start="15" size="1" access="Read/Write" />
+      <BitField name="EONUM_DPID" description="Even odd frame/Endpoint data PID" start="16" size="1" access="ReadOnly" />
+      <BitField name="NAKSTS" description="NAK status" start="17" size="1" access="ReadOnly" />
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write" />
+      <BitField name="SNPM" description="Snoop mode" start="20" size="1" access="Read/Write" />
+      <BitField name="Stall" description="STALL handshake" start="21" size="1" access="Read/Write" />
+      <BitField name="CNAK" description="Clear NAK" start="26" size="1" access="WriteOnly" />
+      <BitField name="SNAK" description="Set NAK" start="27" size="1" access="WriteOnly" />
+      <BitField name="SD0PID_SEVNFRM" description="Set DATA0 PID/Set even frame" start="28" size="1" access="WriteOnly" />
+      <BitField name="SODDFRM" description="Set odd frame" start="29" size="1" access="WriteOnly" />
+      <BitField name="EPDIS" description="Endpoint disable" start="30" size="1" access="Read/Write" />
+      <BitField name="EPENA" description="Endpoint enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HS_DOEPCTL5" description="OTG device endpoint-5 control register" start="+0x3A0" size="4" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="USBAEP" description="USB active endpoint" start="15" size="1" access="Read/Write" />
+      <BitField name="EONUM_DPID" description="Even odd frame/Endpoint data PID" start="16" size="1" access="ReadOnly" />
+      <BitField name="NAKSTS" description="NAK status" start="17" size="1" access="ReadOnly" />
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write" />
+      <BitField name="SNPM" description="Snoop mode" start="20" size="1" access="Read/Write" />
+      <BitField name="Stall" description="STALL handshake" start="21" size="1" access="Read/Write" />
+      <BitField name="CNAK" description="Clear NAK" start="26" size="1" access="WriteOnly" />
+      <BitField name="SNAK" description="Set NAK" start="27" size="1" access="WriteOnly" />
+      <BitField name="SD0PID_SEVNFRM" description="Set DATA0 PID/Set even frame" start="28" size="1" access="WriteOnly" />
+      <BitField name="SODDFRM" description="Set odd frame" start="29" size="1" access="WriteOnly" />
+      <BitField name="EPDIS" description="Endpoint disable" start="30" size="1" access="Read/Write" />
+      <BitField name="EPENA" description="Endpoint enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HS_DOEPCTL6" description="OTG device endpoint-6 control register" start="+0x3C0" size="4" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="USBAEP" description="USB active endpoint" start="15" size="1" access="Read/Write" />
+      <BitField name="EONUM_DPID" description="Even odd frame/Endpoint data PID" start="16" size="1" access="ReadOnly" />
+      <BitField name="NAKSTS" description="NAK status" start="17" size="1" access="ReadOnly" />
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write" />
+      <BitField name="SNPM" description="Snoop mode" start="20" size="1" access="Read/Write" />
+      <BitField name="Stall" description="STALL handshake" start="21" size="1" access="Read/Write" />
+      <BitField name="CNAK" description="Clear NAK" start="26" size="1" access="WriteOnly" />
+      <BitField name="SNAK" description="Set NAK" start="27" size="1" access="WriteOnly" />
+      <BitField name="SD0PID_SEVNFRM" description="Set DATA0 PID/Set even frame" start="28" size="1" access="WriteOnly" />
+      <BitField name="SODDFRM" description="Set odd frame" start="29" size="1" access="WriteOnly" />
+      <BitField name="EPDIS" description="Endpoint disable" start="30" size="1" access="Read/Write" />
+      <BitField name="EPENA" description="Endpoint enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HS_DOEPCTL7" description="OTG device endpoint-7 control register" start="+0x3E0" size="4" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="USBAEP" description="USB active endpoint" start="15" size="1" access="Read/Write" />
+      <BitField name="EONUM_DPID" description="Even odd frame/Endpoint data PID" start="16" size="1" access="ReadOnly" />
+      <BitField name="NAKSTS" description="NAK status" start="17" size="1" access="ReadOnly" />
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write" />
+      <BitField name="SNPM" description="Snoop mode" start="20" size="1" access="Read/Write" />
+      <BitField name="Stall" description="STALL handshake" start="21" size="1" access="Read/Write" />
+      <BitField name="CNAK" description="Clear NAK" start="26" size="1" access="WriteOnly" />
+      <BitField name="SNAK" description="Set NAK" start="27" size="1" access="WriteOnly" />
+      <BitField name="SD0PID_SEVNFRM" description="Set DATA0 PID/Set even frame" start="28" size="1" access="WriteOnly" />
+      <BitField name="SODDFRM" description="Set odd frame" start="29" size="1" access="WriteOnly" />
+      <BitField name="EPDIS" description="Endpoint disable" start="30" size="1" access="Read/Write" />
+      <BitField name="EPENA" description="Endpoint enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HS_DOEPTSIZ5" description="OTG_HS device endpoint-5 transfer size register" start="+0x3B0" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRSIZ" description="Transfer size" start="0" size="19" />
+      <BitField name="PKTCNT" description="Packet count" start="19" size="10" />
+      <BitField name="RXDPID_STUPCNT" description="Received data PID/SETUP packet count" start="29" size="2" />
+    </Register>
+    <Register name="OTG_HS_DOEPTSIZ6" description="OTG_HS device endpoint-6 transfer size register" start="+0x3D0" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRSIZ" description="Transfer size" start="0" size="19" />
+      <BitField name="PKTCNT" description="Packet count" start="19" size="10" />
+      <BitField name="RXDPID_STUPCNT" description="Received data PID/SETUP packet count" start="29" size="2" />
+    </Register>
+    <Register name="OTG_HS_DOEPTSIZ7" description="OTG_HS device endpoint-7 transfer size register" start="+0x3F0" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRSIZ" description="Transfer size" start="0" size="19" />
+      <BitField name="PKTCNT" description="Packet count" start="19" size="10" />
+      <BitField name="RXDPID_STUPCNT" description="Received data PID/SETUP packet count" start="29" size="2" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="OTG2_HS_DEVICE" description="USB 1 on the go high speed" start="0x40080800">
+    <Register name="OTG_HS_DCFG" description="OTG_HS device configuration register" start="+0x0" size="4" access="Read/Write" reset_value="0x02200000" reset_mask="0xFFFFFFFF">
+      <BitField name="DSPD" description="Device speed" start="0" size="2" />
+      <BitField name="NZLSOHSK" description="Nonzero-length status OUT handshake" start="2" size="1" />
+      <BitField name="DAD" description="Device address" start="4" size="7" />
+      <BitField name="PFIVL" description="Periodic (micro)frame interval" start="11" size="2" />
+      <BitField name="PERSCHIVL" description="Periodic scheduling interval" start="24" size="2" />
+    </Register>
+    <Register name="OTG_HS_DCTL" description="OTG_HS device control register" start="+0x4" size="4" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="RWUSIG" description="Remote wakeup signaling" start="0" size="1" access="Read/Write" />
+      <BitField name="SDIS" description="Soft disconnect" start="1" size="1" access="Read/Write" />
+      <BitField name="GINSTS" description="Global IN NAK status" start="2" size="1" access="ReadOnly" />
+      <BitField name="GONSTS" description="Global OUT NAK status" start="3" size="1" access="ReadOnly" />
+      <BitField name="TCTL" description="Test control" start="4" size="3" access="Read/Write" />
+      <BitField name="SGINAK" description="Set global IN NAK" start="7" size="1" access="WriteOnly" />
+      <BitField name="CGINAK" description="Clear global IN NAK" start="8" size="1" access="WriteOnly" />
+      <BitField name="SGONAK" description="Set global OUT NAK" start="9" size="1" access="WriteOnly" />
+      <BitField name="CGONAK" description="Clear global OUT NAK" start="10" size="1" access="WriteOnly" />
+      <BitField name="POPRGDNE" description="Power-on programming done" start="11" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HS_DSTS" description="OTG_HS device status register" start="+0x8" size="4" access="ReadOnly" reset_value="0x00000010" reset_mask="0xFFFFFFFF">
+      <BitField name="SUSPSTS" description="Suspend status" start="0" size="1" />
+      <BitField name="ENUMSPD" description="Enumerated speed" start="1" size="2" />
+      <BitField name="EERR" description="Erratic error" start="3" size="1" />
+      <BitField name="FNSOF" description="Frame number of the received SOF" start="8" size="14" />
+    </Register>
+    <Register name="OTG_HS_DIEPMSK" description="OTG_HS device IN endpoint common interrupt mask register" start="+0x10" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRCM" description="Transfer completed interrupt mask" start="0" size="1" />
+      <BitField name="EPDM" description="Endpoint disabled interrupt mask" start="1" size="1" />
+      <BitField name="TOM" description="Timeout condition mask (nonisochronous endpoints)" start="3" size="1" />
+      <BitField name="ITTXFEMSK" description="IN token received when TxFIFO empty mask" start="4" size="1" />
+      <BitField name="INEPNMM" description="IN token received with EP mismatch mask" start="5" size="1" />
+      <BitField name="INEPNEM" description="IN endpoint NAK effective mask" start="6" size="1" />
+      <BitField name="TXFURM" description="FIFO underrun mask" start="8" size="1" />
+      <BitField name="BIM" description="BNA interrupt mask" start="9" size="1" />
+    </Register>
+    <Register name="OTG_HS_DOEPMSK" description="OTG_HS device OUT endpoint common interrupt mask register" start="+0x14" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRCM" description="Transfer completed interrupt mask" start="0" size="1" />
+      <BitField name="EPDM" description="Endpoint disabled interrupt mask" start="1" size="1" />
+      <BitField name="STUPM" description="SETUP phase done mask" start="3" size="1" />
+      <BitField name="OTEPDM" description="OUT token received when endpoint disabled mask" start="4" size="1" />
+      <BitField name="B2BSTUP" description="Back-to-back SETUP packets received mask" start="6" size="1" />
+      <BitField name="OPEM" description="OUT packet error mask" start="8" size="1" />
+      <BitField name="BOIM" description="BNA interrupt mask" start="9" size="1" />
+    </Register>
+    <Register name="OTG_HS_DAINT" description="OTG_HS device all endpoints interrupt register" start="+0x18" size="4" access="ReadOnly" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="IEPINT" description="IN endpoint interrupt bits" start="0" size="16" />
+      <BitField name="OEPINT" description="OUT endpoint interrupt bits" start="16" size="16" />
+    </Register>
+    <Register name="OTG_HS_DAINTMSK" description="OTG_HS all endpoints interrupt mask register" start="+0x1C" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="IEPM" description="IN EP interrupt mask bits" start="0" size="16" />
+      <BitField name="OEPM" description="OUT EP interrupt mask bits" start="16" size="16" />
+    </Register>
+    <Register name="OTG_HS_DVBUSDIS" description="OTG_HS device VBUS discharge time register" start="+0x28" size="4" access="Read/Write" reset_value="0x000017D7" reset_mask="0xFFFFFFFF">
+      <BitField name="VBUSDT" description="Device VBUS discharge time" start="0" size="16" />
+    </Register>
+    <Register name="OTG_HS_DVBUSPULSE" description="OTG_HS device VBUS pulsing time register" start="+0x2C" size="4" access="Read/Write" reset_value="0x000005B8" reset_mask="0xFFFFFFFF">
+      <BitField name="DVBUSP" description="Device VBUS pulsing time" start="0" size="12" />
+    </Register>
+    <Register name="OTG_HS_DTHRCTL" description="OTG_HS Device threshold control register" start="+0x30" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="NONISOTHREN" description="Nonisochronous IN endpoints threshold enable" start="0" size="1" />
+      <BitField name="ISOTHREN" description="ISO IN endpoint threshold enable" start="1" size="1" />
+      <BitField name="TXTHRLEN" description="Transmit threshold length" start="2" size="9" />
+      <BitField name="RXTHREN" description="Receive threshold enable" start="16" size="1" />
+      <BitField name="RXTHRLEN" description="Receive threshold length" start="17" size="9" />
+      <BitField name="ARPEN" description="Arbiter parking enable" start="27" size="1" />
+    </Register>
+    <Register name="OTG_HS_DIEPEMPMSK" description="OTG_HS device IN endpoint FIFO empty interrupt mask register" start="+0x34" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="INEPTXFEM" description="IN EP Tx FIFO empty interrupt mask bits" start="0" size="16" />
+    </Register>
+    <Register name="OTG_HS_DEACHINT" description="OTG_HS device each endpoint interrupt register" start="+0x38" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="IEP1INT" description="IN endpoint 1interrupt bit" start="1" size="1" />
+      <BitField name="OEP1INT" description="OUT endpoint 1 interrupt bit" start="17" size="1" />
+    </Register>
+    <Register name="OTG_HS_DEACHINTMSK" description="OTG_HS device each endpoint interrupt register mask" start="+0x3C" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="IEP1INTM" description="IN Endpoint 1 interrupt mask bit" start="1" size="1" />
+      <BitField name="OEP1INTM" description="OUT Endpoint 1 interrupt mask bit" start="17" size="1" />
+    </Register>
+    <Register name="OTG_HS_DIEPCTL0" description="OTG device endpoint-0 control register" start="+0x100" size="4" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="USBAEP" description="USB active endpoint" start="15" size="1" access="Read/Write" />
+      <BitField name="EONUM_DPID" description="Even/odd frame" start="16" size="1" access="ReadOnly" />
+      <BitField name="NAKSTS" description="NAK status" start="17" size="1" access="ReadOnly" />
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write" />
+      <BitField name="Stall" description="STALL handshake" start="21" size="1" access="Read/Write" />
+      <BitField name="TXFNUM" description="TxFIFO number" start="22" size="4" access="Read/Write" />
+      <BitField name="CNAK" description="Clear NAK" start="26" size="1" access="WriteOnly" />
+      <BitField name="SNAK" description="Set NAK" start="27" size="1" access="WriteOnly" />
+      <BitField name="SD0PID_SEVNFRM" description="Set DATA0 PID" start="28" size="1" access="WriteOnly" />
+      <BitField name="SODDFRM" description="Set odd frame" start="29" size="1" access="WriteOnly" />
+      <BitField name="EPDIS" description="Endpoint disable" start="30" size="1" access="Read/Write" />
+      <BitField name="EPENA" description="Endpoint enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HS_DIEPCTL1" description="OTG device endpoint-1 control register" start="+0x120" size="4" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="USBAEP" description="USB active endpoint" start="15" size="1" access="Read/Write" />
+      <BitField name="EONUM_DPID" description="Even/odd frame" start="16" size="1" access="ReadOnly" />
+      <BitField name="NAKSTS" description="NAK status" start="17" size="1" access="ReadOnly" />
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write" />
+      <BitField name="Stall" description="STALL handshake" start="21" size="1" access="Read/Write" />
+      <BitField name="TXFNUM" description="TxFIFO number" start="22" size="4" access="Read/Write" />
+      <BitField name="CNAK" description="Clear NAK" start="26" size="1" access="WriteOnly" />
+      <BitField name="SNAK" description="Set NAK" start="27" size="1" access="WriteOnly" />
+      <BitField name="SD0PID_SEVNFRM" description="Set DATA0 PID" start="28" size="1" access="WriteOnly" />
+      <BitField name="SODDFRM" description="Set odd frame" start="29" size="1" access="WriteOnly" />
+      <BitField name="EPDIS" description="Endpoint disable" start="30" size="1" access="Read/Write" />
+      <BitField name="EPENA" description="Endpoint enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HS_DIEPCTL2" description="OTG device endpoint-2 control register" start="+0x140" size="4" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="USBAEP" description="USB active endpoint" start="15" size="1" access="Read/Write" />
+      <BitField name="EONUM_DPID" description="Even/odd frame" start="16" size="1" access="ReadOnly" />
+      <BitField name="NAKSTS" description="NAK status" start="17" size="1" access="ReadOnly" />
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write" />
+      <BitField name="Stall" description="STALL handshake" start="21" size="1" access="Read/Write" />
+      <BitField name="TXFNUM" description="TxFIFO number" start="22" size="4" access="Read/Write" />
+      <BitField name="CNAK" description="Clear NAK" start="26" size="1" access="WriteOnly" />
+      <BitField name="SNAK" description="Set NAK" start="27" size="1" access="WriteOnly" />
+      <BitField name="SD0PID_SEVNFRM" description="Set DATA0 PID" start="28" size="1" access="WriteOnly" />
+      <BitField name="SODDFRM" description="Set odd frame" start="29" size="1" access="WriteOnly" />
+      <BitField name="EPDIS" description="Endpoint disable" start="30" size="1" access="Read/Write" />
+      <BitField name="EPENA" description="Endpoint enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HS_DIEPCTL3" description="OTG device endpoint-3 control register" start="+0x160" size="4" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="USBAEP" description="USB active endpoint" start="15" size="1" access="Read/Write" />
+      <BitField name="EONUM_DPID" description="Even/odd frame" start="16" size="1" access="ReadOnly" />
+      <BitField name="NAKSTS" description="NAK status" start="17" size="1" access="ReadOnly" />
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write" />
+      <BitField name="Stall" description="STALL handshake" start="21" size="1" access="Read/Write" />
+      <BitField name="TXFNUM" description="TxFIFO number" start="22" size="4" access="Read/Write" />
+      <BitField name="CNAK" description="Clear NAK" start="26" size="1" access="WriteOnly" />
+      <BitField name="SNAK" description="Set NAK" start="27" size="1" access="WriteOnly" />
+      <BitField name="SD0PID_SEVNFRM" description="Set DATA0 PID" start="28" size="1" access="WriteOnly" />
+      <BitField name="SODDFRM" description="Set odd frame" start="29" size="1" access="WriteOnly" />
+      <BitField name="EPDIS" description="Endpoint disable" start="30" size="1" access="Read/Write" />
+      <BitField name="EPENA" description="Endpoint enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HS_DIEPCTL4" description="OTG device endpoint-4 control register" start="+0x180" size="4" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="USBAEP" description="USB active endpoint" start="15" size="1" access="Read/Write" />
+      <BitField name="EONUM_DPID" description="Even/odd frame" start="16" size="1" access="ReadOnly" />
+      <BitField name="NAKSTS" description="NAK status" start="17" size="1" access="ReadOnly" />
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write" />
+      <BitField name="Stall" description="STALL handshake" start="21" size="1" access="Read/Write" />
+      <BitField name="TXFNUM" description="TxFIFO number" start="22" size="4" access="Read/Write" />
+      <BitField name="CNAK" description="Clear NAK" start="26" size="1" access="WriteOnly" />
+      <BitField name="SNAK" description="Set NAK" start="27" size="1" access="WriteOnly" />
+      <BitField name="SD0PID_SEVNFRM" description="Set DATA0 PID" start="28" size="1" access="WriteOnly" />
+      <BitField name="SODDFRM" description="Set odd frame" start="29" size="1" access="WriteOnly" />
+      <BitField name="EPDIS" description="Endpoint disable" start="30" size="1" access="Read/Write" />
+      <BitField name="EPENA" description="Endpoint enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HS_DIEPCTL5" description="OTG device endpoint-5 control register" start="+0x1A0" size="4" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="USBAEP" description="USB active endpoint" start="15" size="1" access="Read/Write" />
+      <BitField name="EONUM_DPID" description="Even/odd frame" start="16" size="1" access="ReadOnly" />
+      <BitField name="NAKSTS" description="NAK status" start="17" size="1" access="ReadOnly" />
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write" />
+      <BitField name="Stall" description="STALL handshake" start="21" size="1" access="Read/Write" />
+      <BitField name="TXFNUM" description="TxFIFO number" start="22" size="4" access="Read/Write" />
+      <BitField name="CNAK" description="Clear NAK" start="26" size="1" access="WriteOnly" />
+      <BitField name="SNAK" description="Set NAK" start="27" size="1" access="WriteOnly" />
+      <BitField name="SD0PID_SEVNFRM" description="Set DATA0 PID" start="28" size="1" access="WriteOnly" />
+      <BitField name="SODDFRM" description="Set odd frame" start="29" size="1" access="WriteOnly" />
+      <BitField name="EPDIS" description="Endpoint disable" start="30" size="1" access="Read/Write" />
+      <BitField name="EPENA" description="Endpoint enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HS_DIEPCTL6" description="OTG device endpoint-6 control register" start="+0x1C0" size="4" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="USBAEP" description="USB active endpoint" start="15" size="1" access="Read/Write" />
+      <BitField name="EONUM_DPID" description="Even/odd frame" start="16" size="1" access="ReadOnly" />
+      <BitField name="NAKSTS" description="NAK status" start="17" size="1" access="ReadOnly" />
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write" />
+      <BitField name="Stall" description="STALL handshake" start="21" size="1" access="Read/Write" />
+      <BitField name="TXFNUM" description="TxFIFO number" start="22" size="4" access="Read/Write" />
+      <BitField name="CNAK" description="Clear NAK" start="26" size="1" access="WriteOnly" />
+      <BitField name="SNAK" description="Set NAK" start="27" size="1" access="WriteOnly" />
+      <BitField name="SD0PID_SEVNFRM" description="Set DATA0 PID" start="28" size="1" access="WriteOnly" />
+      <BitField name="SODDFRM" description="Set odd frame" start="29" size="1" access="WriteOnly" />
+      <BitField name="EPDIS" description="Endpoint disable" start="30" size="1" access="Read/Write" />
+      <BitField name="EPENA" description="Endpoint enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HS_DIEPCTL7" description="OTG device endpoint-7 control register" start="+0x1E0" size="4" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="USBAEP" description="USB active endpoint" start="15" size="1" access="Read/Write" />
+      <BitField name="EONUM_DPID" description="Even/odd frame" start="16" size="1" access="ReadOnly" />
+      <BitField name="NAKSTS" description="NAK status" start="17" size="1" access="ReadOnly" />
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write" />
+      <BitField name="Stall" description="STALL handshake" start="21" size="1" access="Read/Write" />
+      <BitField name="TXFNUM" description="TxFIFO number" start="22" size="4" access="Read/Write" />
+      <BitField name="CNAK" description="Clear NAK" start="26" size="1" access="WriteOnly" />
+      <BitField name="SNAK" description="Set NAK" start="27" size="1" access="WriteOnly" />
+      <BitField name="SD0PID_SEVNFRM" description="Set DATA0 PID" start="28" size="1" access="WriteOnly" />
+      <BitField name="SODDFRM" description="Set odd frame" start="29" size="1" access="WriteOnly" />
+      <BitField name="EPDIS" description="Endpoint disable" start="30" size="1" access="Read/Write" />
+      <BitField name="EPENA" description="Endpoint enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HS_DIEPINT0" description="OTG device endpoint-0 interrupt register" start="+0x108" size="4" reset_value="0x00000080" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRC" description="Transfer completed interrupt" start="0" size="1" access="Read/Write" />
+      <BitField name="EPDISD" description="Endpoint disabled interrupt" start="1" size="1" access="Read/Write" />
+      <BitField name="TOC" description="Timeout condition" start="3" size="1" access="Read/Write" />
+      <BitField name="ITTXFE" description="IN token received when TxFIFO is empty" start="4" size="1" access="Read/Write" />
+      <BitField name="INEPNE" description="IN endpoint NAK effective" start="6" size="1" access="Read/Write" />
+      <BitField name="TXFE" description="Transmit FIFO empty" start="7" size="1" access="ReadOnly" />
+      <BitField name="TXFIFOUDRN" description="Transmit Fifo Underrun" start="8" size="1" access="Read/Write" />
+      <BitField name="BNA" description="Buffer not available interrupt" start="9" size="1" access="Read/Write" />
+      <BitField name="PKTDRPSTS" description="Packet dropped status" start="11" size="1" access="Read/Write" />
+      <BitField name="BERR" description="Babble error interrupt" start="12" size="1" access="Read/Write" />
+      <BitField name="NAK" description="NAK interrupt" start="13" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HS_DIEPINT1" description="OTG device endpoint-1 interrupt register" start="+0x128" size="4" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRC" description="Transfer completed interrupt" start="0" size="1" access="Read/Write" />
+      <BitField name="EPDISD" description="Endpoint disabled interrupt" start="1" size="1" access="Read/Write" />
+      <BitField name="TOC" description="Timeout condition" start="3" size="1" access="Read/Write" />
+      <BitField name="ITTXFE" description="IN token received when TxFIFO is empty" start="4" size="1" access="Read/Write" />
+      <BitField name="INEPNE" description="IN endpoint NAK effective" start="6" size="1" access="Read/Write" />
+      <BitField name="TXFE" description="Transmit FIFO empty" start="7" size="1" access="ReadOnly" />
+      <BitField name="TXFIFOUDRN" description="Transmit Fifo Underrun" start="8" size="1" access="Read/Write" />
+      <BitField name="BNA" description="Buffer not available interrupt" start="9" size="1" access="Read/Write" />
+      <BitField name="PKTDRPSTS" description="Packet dropped status" start="11" size="1" access="Read/Write" />
+      <BitField name="BERR" description="Babble error interrupt" start="12" size="1" access="Read/Write" />
+      <BitField name="NAK" description="NAK interrupt" start="13" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HS_DIEPINT2" description="OTG device endpoint-2 interrupt register" start="+0x148" size="4" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRC" description="Transfer completed interrupt" start="0" size="1" access="Read/Write" />
+      <BitField name="EPDISD" description="Endpoint disabled interrupt" start="1" size="1" access="Read/Write" />
+      <BitField name="TOC" description="Timeout condition" start="3" size="1" access="Read/Write" />
+      <BitField name="ITTXFE" description="IN token received when TxFIFO is empty" start="4" size="1" access="Read/Write" />
+      <BitField name="INEPNE" description="IN endpoint NAK effective" start="6" size="1" access="Read/Write" />
+      <BitField name="TXFE" description="Transmit FIFO empty" start="7" size="1" access="ReadOnly" />
+      <BitField name="TXFIFOUDRN" description="Transmit Fifo Underrun" start="8" size="1" access="Read/Write" />
+      <BitField name="BNA" description="Buffer not available interrupt" start="9" size="1" access="Read/Write" />
+      <BitField name="PKTDRPSTS" description="Packet dropped status" start="11" size="1" access="Read/Write" />
+      <BitField name="BERR" description="Babble error interrupt" start="12" size="1" access="Read/Write" />
+      <BitField name="NAK" description="NAK interrupt" start="13" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HS_DIEPINT3" description="OTG device endpoint-3 interrupt register" start="+0x168" size="4" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRC" description="Transfer completed interrupt" start="0" size="1" access="Read/Write" />
+      <BitField name="EPDISD" description="Endpoint disabled interrupt" start="1" size="1" access="Read/Write" />
+      <BitField name="TOC" description="Timeout condition" start="3" size="1" access="Read/Write" />
+      <BitField name="ITTXFE" description="IN token received when TxFIFO is empty" start="4" size="1" access="Read/Write" />
+      <BitField name="INEPNE" description="IN endpoint NAK effective" start="6" size="1" access="Read/Write" />
+      <BitField name="TXFE" description="Transmit FIFO empty" start="7" size="1" access="ReadOnly" />
+      <BitField name="TXFIFOUDRN" description="Transmit Fifo Underrun" start="8" size="1" access="Read/Write" />
+      <BitField name="BNA" description="Buffer not available interrupt" start="9" size="1" access="Read/Write" />
+      <BitField name="PKTDRPSTS" description="Packet dropped status" start="11" size="1" access="Read/Write" />
+      <BitField name="BERR" description="Babble error interrupt" start="12" size="1" access="Read/Write" />
+      <BitField name="NAK" description="NAK interrupt" start="13" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HS_DIEPINT4" description="OTG device endpoint-4 interrupt register" start="+0x188" size="4" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRC" description="Transfer completed interrupt" start="0" size="1" access="Read/Write" />
+      <BitField name="EPDISD" description="Endpoint disabled interrupt" start="1" size="1" access="Read/Write" />
+      <BitField name="TOC" description="Timeout condition" start="3" size="1" access="Read/Write" />
+      <BitField name="ITTXFE" description="IN token received when TxFIFO is empty" start="4" size="1" access="Read/Write" />
+      <BitField name="INEPNE" description="IN endpoint NAK effective" start="6" size="1" access="Read/Write" />
+      <BitField name="TXFE" description="Transmit FIFO empty" start="7" size="1" access="ReadOnly" />
+      <BitField name="TXFIFOUDRN" description="Transmit Fifo Underrun" start="8" size="1" access="Read/Write" />
+      <BitField name="BNA" description="Buffer not available interrupt" start="9" size="1" access="Read/Write" />
+      <BitField name="PKTDRPSTS" description="Packet dropped status" start="11" size="1" access="Read/Write" />
+      <BitField name="BERR" description="Babble error interrupt" start="12" size="1" access="Read/Write" />
+      <BitField name="NAK" description="NAK interrupt" start="13" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HS_DIEPINT5" description="OTG device endpoint-5 interrupt register" start="+0x1A8" size="4" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRC" description="Transfer completed interrupt" start="0" size="1" access="Read/Write" />
+      <BitField name="EPDISD" description="Endpoint disabled interrupt" start="1" size="1" access="Read/Write" />
+      <BitField name="TOC" description="Timeout condition" start="3" size="1" access="Read/Write" />
+      <BitField name="ITTXFE" description="IN token received when TxFIFO is empty" start="4" size="1" access="Read/Write" />
+      <BitField name="INEPNE" description="IN endpoint NAK effective" start="6" size="1" access="Read/Write" />
+      <BitField name="TXFE" description="Transmit FIFO empty" start="7" size="1" access="ReadOnly" />
+      <BitField name="TXFIFOUDRN" description="Transmit Fifo Underrun" start="8" size="1" access="Read/Write" />
+      <BitField name="BNA" description="Buffer not available interrupt" start="9" size="1" access="Read/Write" />
+      <BitField name="PKTDRPSTS" description="Packet dropped status" start="11" size="1" access="Read/Write" />
+      <BitField name="BERR" description="Babble error interrupt" start="12" size="1" access="Read/Write" />
+      <BitField name="NAK" description="NAK interrupt" start="13" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HS_DIEPINT6" description="OTG device endpoint-6 interrupt register" start="+0x1C8" size="4" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRC" description="Transfer completed interrupt" start="0" size="1" access="Read/Write" />
+      <BitField name="EPDISD" description="Endpoint disabled interrupt" start="1" size="1" access="Read/Write" />
+      <BitField name="TOC" description="Timeout condition" start="3" size="1" access="Read/Write" />
+      <BitField name="ITTXFE" description="IN token received when TxFIFO is empty" start="4" size="1" access="Read/Write" />
+      <BitField name="INEPNE" description="IN endpoint NAK effective" start="6" size="1" access="Read/Write" />
+      <BitField name="TXFE" description="Transmit FIFO empty" start="7" size="1" access="ReadOnly" />
+      <BitField name="TXFIFOUDRN" description="Transmit Fifo Underrun" start="8" size="1" access="Read/Write" />
+      <BitField name="BNA" description="Buffer not available interrupt" start="9" size="1" access="Read/Write" />
+      <BitField name="PKTDRPSTS" description="Packet dropped status" start="11" size="1" access="Read/Write" />
+      <BitField name="BERR" description="Babble error interrupt" start="12" size="1" access="Read/Write" />
+      <BitField name="NAK" description="NAK interrupt" start="13" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HS_DIEPINT7" description="OTG device endpoint-7 interrupt register" start="+0x1E8" size="4" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRC" description="Transfer completed interrupt" start="0" size="1" access="Read/Write" />
+      <BitField name="EPDISD" description="Endpoint disabled interrupt" start="1" size="1" access="Read/Write" />
+      <BitField name="TOC" description="Timeout condition" start="3" size="1" access="Read/Write" />
+      <BitField name="ITTXFE" description="IN token received when TxFIFO is empty" start="4" size="1" access="Read/Write" />
+      <BitField name="INEPNE" description="IN endpoint NAK effective" start="6" size="1" access="Read/Write" />
+      <BitField name="TXFE" description="Transmit FIFO empty" start="7" size="1" access="ReadOnly" />
+      <BitField name="TXFIFOUDRN" description="Transmit Fifo Underrun" start="8" size="1" access="Read/Write" />
+      <BitField name="BNA" description="Buffer not available interrupt" start="9" size="1" access="Read/Write" />
+      <BitField name="PKTDRPSTS" description="Packet dropped status" start="11" size="1" access="Read/Write" />
+      <BitField name="BERR" description="Babble error interrupt" start="12" size="1" access="Read/Write" />
+      <BitField name="NAK" description="NAK interrupt" start="13" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HS_DIEPTSIZ0" description="OTG_HS device IN endpoint 0 transfer size register" start="+0x110" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRSIZ" description="Transfer size" start="0" size="7" />
+      <BitField name="PKTCNT" description="Packet count" start="19" size="2" />
+    </Register>
+    <Register name="OTG_HS_DIEPDMA1" description="OTG_HS device endpoint-1 DMA address register" start="+0x114" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAADDR" description="DMA address" start="0" size="32" />
+    </Register>
+    <Register name="OTG_HS_DIEPDMA2" description="OTG_HS device endpoint-2 DMA address register" start="+0x134" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAADDR" description="DMA address" start="0" size="32" />
+    </Register>
+    <Register name="OTG_HS_DIEPDMA3" description="OTG_HS device endpoint-3 DMA address register" start="+0x154" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAADDR" description="DMA address" start="0" size="32" />
+    </Register>
+    <Register name="OTG_HS_DIEPDMA4" description="OTG_HS device endpoint-4 DMA address register" start="+0x174" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAADDR" description="DMA address" start="0" size="32" />
+    </Register>
+    <Register name="OTG_HS_DIEPDMA5" description="OTG_HS device endpoint-5 DMA address register" start="+0x194" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAADDR" description="DMA address" start="0" size="32" />
+    </Register>
+    <Register name="OTG_HS_DTXFSTS0" description="OTG_HS device IN endpoint transmit FIFO status register" start="+0x118" size="4" access="ReadOnly" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="INEPTFSAV" description="IN endpoint TxFIFO space avail" start="0" size="16" />
+    </Register>
+    <Register name="OTG_HS_DTXFSTS1" description="OTG_HS device IN endpoint transmit FIFO status register" start="+0x138" size="4" access="ReadOnly" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="INEPTFSAV" description="IN endpoint TxFIFO space avail" start="0" size="16" />
+    </Register>
+    <Register name="OTG_HS_DTXFSTS2" description="OTG_HS device IN endpoint transmit FIFO status register" start="+0x158" size="4" access="ReadOnly" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="INEPTFSAV" description="IN endpoint TxFIFO space avail" start="0" size="16" />
+    </Register>
+    <Register name="OTG_HS_DTXFSTS3" description="OTG_HS device IN endpoint transmit FIFO status register" start="+0x178" size="4" access="ReadOnly" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="INEPTFSAV" description="IN endpoint TxFIFO space avail" start="0" size="16" />
+    </Register>
+    <Register name="OTG_HS_DTXFSTS4" description="OTG_HS device IN endpoint transmit FIFO status register" start="+0x198" size="4" access="ReadOnly" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="INEPTFSAV" description="IN endpoint TxFIFO space avail" start="0" size="16" />
+    </Register>
+    <Register name="OTG_HS_DTXFSTS5" description="OTG_HS device IN endpoint transmit FIFO status register" start="+0x1B8" size="4" access="ReadOnly" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="INEPTFSAV" description="IN endpoint TxFIFO space avail" start="0" size="16" />
+    </Register>
+    <Register name="OTG_HS_DIEPTSIZ1" description="OTG_HS device endpoint transfer size register" start="+0x130" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRSIZ" description="Transfer size" start="0" size="19" />
+      <BitField name="PKTCNT" description="Packet count" start="19" size="10" />
+      <BitField name="MCNT" description="Multi count" start="29" size="2" />
+    </Register>
+    <Register name="OTG_HS_DIEPTSIZ2" description="OTG_HS device endpoint transfer size register" start="+0x150" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRSIZ" description="Transfer size" start="0" size="19" />
+      <BitField name="PKTCNT" description="Packet count" start="19" size="10" />
+      <BitField name="MCNT" description="Multi count" start="29" size="2" />
+    </Register>
+    <Register name="OTG_HS_DIEPTSIZ3" description="OTG_HS device endpoint transfer size register" start="+0x170" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRSIZ" description="Transfer size" start="0" size="19" />
+      <BitField name="PKTCNT" description="Packet count" start="19" size="10" />
+      <BitField name="MCNT" description="Multi count" start="29" size="2" />
+    </Register>
+    <Register name="OTG_HS_DIEPTSIZ4" description="OTG_HS device endpoint transfer size register" start="+0x190" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRSIZ" description="Transfer size" start="0" size="19" />
+      <BitField name="PKTCNT" description="Packet count" start="19" size="10" />
+      <BitField name="MCNT" description="Multi count" start="29" size="2" />
+    </Register>
+    <Register name="OTG_HS_DIEPTSIZ5" description="OTG_HS device endpoint transfer size register" start="+0x1B0" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRSIZ" description="Transfer size" start="0" size="19" />
+      <BitField name="PKTCNT" description="Packet count" start="19" size="10" />
+      <BitField name="MCNT" description="Multi count" start="29" size="2" />
+    </Register>
+    <Register name="OTG_HS_DOEPCTL0" description="OTG_HS device control OUT endpoint 0 control register" start="+0x300" size="4" reset_value="0x00008000" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="2" access="ReadOnly" />
+      <BitField name="USBAEP" description="USB active endpoint" start="15" size="1" access="ReadOnly" />
+      <BitField name="NAKSTS" description="NAK status" start="17" size="1" access="ReadOnly" />
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="ReadOnly" />
+      <BitField name="SNPM" description="Snoop mode" start="20" size="1" access="Read/Write" />
+      <BitField name="Stall" description="STALL handshake" start="21" size="1" access="Read/Write" />
+      <BitField name="CNAK" description="Clear NAK" start="26" size="1" access="WriteOnly" />
+      <BitField name="SNAK" description="Set NAK" start="27" size="1" access="WriteOnly" />
+      <BitField name="EPDIS" description="Endpoint disable" start="30" size="1" access="ReadOnly" />
+      <BitField name="EPENA" description="Endpoint enable" start="31" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="OTG_HS_DOEPCTL1" description="OTG device endpoint-1 control register" start="+0x320" size="4" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="USBAEP" description="USB active endpoint" start="15" size="1" access="Read/Write" />
+      <BitField name="EONUM_DPID" description="Even odd frame/Endpoint data PID" start="16" size="1" access="ReadOnly" />
+      <BitField name="NAKSTS" description="NAK status" start="17" size="1" access="ReadOnly" />
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write" />
+      <BitField name="SNPM" description="Snoop mode" start="20" size="1" access="Read/Write" />
+      <BitField name="Stall" description="STALL handshake" start="21" size="1" access="Read/Write" />
+      <BitField name="CNAK" description="Clear NAK" start="26" size="1" access="WriteOnly" />
+      <BitField name="SNAK" description="Set NAK" start="27" size="1" access="WriteOnly" />
+      <BitField name="SD0PID_SEVNFRM" description="Set DATA0 PID/Set even frame" start="28" size="1" access="WriteOnly" />
+      <BitField name="SODDFRM" description="Set odd frame" start="29" size="1" access="WriteOnly" />
+      <BitField name="EPDIS" description="Endpoint disable" start="30" size="1" access="Read/Write" />
+      <BitField name="EPENA" description="Endpoint enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HS_DOEPCTL2" description="OTG device endpoint-2 control register" start="+0x340" size="4" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="USBAEP" description="USB active endpoint" start="15" size="1" access="Read/Write" />
+      <BitField name="EONUM_DPID" description="Even odd frame/Endpoint data PID" start="16" size="1" access="ReadOnly" />
+      <BitField name="NAKSTS" description="NAK status" start="17" size="1" access="ReadOnly" />
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write" />
+      <BitField name="SNPM" description="Snoop mode" start="20" size="1" access="Read/Write" />
+      <BitField name="Stall" description="STALL handshake" start="21" size="1" access="Read/Write" />
+      <BitField name="CNAK" description="Clear NAK" start="26" size="1" access="WriteOnly" />
+      <BitField name="SNAK" description="Set NAK" start="27" size="1" access="WriteOnly" />
+      <BitField name="SD0PID_SEVNFRM" description="Set DATA0 PID/Set even frame" start="28" size="1" access="WriteOnly" />
+      <BitField name="SODDFRM" description="Set odd frame" start="29" size="1" access="WriteOnly" />
+      <BitField name="EPDIS" description="Endpoint disable" start="30" size="1" access="Read/Write" />
+      <BitField name="EPENA" description="Endpoint enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HS_DOEPCTL3" description="OTG device endpoint-3 control register" start="+0x360" size="4" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="USBAEP" description="USB active endpoint" start="15" size="1" access="Read/Write" />
+      <BitField name="EONUM_DPID" description="Even odd frame/Endpoint data PID" start="16" size="1" access="ReadOnly" />
+      <BitField name="NAKSTS" description="NAK status" start="17" size="1" access="ReadOnly" />
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write" />
+      <BitField name="SNPM" description="Snoop mode" start="20" size="1" access="Read/Write" />
+      <BitField name="Stall" description="STALL handshake" start="21" size="1" access="Read/Write" />
+      <BitField name="CNAK" description="Clear NAK" start="26" size="1" access="WriteOnly" />
+      <BitField name="SNAK" description="Set NAK" start="27" size="1" access="WriteOnly" />
+      <BitField name="SD0PID_SEVNFRM" description="Set DATA0 PID/Set even frame" start="28" size="1" access="WriteOnly" />
+      <BitField name="SODDFRM" description="Set odd frame" start="29" size="1" access="WriteOnly" />
+      <BitField name="EPDIS" description="Endpoint disable" start="30" size="1" access="Read/Write" />
+      <BitField name="EPENA" description="Endpoint enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HS_DOEPINT0" description="OTG_HS device endpoint-0 interrupt register" start="+0x308" size="4" access="Read/Write" reset_value="0x00000080" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRC" description="Transfer completed interrupt" start="0" size="1" />
+      <BitField name="EPDISD" description="Endpoint disabled interrupt" start="1" size="1" />
+      <BitField name="STUP" description="SETUP phase done" start="3" size="1" />
+      <BitField name="OTEPDIS" description="OUT token received when endpoint disabled" start="4" size="1" />
+      <BitField name="B2BSTUP" description="Back-to-back SETUP packets received" start="6" size="1" />
+      <BitField name="NYET" description="NYET interrupt" start="14" size="1" />
+    </Register>
+    <Register name="OTG_HS_DOEPINT1" description="OTG_HS device endpoint-1 interrupt register" start="+0x328" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRC" description="Transfer completed interrupt" start="0" size="1" />
+      <BitField name="EPDISD" description="Endpoint disabled interrupt" start="1" size="1" />
+      <BitField name="STUP" description="SETUP phase done" start="3" size="1" />
+      <BitField name="OTEPDIS" description="OUT token received when endpoint disabled" start="4" size="1" />
+      <BitField name="B2BSTUP" description="Back-to-back SETUP packets received" start="6" size="1" />
+      <BitField name="NYET" description="NYET interrupt" start="14" size="1" />
+    </Register>
+    <Register name="OTG_HS_DOEPINT2" description="OTG_HS device endpoint-2 interrupt register" start="+0x348" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRC" description="Transfer completed interrupt" start="0" size="1" />
+      <BitField name="EPDISD" description="Endpoint disabled interrupt" start="1" size="1" />
+      <BitField name="STUP" description="SETUP phase done" start="3" size="1" />
+      <BitField name="OTEPDIS" description="OUT token received when endpoint disabled" start="4" size="1" />
+      <BitField name="B2BSTUP" description="Back-to-back SETUP packets received" start="6" size="1" />
+      <BitField name="NYET" description="NYET interrupt" start="14" size="1" />
+    </Register>
+    <Register name="OTG_HS_DOEPINT3" description="OTG_HS device endpoint-3 interrupt register" start="+0x368" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRC" description="Transfer completed interrupt" start="0" size="1" />
+      <BitField name="EPDISD" description="Endpoint disabled interrupt" start="1" size="1" />
+      <BitField name="STUP" description="SETUP phase done" start="3" size="1" />
+      <BitField name="OTEPDIS" description="OUT token received when endpoint disabled" start="4" size="1" />
+      <BitField name="B2BSTUP" description="Back-to-back SETUP packets received" start="6" size="1" />
+      <BitField name="NYET" description="NYET interrupt" start="14" size="1" />
+    </Register>
+    <Register name="OTG_HS_DOEPINT4" description="OTG_HS device endpoint-4 interrupt register" start="+0x388" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRC" description="Transfer completed interrupt" start="0" size="1" />
+      <BitField name="EPDISD" description="Endpoint disabled interrupt" start="1" size="1" />
+      <BitField name="STUP" description="SETUP phase done" start="3" size="1" />
+      <BitField name="OTEPDIS" description="OUT token received when endpoint disabled" start="4" size="1" />
+      <BitField name="B2BSTUP" description="Back-to-back SETUP packets received" start="6" size="1" />
+      <BitField name="NYET" description="NYET interrupt" start="14" size="1" />
+    </Register>
+    <Register name="OTG_HS_DOEPINT5" description="OTG_HS device endpoint-5 interrupt register" start="+0x3A8" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRC" description="Transfer completed interrupt" start="0" size="1" />
+      <BitField name="EPDISD" description="Endpoint disabled interrupt" start="1" size="1" />
+      <BitField name="STUP" description="SETUP phase done" start="3" size="1" />
+      <BitField name="OTEPDIS" description="OUT token received when endpoint disabled" start="4" size="1" />
+      <BitField name="B2BSTUP" description="Back-to-back SETUP packets received" start="6" size="1" />
+      <BitField name="NYET" description="NYET interrupt" start="14" size="1" />
+    </Register>
+    <Register name="OTG_HS_DOEPINT6" description="OTG_HS device endpoint-6 interrupt register" start="+0x3C8" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRC" description="Transfer completed interrupt" start="0" size="1" />
+      <BitField name="EPDISD" description="Endpoint disabled interrupt" start="1" size="1" />
+      <BitField name="STUP" description="SETUP phase done" start="3" size="1" />
+      <BitField name="OTEPDIS" description="OUT token received when endpoint disabled" start="4" size="1" />
+      <BitField name="B2BSTUP" description="Back-to-back SETUP packets received" start="6" size="1" />
+      <BitField name="NYET" description="NYET interrupt" start="14" size="1" />
+    </Register>
+    <Register name="OTG_HS_DOEPINT7" description="OTG_HS device endpoint-7 interrupt register" start="+0x3E8" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRC" description="Transfer completed interrupt" start="0" size="1" />
+      <BitField name="EPDISD" description="Endpoint disabled interrupt" start="1" size="1" />
+      <BitField name="STUP" description="SETUP phase done" start="3" size="1" />
+      <BitField name="OTEPDIS" description="OUT token received when endpoint disabled" start="4" size="1" />
+      <BitField name="B2BSTUP" description="Back-to-back SETUP packets received" start="6" size="1" />
+      <BitField name="NYET" description="NYET interrupt" start="14" size="1" />
+    </Register>
+    <Register name="OTG_HS_DOEPTSIZ0" description="OTG_HS device endpoint-0 transfer size register" start="+0x310" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRSIZ" description="Transfer size" start="0" size="7" />
+      <BitField name="PKTCNT" description="Packet count" start="19" size="1" />
+      <BitField name="STUPCNT" description="SETUP packet count" start="29" size="2" />
+    </Register>
+    <Register name="OTG_HS_DOEPTSIZ1" description="OTG_HS device endpoint-1 transfer size register" start="+0x330" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRSIZ" description="Transfer size" start="0" size="19" />
+      <BitField name="PKTCNT" description="Packet count" start="19" size="10" />
+      <BitField name="RXDPID_STUPCNT" description="Received data PID/SETUP packet count" start="29" size="2" />
+    </Register>
+    <Register name="OTG_HS_DOEPTSIZ2" description="OTG_HS device endpoint-2 transfer size register" start="+0x350" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRSIZ" description="Transfer size" start="0" size="19" />
+      <BitField name="PKTCNT" description="Packet count" start="19" size="10" />
+      <BitField name="RXDPID_STUPCNT" description="Received data PID/SETUP packet count" start="29" size="2" />
+    </Register>
+    <Register name="OTG_HS_DOEPTSIZ3" description="OTG_HS device endpoint-3 transfer size register" start="+0x370" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRSIZ" description="Transfer size" start="0" size="19" />
+      <BitField name="PKTCNT" description="Packet count" start="19" size="10" />
+      <BitField name="RXDPID_STUPCNT" description="Received data PID/SETUP packet count" start="29" size="2" />
+    </Register>
+    <Register name="OTG_HS_DOEPTSIZ4" description="OTG_HS device endpoint-4 transfer size register" start="+0x390" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRSIZ" description="Transfer size" start="0" size="19" />
+      <BitField name="PKTCNT" description="Packet count" start="19" size="10" />
+      <BitField name="RXDPID_STUPCNT" description="Received data PID/SETUP packet count" start="29" size="2" />
+    </Register>
+    <Register name="OTG_HS_DIEPTSIZ6" description="OTG_HS device endpoint transfer size register" start="+0x1A0" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRSIZ" description="Transfer size" start="0" size="19" />
+      <BitField name="PKTCNT" description="Packet count" start="19" size="10" />
+      <BitField name="MCNT" description="Multi count" start="29" size="2" />
+    </Register>
+    <Register name="OTG_HS_DTXFSTS6" description="OTG_HS device IN endpoint transmit FIFO status register" start="+0x1A4" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="INEPTFSAV" description="IN endpoint TxFIFO space avail" start="0" size="16" />
+    </Register>
+    <Register name="OTG_HS_DIEPTSIZ7" description="OTG_HS device endpoint transfer size register" start="+0x1A8" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRSIZ" description="Transfer size" start="0" size="19" />
+      <BitField name="PKTCNT" description="Packet count" start="19" size="10" />
+      <BitField name="MCNT" description="Multi count" start="29" size="2" />
+    </Register>
+    <Register name="OTG_HS_DTXFSTS7" description="OTG_HS device IN endpoint transmit FIFO status register" start="+0x1AC" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="INEPTFSAV" description="IN endpoint TxFIFO space avail" start="0" size="16" />
+    </Register>
+    <Register name="OTG_HS_DOEPCTL4" description="OTG device endpoint-4 control register" start="+0x380" size="4" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="USBAEP" description="USB active endpoint" start="15" size="1" access="Read/Write" />
+      <BitField name="EONUM_DPID" description="Even odd frame/Endpoint data PID" start="16" size="1" access="ReadOnly" />
+      <BitField name="NAKSTS" description="NAK status" start="17" size="1" access="ReadOnly" />
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write" />
+      <BitField name="SNPM" description="Snoop mode" start="20" size="1" access="Read/Write" />
+      <BitField name="Stall" description="STALL handshake" start="21" size="1" access="Read/Write" />
+      <BitField name="CNAK" description="Clear NAK" start="26" size="1" access="WriteOnly" />
+      <BitField name="SNAK" description="Set NAK" start="27" size="1" access="WriteOnly" />
+      <BitField name="SD0PID_SEVNFRM" description="Set DATA0 PID/Set even frame" start="28" size="1" access="WriteOnly" />
+      <BitField name="SODDFRM" description="Set odd frame" start="29" size="1" access="WriteOnly" />
+      <BitField name="EPDIS" description="Endpoint disable" start="30" size="1" access="Read/Write" />
+      <BitField name="EPENA" description="Endpoint enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HS_DOEPCTL5" description="OTG device endpoint-5 control register" start="+0x3A0" size="4" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="USBAEP" description="USB active endpoint" start="15" size="1" access="Read/Write" />
+      <BitField name="EONUM_DPID" description="Even odd frame/Endpoint data PID" start="16" size="1" access="ReadOnly" />
+      <BitField name="NAKSTS" description="NAK status" start="17" size="1" access="ReadOnly" />
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write" />
+      <BitField name="SNPM" description="Snoop mode" start="20" size="1" access="Read/Write" />
+      <BitField name="Stall" description="STALL handshake" start="21" size="1" access="Read/Write" />
+      <BitField name="CNAK" description="Clear NAK" start="26" size="1" access="WriteOnly" />
+      <BitField name="SNAK" description="Set NAK" start="27" size="1" access="WriteOnly" />
+      <BitField name="SD0PID_SEVNFRM" description="Set DATA0 PID/Set even frame" start="28" size="1" access="WriteOnly" />
+      <BitField name="SODDFRM" description="Set odd frame" start="29" size="1" access="WriteOnly" />
+      <BitField name="EPDIS" description="Endpoint disable" start="30" size="1" access="Read/Write" />
+      <BitField name="EPENA" description="Endpoint enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HS_DOEPCTL6" description="OTG device endpoint-6 control register" start="+0x3C0" size="4" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="USBAEP" description="USB active endpoint" start="15" size="1" access="Read/Write" />
+      <BitField name="EONUM_DPID" description="Even odd frame/Endpoint data PID" start="16" size="1" access="ReadOnly" />
+      <BitField name="NAKSTS" description="NAK status" start="17" size="1" access="ReadOnly" />
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write" />
+      <BitField name="SNPM" description="Snoop mode" start="20" size="1" access="Read/Write" />
+      <BitField name="Stall" description="STALL handshake" start="21" size="1" access="Read/Write" />
+      <BitField name="CNAK" description="Clear NAK" start="26" size="1" access="WriteOnly" />
+      <BitField name="SNAK" description="Set NAK" start="27" size="1" access="WriteOnly" />
+      <BitField name="SD0PID_SEVNFRM" description="Set DATA0 PID/Set even frame" start="28" size="1" access="WriteOnly" />
+      <BitField name="SODDFRM" description="Set odd frame" start="29" size="1" access="WriteOnly" />
+      <BitField name="EPDIS" description="Endpoint disable" start="30" size="1" access="Read/Write" />
+      <BitField name="EPENA" description="Endpoint enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HS_DOEPCTL7" description="OTG device endpoint-7 control register" start="+0x3E0" size="4" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" access="Read/Write" />
+      <BitField name="USBAEP" description="USB active endpoint" start="15" size="1" access="Read/Write" />
+      <BitField name="EONUM_DPID" description="Even odd frame/Endpoint data PID" start="16" size="1" access="ReadOnly" />
+      <BitField name="NAKSTS" description="NAK status" start="17" size="1" access="ReadOnly" />
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" access="Read/Write" />
+      <BitField name="SNPM" description="Snoop mode" start="20" size="1" access="Read/Write" />
+      <BitField name="Stall" description="STALL handshake" start="21" size="1" access="Read/Write" />
+      <BitField name="CNAK" description="Clear NAK" start="26" size="1" access="WriteOnly" />
+      <BitField name="SNAK" description="Set NAK" start="27" size="1" access="WriteOnly" />
+      <BitField name="SD0PID_SEVNFRM" description="Set DATA0 PID/Set even frame" start="28" size="1" access="WriteOnly" />
+      <BitField name="SODDFRM" description="Set odd frame" start="29" size="1" access="WriteOnly" />
+      <BitField name="EPDIS" description="Endpoint disable" start="30" size="1" access="Read/Write" />
+      <BitField name="EPENA" description="Endpoint enable" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HS_DOEPTSIZ5" description="OTG_HS device endpoint-5 transfer size register" start="+0x3B0" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRSIZ" description="Transfer size" start="0" size="19" />
+      <BitField name="PKTCNT" description="Packet count" start="19" size="10" />
+      <BitField name="RXDPID_STUPCNT" description="Received data PID/SETUP packet count" start="29" size="2" />
+    </Register>
+    <Register name="OTG_HS_DOEPTSIZ6" description="OTG_HS device endpoint-6 transfer size register" start="+0x3D0" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRSIZ" description="Transfer size" start="0" size="19" />
+      <BitField name="PKTCNT" description="Packet count" start="19" size="10" />
+      <BitField name="RXDPID_STUPCNT" description="Received data PID/SETUP packet count" start="29" size="2" />
+    </Register>
+    <Register name="OTG_HS_DOEPTSIZ7" description="OTG_HS device endpoint-7 transfer size register" start="+0x3F0" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRSIZ" description="Transfer size" start="0" size="19" />
+      <BitField name="PKTCNT" description="Packet count" start="19" size="10" />
+      <BitField name="RXDPID_STUPCNT" description="Received data PID/SETUP packet count" start="29" size="2" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="OTG1_HS_GLOBAL" description="USB 1 on the go high speed" start="0x40040000">
+    <Register name="OTG_HS_GOTGCTL" description="OTG_HS control and status register" start="+0x0" size="4" reset_value="0x00000800" reset_mask="0xFFFFFFFF">
+      <BitField name="SRQSCS" description="Session request success" start="0" size="1" access="ReadOnly" />
+      <BitField name="SRQ" description="Session request" start="1" size="1" access="Read/Write" />
+      <BitField name="HNGSCS" description="Host negotiation success" start="8" size="1" access="ReadOnly" />
+      <BitField name="HNPRQ" description="HNP request" start="9" size="1" access="Read/Write" />
+      <BitField name="HSHNPEN" description="Host set HNP enable" start="10" size="1" access="Read/Write" />
+      <BitField name="DHNPEN" description="Device HNP enabled" start="11" size="1" access="Read/Write" />
+      <BitField name="CIDSTS" description="Connector ID status" start="16" size="1" access="ReadOnly" />
+      <BitField name="DBCT" description="Long/short debounce time" start="17" size="1" access="ReadOnly" />
+      <BitField name="ASVLD" description="A-session valid" start="18" size="1" access="ReadOnly" />
+      <BitField name="BSVLD" description="B-session valid" start="19" size="1" access="ReadOnly" />
+      <BitField name="EHEN" description="Embedded host enable" start="12" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HS_GOTGINT" description="OTG_HS interrupt register" start="+0x4" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="SEDET" description="Session end detected" start="2" size="1" />
+      <BitField name="SRSSCHG" description="Session request success status change" start="8" size="1" />
+      <BitField name="HNSSCHG" description="Host negotiation success status change" start="9" size="1" />
+      <BitField name="HNGDET" description="Host negotiation detected" start="17" size="1" />
+      <BitField name="ADTOCHG" description="A-device timeout change" start="18" size="1" />
+      <BitField name="DBCDNE" description="Debounce done" start="19" size="1" />
+      <BitField name="IDCHNG" description="ID input pin changed" start="20" size="1" />
+    </Register>
+    <Register name="OTG_HS_GAHBCFG" description="OTG_HS AHB configuration register" start="+0x8" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="GINT" description="Global interrupt mask" start="0" size="1" />
+      <BitField name="HBSTLEN" description="Burst length/type" start="1" size="4" />
+      <BitField name="DMAEN" description="DMA enable" start="5" size="1" />
+      <BitField name="TXFELVL" description="TxFIFO empty level" start="7" size="1" />
+      <BitField name="PTXFELVL" description="Periodic TxFIFO empty level" start="8" size="1" />
+    </Register>
+    <Register name="OTG_HS_GUSBCFG" description="OTG_HS USB configuration register" start="+0xC" size="4" reset_value="0x00000A00" reset_mask="0xFFFFFFFF">
+      <BitField name="TOCAL" description="FS timeout calibration" start="0" size="3" access="Read/Write" />
+      <BitField name="PHYSEL" description="USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select" start="6" size="1" access="WriteOnly" />
+      <BitField name="SRPCAP" description="SRP-capable" start="8" size="1" access="Read/Write" />
+      <BitField name="HNPCAP" description="HNP-capable" start="9" size="1" access="Read/Write" />
+      <BitField name="TRDT" description="USB turnaround time" start="10" size="4" access="Read/Write" />
+      <BitField name="PHYLPCS" description="PHY Low-power clock select" start="15" size="1" access="Read/Write" />
+      <BitField name="ULPIFSLS" description="ULPI FS/LS select" start="17" size="1" access="Read/Write" />
+      <BitField name="ULPIAR" description="ULPI Auto-resume" start="18" size="1" access="Read/Write" />
+      <BitField name="ULPICSM" description="ULPI Clock SuspendM" start="19" size="1" access="Read/Write" />
+      <BitField name="ULPIEVBUSD" description="ULPI External VBUS Drive" start="20" size="1" access="Read/Write" />
+      <BitField name="ULPIEVBUSI" description="ULPI external VBUS indicator" start="21" size="1" access="Read/Write" />
+      <BitField name="TSDPS" description="TermSel DLine pulsing selection" start="22" size="1" access="Read/Write" />
+      <BitField name="PCCI" description="Indicator complement" start="23" size="1" access="Read/Write" />
+      <BitField name="PTCI" description="Indicator pass through" start="24" size="1" access="Read/Write" />
+      <BitField name="ULPIIPD" description="ULPI interface protect disable" start="25" size="1" access="Read/Write" />
+      <BitField name="FHMOD" description="Forced host mode" start="29" size="1" access="Read/Write" />
+      <BitField name="FDMOD" description="Forced peripheral mode" start="30" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HS_GRSTCTL" description="OTG_HS reset register" start="+0x10" size="4" reset_value="0x20000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CSRST" description="Core soft reset" start="0" size="1" access="Read/Write" />
+      <BitField name="HSRST" description="HCLK soft reset" start="1" size="1" access="Read/Write" />
+      <BitField name="FCRST" description="Host frame counter reset" start="2" size="1" access="Read/Write" />
+      <BitField name="RXFFLSH" description="RxFIFO flush" start="4" size="1" access="Read/Write" />
+      <BitField name="TXFFLSH" description="TxFIFO flush" start="5" size="1" access="Read/Write" />
+      <BitField name="TXFNUM" description="TxFIFO number" start="6" size="5" access="Read/Write" />
+      <BitField name="AHBIDL" description="AHB master idle" start="31" size="1" access="ReadOnly" />
+      <BitField name="DMAREQ" description="DMA request signal enabled for USB OTG HS" start="30" size="1" access="ReadOnly" />
+    </Register>
+    <Register name="OTG_HS_GINTSTS" description="OTG_HS core interrupt register" start="+0x14" size="4" reset_value="0x04000020" reset_mask="0xFFFFFFFF">
+      <BitField name="CMOD" description="Current mode of operation" start="0" size="1" access="ReadOnly" />
+      <BitField name="MMIS" description="Mode mismatch interrupt" start="1" size="1" access="Read/Write" />
+      <BitField name="OTGINT" description="OTG interrupt" start="2" size="1" access="ReadOnly" />
+      <BitField name="SOF" description="Start of frame" start="3" size="1" access="Read/Write" />
+      <BitField name="RXFLVL" description="RxFIFO nonempty" start="4" size="1" access="ReadOnly" />
+      <BitField name="NPTXFE" description="Nonperiodic TxFIFO empty" start="5" size="1" access="ReadOnly" />
+      <BitField name="GINAKEFF" description="Global IN nonperiodic NAK effective" start="6" size="1" access="ReadOnly" />
+      <BitField name="BOUTNAKEFF" description="Global OUT NAK effective" start="7" size="1" access="ReadOnly" />
+      <BitField name="ESUSP" description="Early suspend" start="10" size="1" access="Read/Write" />
+      <BitField name="USBSUSP" description="USB suspend" start="11" size="1" access="Read/Write" />
+      <BitField name="USBRST" description="USB reset" start="12" size="1" access="Read/Write" />
+      <BitField name="ENUMDNE" description="Enumeration done" start="13" size="1" access="Read/Write" />
+      <BitField name="ISOODRP" description="Isochronous OUT packet dropped interrupt" start="14" size="1" access="Read/Write" />
+      <BitField name="EOPF" description="End of periodic frame interrupt" start="15" size="1" access="Read/Write" />
+      <BitField name="IEPINT" description="IN endpoint interrupt" start="18" size="1" access="ReadOnly" />
+      <BitField name="OEPINT" description="OUT endpoint interrupt" start="19" size="1" access="ReadOnly" />
+      <BitField name="IISOIXFR" description="Incomplete isochronous IN transfer" start="20" size="1" access="Read/Write" />
+      <BitField name="PXFR_INCOMPISOOUT" description="Incomplete periodic transfer" start="21" size="1" access="Read/Write" />
+      <BitField name="DATAFSUSP" description="Data fetch suspended" start="22" size="1" access="Read/Write" />
+      <BitField name="HPRTINT" description="Host port interrupt" start="24" size="1" access="ReadOnly" />
+      <BitField name="HCINT" description="Host channels interrupt" start="25" size="1" access="ReadOnly" />
+      <BitField name="PTXFE" description="Periodic TxFIFO empty" start="26" size="1" access="ReadOnly" />
+      <BitField name="CIDSCHG" description="Connector ID status change" start="28" size="1" access="Read/Write" />
+      <BitField name="DISCINT" description="Disconnect detected interrupt" start="29" size="1" access="Read/Write" />
+      <BitField name="SRQINT" description="Session request/new session detected interrupt" start="30" size="1" access="Read/Write" />
+      <BitField name="WKUINT" description="Resume/remote wakeup detected interrupt" start="31" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HS_GINTMSK" description="OTG_HS interrupt mask register" start="+0x18" size="4" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="MMISM" description="Mode mismatch interrupt mask" start="1" size="1" access="Read/Write" />
+      <BitField name="OTGINT" description="OTG interrupt mask" start="2" size="1" access="Read/Write" />
+      <BitField name="SOFM" description="Start of frame mask" start="3" size="1" access="Read/Write" />
+      <BitField name="RXFLVLM" description="Receive FIFO nonempty mask" start="4" size="1" access="Read/Write" />
+      <BitField name="NPTXFEM" description="Nonperiodic TxFIFO empty mask" start="5" size="1" access="Read/Write" />
+      <BitField name="GINAKEFFM" description="Global nonperiodic IN NAK effective mask" start="6" size="1" access="Read/Write" />
+      <BitField name="GONAKEFFM" description="Global OUT NAK effective mask" start="7" size="1" access="Read/Write" />
+      <BitField name="ESUSPM" description="Early suspend mask" start="10" size="1" access="Read/Write" />
+      <BitField name="USBSUSPM" description="USB suspend mask" start="11" size="1" access="Read/Write" />
+      <BitField name="USBRST" description="USB reset mask" start="12" size="1" access="Read/Write" />
+      <BitField name="ENUMDNEM" description="Enumeration done mask" start="13" size="1" access="Read/Write" />
+      <BitField name="ISOODRPM" description="Isochronous OUT packet dropped interrupt mask" start="14" size="1" access="Read/Write" />
+      <BitField name="EOPFM" description="End of periodic frame interrupt mask" start="15" size="1" access="Read/Write" />
+      <BitField name="IEPINT" description="IN endpoints interrupt mask" start="18" size="1" access="Read/Write" />
+      <BitField name="OEPINT" description="OUT endpoints interrupt mask" start="19" size="1" access="Read/Write" />
+      <BitField name="IISOIXFRM" description="Incomplete isochronous IN transfer mask" start="20" size="1" access="Read/Write" />
+      <BitField name="PXFRM_IISOOXFRM" description="Incomplete periodic transfer mask" start="21" size="1" access="Read/Write" />
+      <BitField name="FSUSPM" description="Data fetch suspended mask" start="22" size="1" access="Read/Write" />
+      <BitField name="PRTIM" description="Host port interrupt mask" start="24" size="1" access="ReadOnly" />
+      <BitField name="HCIM" description="Host channels interrupt mask" start="25" size="1" access="Read/Write" />
+      <BitField name="PTXFEM" description="Periodic TxFIFO empty mask" start="26" size="1" access="Read/Write" />
+      <BitField name="CIDSCHGM" description="Connector ID status change mask" start="28" size="1" access="Read/Write" />
+      <BitField name="DISCINT" description="Disconnect detected interrupt mask" start="29" size="1" access="Read/Write" />
+      <BitField name="SRQIM" description="Session request/new session detected interrupt mask" start="30" size="1" access="Read/Write" />
+      <BitField name="WUIM" description="Resume/remote wakeup detected interrupt mask" start="31" size="1" access="Read/Write" />
+      <BitField name="RSTDE" description="Reset detected interrupt mask" start="23" size="1" access="Read/Write" />
+      <BitField name="LPMINTM" description="LPM interrupt mask" start="27" size="1" access="Read/Write" />
+    </Register>
+    <Register name="OTG_HS_GRXSTSR_Host" description="OTG_HS Receive status debug read register (host mode)" start="+0x1C" size="4" access="ReadOnly" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="CHNUM" description="Channel number" start="0" size="4" />
+      <BitField name="BCNT" description="Byte count" start="4" size="11" />
+      <BitField name="DPID" description="Data PID" start="15" size="2" />
+      <BitField name="PKTSTS" description="Packet status" start="17" size="4" />
+    </Register>
+    <Register name="OTG_HS_GRXSTSP_Host" description="OTG_HS status read and pop register (host mode)" start="+0x20" size="4" access="ReadOnly" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="CHNUM" description="Channel number" start="0" size="4" />
+      <BitField name="BCNT" description="Byte count" start="4" size="11" />
+      <BitField name="DPID" description="Data PID" start="15" size="2" />
+      <BitField name="PKTSTS" description="Packet status" start="17" size="4" />
+    </Register>
+    <Register name="OTG_HS_GRXFSIZ" description="OTG_HS Receive FIFO size register" start="+0x24" size="4" access="Read/Write" reset_value="0x00000200" reset_mask="0xFFFFFFFF">
+      <BitField name="RXFD" description="RxFIFO depth" start="0" size="16" />
+    </Register>
+    <Register name="OTG_HS_HNPTXFSIZ_Host" description="OTG_HS nonperiodic transmit FIFO size register (host mode)" start="+0x28" size="4" access="Read/Write" reset_value="0x00000200" reset_mask="0xFFFFFFFF">
+      <BitField name="NPTXFSA" description="Nonperiodic transmit RAM start address" start="0" size="16" />
+      <BitField name="NPTXFD" description="Nonperiodic TxFIFO depth" start="16" size="16" />
+    </Register>
+    <Register name="OTG_HS_DIEPTXF0_Device" description="Endpoint 0 transmit FIFO size (peripheral mode)" start="+0x28" size="4" access="Read/Write" reset_value="0x00000200" reset_mask="0xFFFFFFFF">
+      <BitField name="TX0FSA" description="Endpoint 0 transmit RAM start address" start="0" size="16" />
+      <BitField name="TX0FD" description="Endpoint 0 TxFIFO depth" start="16" size="16" />
+    </Register>
+    <Register name="OTG_HS_GNPTXSTS" description="OTG_HS nonperiodic transmit FIFO/queue status register" start="+0x2C" size="4" access="ReadOnly" reset_value="0x00080200" reset_mask="0xFFFFFFFF">
+      <BitField name="NPTXFSAV" description="Nonperiodic TxFIFO space available" start="0" size="16" />
+      <BitField name="NPTQXSAV" description="Nonperiodic transmit request queue space available" start="16" size="8" />
+      <BitField name="NPTXQTOP" description="Top of the nonperiodic transmit request queue" start="24" size="7" />
+    </Register>
+    <Register name="OTG_HS_GCCFG" description="OTG_HS general core configuration register" start="+0x38" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="PWRDWN" description="Power down" start="16" size="1" />
+      <BitField name="BCDEN" description="Battery charging detector (BCD) enable" start="17" size="1" />
+      <BitField name="DCDEN" description="Data contact detection (DCD) mode enable" start="18" size="1" />
+      <BitField name="PDEN" description="Primary detection (PD) mode enable" start="19" size="1" />
+      <BitField name="SDEN" description="Secondary detection (SD) mode enable" start="20" size="1" />
+      <BitField name="VBDEN" description="USB VBUS detection enable" start="21" size="1" />
+      <BitField name="DCDET" description="Data contact detection (DCD) status" start="0" size="1" />
+      <BitField name="PDET" description="Primary detection (PD) status" start="1" size="1" />
+      <BitField name="SDET" description="Secondary detection (SD) status" start="2" size="1" />
+      <BitField name="PS2DET" description="DM pull-up detection status" start="3" size="1" />
+    </Register>
+    <Register name="OTG_HS_CID" description="OTG_HS core ID register" start="+0x3C" size="4" access="Read/Write" reset_value="0x00001200" reset_mask="0xFFFFFFFF">
+      <BitField name="PRODUCT_ID" description="Product ID field" start="0" size="32" />
+    </Register>
+    <Register name="OTG_HS_HPTXFSIZ" description="OTG_HS Host periodic transmit FIFO size register" start="+0x100" size="4" access="Read/Write" reset_value="0x02000600" reset_mask="0xFFFFFFFF">
+      <BitField name="PTXSA" description="Host periodic TxFIFO start address" start="0" size="16" />
+      <BitField name="PTXFD" description="Host periodic TxFIFO depth" start="16" size="16" />
+    </Register>
+    <Register name="OTG_HS_DIEPTXF1" description="OTG_HS device IN endpoint transmit FIFO size register" start="+0x104" size="4" access="Read/Write" reset_value="0x02000400" reset_mask="0xFFFFFFFF">
+      <BitField name="INEPTXSA" description="IN endpoint FIFOx transmit RAM start address" start="0" size="16" />
+      <BitField name="INEPTXFD" description="IN endpoint TxFIFO depth" start="16" size="16" />
+    </Register>
+    <Register name="OTG_HS_DIEPTXF2" description="OTG_HS device IN endpoint transmit FIFO size register" start="+0x108" size="4" access="Read/Write" reset_value="0x02000400" reset_mask="0xFFFFFFFF">
+      <BitField name="INEPTXSA" description="IN endpoint FIFOx transmit RAM start address" start="0" size="16" />
+      <BitField name="INEPTXFD" description="IN endpoint TxFIFO depth" start="16" size="16" />
+    </Register>
+    <Register name="OTG_HS_DIEPTXF3" description="OTG_HS device IN endpoint transmit FIFO size register" start="+0x11C" size="4" access="Read/Write" reset_value="0x02000400" reset_mask="0xFFFFFFFF">
+      <BitField name="INEPTXSA" description="IN endpoint FIFOx transmit RAM start address" start="0" size="16" />
+      <BitField name="INEPTXFD" description="IN endpoint TxFIFO depth" start="16" size="16" />
+    </Register>
+    <Register name="OTG_HS_DIEPTXF4" description="OTG_HS device IN endpoint transmit FIFO size register" start="+0x120" size="4" access="Read/Write" reset_value="0x02000400" reset_mask="0xFFFFFFFF">
+      <BitField name="INEPTXSA" description="IN endpoint FIFOx transmit RAM start address" start="0" size="16" />
+      <BitField name="INEPTXFD" description="IN endpoint TxFIFO depth" start="16" size="16" />
+    </Register>
+    <Register name="OTG_HS_DIEPTXF5" description="OTG_HS device IN endpoint transmit FIFO size register" start="+0x124" size="4" access="Read/Write" reset_value="0x02000400" reset_mask="0xFFFFFFFF">
+      <BitField name="INEPTXSA" description="IN endpoint FIFOx transmit RAM start address" start="0" size="16" />
+      <BitField name="INEPTXFD" description="IN endpoint TxFIFO depth" start="16" size="16" />
+    </Register>
+    <Register name="OTG_HS_DIEPTXF6" description="OTG_HS device IN endpoint transmit FIFO size register" start="+0x128" size="4" access="Read/Write" reset_value="0x02000400" reset_mask="0xFFFFFFFF">
+      <BitField name="INEPTXSA" description="IN endpoint FIFOx transmit RAM start address" start="0" size="16" />
+      <BitField name="INEPTXFD" description="IN endpoint TxFIFO depth" start="16" size="16" />
+    </Register>
+    <Register name="OTG_HS_DIEPTXF7" description="OTG_HS device IN endpoint transmit FIFO size register" start="+0x12C" size="4" access="Read/Write" reset_value="0x02000400" reset_mask="0xFFFFFFFF">
+      <BitField name="INEPTXSA" description="IN endpoint FIFOx transmit RAM start address" start="0" size="16" />
+      <BitField name="INEPTXFD" description="IN endpoint TxFIFO depth" start="16" size="16" />
+    </Register>
+    <Register name="OTG_HS_GRXSTSR_Device" description="OTG_HS Receive status debug read register (peripheral mode mode)" start="+0x1C" size="4" access="ReadOnly" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="EPNUM" description="Endpoint number" start="0" size="4" />
+      <BitField name="BCNT" description="Byte count" start="4" size="11" />
+      <BitField name="DPID" description="Data PID" start="15" size="2" />
+      <BitField name="PKTSTS" description="Packet status" start="17" size="4" />
+      <BitField name="FRMNUM" description="Frame number" start="21" size="4" />
+    </Register>
+    <Register name="OTG_HS_GRXSTSP_Device" description="OTG_HS status read and pop register (peripheral mode)" start="+0x20" size="4" access="ReadOnly" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="EPNUM" description="Endpoint number" start="0" size="4" />
+      <BitField name="BCNT" description="Byte count" start="4" size="11" />
+      <BitField name="DPID" description="Data PID" start="15" size="2" />
+      <BitField name="PKTSTS" description="Packet status" start="17" size="4" />
+      <BitField name="FRMNUM" description="Frame number" start="21" size="4" />
+    </Register>
+    <Register name="OTG_HS_GLPMCFG" description="OTG core LPM configuration register" start="+0x54" size="4" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="LPMEN" description="LPM support enable" start="0" size="1" access="Read/Write" />
+      <BitField name="LPMACK" description="LPM token acknowledge enable" start="1" size="1" access="Read/Write" />
+      <BitField name="BESL" description="Best effort service latency" start="2" size="4" access="ReadOnly" />
+      <BitField name="REMWAKE" description="bRemoteWake value" start="6" size="1" access="ReadOnly" />
+      <BitField name="L1SSEN" description="L1 Shallow Sleep enable" start="7" size="1" access="Read/Write" />
+      <BitField name="BESLTHRS" description="BESL threshold" start="8" size="4" access="Read/Write" />
+      <BitField name="L1DSEN" description="L1 deep sleep enable" start="12" size="1" access="Read/Write" />
+      <BitField name="LPMRST" description="LPM response" start="13" size="2" access="ReadOnly" />
+      <BitField name="SLPSTS" description="Port sleep status" start="15" size="1" access="ReadOnly" />
+      <BitField name="L1RSMOK" description="Sleep State Resume OK" start="16" size="1" access="ReadOnly" />
+      <BitField name="LPMCHIDX" description="LPM Channel Index" start="17" size="4" access="Read/Write" />
+      <BitField name="LPMRCNT" description="LPM retry count" start="21" size="3" access="Read/Write" />
+      <BitField name="SNDLPM" description="Send LPM transaction" start="24" size="1" access="Read/Write" />
+      <BitField name="LPMRCNTSTS" description="LPM retry count status" start="25" size="3" access="ReadOnly" />
+      <BitField name="ENBESL" description="Enable best effort service latency" start="28" size="1" access="Read/Write" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="OTG1_HS_HOST" description="USB 1 on the go high speed" start="0x40040400">
+    <Register name="OTG_HS_HCFG" description="OTG_HS host configuration register" start="+0x0" size="4" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="FSLSPCS" description="FS/LS PHY clock select" start="0" size="2" access="Read/Write" />
+      <BitField name="FSLSS" description="FS- and LS-only support" start="2" size="1" access="ReadOnly" />
+    </Register>
+    <Register name="OTG_HS_HFIR" description="OTG_HS Host frame interval register" start="+0x4" size="4" access="Read/Write" reset_value="0x0000EA60" reset_mask="0xFFFFFFFF">
+      <BitField name="FRIVL" description="Frame interval" start="0" size="16" />
+    </Register>
+    <Register name="OTG_HS_HFNUM" description="OTG_HS host frame number/frame time remaining register" start="+0x8" size="4" access="ReadOnly" reset_value="0x00003FFF" reset_mask="0xFFFFFFFF">
+      <BitField name="FRNUM" description="Frame number" start="0" size="16" />
+      <BitField name="FTREM" description="Frame time remaining" start="16" size="16" />
+    </Register>
+    <Register name="OTG_HS_HPTXSTS" description="OTG_HS_Host periodic transmit FIFO/queue status register" start="+0x10" size="4" reset_value="0x00080100" reset_mask="0xFFFFFFFF">
+      <BitField name="PTXFSAVL" description="Periodic transmit data FIFO space available" start="0" size="16" access="Read/Write" />
+      <BitField name="PTXQSAV" description="Periodic transmit request queue space available" start="16" size="8" access="ReadOnly" />
+      <BitField name="PTXQTOP" description="Top of the periodic transmit request queue" start="24" size="8" access="ReadOnly" />
+    </Register>
+    <Register name="OTG_HS_HAINT" description="OTG_HS Host all channels interrupt register" start="+0x14" size="4" access="ReadOnly" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="HAINT" description="Channel interrupts" start="0" size="16" />
+    </Register>
+    <Register name="OTG_HS_HAINTMSK" description="OTG_HS host all channels interrupt mask register" start="+0x18" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="HAINTM" description="Channel interrupt mask" start="0" size="16" />
+    </Register>
+    <Register name="OTG_HS_HPRT" description="OTG_HS host port control and status register" start="+0x40" size="4" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="PCSTS" description="Port connect status" start="0" size="1" access="ReadOnly" />
+      <BitField name="PCDET" description="Port connect detected" start="1" size="1" access="Read/Write" />
+      <BitField name="PENA" description="Port enable" start="2" size="1" access="Read/Write" />
+      <BitField name="PENCHNG" description="Port enable/disable change" start="3" size="1" access="Read/Write" />
+      <BitField name="POCA" description="Port overcurrent active" start="4" size="1" access="ReadOnly" />
+      <BitField name="POCCHNG" description="Port overcurrent change" start="5" size="1" access="Read/Write" />
+      <BitField name="PRES" description="Port resume" start="6" size="1" access="Read/Write" />
+      <BitField name="PSUSP" description="Port suspend" start="7" size="1" access="Read/Write" />
+      <BitField name="PRST" description="Port reset" start="8" size="1" access="Read/Write" />
+      <BitField name="PLSTS" description="Port line status" start="10" size="2" access="ReadOnly" />
+      <BitField name="PPWR" description="Port power" start="12" size="1" access="Read/Write" />
+      <BitField name="PTCTL" description="Port test control" start="13" size="4" access="Read/Write" />
+      <BitField name="PSPD" description="Port speed" start="17" size="2" access="ReadOnly" />
+    </Register>
+    <Register name="OTG_HS_HCCHAR0" description="OTG_HS host channel-0 characteristics register" start="+0x100" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" />
+      <BitField name="EPNUM" description="Endpoint number" start="11" size="4" />
+      <BitField name="EPDIR" description="Endpoint direction" start="15" size="1" />
+      <BitField name="LSDEV" description="Low-speed device" start="17" size="1" />
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" />
+      <BitField name="MC" description="Multi Count (MC) / Error Count (EC)" start="20" size="2" />
+      <BitField name="DAD" description="Device address" start="22" size="7" />
+      <BitField name="ODDFRM" description="Odd frame" start="29" size="1" />
+      <BitField name="CHDIS" description="Channel disable" start="30" size="1" />
+      <BitField name="CHENA" description="Channel enable" start="31" size="1" />
+    </Register>
+    <Register name="OTG_HS_HCCHAR1" description="OTG_HS host channel-1 characteristics register" start="+0x120" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" />
+      <BitField name="EPNUM" description="Endpoint number" start="11" size="4" />
+      <BitField name="EPDIR" description="Endpoint direction" start="15" size="1" />
+      <BitField name="LSDEV" description="Low-speed device" start="17" size="1" />
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" />
+      <BitField name="MC" description="Multi Count (MC) / Error Count (EC)" start="20" size="2" />
+      <BitField name="DAD" description="Device address" start="22" size="7" />
+      <BitField name="ODDFRM" description="Odd frame" start="29" size="1" />
+      <BitField name="CHDIS" description="Channel disable" start="30" size="1" />
+      <BitField name="CHENA" description="Channel enable" start="31" size="1" />
+    </Register>
+    <Register name="OTG_HS_HCCHAR2" description="OTG_HS host channel-2 characteristics register" start="+0x140" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" />
+      <BitField name="EPNUM" description="Endpoint number" start="11" size="4" />
+      <BitField name="EPDIR" description="Endpoint direction" start="15" size="1" />
+      <BitField name="LSDEV" description="Low-speed device" start="17" size="1" />
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" />
+      <BitField name="MC" description="Multi Count (MC) / Error Count (EC)" start="20" size="2" />
+      <BitField name="DAD" description="Device address" start="22" size="7" />
+      <BitField name="ODDFRM" description="Odd frame" start="29" size="1" />
+      <BitField name="CHDIS" description="Channel disable" start="30" size="1" />
+      <BitField name="CHENA" description="Channel enable" start="31" size="1" />
+    </Register>
+    <Register name="OTG_HS_HCCHAR3" description="OTG_HS host channel-3 characteristics register" start="+0x160" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" />
+      <BitField name="EPNUM" description="Endpoint number" start="11" size="4" />
+      <BitField name="EPDIR" description="Endpoint direction" start="15" size="1" />
+      <BitField name="LSDEV" description="Low-speed device" start="17" size="1" />
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" />
+      <BitField name="MC" description="Multi Count (MC) / Error Count (EC)" start="20" size="2" />
+      <BitField name="DAD" description="Device address" start="22" size="7" />
+      <BitField name="ODDFRM" description="Odd frame" start="29" size="1" />
+      <BitField name="CHDIS" description="Channel disable" start="30" size="1" />
+      <BitField name="CHENA" description="Channel enable" start="31" size="1" />
+    </Register>
+    <Register name="OTG_HS_HCCHAR4" description="OTG_HS host channel-4 characteristics register" start="+0x180" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" />
+      <BitField name="EPNUM" description="Endpoint number" start="11" size="4" />
+      <BitField name="EPDIR" description="Endpoint direction" start="15" size="1" />
+      <BitField name="LSDEV" description="Low-speed device" start="17" size="1" />
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" />
+      <BitField name="MC" description="Multi Count (MC) / Error Count (EC)" start="20" size="2" />
+      <BitField name="DAD" description="Device address" start="22" size="7" />
+      <BitField name="ODDFRM" description="Odd frame" start="29" size="1" />
+      <BitField name="CHDIS" description="Channel disable" start="30" size="1" />
+      <BitField name="CHENA" description="Channel enable" start="31" size="1" />
+    </Register>
+    <Register name="OTG_HS_HCCHAR5" description="OTG_HS host channel-5 characteristics register" start="+0x1A0" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" />
+      <BitField name="EPNUM" description="Endpoint number" start="11" size="4" />
+      <BitField name="EPDIR" description="Endpoint direction" start="15" size="1" />
+      <BitField name="LSDEV" description="Low-speed device" start="17" size="1" />
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" />
+      <BitField name="MC" description="Multi Count (MC) / Error Count (EC)" start="20" size="2" />
+      <BitField name="DAD" description="Device address" start="22" size="7" />
+      <BitField name="ODDFRM" description="Odd frame" start="29" size="1" />
+      <BitField name="CHDIS" description="Channel disable" start="30" size="1" />
+      <BitField name="CHENA" description="Channel enable" start="31" size="1" />
+    </Register>
+    <Register name="OTG_HS_HCCHAR6" description="OTG_HS host channel-6 characteristics register" start="+0x1C0" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" />
+      <BitField name="EPNUM" description="Endpoint number" start="11" size="4" />
+      <BitField name="EPDIR" description="Endpoint direction" start="15" size="1" />
+      <BitField name="LSDEV" description="Low-speed device" start="17" size="1" />
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" />
+      <BitField name="MC" description="Multi Count (MC) / Error Count (EC)" start="20" size="2" />
+      <BitField name="DAD" description="Device address" start="22" size="7" />
+      <BitField name="ODDFRM" description="Odd frame" start="29" size="1" />
+      <BitField name="CHDIS" description="Channel disable" start="30" size="1" />
+      <BitField name="CHENA" description="Channel enable" start="31" size="1" />
+    </Register>
+    <Register name="OTG_HS_HCCHAR7" description="OTG_HS host channel-7 characteristics register" start="+0x1E0" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" />
+      <BitField name="EPNUM" description="Endpoint number" start="11" size="4" />
+      <BitField name="EPDIR" description="Endpoint direction" start="15" size="1" />
+      <BitField name="LSDEV" description="Low-speed device" start="17" size="1" />
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" />
+      <BitField name="MC" description="Multi Count (MC) / Error Count (EC)" start="20" size="2" />
+      <BitField name="DAD" description="Device address" start="22" size="7" />
+      <BitField name="ODDFRM" description="Odd frame" start="29" size="1" />
+      <BitField name="CHDIS" description="Channel disable" start="30" size="1" />
+      <BitField name="CHENA" description="Channel enable" start="31" size="1" />
+    </Register>
+    <Register name="OTG_HS_HCCHAR8" description="OTG_HS host channel-8 characteristics register" start="+0x200" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" />
+      <BitField name="EPNUM" description="Endpoint number" start="11" size="4" />
+      <BitField name="EPDIR" description="Endpoint direction" start="15" size="1" />
+      <BitField name="LSDEV" description="Low-speed device" start="17" size="1" />
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" />
+      <BitField name="MC" description="Multi Count (MC) / Error Count (EC)" start="20" size="2" />
+      <BitField name="DAD" description="Device address" start="22" size="7" />
+      <BitField name="ODDFRM" description="Odd frame" start="29" size="1" />
+      <BitField name="CHDIS" description="Channel disable" start="30" size="1" />
+      <BitField name="CHENA" description="Channel enable" start="31" size="1" />
+    </Register>
+    <Register name="OTG_HS_HCCHAR9" description="OTG_HS host channel-9 characteristics register" start="+0x220" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" />
+      <BitField name="EPNUM" description="Endpoint number" start="11" size="4" />
+      <BitField name="EPDIR" description="Endpoint direction" start="15" size="1" />
+      <BitField name="LSDEV" description="Low-speed device" start="17" size="1" />
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" />
+      <BitField name="MC" description="Multi Count (MC) / Error Count (EC)" start="20" size="2" />
+      <BitField name="DAD" description="Device address" start="22" size="7" />
+      <BitField name="ODDFRM" description="Odd frame" start="29" size="1" />
+      <BitField name="CHDIS" description="Channel disable" start="30" size="1" />
+      <BitField name="CHENA" description="Channel enable" start="31" size="1" />
+    </Register>
+    <Register name="OTG_HS_HCCHAR10" description="OTG_HS host channel-10 characteristics register" start="+0x240" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" />
+      <BitField name="EPNUM" description="Endpoint number" start="11" size="4" />
+      <BitField name="EPDIR" description="Endpoint direction" start="15" size="1" />
+      <BitField name="LSDEV" description="Low-speed device" start="17" size="1" />
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" />
+      <BitField name="MC" description="Multi Count (MC) / Error Count (EC)" start="20" size="2" />
+      <BitField name="DAD" description="Device address" start="22" size="7" />
+      <BitField name="ODDFRM" description="Odd frame" start="29" size="1" />
+      <BitField name="CHDIS" description="Channel disable" start="30" size="1" />
+      <BitField name="CHENA" description="Channel enable" start="31" size="1" />
+    </Register>
+    <Register name="OTG_HS_HCCHAR11" description="OTG_HS host channel-11 characteristics register" start="+0x260" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" />
+      <BitField name="EPNUM" description="Endpoint number" start="11" size="4" />
+      <BitField name="EPDIR" description="Endpoint direction" start="15" size="1" />
+      <BitField name="LSDEV" description="Low-speed device" start="17" size="1" />
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" />
+      <BitField name="MC" description="Multi Count (MC) / Error Count (EC)" start="20" size="2" />
+      <BitField name="DAD" description="Device address" start="22" size="7" />
+      <BitField name="ODDFRM" description="Odd frame" start="29" size="1" />
+      <BitField name="CHDIS" description="Channel disable" start="30" size="1" />
+      <BitField name="CHENA" description="Channel enable" start="31" size="1" />
+    </Register>
+    <Register name="OTG_HS_HCSPLT0" description="OTG_HS host channel-0 split control register" start="+0x104" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="PRTADDR" description="Port address" start="0" size="7" />
+      <BitField name="HUBADDR" description="Hub address" start="7" size="7" />
+      <BitField name="XACTPOS" description="XACTPOS" start="14" size="2" />
+      <BitField name="COMPLSPLT" description="Do complete split" start="16" size="1" />
+      <BitField name="SPLITEN" description="Split enable" start="31" size="1" />
+    </Register>
+    <Register name="OTG_HS_HCSPLT1" description="OTG_HS host channel-1 split control register" start="+0x124" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="PRTADDR" description="Port address" start="0" size="7" />
+      <BitField name="HUBADDR" description="Hub address" start="7" size="7" />
+      <BitField name="XACTPOS" description="XACTPOS" start="14" size="2" />
+      <BitField name="COMPLSPLT" description="Do complete split" start="16" size="1" />
+      <BitField name="SPLITEN" description="Split enable" start="31" size="1" />
+    </Register>
+    <Register name="OTG_HS_HCSPLT2" description="OTG_HS host channel-2 split control register" start="+0x144" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="PRTADDR" description="Port address" start="0" size="7" />
+      <BitField name="HUBADDR" description="Hub address" start="7" size="7" />
+      <BitField name="XACTPOS" description="XACTPOS" start="14" size="2" />
+      <BitField name="COMPLSPLT" description="Do complete split" start="16" size="1" />
+      <BitField name="SPLITEN" description="Split enable" start="31" size="1" />
+    </Register>
+    <Register name="OTG_HS_HCSPLT3" description="OTG_HS host channel-3 split control register" start="+0x164" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="PRTADDR" description="Port address" start="0" size="7" />
+      <BitField name="HUBADDR" description="Hub address" start="7" size="7" />
+      <BitField name="XACTPOS" description="XACTPOS" start="14" size="2" />
+      <BitField name="COMPLSPLT" description="Do complete split" start="16" size="1" />
+      <BitField name="SPLITEN" description="Split enable" start="31" size="1" />
+    </Register>
+    <Register name="OTG_HS_HCSPLT4" description="OTG_HS host channel-4 split control register" start="+0x184" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="PRTADDR" description="Port address" start="0" size="7" />
+      <BitField name="HUBADDR" description="Hub address" start="7" size="7" />
+      <BitField name="XACTPOS" description="XACTPOS" start="14" size="2" />
+      <BitField name="COMPLSPLT" description="Do complete split" start="16" size="1" />
+      <BitField name="SPLITEN" description="Split enable" start="31" size="1" />
+    </Register>
+    <Register name="OTG_HS_HCSPLT5" description="OTG_HS host channel-5 split control register" start="+0x1A4" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="PRTADDR" description="Port address" start="0" size="7" />
+      <BitField name="HUBADDR" description="Hub address" start="7" size="7" />
+      <BitField name="XACTPOS" description="XACTPOS" start="14" size="2" />
+      <BitField name="COMPLSPLT" description="Do complete split" start="16" size="1" />
+      <BitField name="SPLITEN" description="Split enable" start="31" size="1" />
+    </Register>
+    <Register name="OTG_HS_HCSPLT6" description="OTG_HS host channel-6 split control register" start="+0x1C4" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="PRTADDR" description="Port address" start="0" size="7" />
+      <BitField name="HUBADDR" description="Hub address" start="7" size="7" />
+      <BitField name="XACTPOS" description="XACTPOS" start="14" size="2" />
+      <BitField name="COMPLSPLT" description="Do complete split" start="16" size="1" />
+      <BitField name="SPLITEN" description="Split enable" start="31" size="1" />
+    </Register>
+    <Register name="OTG_HS_HCSPLT7" description="OTG_HS host channel-7 split control register" start="+0x1E4" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="PRTADDR" description="Port address" start="0" size="7" />
+      <BitField name="HUBADDR" description="Hub address" start="7" size="7" />
+      <BitField name="XACTPOS" description="XACTPOS" start="14" size="2" />
+      <BitField name="COMPLSPLT" description="Do complete split" start="16" size="1" />
+      <BitField name="SPLITEN" description="Split enable" start="31" size="1" />
+    </Register>
+    <Register name="OTG_HS_HCSPLT8" description="OTG_HS host channel-8 split control register" start="+0x204" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="PRTADDR" description="Port address" start="0" size="7" />
+      <BitField name="HUBADDR" description="Hub address" start="7" size="7" />
+      <BitField name="XACTPOS" description="XACTPOS" start="14" size="2" />
+      <BitField name="COMPLSPLT" description="Do complete split" start="16" size="1" />
+      <BitField name="SPLITEN" description="Split enable" start="31" size="1" />
+    </Register>
+    <Register name="OTG_HS_HCSPLT9" description="OTG_HS host channel-9 split control register" start="+0x224" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="PRTADDR" description="Port address" start="0" size="7" />
+      <BitField name="HUBADDR" description="Hub address" start="7" size="7" />
+      <BitField name="XACTPOS" description="XACTPOS" start="14" size="2" />
+      <BitField name="COMPLSPLT" description="Do complete split" start="16" size="1" />
+      <BitField name="SPLITEN" description="Split enable" start="31" size="1" />
+    </Register>
+    <Register name="OTG_HS_HCSPLT10" description="OTG_HS host channel-10 split control register" start="+0x244" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="PRTADDR" description="Port address" start="0" size="7" />
+      <BitField name="HUBADDR" description="Hub address" start="7" size="7" />
+      <BitField name="XACTPOS" description="XACTPOS" start="14" size="2" />
+      <BitField name="COMPLSPLT" description="Do complete split" start="16" size="1" />
+      <BitField name="SPLITEN" description="Split enable" start="31" size="1" />
+    </Register>
+    <Register name="OTG_HS_HCSPLT11" description="OTG_HS host channel-11 split control register" start="+0x264" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="PRTADDR" description="Port address" start="0" size="7" />
+      <BitField name="HUBADDR" description="Hub address" start="7" size="7" />
+      <BitField name="XACTPOS" description="XACTPOS" start="14" size="2" />
+      <BitField name="COMPLSPLT" description="Do complete split" start="16" size="1" />
+      <BitField name="SPLITEN" description="Split enable" start="31" size="1" />
+    </Register>
+    <Register name="OTG_HS_HCINT0" description="OTG_HS host channel-11 interrupt register" start="+0x108" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRC" description="Transfer completed" start="0" size="1" />
+      <BitField name="CHH" description="Channel halted" start="1" size="1" />
+      <BitField name="AHBERR" description="AHB error" start="2" size="1" />
+      <BitField name="STALL" description="STALL response received interrupt" start="3" size="1" />
+      <BitField name="NAK" description="NAK response received interrupt" start="4" size="1" />
+      <BitField name="ACK" description="ACK response received/transmitted interrupt" start="5" size="1" />
+      <BitField name="NYET" description="Response received interrupt" start="6" size="1" />
+      <BitField name="TXERR" description="Transaction error" start="7" size="1" />
+      <BitField name="BBERR" description="Babble error" start="8" size="1" />
+      <BitField name="FRMOR" description="Frame overrun" start="9" size="1" />
+      <BitField name="DTERR" description="Data toggle error" start="10" size="1" />
+    </Register>
+    <Register name="OTG_HS_HCINT1" description="OTG_HS host channel-1 interrupt register" start="+0x128" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRC" description="Transfer completed" start="0" size="1" />
+      <BitField name="CHH" description="Channel halted" start="1" size="1" />
+      <BitField name="AHBERR" description="AHB error" start="2" size="1" />
+      <BitField name="STALL" description="STALL response received interrupt" start="3" size="1" />
+      <BitField name="NAK" description="NAK response received interrupt" start="4" size="1" />
+      <BitField name="ACK" description="ACK response received/transmitted interrupt" start="5" size="1" />
+      <BitField name="NYET" description="Response received interrupt" start="6" size="1" />
+      <BitField name="TXERR" description="Transaction error" start="7" size="1" />
+      <BitField name="BBERR" description="Babble error" start="8" size="1" />
+      <BitField name="FRMOR" description="Frame overrun" start="9" size="1" />
+      <BitField name="DTERR" description="Data toggle error" start="10" size="1" />
+    </Register>
+    <Register name="OTG_HS_HCINT2" description="OTG_HS host channel-2 interrupt register" start="+0x148" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRC" description="Transfer completed" start="0" size="1" />
+      <BitField name="CHH" description="Channel halted" start="1" size="1" />
+      <BitField name="AHBERR" description="AHB error" start="2" size="1" />
+      <BitField name="STALL" description="STALL response received interrupt" start="3" size="1" />
+      <BitField name="NAK" description="NAK response received interrupt" start="4" size="1" />
+      <BitField name="ACK" description="ACK response received/transmitted interrupt" start="5" size="1" />
+      <BitField name="NYET" description="Response received interrupt" start="6" size="1" />
+      <BitField name="TXERR" description="Transaction error" start="7" size="1" />
+      <BitField name="BBERR" description="Babble error" start="8" size="1" />
+      <BitField name="FRMOR" description="Frame overrun" start="9" size="1" />
+      <BitField name="DTERR" description="Data toggle error" start="10" size="1" />
+    </Register>
+    <Register name="OTG_HS_HCINT3" description="OTG_HS host channel-3 interrupt register" start="+0x168" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRC" description="Transfer completed" start="0" size="1" />
+      <BitField name="CHH" description="Channel halted" start="1" size="1" />
+      <BitField name="AHBERR" description="AHB error" start="2" size="1" />
+      <BitField name="STALL" description="STALL response received interrupt" start="3" size="1" />
+      <BitField name="NAK" description="NAK response received interrupt" start="4" size="1" />
+      <BitField name="ACK" description="ACK response received/transmitted interrupt" start="5" size="1" />
+      <BitField name="NYET" description="Response received interrupt" start="6" size="1" />
+      <BitField name="TXERR" description="Transaction error" start="7" size="1" />
+      <BitField name="BBERR" description="Babble error" start="8" size="1" />
+      <BitField name="FRMOR" description="Frame overrun" start="9" size="1" />
+      <BitField name="DTERR" description="Data toggle error" start="10" size="1" />
+    </Register>
+    <Register name="OTG_HS_HCINT4" description="OTG_HS host channel-4 interrupt register" start="+0x188" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRC" description="Transfer completed" start="0" size="1" />
+      <BitField name="CHH" description="Channel halted" start="1" size="1" />
+      <BitField name="AHBERR" description="AHB error" start="2" size="1" />
+      <BitField name="STALL" description="STALL response received interrupt" start="3" size="1" />
+      <BitField name="NAK" description="NAK response received interrupt" start="4" size="1" />
+      <BitField name="ACK" description="ACK response received/transmitted interrupt" start="5" size="1" />
+      <BitField name="NYET" description="Response received interrupt" start="6" size="1" />
+      <BitField name="TXERR" description="Transaction error" start="7" size="1" />
+      <BitField name="BBERR" description="Babble error" start="8" size="1" />
+      <BitField name="FRMOR" description="Frame overrun" start="9" size="1" />
+      <BitField name="DTERR" description="Data toggle error" start="10" size="1" />
+    </Register>
+    <Register name="OTG_HS_HCINT5" description="OTG_HS host channel-5 interrupt register" start="+0x1A8" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRC" description="Transfer completed" start="0" size="1" />
+      <BitField name="CHH" description="Channel halted" start="1" size="1" />
+      <BitField name="AHBERR" description="AHB error" start="2" size="1" />
+      <BitField name="STALL" description="STALL response received interrupt" start="3" size="1" />
+      <BitField name="NAK" description="NAK response received interrupt" start="4" size="1" />
+      <BitField name="ACK" description="ACK response received/transmitted interrupt" start="5" size="1" />
+      <BitField name="NYET" description="Response received interrupt" start="6" size="1" />
+      <BitField name="TXERR" description="Transaction error" start="7" size="1" />
+      <BitField name="BBERR" description="Babble error" start="8" size="1" />
+      <BitField name="FRMOR" description="Frame overrun" start="9" size="1" />
+      <BitField name="DTERR" description="Data toggle error" start="10" size="1" />
+    </Register>
+    <Register name="OTG_HS_HCINT6" description="OTG_HS host channel-6 interrupt register" start="+0x1C8" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRC" description="Transfer completed" start="0" size="1" />
+      <BitField name="CHH" description="Channel halted" start="1" size="1" />
+      <BitField name="AHBERR" description="AHB error" start="2" size="1" />
+      <BitField name="STALL" description="STALL response received interrupt" start="3" size="1" />
+      <BitField name="NAK" description="NAK response received interrupt" start="4" size="1" />
+      <BitField name="ACK" description="ACK response received/transmitted interrupt" start="5" size="1" />
+      <BitField name="NYET" description="Response received interrupt" start="6" size="1" />
+      <BitField name="TXERR" description="Transaction error" start="7" size="1" />
+      <BitField name="BBERR" description="Babble error" start="8" size="1" />
+      <BitField name="FRMOR" description="Frame overrun" start="9" size="1" />
+      <BitField name="DTERR" description="Data toggle error" start="10" size="1" />
+    </Register>
+    <Register name="OTG_HS_HCINT7" description="OTG_HS host channel-7 interrupt register" start="+0x1E8" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRC" description="Transfer completed" start="0" size="1" />
+      <BitField name="CHH" description="Channel halted" start="1" size="1" />
+      <BitField name="AHBERR" description="AHB error" start="2" size="1" />
+      <BitField name="STALL" description="STALL response received interrupt" start="3" size="1" />
+      <BitField name="NAK" description="NAK response received interrupt" start="4" size="1" />
+      <BitField name="ACK" description="ACK response received/transmitted interrupt" start="5" size="1" />
+      <BitField name="NYET" description="Response received interrupt" start="6" size="1" />
+      <BitField name="TXERR" description="Transaction error" start="7" size="1" />
+      <BitField name="BBERR" description="Babble error" start="8" size="1" />
+      <BitField name="FRMOR" description="Frame overrun" start="9" size="1" />
+      <BitField name="DTERR" description="Data toggle error" start="10" size="1" />
+    </Register>
+    <Register name="OTG_HS_HCINT8" description="OTG_HS host channel-8 interrupt register" start="+0x208" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRC" description="Transfer completed" start="0" size="1" />
+      <BitField name="CHH" description="Channel halted" start="1" size="1" />
+      <BitField name="AHBERR" description="AHB error" start="2" size="1" />
+      <BitField name="STALL" description="STALL response received interrupt" start="3" size="1" />
+      <BitField name="NAK" description="NAK response received interrupt" start="4" size="1" />
+      <BitField name="ACK" description="ACK response received/transmitted interrupt" start="5" size="1" />
+      <BitField name="NYET" description="Response received interrupt" start="6" size="1" />
+      <BitField name="TXERR" description="Transaction error" start="7" size="1" />
+      <BitField name="BBERR" description="Babble error" start="8" size="1" />
+      <BitField name="FRMOR" description="Frame overrun" start="9" size="1" />
+      <BitField name="DTERR" description="Data toggle error" start="10" size="1" />
+    </Register>
+    <Register name="OTG_HS_HCINT9" description="OTG_HS host channel-9 interrupt register" start="+0x228" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRC" description="Transfer completed" start="0" size="1" />
+      <BitField name="CHH" description="Channel halted" start="1" size="1" />
+      <BitField name="AHBERR" description="AHB error" start="2" size="1" />
+      <BitField name="STALL" description="STALL response received interrupt" start="3" size="1" />
+      <BitField name="NAK" description="NAK response received interrupt" start="4" size="1" />
+      <BitField name="ACK" description="ACK response received/transmitted interrupt" start="5" size="1" />
+      <BitField name="NYET" description="Response received interrupt" start="6" size="1" />
+      <BitField name="TXERR" description="Transaction error" start="7" size="1" />
+      <BitField name="BBERR" description="Babble error" start="8" size="1" />
+      <BitField name="FRMOR" description="Frame overrun" start="9" size="1" />
+      <BitField name="DTERR" description="Data toggle error" start="10" size="1" />
+    </Register>
+    <Register name="OTG_HS_HCINT10" description="OTG_HS host channel-10 interrupt register" start="+0x248" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRC" description="Transfer completed" start="0" size="1" />
+      <BitField name="CHH" description="Channel halted" start="1" size="1" />
+      <BitField name="AHBERR" description="AHB error" start="2" size="1" />
+      <BitField name="STALL" description="STALL response received interrupt" start="3" size="1" />
+      <BitField name="NAK" description="NAK response received interrupt" start="4" size="1" />
+      <BitField name="ACK" description="ACK response received/transmitted interrupt" start="5" size="1" />
+      <BitField name="NYET" description="Response received interrupt" start="6" size="1" />
+      <BitField name="TXERR" description="Transaction error" start="7" size="1" />
+      <BitField name="BBERR" description="Babble error" start="8" size="1" />
+      <BitField name="FRMOR" description="Frame overrun" start="9" size="1" />
+      <BitField name="DTERR" description="Data toggle error" start="10" size="1" />
+    </Register>
+    <Register name="OTG_HS_HCINT11" description="OTG_HS host channel-11 interrupt register" start="+0x268" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRC" description="Transfer completed" start="0" size="1" />
+      <BitField name="CHH" description="Channel halted" start="1" size="1" />
+      <BitField name="AHBERR" description="AHB error" start="2" size="1" />
+      <BitField name="STALL" description="STALL response received interrupt" start="3" size="1" />
+      <BitField name="NAK" description="NAK response received interrupt" start="4" size="1" />
+      <BitField name="ACK" description="ACK response received/transmitted interrupt" start="5" size="1" />
+      <BitField name="NYET" description="Response received interrupt" start="6" size="1" />
+      <BitField name="TXERR" description="Transaction error" start="7" size="1" />
+      <BitField name="BBERR" description="Babble error" start="8" size="1" />
+      <BitField name="FRMOR" description="Frame overrun" start="9" size="1" />
+      <BitField name="DTERR" description="Data toggle error" start="10" size="1" />
+    </Register>
+    <Register name="OTG_HS_HCINTMSK0" description="OTG_HS host channel-11 interrupt mask register" start="+0x10C" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRCM" description="Transfer completed mask" start="0" size="1" />
+      <BitField name="CHHM" description="Channel halted mask" start="1" size="1" />
+      <BitField name="AHBERR" description="AHB error" start="2" size="1" />
+      <BitField name="STALLM" description="STALL response received interrupt mask" start="3" size="1" />
+      <BitField name="NAKM" description="NAK response received interrupt mask" start="4" size="1" />
+      <BitField name="ACKM" description="ACK response received/transmitted interrupt mask" start="5" size="1" />
+      <BitField name="NYET" description="response received interrupt mask" start="6" size="1" />
+      <BitField name="TXERRM" description="Transaction error mask" start="7" size="1" />
+      <BitField name="BBERRM" description="Babble error mask" start="8" size="1" />
+      <BitField name="FRMORM" description="Frame overrun mask" start="9" size="1" />
+      <BitField name="DTERRM" description="Data toggle error mask" start="10" size="1" />
+    </Register>
+    <Register name="OTG_HS_HCINTMSK1" description="OTG_HS host channel-1 interrupt mask register" start="+0x12C" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRCM" description="Transfer completed mask" start="0" size="1" />
+      <BitField name="CHHM" description="Channel halted mask" start="1" size="1" />
+      <BitField name="AHBERR" description="AHB error" start="2" size="1" />
+      <BitField name="STALLM" description="STALL response received interrupt mask" start="3" size="1" />
+      <BitField name="NAKM" description="NAK response received interrupt mask" start="4" size="1" />
+      <BitField name="ACKM" description="ACK response received/transmitted interrupt mask" start="5" size="1" />
+      <BitField name="NYET" description="response received interrupt mask" start="6" size="1" />
+      <BitField name="TXERRM" description="Transaction error mask" start="7" size="1" />
+      <BitField name="BBERRM" description="Babble error mask" start="8" size="1" />
+      <BitField name="FRMORM" description="Frame overrun mask" start="9" size="1" />
+      <BitField name="DTERRM" description="Data toggle error mask" start="10" size="1" />
+    </Register>
+    <Register name="OTG_HS_HCINTMSK2" description="OTG_HS host channel-2 interrupt mask register" start="+0x14C" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRCM" description="Transfer completed mask" start="0" size="1" />
+      <BitField name="CHHM" description="Channel halted mask" start="1" size="1" />
+      <BitField name="AHBERR" description="AHB error" start="2" size="1" />
+      <BitField name="STALLM" description="STALL response received interrupt mask" start="3" size="1" />
+      <BitField name="NAKM" description="NAK response received interrupt mask" start="4" size="1" />
+      <BitField name="ACKM" description="ACK response received/transmitted interrupt mask" start="5" size="1" />
+      <BitField name="NYET" description="response received interrupt mask" start="6" size="1" />
+      <BitField name="TXERRM" description="Transaction error mask" start="7" size="1" />
+      <BitField name="BBERRM" description="Babble error mask" start="8" size="1" />
+      <BitField name="FRMORM" description="Frame overrun mask" start="9" size="1" />
+      <BitField name="DTERRM" description="Data toggle error mask" start="10" size="1" />
+    </Register>
+    <Register name="OTG_HS_HCINTMSK3" description="OTG_HS host channel-3 interrupt mask register" start="+0x16C" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRCM" description="Transfer completed mask" start="0" size="1" />
+      <BitField name="CHHM" description="Channel halted mask" start="1" size="1" />
+      <BitField name="AHBERR" description="AHB error" start="2" size="1" />
+      <BitField name="STALLM" description="STALL response received interrupt mask" start="3" size="1" />
+      <BitField name="NAKM" description="NAK response received interrupt mask" start="4" size="1" />
+      <BitField name="ACKM" description="ACK response received/transmitted interrupt mask" start="5" size="1" />
+      <BitField name="NYET" description="response received interrupt mask" start="6" size="1" />
+      <BitField name="TXERRM" description="Transaction error mask" start="7" size="1" />
+      <BitField name="BBERRM" description="Babble error mask" start="8" size="1" />
+      <BitField name="FRMORM" description="Frame overrun mask" start="9" size="1" />
+      <BitField name="DTERRM" description="Data toggle error mask" start="10" size="1" />
+    </Register>
+    <Register name="OTG_HS_HCINTMSK4" description="OTG_HS host channel-4 interrupt mask register" start="+0x18C" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRCM" description="Transfer completed mask" start="0" size="1" />
+      <BitField name="CHHM" description="Channel halted mask" start="1" size="1" />
+      <BitField name="AHBERR" description="AHB error" start="2" size="1" />
+      <BitField name="STALLM" description="STALL response received interrupt mask" start="3" size="1" />
+      <BitField name="NAKM" description="NAK response received interrupt mask" start="4" size="1" />
+      <BitField name="ACKM" description="ACK response received/transmitted interrupt mask" start="5" size="1" />
+      <BitField name="NYET" description="response received interrupt mask" start="6" size="1" />
+      <BitField name="TXERRM" description="Transaction error mask" start="7" size="1" />
+      <BitField name="BBERRM" description="Babble error mask" start="8" size="1" />
+      <BitField name="FRMORM" description="Frame overrun mask" start="9" size="1" />
+      <BitField name="DTERRM" description="Data toggle error mask" start="10" size="1" />
+    </Register>
+    <Register name="OTG_HS_HCINTMSK5" description="OTG_HS host channel-5 interrupt mask register" start="+0x1AC" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRCM" description="Transfer completed mask" start="0" size="1" />
+      <BitField name="CHHM" description="Channel halted mask" start="1" size="1" />
+      <BitField name="AHBERR" description="AHB error" start="2" size="1" />
+      <BitField name="STALLM" description="STALL response received interrupt mask" start="3" size="1" />
+      <BitField name="NAKM" description="NAK response received interrupt mask" start="4" size="1" />
+      <BitField name="ACKM" description="ACK response received/transmitted interrupt mask" start="5" size="1" />
+      <BitField name="NYET" description="response received interrupt mask" start="6" size="1" />
+      <BitField name="TXERRM" description="Transaction error mask" start="7" size="1" />
+      <BitField name="BBERRM" description="Babble error mask" start="8" size="1" />
+      <BitField name="FRMORM" description="Frame overrun mask" start="9" size="1" />
+      <BitField name="DTERRM" description="Data toggle error mask" start="10" size="1" />
+    </Register>
+    <Register name="OTG_HS_HCINTMSK6" description="OTG_HS host channel-6 interrupt mask register" start="+0x1CC" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRCM" description="Transfer completed mask" start="0" size="1" />
+      <BitField name="CHHM" description="Channel halted mask" start="1" size="1" />
+      <BitField name="AHBERR" description="AHB error" start="2" size="1" />
+      <BitField name="STALLM" description="STALL response received interrupt mask" start="3" size="1" />
+      <BitField name="NAKM" description="NAK response received interrupt mask" start="4" size="1" />
+      <BitField name="ACKM" description="ACK response received/transmitted interrupt mask" start="5" size="1" />
+      <BitField name="NYET" description="response received interrupt mask" start="6" size="1" />
+      <BitField name="TXERRM" description="Transaction error mask" start="7" size="1" />
+      <BitField name="BBERRM" description="Babble error mask" start="8" size="1" />
+      <BitField name="FRMORM" description="Frame overrun mask" start="9" size="1" />
+      <BitField name="DTERRM" description="Data toggle error mask" start="10" size="1" />
+    </Register>
+    <Register name="OTG_HS_HCINTMSK7" description="OTG_HS host channel-7 interrupt mask register" start="+0x1EC" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRCM" description="Transfer completed mask" start="0" size="1" />
+      <BitField name="CHHM" description="Channel halted mask" start="1" size="1" />
+      <BitField name="AHBERR" description="AHB error" start="2" size="1" />
+      <BitField name="STALLM" description="STALL response received interrupt mask" start="3" size="1" />
+      <BitField name="NAKM" description="NAK response received interrupt mask" start="4" size="1" />
+      <BitField name="ACKM" description="ACK response received/transmitted interrupt mask" start="5" size="1" />
+      <BitField name="NYET" description="response received interrupt mask" start="6" size="1" />
+      <BitField name="TXERRM" description="Transaction error mask" start="7" size="1" />
+      <BitField name="BBERRM" description="Babble error mask" start="8" size="1" />
+      <BitField name="FRMORM" description="Frame overrun mask" start="9" size="1" />
+      <BitField name="DTERRM" description="Data toggle error mask" start="10" size="1" />
+    </Register>
+    <Register name="OTG_HS_HCINTMSK8" description="OTG_HS host channel-8 interrupt mask register" start="+0x20C" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRCM" description="Transfer completed mask" start="0" size="1" />
+      <BitField name="CHHM" description="Channel halted mask" start="1" size="1" />
+      <BitField name="AHBERR" description="AHB error" start="2" size="1" />
+      <BitField name="STALLM" description="STALL response received interrupt mask" start="3" size="1" />
+      <BitField name="NAKM" description="NAK response received interrupt mask" start="4" size="1" />
+      <BitField name="ACKM" description="ACK response received/transmitted interrupt mask" start="5" size="1" />
+      <BitField name="NYET" description="response received interrupt mask" start="6" size="1" />
+      <BitField name="TXERRM" description="Transaction error mask" start="7" size="1" />
+      <BitField name="BBERRM" description="Babble error mask" start="8" size="1" />
+      <BitField name="FRMORM" description="Frame overrun mask" start="9" size="1" />
+      <BitField name="DTERRM" description="Data toggle error mask" start="10" size="1" />
+    </Register>
+    <Register name="OTG_HS_HCINTMSK9" description="OTG_HS host channel-9 interrupt mask register" start="+0x22C" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRCM" description="Transfer completed mask" start="0" size="1" />
+      <BitField name="CHHM" description="Channel halted mask" start="1" size="1" />
+      <BitField name="AHBERR" description="AHB error" start="2" size="1" />
+      <BitField name="STALLM" description="STALL response received interrupt mask" start="3" size="1" />
+      <BitField name="NAKM" description="NAK response received interrupt mask" start="4" size="1" />
+      <BitField name="ACKM" description="ACK response received/transmitted interrupt mask" start="5" size="1" />
+      <BitField name="NYET" description="response received interrupt mask" start="6" size="1" />
+      <BitField name="TXERRM" description="Transaction error mask" start="7" size="1" />
+      <BitField name="BBERRM" description="Babble error mask" start="8" size="1" />
+      <BitField name="FRMORM" description="Frame overrun mask" start="9" size="1" />
+      <BitField name="DTERRM" description="Data toggle error mask" start="10" size="1" />
+    </Register>
+    <Register name="OTG_HS_HCINTMSK10" description="OTG_HS host channel-10 interrupt mask register" start="+0x24C" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRCM" description="Transfer completed mask" start="0" size="1" />
+      <BitField name="CHHM" description="Channel halted mask" start="1" size="1" />
+      <BitField name="AHBERR" description="AHB error" start="2" size="1" />
+      <BitField name="STALLM" description="STALL response received interrupt mask" start="3" size="1" />
+      <BitField name="NAKM" description="NAK response received interrupt mask" start="4" size="1" />
+      <BitField name="ACKM" description="ACK response received/transmitted interrupt mask" start="5" size="1" />
+      <BitField name="NYET" description="response received interrupt mask" start="6" size="1" />
+      <BitField name="TXERRM" description="Transaction error mask" start="7" size="1" />
+      <BitField name="BBERRM" description="Babble error mask" start="8" size="1" />
+      <BitField name="FRMORM" description="Frame overrun mask" start="9" size="1" />
+      <BitField name="DTERRM" description="Data toggle error mask" start="10" size="1" />
+    </Register>
+    <Register name="OTG_HS_HCINTMSK11" description="OTG_HS host channel-11 interrupt mask register" start="+0x26C" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRCM" description="Transfer completed mask" start="0" size="1" />
+      <BitField name="CHHM" description="Channel halted mask" start="1" size="1" />
+      <BitField name="AHBERR" description="AHB error" start="2" size="1" />
+      <BitField name="STALLM" description="STALL response received interrupt mask" start="3" size="1" />
+      <BitField name="NAKM" description="NAK response received interrupt mask" start="4" size="1" />
+      <BitField name="ACKM" description="ACK response received/transmitted interrupt mask" start="5" size="1" />
+      <BitField name="NYET" description="response received interrupt mask" start="6" size="1" />
+      <BitField name="TXERRM" description="Transaction error mask" start="7" size="1" />
+      <BitField name="BBERRM" description="Babble error mask" start="8" size="1" />
+      <BitField name="FRMORM" description="Frame overrun mask" start="9" size="1" />
+      <BitField name="DTERRM" description="Data toggle error mask" start="10" size="1" />
+    </Register>
+    <Register name="OTG_HS_HCTSIZ0" description="OTG_HS host channel-11 transfer size register" start="+0x110" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRSIZ" description="Transfer size" start="0" size="19" />
+      <BitField name="PKTCNT" description="Packet count" start="19" size="10" />
+      <BitField name="DPID" description="Data PID" start="29" size="2" />
+    </Register>
+    <Register name="OTG_HS_HCTSIZ1" description="OTG_HS host channel-1 transfer size register" start="+0x130" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRSIZ" description="Transfer size" start="0" size="19" />
+      <BitField name="PKTCNT" description="Packet count" start="19" size="10" />
+      <BitField name="DPID" description="Data PID" start="29" size="2" />
+    </Register>
+    <Register name="OTG_HS_HCTSIZ2" description="OTG_HS host channel-2 transfer size register" start="+0x150" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRSIZ" description="Transfer size" start="0" size="19" />
+      <BitField name="PKTCNT" description="Packet count" start="19" size="10" />
+      <BitField name="DPID" description="Data PID" start="29" size="2" />
+    </Register>
+    <Register name="OTG_HS_HCTSIZ3" description="OTG_HS host channel-3 transfer size register" start="+0x170" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRSIZ" description="Transfer size" start="0" size="19" />
+      <BitField name="PKTCNT" description="Packet count" start="19" size="10" />
+      <BitField name="DPID" description="Data PID" start="29" size="2" />
+    </Register>
+    <Register name="OTG_HS_HCTSIZ4" description="OTG_HS host channel-4 transfer size register" start="+0x190" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRSIZ" description="Transfer size" start="0" size="19" />
+      <BitField name="PKTCNT" description="Packet count" start="19" size="10" />
+      <BitField name="DPID" description="Data PID" start="29" size="2" />
+    </Register>
+    <Register name="OTG_HS_HCTSIZ5" description="OTG_HS host channel-5 transfer size register" start="+0x1B0" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRSIZ" description="Transfer size" start="0" size="19" />
+      <BitField name="PKTCNT" description="Packet count" start="19" size="10" />
+      <BitField name="DPID" description="Data PID" start="29" size="2" />
+    </Register>
+    <Register name="OTG_HS_HCTSIZ6" description="OTG_HS host channel-6 transfer size register" start="+0x1D0" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRSIZ" description="Transfer size" start="0" size="19" />
+      <BitField name="PKTCNT" description="Packet count" start="19" size="10" />
+      <BitField name="DPID" description="Data PID" start="29" size="2" />
+    </Register>
+    <Register name="OTG_HS_HCTSIZ7" description="OTG_HS host channel-7 transfer size register" start="+0x1F0" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRSIZ" description="Transfer size" start="0" size="19" />
+      <BitField name="PKTCNT" description="Packet count" start="19" size="10" />
+      <BitField name="DPID" description="Data PID" start="29" size="2" />
+    </Register>
+    <Register name="OTG_HS_HCTSIZ8" description="OTG_HS host channel-8 transfer size register" start="+0x210" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRSIZ" description="Transfer size" start="0" size="19" />
+      <BitField name="PKTCNT" description="Packet count" start="19" size="10" />
+      <BitField name="DPID" description="Data PID" start="29" size="2" />
+    </Register>
+    <Register name="OTG_HS_HCTSIZ9" description="OTG_HS host channel-9 transfer size register" start="+0x230" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRSIZ" description="Transfer size" start="0" size="19" />
+      <BitField name="PKTCNT" description="Packet count" start="19" size="10" />
+      <BitField name="DPID" description="Data PID" start="29" size="2" />
+    </Register>
+    <Register name="OTG_HS_HCTSIZ10" description="OTG_HS host channel-10 transfer size register" start="+0x250" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRSIZ" description="Transfer size" start="0" size="19" />
+      <BitField name="PKTCNT" description="Packet count" start="19" size="10" />
+      <BitField name="DPID" description="Data PID" start="29" size="2" />
+    </Register>
+    <Register name="OTG_HS_HCTSIZ11" description="OTG_HS host channel-11 transfer size register" start="+0x270" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRSIZ" description="Transfer size" start="0" size="19" />
+      <BitField name="PKTCNT" description="Packet count" start="19" size="10" />
+      <BitField name="DPID" description="Data PID" start="29" size="2" />
+    </Register>
+    <Register name="OTG_HS_HCDMA0" description="OTG_HS host channel-0 DMA address register" start="+0x114" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAADDR" description="DMA address" start="0" size="32" />
+    </Register>
+    <Register name="OTG_HS_HCDMA1" description="OTG_HS host channel-1 DMA address register" start="+0x134" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAADDR" description="DMA address" start="0" size="32" />
+    </Register>
+    <Register name="OTG_HS_HCDMA2" description="OTG_HS host channel-2 DMA address register" start="+0x154" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAADDR" description="DMA address" start="0" size="32" />
+    </Register>
+    <Register name="OTG_HS_HCDMA3" description="OTG_HS host channel-3 DMA address register" start="+0x174" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAADDR" description="DMA address" start="0" size="32" />
+    </Register>
+    <Register name="OTG_HS_HCDMA4" description="OTG_HS host channel-4 DMA address register" start="+0x194" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAADDR" description="DMA address" start="0" size="32" />
+    </Register>
+    <Register name="OTG_HS_HCDMA5" description="OTG_HS host channel-5 DMA address register" start="+0x1B4" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAADDR" description="DMA address" start="0" size="32" />
+    </Register>
+    <Register name="OTG_HS_HCDMA6" description="OTG_HS host channel-6 DMA address register" start="+0x1D4" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAADDR" description="DMA address" start="0" size="32" />
+    </Register>
+    <Register name="OTG_HS_HCDMA7" description="OTG_HS host channel-7 DMA address register" start="+0x1F4" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAADDR" description="DMA address" start="0" size="32" />
+    </Register>
+    <Register name="OTG_HS_HCDMA8" description="OTG_HS host channel-8 DMA address register" start="+0x214" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAADDR" description="DMA address" start="0" size="32" />
+    </Register>
+    <Register name="OTG_HS_HCDMA9" description="OTG_HS host channel-9 DMA address register" start="+0x234" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAADDR" description="DMA address" start="0" size="32" />
+    </Register>
+    <Register name="OTG_HS_HCDMA10" description="OTG_HS host channel-10 DMA address register" start="+0x254" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAADDR" description="DMA address" start="0" size="32" />
+    </Register>
+    <Register name="OTG_HS_HCDMA11" description="OTG_HS host channel-11 DMA address register" start="+0x274" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAADDR" description="DMA address" start="0" size="32" />
+    </Register>
+    <Register name="OTG_HS_HCCHAR12" description="OTG_HS host channel-12 characteristics register" start="+0x278" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" />
+      <BitField name="EPNUM" description="Endpoint number" start="11" size="4" />
+      <BitField name="EPDIR" description="Endpoint direction" start="15" size="1" />
+      <BitField name="LSDEV" description="Low-speed device" start="17" size="1" />
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" />
+      <BitField name="MC" description="Multi Count (MC) / Error Count (EC)" start="20" size="2" />
+      <BitField name="DAD" description="Device address" start="22" size="7" />
+      <BitField name="ODDFRM" description="Odd frame" start="29" size="1" />
+      <BitField name="CHDIS" description="Channel disable" start="30" size="1" />
+      <BitField name="CHENA" description="Channel enable" start="31" size="1" />
+    </Register>
+    <Register name="OTG_HS_HCSPLT12" description="OTG_HS host channel-12 split control register" start="+0x27C" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="PRTADDR" description="Port address" start="0" size="7" />
+      <BitField name="HUBADDR" description="Hub address" start="7" size="7" />
+      <BitField name="XACTPOS" description="XACTPOS" start="14" size="2" />
+      <BitField name="COMPLSPLT" description="Do complete split" start="16" size="1" />
+      <BitField name="SPLITEN" description="Split enable" start="31" size="1" />
+    </Register>
+    <Register name="OTG_HS_HCINT12" description="OTG_HS host channel-12 interrupt register" start="+0x280" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRC" description="Transfer completed" start="0" size="1" />
+      <BitField name="CHH" description="Channel halted" start="1" size="1" />
+      <BitField name="AHBERR" description="AHB error" start="2" size="1" />
+      <BitField name="STALL" description="STALL response received interrupt" start="3" size="1" />
+      <BitField name="NAK" description="NAK response received interrupt" start="4" size="1" />
+      <BitField name="ACK" description="ACK response received/transmitted interrupt" start="5" size="1" />
+      <BitField name="NYET" description="Response received interrupt" start="6" size="1" />
+      <BitField name="TXERR" description="Transaction error" start="7" size="1" />
+      <BitField name="BBERR" description="Babble error" start="8" size="1" />
+      <BitField name="FRMOR" description="Frame overrun" start="9" size="1" />
+      <BitField name="DTERR" description="Data toggle error" start="10" size="1" />
+    </Register>
+    <Register name="OTG_HS_HCINTMSK12" description="OTG_HS host channel-12 interrupt mask register" start="+0x284" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRCM" description="Transfer completed mask" start="0" size="1" />
+      <BitField name="CHHM" description="Channel halted mask" start="1" size="1" />
+      <BitField name="AHBERR" description="AHB error" start="2" size="1" />
+      <BitField name="STALLM" description="STALL response received interrupt mask" start="3" size="1" />
+      <BitField name="NAKM" description="NAK response received interrupt mask" start="4" size="1" />
+      <BitField name="ACKM" description="ACK response received/transmitted interrupt mask" start="5" size="1" />
+      <BitField name="NYET" description="Response received interrupt" start="6" size="1" />
+      <BitField name="TXERRM" description="Transaction error" start="7" size="1" />
+      <BitField name="BBERRM" description="Babble error" start="8" size="1" />
+      <BitField name="FRMORM" description="Frame overrun mask" start="9" size="1" />
+      <BitField name="DTERRM" description="Data toggle error mask" start="10" size="1" />
+    </Register>
+    <Register name="OTG_HS_HCTSIZ12" description="OTG_HS host channel-12 transfer size register" start="+0x288" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRSIZ" description="Transfer size" start="0" size="19" />
+      <BitField name="PKTCNT" description="Packet count" start="19" size="10" />
+      <BitField name="DPID" description="Data PID" start="29" size="2" />
+    </Register>
+    <Register name="OTG_HS_HCDMA12" description="OTG_HS host channel-12 DMA address register" start="+0x28C" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAADDR" description="DMA address" start="0" size="32" />
+    </Register>
+    <Register name="OTG_HS_HCCHAR13" description="OTG_HS host channel-13 characteristics register" start="+0x290" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" />
+      <BitField name="EPNUM" description="Endpoint number" start="11" size="4" />
+      <BitField name="EPDIR" description="Endpoint direction" start="15" size="1" />
+      <BitField name="LSDEV" description="Low-speed device" start="17" size="1" />
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" />
+      <BitField name="MC" description="Multi Count (MC) / Error Count (EC)" start="20" size="2" />
+      <BitField name="DAD" description="Device address" start="22" size="7" />
+      <BitField name="ODDFRM" description="Odd frame" start="29" size="1" />
+      <BitField name="CHDIS" description="Channel disable" start="30" size="1" />
+      <BitField name="CHENA" description="Channel enable" start="31" size="1" />
+    </Register>
+    <Register name="OTG_HS_HCSPLT13" description="OTG_HS host channel-13 split control register" start="+0x294" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="PRTADDR" description="Port address" start="0" size="7" />
+      <BitField name="HUBADDR" description="Hub address" start="7" size="7" />
+      <BitField name="XACTPOS" description="XACTPOS" start="14" size="2" />
+      <BitField name="COMPLSPLT" description="Do complete split" start="16" size="1" />
+      <BitField name="SPLITEN" description="Split enable" start="31" size="1" />
+    </Register>
+    <Register name="OTG_HS_HCINT13" description="OTG_HS host channel-13 interrupt register" start="+0x298" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRC" description="Transfer completed" start="0" size="1" />
+      <BitField name="CHH" description="Channel halted" start="1" size="1" />
+      <BitField name="AHBERR" description="AHB error" start="2" size="1" />
+      <BitField name="STALL" description="STALL response received interrupt" start="3" size="1" />
+      <BitField name="NAK" description="NAK response received interrupt" start="4" size="1" />
+      <BitField name="ACK" description="ACK response received/transmitted interrupt" start="5" size="1" />
+      <BitField name="NYET" description="Response received interrupt" start="6" size="1" />
+      <BitField name="TXERR" description="Transaction error" start="7" size="1" />
+      <BitField name="BBERR" description="Babble error" start="8" size="1" />
+      <BitField name="FRMOR" description="Frame overrun" start="9" size="1" />
+      <BitField name="DTERR" description="Data toggle error" start="10" size="1" />
+    </Register>
+    <Register name="OTG_HS_HCINTMSK13" description="OTG_HS host channel-13 interrupt mask register" start="+0x29C" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRCM" description="Transfer completed mask" start="0" size="1" />
+      <BitField name="CHHM" description="Channel halted mask" start="1" size="1" />
+      <BitField name="AHBERR" description="AHB error" start="2" size="1" />
+      <BitField name="STALLM" description="STALLM response received interrupt mask" start="3" size="1" />
+      <BitField name="NAKM" description="NAK response received interrupt mask" start="4" size="1" />
+      <BitField name="ACKM" description="ACK response received/transmitted interrupt mask" start="5" size="1" />
+      <BitField name="NYET" description="Response received interrupt" start="6" size="1" />
+      <BitField name="TXERRM" description="Transaction error" start="7" size="1" />
+      <BitField name="BBERRM" description="Babble error" start="8" size="1" />
+      <BitField name="FRMORM" description="Frame overrun mask" start="9" size="1" />
+      <BitField name="DTERRM" description="Data toggle error mask" start="10" size="1" />
+    </Register>
+    <Register name="OTG_HS_HCTSIZ13" description="OTG_HS host channel-13 transfer size register" start="+0x2A0" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRSIZ" description="Transfer size" start="0" size="19" />
+      <BitField name="PKTCNT" description="Packet count" start="19" size="10" />
+      <BitField name="DPID" description="Data PID" start="29" size="2" />
+    </Register>
+    <Register name="OTG_HS_HCDMA13" description="OTG_HS host channel-13 DMA address register" start="+0x2A4" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAADDR" description="DMA address" start="0" size="32" />
+    </Register>
+    <Register name="OTG_HS_HCCHAR14" description="OTG_HS host channel-14 characteristics register" start="+0x2A8" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" />
+      <BitField name="EPNUM" description="Endpoint number" start="11" size="4" />
+      <BitField name="EPDIR" description="Endpoint direction" start="15" size="1" />
+      <BitField name="LSDEV" description="Low-speed device" start="17" size="1" />
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" />
+      <BitField name="MC" description="Multi Count (MC) / Error Count (EC)" start="20" size="2" />
+      <BitField name="DAD" description="Device address" start="22" size="7" />
+      <BitField name="ODDFRM" description="Odd frame" start="29" size="1" />
+      <BitField name="CHDIS" description="Channel disable" start="30" size="1" />
+      <BitField name="CHENA" description="Channel enable" start="31" size="1" />
+    </Register>
+    <Register name="OTG_HS_HCSPLT14" description="OTG_HS host channel-14 split control register" start="+0x2AC" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="PRTADDR" description="Port address" start="0" size="7" />
+      <BitField name="HUBADDR" description="Hub address" start="7" size="7" />
+      <BitField name="XACTPOS" description="XACTPOS" start="14" size="2" />
+      <BitField name="COMPLSPLT" description="Do complete split" start="16" size="1" />
+      <BitField name="SPLITEN" description="Split enable" start="31" size="1" />
+    </Register>
+    <Register name="OTG_HS_HCINT14" description="OTG_HS host channel-14 interrupt register" start="+0x2B0" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRC" description="Transfer completed" start="0" size="1" />
+      <BitField name="CHH" description="Channel halted" start="1" size="1" />
+      <BitField name="AHBERR" description="AHB error" start="2" size="1" />
+      <BitField name="STALL" description="STALL response received interrupt" start="3" size="1" />
+      <BitField name="NAK" description="NAK response received interrupt" start="4" size="1" />
+      <BitField name="ACK" description="ACK response received/transmitted interrupt" start="5" size="1" />
+      <BitField name="NYET" description="Response received interrupt" start="6" size="1" />
+      <BitField name="TXERR" description="Transaction error" start="7" size="1" />
+      <BitField name="BBERR" description="Babble error" start="8" size="1" />
+      <BitField name="FRMOR" description="Frame overrun" start="9" size="1" />
+      <BitField name="DTERR" description="Data toggle error" start="10" size="1" />
+    </Register>
+    <Register name="OTG_HS_HCINTMSK14" description="OTG_HS host channel-14 interrupt mask register" start="+0x2B4" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRCM" description="Transfer completed mask" start="0" size="1" />
+      <BitField name="CHHM" description="Channel halted mask" start="1" size="1" />
+      <BitField name="AHBERR" description="AHB error" start="2" size="1" />
+      <BitField name="STALLM" description="STALL response received interrupt mask" start="3" size="1" />
+      <BitField name="NAKM" description="NAKM response received interrupt mask" start="4" size="1" />
+      <BitField name="ACKM" description="ACKM response received/transmitted interrupt mask" start="5" size="1" />
+      <BitField name="NYET" description="Response received interrupt" start="6" size="1" />
+      <BitField name="TXERRM" description="Transaction error" start="7" size="1" />
+      <BitField name="BBERRM" description="Babble error" start="8" size="1" />
+      <BitField name="FRMORM" description="Frame overrun mask" start="9" size="1" />
+      <BitField name="DTERRM" description="Data toggle error mask" start="10" size="1" />
+    </Register>
+    <Register name="OTG_HS_HCTSIZ14" description="OTG_HS host channel-14 transfer size register" start="+0x2B8" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRSIZ" description="Transfer size" start="0" size="19" />
+      <BitField name="PKTCNT" description="Packet count" start="19" size="10" />
+      <BitField name="DPID" description="Data PID" start="29" size="2" />
+    </Register>
+    <Register name="OTG_HS_HCDMA14" description="OTG_HS host channel-14 DMA address register" start="+0x2BC" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAADDR" description="DMA address" start="0" size="32" />
+    </Register>
+    <Register name="OTG_HS_HCCHAR15" description="OTG_HS host channel-15 characteristics register" start="+0x2C0" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" />
+      <BitField name="EPNUM" description="Endpoint number" start="11" size="4" />
+      <BitField name="EPDIR" description="Endpoint direction" start="15" size="1" />
+      <BitField name="LSDEV" description="Low-speed device" start="17" size="1" />
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" />
+      <BitField name="MC" description="Multi Count (MC) / Error Count (EC)" start="20" size="2" />
+      <BitField name="DAD" description="Device address" start="22" size="7" />
+      <BitField name="ODDFRM" description="Odd frame" start="29" size="1" />
+      <BitField name="CHDIS" description="Channel disable" start="30" size="1" />
+      <BitField name="CHENA" description="Channel enable" start="31" size="1" />
+    </Register>
+    <Register name="OTG_HS_HCSPLT15" description="OTG_HS host channel-15 split control register" start="+0x2C4" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="PRTADDR" description="Port address" start="0" size="7" />
+      <BitField name="HUBADDR" description="Hub address" start="7" size="7" />
+      <BitField name="XACTPOS" description="XACTPOS" start="14" size="2" />
+      <BitField name="COMPLSPLT" description="Do complete split" start="16" size="1" />
+      <BitField name="SPLITEN" description="Split enable" start="31" size="1" />
+    </Register>
+    <Register name="OTG_HS_HCINT15" description="OTG_HS host channel-15 interrupt register" start="+0x2C8" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRC" description="Transfer completed" start="0" size="1" />
+      <BitField name="CHH" description="Channel halted" start="1" size="1" />
+      <BitField name="AHBERR" description="AHB error" start="2" size="1" />
+      <BitField name="STALL" description="STALL response received interrupt" start="3" size="1" />
+      <BitField name="NAK" description="NAK response received interrupt" start="4" size="1" />
+      <BitField name="ACK" description="ACK response received/transmitted interrupt" start="5" size="1" />
+      <BitField name="NYET" description="Response received interrupt" start="6" size="1" />
+      <BitField name="TXERR" description="Transaction error" start="7" size="1" />
+      <BitField name="BBERR" description="Babble error" start="8" size="1" />
+      <BitField name="FRMOR" description="Frame overrun" start="9" size="1" />
+      <BitField name="DTERR" description="Data toggle error" start="10" size="1" />
+    </Register>
+    <Register name="OTG_HS_HCINTMSK15" description="OTG_HS host channel-15 interrupt mask register" start="+0x2CC" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRCM" description="Transfer completed mask" start="0" size="1" />
+      <BitField name="CHHM" description="Channel halted mask" start="1" size="1" />
+      <BitField name="AHBERR" description="AHB error" start="2" size="1" />
+      <BitField name="STALL" description="STALL response received interrupt mask" start="3" size="1" />
+      <BitField name="NAKM" description="NAK response received interrupt mask" start="4" size="1" />
+      <BitField name="ACKM" description="ACK response received/transmitted interrupt mask" start="5" size="1" />
+      <BitField name="NYET" description="Response received interrupt" start="6" size="1" />
+      <BitField name="TXERRM" description="Transaction error" start="7" size="1" />
+      <BitField name="BBERRM" description="Babble error" start="8" size="1" />
+      <BitField name="FRMORM" description="Frame overrun mask" start="9" size="1" />
+      <BitField name="DTERRM" description="Data toggle error mask" start="10" size="1" />
+    </Register>
+    <Register name="OTG_HS_HCTSIZ15" description="OTG_HS host channel-15 transfer size register" start="+0x2D0" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRSIZ" description="Transfer size" start="0" size="19" />
+      <BitField name="PKTCNT" description="Packet count" start="19" size="10" />
+      <BitField name="DPID" description="Data PID" start="29" size="2" />
+    </Register>
+    <Register name="OTG_HS_HCDMA15" description="OTG_HS host channel-15 DMA address register" start="+0x2D4" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAADDR" description="DMA address" start="0" size="32" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="OTG2_HS_HOST" description="USB 1 on the go high speed" start="0x40080400">
+    <Register name="OTG_HS_HCFG" description="OTG_HS host configuration register" start="+0x0" size="4" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="FSLSPCS" description="FS/LS PHY clock select" start="0" size="2" access="Read/Write" />
+      <BitField name="FSLSS" description="FS- and LS-only support" start="2" size="1" access="ReadOnly" />
+    </Register>
+    <Register name="OTG_HS_HFIR" description="OTG_HS Host frame interval register" start="+0x4" size="4" access="Read/Write" reset_value="0x0000EA60" reset_mask="0xFFFFFFFF">
+      <BitField name="FRIVL" description="Frame interval" start="0" size="16" />
+    </Register>
+    <Register name="OTG_HS_HFNUM" description="OTG_HS host frame number/frame time remaining register" start="+0x8" size="4" access="ReadOnly" reset_value="0x00003FFF" reset_mask="0xFFFFFFFF">
+      <BitField name="FRNUM" description="Frame number" start="0" size="16" />
+      <BitField name="FTREM" description="Frame time remaining" start="16" size="16" />
+    </Register>
+    <Register name="OTG_HS_HPTXSTS" description="OTG_HS_Host periodic transmit FIFO/queue status register" start="+0x10" size="4" reset_value="0x00080100" reset_mask="0xFFFFFFFF">
+      <BitField name="PTXFSAVL" description="Periodic transmit data FIFO space available" start="0" size="16" access="Read/Write" />
+      <BitField name="PTXQSAV" description="Periodic transmit request queue space available" start="16" size="8" access="ReadOnly" />
+      <BitField name="PTXQTOP" description="Top of the periodic transmit request queue" start="24" size="8" access="ReadOnly" />
+    </Register>
+    <Register name="OTG_HS_HAINT" description="OTG_HS Host all channels interrupt register" start="+0x14" size="4" access="ReadOnly" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="HAINT" description="Channel interrupts" start="0" size="16" />
+    </Register>
+    <Register name="OTG_HS_HAINTMSK" description="OTG_HS host all channels interrupt mask register" start="+0x18" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="HAINTM" description="Channel interrupt mask" start="0" size="16" />
+    </Register>
+    <Register name="OTG_HS_HPRT" description="OTG_HS host port control and status register" start="+0x40" size="4" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="PCSTS" description="Port connect status" start="0" size="1" access="ReadOnly" />
+      <BitField name="PCDET" description="Port connect detected" start="1" size="1" access="Read/Write" />
+      <BitField name="PENA" description="Port enable" start="2" size="1" access="Read/Write" />
+      <BitField name="PENCHNG" description="Port enable/disable change" start="3" size="1" access="Read/Write" />
+      <BitField name="POCA" description="Port overcurrent active" start="4" size="1" access="ReadOnly" />
+      <BitField name="POCCHNG" description="Port overcurrent change" start="5" size="1" access="Read/Write" />
+      <BitField name="PRES" description="Port resume" start="6" size="1" access="Read/Write" />
+      <BitField name="PSUSP" description="Port suspend" start="7" size="1" access="Read/Write" />
+      <BitField name="PRST" description="Port reset" start="8" size="1" access="Read/Write" />
+      <BitField name="PLSTS" description="Port line status" start="10" size="2" access="ReadOnly" />
+      <BitField name="PPWR" description="Port power" start="12" size="1" access="Read/Write" />
+      <BitField name="PTCTL" description="Port test control" start="13" size="4" access="Read/Write" />
+      <BitField name="PSPD" description="Port speed" start="17" size="2" access="ReadOnly" />
+    </Register>
+    <Register name="OTG_HS_HCCHAR0" description="OTG_HS host channel-0 characteristics register" start="+0x100" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" />
+      <BitField name="EPNUM" description="Endpoint number" start="11" size="4" />
+      <BitField name="EPDIR" description="Endpoint direction" start="15" size="1" />
+      <BitField name="LSDEV" description="Low-speed device" start="17" size="1" />
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" />
+      <BitField name="MC" description="Multi Count (MC) / Error Count (EC)" start="20" size="2" />
+      <BitField name="DAD" description="Device address" start="22" size="7" />
+      <BitField name="ODDFRM" description="Odd frame" start="29" size="1" />
+      <BitField name="CHDIS" description="Channel disable" start="30" size="1" />
+      <BitField name="CHENA" description="Channel enable" start="31" size="1" />
+    </Register>
+    <Register name="OTG_HS_HCCHAR1" description="OTG_HS host channel-1 characteristics register" start="+0x120" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" />
+      <BitField name="EPNUM" description="Endpoint number" start="11" size="4" />
+      <BitField name="EPDIR" description="Endpoint direction" start="15" size="1" />
+      <BitField name="LSDEV" description="Low-speed device" start="17" size="1" />
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" />
+      <BitField name="MC" description="Multi Count (MC) / Error Count (EC)" start="20" size="2" />
+      <BitField name="DAD" description="Device address" start="22" size="7" />
+      <BitField name="ODDFRM" description="Odd frame" start="29" size="1" />
+      <BitField name="CHDIS" description="Channel disable" start="30" size="1" />
+      <BitField name="CHENA" description="Channel enable" start="31" size="1" />
+    </Register>
+    <Register name="OTG_HS_HCCHAR2" description="OTG_HS host channel-2 characteristics register" start="+0x140" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" />
+      <BitField name="EPNUM" description="Endpoint number" start="11" size="4" />
+      <BitField name="EPDIR" description="Endpoint direction" start="15" size="1" />
+      <BitField name="LSDEV" description="Low-speed device" start="17" size="1" />
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" />
+      <BitField name="MC" description="Multi Count (MC) / Error Count (EC)" start="20" size="2" />
+      <BitField name="DAD" description="Device address" start="22" size="7" />
+      <BitField name="ODDFRM" description="Odd frame" start="29" size="1" />
+      <BitField name="CHDIS" description="Channel disable" start="30" size="1" />
+      <BitField name="CHENA" description="Channel enable" start="31" size="1" />
+    </Register>
+    <Register name="OTG_HS_HCCHAR3" description="OTG_HS host channel-3 characteristics register" start="+0x160" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" />
+      <BitField name="EPNUM" description="Endpoint number" start="11" size="4" />
+      <BitField name="EPDIR" description="Endpoint direction" start="15" size="1" />
+      <BitField name="LSDEV" description="Low-speed device" start="17" size="1" />
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" />
+      <BitField name="MC" description="Multi Count (MC) / Error Count (EC)" start="20" size="2" />
+      <BitField name="DAD" description="Device address" start="22" size="7" />
+      <BitField name="ODDFRM" description="Odd frame" start="29" size="1" />
+      <BitField name="CHDIS" description="Channel disable" start="30" size="1" />
+      <BitField name="CHENA" description="Channel enable" start="31" size="1" />
+    </Register>
+    <Register name="OTG_HS_HCCHAR4" description="OTG_HS host channel-4 characteristics register" start="+0x180" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" />
+      <BitField name="EPNUM" description="Endpoint number" start="11" size="4" />
+      <BitField name="EPDIR" description="Endpoint direction" start="15" size="1" />
+      <BitField name="LSDEV" description="Low-speed device" start="17" size="1" />
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" />
+      <BitField name="MC" description="Multi Count (MC) / Error Count (EC)" start="20" size="2" />
+      <BitField name="DAD" description="Device address" start="22" size="7" />
+      <BitField name="ODDFRM" description="Odd frame" start="29" size="1" />
+      <BitField name="CHDIS" description="Channel disable" start="30" size="1" />
+      <BitField name="CHENA" description="Channel enable" start="31" size="1" />
+    </Register>
+    <Register name="OTG_HS_HCCHAR5" description="OTG_HS host channel-5 characteristics register" start="+0x1A0" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" />
+      <BitField name="EPNUM" description="Endpoint number" start="11" size="4" />
+      <BitField name="EPDIR" description="Endpoint direction" start="15" size="1" />
+      <BitField name="LSDEV" description="Low-speed device" start="17" size="1" />
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" />
+      <BitField name="MC" description="Multi Count (MC) / Error Count (EC)" start="20" size="2" />
+      <BitField name="DAD" description="Device address" start="22" size="7" />
+      <BitField name="ODDFRM" description="Odd frame" start="29" size="1" />
+      <BitField name="CHDIS" description="Channel disable" start="30" size="1" />
+      <BitField name="CHENA" description="Channel enable" start="31" size="1" />
+    </Register>
+    <Register name="OTG_HS_HCCHAR6" description="OTG_HS host channel-6 characteristics register" start="+0x1C0" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" />
+      <BitField name="EPNUM" description="Endpoint number" start="11" size="4" />
+      <BitField name="EPDIR" description="Endpoint direction" start="15" size="1" />
+      <BitField name="LSDEV" description="Low-speed device" start="17" size="1" />
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" />
+      <BitField name="MC" description="Multi Count (MC) / Error Count (EC)" start="20" size="2" />
+      <BitField name="DAD" description="Device address" start="22" size="7" />
+      <BitField name="ODDFRM" description="Odd frame" start="29" size="1" />
+      <BitField name="CHDIS" description="Channel disable" start="30" size="1" />
+      <BitField name="CHENA" description="Channel enable" start="31" size="1" />
+    </Register>
+    <Register name="OTG_HS_HCCHAR7" description="OTG_HS host channel-7 characteristics register" start="+0x1E0" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" />
+      <BitField name="EPNUM" description="Endpoint number" start="11" size="4" />
+      <BitField name="EPDIR" description="Endpoint direction" start="15" size="1" />
+      <BitField name="LSDEV" description="Low-speed device" start="17" size="1" />
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" />
+      <BitField name="MC" description="Multi Count (MC) / Error Count (EC)" start="20" size="2" />
+      <BitField name="DAD" description="Device address" start="22" size="7" />
+      <BitField name="ODDFRM" description="Odd frame" start="29" size="1" />
+      <BitField name="CHDIS" description="Channel disable" start="30" size="1" />
+      <BitField name="CHENA" description="Channel enable" start="31" size="1" />
+    </Register>
+    <Register name="OTG_HS_HCCHAR8" description="OTG_HS host channel-8 characteristics register" start="+0x200" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" />
+      <BitField name="EPNUM" description="Endpoint number" start="11" size="4" />
+      <BitField name="EPDIR" description="Endpoint direction" start="15" size="1" />
+      <BitField name="LSDEV" description="Low-speed device" start="17" size="1" />
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" />
+      <BitField name="MC" description="Multi Count (MC) / Error Count (EC)" start="20" size="2" />
+      <BitField name="DAD" description="Device address" start="22" size="7" />
+      <BitField name="ODDFRM" description="Odd frame" start="29" size="1" />
+      <BitField name="CHDIS" description="Channel disable" start="30" size="1" />
+      <BitField name="CHENA" description="Channel enable" start="31" size="1" />
+    </Register>
+    <Register name="OTG_HS_HCCHAR9" description="OTG_HS host channel-9 characteristics register" start="+0x220" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" />
+      <BitField name="EPNUM" description="Endpoint number" start="11" size="4" />
+      <BitField name="EPDIR" description="Endpoint direction" start="15" size="1" />
+      <BitField name="LSDEV" description="Low-speed device" start="17" size="1" />
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" />
+      <BitField name="MC" description="Multi Count (MC) / Error Count (EC)" start="20" size="2" />
+      <BitField name="DAD" description="Device address" start="22" size="7" />
+      <BitField name="ODDFRM" description="Odd frame" start="29" size="1" />
+      <BitField name="CHDIS" description="Channel disable" start="30" size="1" />
+      <BitField name="CHENA" description="Channel enable" start="31" size="1" />
+    </Register>
+    <Register name="OTG_HS_HCCHAR10" description="OTG_HS host channel-10 characteristics register" start="+0x240" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" />
+      <BitField name="EPNUM" description="Endpoint number" start="11" size="4" />
+      <BitField name="EPDIR" description="Endpoint direction" start="15" size="1" />
+      <BitField name="LSDEV" description="Low-speed device" start="17" size="1" />
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" />
+      <BitField name="MC" description="Multi Count (MC) / Error Count (EC)" start="20" size="2" />
+      <BitField name="DAD" description="Device address" start="22" size="7" />
+      <BitField name="ODDFRM" description="Odd frame" start="29" size="1" />
+      <BitField name="CHDIS" description="Channel disable" start="30" size="1" />
+      <BitField name="CHENA" description="Channel enable" start="31" size="1" />
+    </Register>
+    <Register name="OTG_HS_HCCHAR11" description="OTG_HS host channel-11 characteristics register" start="+0x260" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" />
+      <BitField name="EPNUM" description="Endpoint number" start="11" size="4" />
+      <BitField name="EPDIR" description="Endpoint direction" start="15" size="1" />
+      <BitField name="LSDEV" description="Low-speed device" start="17" size="1" />
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" />
+      <BitField name="MC" description="Multi Count (MC) / Error Count (EC)" start="20" size="2" />
+      <BitField name="DAD" description="Device address" start="22" size="7" />
+      <BitField name="ODDFRM" description="Odd frame" start="29" size="1" />
+      <BitField name="CHDIS" description="Channel disable" start="30" size="1" />
+      <BitField name="CHENA" description="Channel enable" start="31" size="1" />
+    </Register>
+    <Register name="OTG_HS_HCSPLT0" description="OTG_HS host channel-0 split control register" start="+0x104" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="PRTADDR" description="Port address" start="0" size="7" />
+      <BitField name="HUBADDR" description="Hub address" start="7" size="7" />
+      <BitField name="XACTPOS" description="XACTPOS" start="14" size="2" />
+      <BitField name="COMPLSPLT" description="Do complete split" start="16" size="1" />
+      <BitField name="SPLITEN" description="Split enable" start="31" size="1" />
+    </Register>
+    <Register name="OTG_HS_HCSPLT1" description="OTG_HS host channel-1 split control register" start="+0x124" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="PRTADDR" description="Port address" start="0" size="7" />
+      <BitField name="HUBADDR" description="Hub address" start="7" size="7" />
+      <BitField name="XACTPOS" description="XACTPOS" start="14" size="2" />
+      <BitField name="COMPLSPLT" description="Do complete split" start="16" size="1" />
+      <BitField name="SPLITEN" description="Split enable" start="31" size="1" />
+    </Register>
+    <Register name="OTG_HS_HCSPLT2" description="OTG_HS host channel-2 split control register" start="+0x144" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="PRTADDR" description="Port address" start="0" size="7" />
+      <BitField name="HUBADDR" description="Hub address" start="7" size="7" />
+      <BitField name="XACTPOS" description="XACTPOS" start="14" size="2" />
+      <BitField name="COMPLSPLT" description="Do complete split" start="16" size="1" />
+      <BitField name="SPLITEN" description="Split enable" start="31" size="1" />
+    </Register>
+    <Register name="OTG_HS_HCSPLT3" description="OTG_HS host channel-3 split control register" start="+0x164" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="PRTADDR" description="Port address" start="0" size="7" />
+      <BitField name="HUBADDR" description="Hub address" start="7" size="7" />
+      <BitField name="XACTPOS" description="XACTPOS" start="14" size="2" />
+      <BitField name="COMPLSPLT" description="Do complete split" start="16" size="1" />
+      <BitField name="SPLITEN" description="Split enable" start="31" size="1" />
+    </Register>
+    <Register name="OTG_HS_HCSPLT4" description="OTG_HS host channel-4 split control register" start="+0x184" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="PRTADDR" description="Port address" start="0" size="7" />
+      <BitField name="HUBADDR" description="Hub address" start="7" size="7" />
+      <BitField name="XACTPOS" description="XACTPOS" start="14" size="2" />
+      <BitField name="COMPLSPLT" description="Do complete split" start="16" size="1" />
+      <BitField name="SPLITEN" description="Split enable" start="31" size="1" />
+    </Register>
+    <Register name="OTG_HS_HCSPLT5" description="OTG_HS host channel-5 split control register" start="+0x1A4" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="PRTADDR" description="Port address" start="0" size="7" />
+      <BitField name="HUBADDR" description="Hub address" start="7" size="7" />
+      <BitField name="XACTPOS" description="XACTPOS" start="14" size="2" />
+      <BitField name="COMPLSPLT" description="Do complete split" start="16" size="1" />
+      <BitField name="SPLITEN" description="Split enable" start="31" size="1" />
+    </Register>
+    <Register name="OTG_HS_HCSPLT6" description="OTG_HS host channel-6 split control register" start="+0x1C4" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="PRTADDR" description="Port address" start="0" size="7" />
+      <BitField name="HUBADDR" description="Hub address" start="7" size="7" />
+      <BitField name="XACTPOS" description="XACTPOS" start="14" size="2" />
+      <BitField name="COMPLSPLT" description="Do complete split" start="16" size="1" />
+      <BitField name="SPLITEN" description="Split enable" start="31" size="1" />
+    </Register>
+    <Register name="OTG_HS_HCSPLT7" description="OTG_HS host channel-7 split control register" start="+0x1E4" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="PRTADDR" description="Port address" start="0" size="7" />
+      <BitField name="HUBADDR" description="Hub address" start="7" size="7" />
+      <BitField name="XACTPOS" description="XACTPOS" start="14" size="2" />
+      <BitField name="COMPLSPLT" description="Do complete split" start="16" size="1" />
+      <BitField name="SPLITEN" description="Split enable" start="31" size="1" />
+    </Register>
+    <Register name="OTG_HS_HCSPLT8" description="OTG_HS host channel-8 split control register" start="+0x204" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="PRTADDR" description="Port address" start="0" size="7" />
+      <BitField name="HUBADDR" description="Hub address" start="7" size="7" />
+      <BitField name="XACTPOS" description="XACTPOS" start="14" size="2" />
+      <BitField name="COMPLSPLT" description="Do complete split" start="16" size="1" />
+      <BitField name="SPLITEN" description="Split enable" start="31" size="1" />
+    </Register>
+    <Register name="OTG_HS_HCSPLT9" description="OTG_HS host channel-9 split control register" start="+0x224" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="PRTADDR" description="Port address" start="0" size="7" />
+      <BitField name="HUBADDR" description="Hub address" start="7" size="7" />
+      <BitField name="XACTPOS" description="XACTPOS" start="14" size="2" />
+      <BitField name="COMPLSPLT" description="Do complete split" start="16" size="1" />
+      <BitField name="SPLITEN" description="Split enable" start="31" size="1" />
+    </Register>
+    <Register name="OTG_HS_HCSPLT10" description="OTG_HS host channel-10 split control register" start="+0x244" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="PRTADDR" description="Port address" start="0" size="7" />
+      <BitField name="HUBADDR" description="Hub address" start="7" size="7" />
+      <BitField name="XACTPOS" description="XACTPOS" start="14" size="2" />
+      <BitField name="COMPLSPLT" description="Do complete split" start="16" size="1" />
+      <BitField name="SPLITEN" description="Split enable" start="31" size="1" />
+    </Register>
+    <Register name="OTG_HS_HCSPLT11" description="OTG_HS host channel-11 split control register" start="+0x264" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="PRTADDR" description="Port address" start="0" size="7" />
+      <BitField name="HUBADDR" description="Hub address" start="7" size="7" />
+      <BitField name="XACTPOS" description="XACTPOS" start="14" size="2" />
+      <BitField name="COMPLSPLT" description="Do complete split" start="16" size="1" />
+      <BitField name="SPLITEN" description="Split enable" start="31" size="1" />
+    </Register>
+    <Register name="OTG_HS_HCINT0" description="OTG_HS host channel-11 interrupt register" start="+0x108" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRC" description="Transfer completed" start="0" size="1" />
+      <BitField name="CHH" description="Channel halted" start="1" size="1" />
+      <BitField name="AHBERR" description="AHB error" start="2" size="1" />
+      <BitField name="STALL" description="STALL response received interrupt" start="3" size="1" />
+      <BitField name="NAK" description="NAK response received interrupt" start="4" size="1" />
+      <BitField name="ACK" description="ACK response received/transmitted interrupt" start="5" size="1" />
+      <BitField name="NYET" description="Response received interrupt" start="6" size="1" />
+      <BitField name="TXERR" description="Transaction error" start="7" size="1" />
+      <BitField name="BBERR" description="Babble error" start="8" size="1" />
+      <BitField name="FRMOR" description="Frame overrun" start="9" size="1" />
+      <BitField name="DTERR" description="Data toggle error" start="10" size="1" />
+    </Register>
+    <Register name="OTG_HS_HCINT1" description="OTG_HS host channel-1 interrupt register" start="+0x128" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRC" description="Transfer completed" start="0" size="1" />
+      <BitField name="CHH" description="Channel halted" start="1" size="1" />
+      <BitField name="AHBERR" description="AHB error" start="2" size="1" />
+      <BitField name="STALL" description="STALL response received interrupt" start="3" size="1" />
+      <BitField name="NAK" description="NAK response received interrupt" start="4" size="1" />
+      <BitField name="ACK" description="ACK response received/transmitted interrupt" start="5" size="1" />
+      <BitField name="NYET" description="Response received interrupt" start="6" size="1" />
+      <BitField name="TXERR" description="Transaction error" start="7" size="1" />
+      <BitField name="BBERR" description="Babble error" start="8" size="1" />
+      <BitField name="FRMOR" description="Frame overrun" start="9" size="1" />
+      <BitField name="DTERR" description="Data toggle error" start="10" size="1" />
+    </Register>
+    <Register name="OTG_HS_HCINT2" description="OTG_HS host channel-2 interrupt register" start="+0x148" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRC" description="Transfer completed" start="0" size="1" />
+      <BitField name="CHH" description="Channel halted" start="1" size="1" />
+      <BitField name="AHBERR" description="AHB error" start="2" size="1" />
+      <BitField name="STALL" description="STALL response received interrupt" start="3" size="1" />
+      <BitField name="NAK" description="NAK response received interrupt" start="4" size="1" />
+      <BitField name="ACK" description="ACK response received/transmitted interrupt" start="5" size="1" />
+      <BitField name="NYET" description="Response received interrupt" start="6" size="1" />
+      <BitField name="TXERR" description="Transaction error" start="7" size="1" />
+      <BitField name="BBERR" description="Babble error" start="8" size="1" />
+      <BitField name="FRMOR" description="Frame overrun" start="9" size="1" />
+      <BitField name="DTERR" description="Data toggle error" start="10" size="1" />
+    </Register>
+    <Register name="OTG_HS_HCINT3" description="OTG_HS host channel-3 interrupt register" start="+0x168" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRC" description="Transfer completed" start="0" size="1" />
+      <BitField name="CHH" description="Channel halted" start="1" size="1" />
+      <BitField name="AHBERR" description="AHB error" start="2" size="1" />
+      <BitField name="STALL" description="STALL response received interrupt" start="3" size="1" />
+      <BitField name="NAK" description="NAK response received interrupt" start="4" size="1" />
+      <BitField name="ACK" description="ACK response received/transmitted interrupt" start="5" size="1" />
+      <BitField name="NYET" description="Response received interrupt" start="6" size="1" />
+      <BitField name="TXERR" description="Transaction error" start="7" size="1" />
+      <BitField name="BBERR" description="Babble error" start="8" size="1" />
+      <BitField name="FRMOR" description="Frame overrun" start="9" size="1" />
+      <BitField name="DTERR" description="Data toggle error" start="10" size="1" />
+    </Register>
+    <Register name="OTG_HS_HCINT4" description="OTG_HS host channel-4 interrupt register" start="+0x188" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRC" description="Transfer completed" start="0" size="1" />
+      <BitField name="CHH" description="Channel halted" start="1" size="1" />
+      <BitField name="AHBERR" description="AHB error" start="2" size="1" />
+      <BitField name="STALL" description="STALL response received interrupt" start="3" size="1" />
+      <BitField name="NAK" description="NAK response received interrupt" start="4" size="1" />
+      <BitField name="ACK" description="ACK response received/transmitted interrupt" start="5" size="1" />
+      <BitField name="NYET" description="Response received interrupt" start="6" size="1" />
+      <BitField name="TXERR" description="Transaction error" start="7" size="1" />
+      <BitField name="BBERR" description="Babble error" start="8" size="1" />
+      <BitField name="FRMOR" description="Frame overrun" start="9" size="1" />
+      <BitField name="DTERR" description="Data toggle error" start="10" size="1" />
+    </Register>
+    <Register name="OTG_HS_HCINT5" description="OTG_HS host channel-5 interrupt register" start="+0x1A8" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRC" description="Transfer completed" start="0" size="1" />
+      <BitField name="CHH" description="Channel halted" start="1" size="1" />
+      <BitField name="AHBERR" description="AHB error" start="2" size="1" />
+      <BitField name="STALL" description="STALL response received interrupt" start="3" size="1" />
+      <BitField name="NAK" description="NAK response received interrupt" start="4" size="1" />
+      <BitField name="ACK" description="ACK response received/transmitted interrupt" start="5" size="1" />
+      <BitField name="NYET" description="Response received interrupt" start="6" size="1" />
+      <BitField name="TXERR" description="Transaction error" start="7" size="1" />
+      <BitField name="BBERR" description="Babble error" start="8" size="1" />
+      <BitField name="FRMOR" description="Frame overrun" start="9" size="1" />
+      <BitField name="DTERR" description="Data toggle error" start="10" size="1" />
+    </Register>
+    <Register name="OTG_HS_HCINT6" description="OTG_HS host channel-6 interrupt register" start="+0x1C8" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRC" description="Transfer completed" start="0" size="1" />
+      <BitField name="CHH" description="Channel halted" start="1" size="1" />
+      <BitField name="AHBERR" description="AHB error" start="2" size="1" />
+      <BitField name="STALL" description="STALL response received interrupt" start="3" size="1" />
+      <BitField name="NAK" description="NAK response received interrupt" start="4" size="1" />
+      <BitField name="ACK" description="ACK response received/transmitted interrupt" start="5" size="1" />
+      <BitField name="NYET" description="Response received interrupt" start="6" size="1" />
+      <BitField name="TXERR" description="Transaction error" start="7" size="1" />
+      <BitField name="BBERR" description="Babble error" start="8" size="1" />
+      <BitField name="FRMOR" description="Frame overrun" start="9" size="1" />
+      <BitField name="DTERR" description="Data toggle error" start="10" size="1" />
+    </Register>
+    <Register name="OTG_HS_HCINT7" description="OTG_HS host channel-7 interrupt register" start="+0x1E8" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRC" description="Transfer completed" start="0" size="1" />
+      <BitField name="CHH" description="Channel halted" start="1" size="1" />
+      <BitField name="AHBERR" description="AHB error" start="2" size="1" />
+      <BitField name="STALL" description="STALL response received interrupt" start="3" size="1" />
+      <BitField name="NAK" description="NAK response received interrupt" start="4" size="1" />
+      <BitField name="ACK" description="ACK response received/transmitted interrupt" start="5" size="1" />
+      <BitField name="NYET" description="Response received interrupt" start="6" size="1" />
+      <BitField name="TXERR" description="Transaction error" start="7" size="1" />
+      <BitField name="BBERR" description="Babble error" start="8" size="1" />
+      <BitField name="FRMOR" description="Frame overrun" start="9" size="1" />
+      <BitField name="DTERR" description="Data toggle error" start="10" size="1" />
+    </Register>
+    <Register name="OTG_HS_HCINT8" description="OTG_HS host channel-8 interrupt register" start="+0x208" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRC" description="Transfer completed" start="0" size="1" />
+      <BitField name="CHH" description="Channel halted" start="1" size="1" />
+      <BitField name="AHBERR" description="AHB error" start="2" size="1" />
+      <BitField name="STALL" description="STALL response received interrupt" start="3" size="1" />
+      <BitField name="NAK" description="NAK response received interrupt" start="4" size="1" />
+      <BitField name="ACK" description="ACK response received/transmitted interrupt" start="5" size="1" />
+      <BitField name="NYET" description="Response received interrupt" start="6" size="1" />
+      <BitField name="TXERR" description="Transaction error" start="7" size="1" />
+      <BitField name="BBERR" description="Babble error" start="8" size="1" />
+      <BitField name="FRMOR" description="Frame overrun" start="9" size="1" />
+      <BitField name="DTERR" description="Data toggle error" start="10" size="1" />
+    </Register>
+    <Register name="OTG_HS_HCINT9" description="OTG_HS host channel-9 interrupt register" start="+0x228" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRC" description="Transfer completed" start="0" size="1" />
+      <BitField name="CHH" description="Channel halted" start="1" size="1" />
+      <BitField name="AHBERR" description="AHB error" start="2" size="1" />
+      <BitField name="STALL" description="STALL response received interrupt" start="3" size="1" />
+      <BitField name="NAK" description="NAK response received interrupt" start="4" size="1" />
+      <BitField name="ACK" description="ACK response received/transmitted interrupt" start="5" size="1" />
+      <BitField name="NYET" description="Response received interrupt" start="6" size="1" />
+      <BitField name="TXERR" description="Transaction error" start="7" size="1" />
+      <BitField name="BBERR" description="Babble error" start="8" size="1" />
+      <BitField name="FRMOR" description="Frame overrun" start="9" size="1" />
+      <BitField name="DTERR" description="Data toggle error" start="10" size="1" />
+    </Register>
+    <Register name="OTG_HS_HCINT10" description="OTG_HS host channel-10 interrupt register" start="+0x248" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRC" description="Transfer completed" start="0" size="1" />
+      <BitField name="CHH" description="Channel halted" start="1" size="1" />
+      <BitField name="AHBERR" description="AHB error" start="2" size="1" />
+      <BitField name="STALL" description="STALL response received interrupt" start="3" size="1" />
+      <BitField name="NAK" description="NAK response received interrupt" start="4" size="1" />
+      <BitField name="ACK" description="ACK response received/transmitted interrupt" start="5" size="1" />
+      <BitField name="NYET" description="Response received interrupt" start="6" size="1" />
+      <BitField name="TXERR" description="Transaction error" start="7" size="1" />
+      <BitField name="BBERR" description="Babble error" start="8" size="1" />
+      <BitField name="FRMOR" description="Frame overrun" start="9" size="1" />
+      <BitField name="DTERR" description="Data toggle error" start="10" size="1" />
+    </Register>
+    <Register name="OTG_HS_HCINT11" description="OTG_HS host channel-11 interrupt register" start="+0x268" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRC" description="Transfer completed" start="0" size="1" />
+      <BitField name="CHH" description="Channel halted" start="1" size="1" />
+      <BitField name="AHBERR" description="AHB error" start="2" size="1" />
+      <BitField name="STALL" description="STALL response received interrupt" start="3" size="1" />
+      <BitField name="NAK" description="NAK response received interrupt" start="4" size="1" />
+      <BitField name="ACK" description="ACK response received/transmitted interrupt" start="5" size="1" />
+      <BitField name="NYET" description="Response received interrupt" start="6" size="1" />
+      <BitField name="TXERR" description="Transaction error" start="7" size="1" />
+      <BitField name="BBERR" description="Babble error" start="8" size="1" />
+      <BitField name="FRMOR" description="Frame overrun" start="9" size="1" />
+      <BitField name="DTERR" description="Data toggle error" start="10" size="1" />
+    </Register>
+    <Register name="OTG_HS_HCINTMSK0" description="OTG_HS host channel-11 interrupt mask register" start="+0x10C" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRCM" description="Transfer completed mask" start="0" size="1" />
+      <BitField name="CHHM" description="Channel halted mask" start="1" size="1" />
+      <BitField name="AHBERR" description="AHB error" start="2" size="1" />
+      <BitField name="STALLM" description="STALL response received interrupt mask" start="3" size="1" />
+      <BitField name="NAKM" description="NAK response received interrupt mask" start="4" size="1" />
+      <BitField name="ACKM" description="ACK response received/transmitted interrupt mask" start="5" size="1" />
+      <BitField name="NYET" description="response received interrupt mask" start="6" size="1" />
+      <BitField name="TXERRM" description="Transaction error mask" start="7" size="1" />
+      <BitField name="BBERRM" description="Babble error mask" start="8" size="1" />
+      <BitField name="FRMORM" description="Frame overrun mask" start="9" size="1" />
+      <BitField name="DTERRM" description="Data toggle error mask" start="10" size="1" />
+    </Register>
+    <Register name="OTG_HS_HCINTMSK1" description="OTG_HS host channel-1 interrupt mask register" start="+0x12C" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRCM" description="Transfer completed mask" start="0" size="1" />
+      <BitField name="CHHM" description="Channel halted mask" start="1" size="1" />
+      <BitField name="AHBERR" description="AHB error" start="2" size="1" />
+      <BitField name="STALLM" description="STALL response received interrupt mask" start="3" size="1" />
+      <BitField name="NAKM" description="NAK response received interrupt mask" start="4" size="1" />
+      <BitField name="ACKM" description="ACK response received/transmitted interrupt mask" start="5" size="1" />
+      <BitField name="NYET" description="response received interrupt mask" start="6" size="1" />
+      <BitField name="TXERRM" description="Transaction error mask" start="7" size="1" />
+      <BitField name="BBERRM" description="Babble error mask" start="8" size="1" />
+      <BitField name="FRMORM" description="Frame overrun mask" start="9" size="1" />
+      <BitField name="DTERRM" description="Data toggle error mask" start="10" size="1" />
+    </Register>
+    <Register name="OTG_HS_HCINTMSK2" description="OTG_HS host channel-2 interrupt mask register" start="+0x14C" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRCM" description="Transfer completed mask" start="0" size="1" />
+      <BitField name="CHHM" description="Channel halted mask" start="1" size="1" />
+      <BitField name="AHBERR" description="AHB error" start="2" size="1" />
+      <BitField name="STALLM" description="STALL response received interrupt mask" start="3" size="1" />
+      <BitField name="NAKM" description="NAK response received interrupt mask" start="4" size="1" />
+      <BitField name="ACKM" description="ACK response received/transmitted interrupt mask" start="5" size="1" />
+      <BitField name="NYET" description="response received interrupt mask" start="6" size="1" />
+      <BitField name="TXERRM" description="Transaction error mask" start="7" size="1" />
+      <BitField name="BBERRM" description="Babble error mask" start="8" size="1" />
+      <BitField name="FRMORM" description="Frame overrun mask" start="9" size="1" />
+      <BitField name="DTERRM" description="Data toggle error mask" start="10" size="1" />
+    </Register>
+    <Register name="OTG_HS_HCINTMSK3" description="OTG_HS host channel-3 interrupt mask register" start="+0x16C" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRCM" description="Transfer completed mask" start="0" size="1" />
+      <BitField name="CHHM" description="Channel halted mask" start="1" size="1" />
+      <BitField name="AHBERR" description="AHB error" start="2" size="1" />
+      <BitField name="STALLM" description="STALL response received interrupt mask" start="3" size="1" />
+      <BitField name="NAKM" description="NAK response received interrupt mask" start="4" size="1" />
+      <BitField name="ACKM" description="ACK response received/transmitted interrupt mask" start="5" size="1" />
+      <BitField name="NYET" description="response received interrupt mask" start="6" size="1" />
+      <BitField name="TXERRM" description="Transaction error mask" start="7" size="1" />
+      <BitField name="BBERRM" description="Babble error mask" start="8" size="1" />
+      <BitField name="FRMORM" description="Frame overrun mask" start="9" size="1" />
+      <BitField name="DTERRM" description="Data toggle error mask" start="10" size="1" />
+    </Register>
+    <Register name="OTG_HS_HCINTMSK4" description="OTG_HS host channel-4 interrupt mask register" start="+0x18C" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRCM" description="Transfer completed mask" start="0" size="1" />
+      <BitField name="CHHM" description="Channel halted mask" start="1" size="1" />
+      <BitField name="AHBERR" description="AHB error" start="2" size="1" />
+      <BitField name="STALLM" description="STALL response received interrupt mask" start="3" size="1" />
+      <BitField name="NAKM" description="NAK response received interrupt mask" start="4" size="1" />
+      <BitField name="ACKM" description="ACK response received/transmitted interrupt mask" start="5" size="1" />
+      <BitField name="NYET" description="response received interrupt mask" start="6" size="1" />
+      <BitField name="TXERRM" description="Transaction error mask" start="7" size="1" />
+      <BitField name="BBERRM" description="Babble error mask" start="8" size="1" />
+      <BitField name="FRMORM" description="Frame overrun mask" start="9" size="1" />
+      <BitField name="DTERRM" description="Data toggle error mask" start="10" size="1" />
+    </Register>
+    <Register name="OTG_HS_HCINTMSK5" description="OTG_HS host channel-5 interrupt mask register" start="+0x1AC" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRCM" description="Transfer completed mask" start="0" size="1" />
+      <BitField name="CHHM" description="Channel halted mask" start="1" size="1" />
+      <BitField name="AHBERR" description="AHB error" start="2" size="1" />
+      <BitField name="STALLM" description="STALL response received interrupt mask" start="3" size="1" />
+      <BitField name="NAKM" description="NAK response received interrupt mask" start="4" size="1" />
+      <BitField name="ACKM" description="ACK response received/transmitted interrupt mask" start="5" size="1" />
+      <BitField name="NYET" description="response received interrupt mask" start="6" size="1" />
+      <BitField name="TXERRM" description="Transaction error mask" start="7" size="1" />
+      <BitField name="BBERRM" description="Babble error mask" start="8" size="1" />
+      <BitField name="FRMORM" description="Frame overrun mask" start="9" size="1" />
+      <BitField name="DTERRM" description="Data toggle error mask" start="10" size="1" />
+    </Register>
+    <Register name="OTG_HS_HCINTMSK6" description="OTG_HS host channel-6 interrupt mask register" start="+0x1CC" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRCM" description="Transfer completed mask" start="0" size="1" />
+      <BitField name="CHHM" description="Channel halted mask" start="1" size="1" />
+      <BitField name="AHBERR" description="AHB error" start="2" size="1" />
+      <BitField name="STALLM" description="STALL response received interrupt mask" start="3" size="1" />
+      <BitField name="NAKM" description="NAK response received interrupt mask" start="4" size="1" />
+      <BitField name="ACKM" description="ACK response received/transmitted interrupt mask" start="5" size="1" />
+      <BitField name="NYET" description="response received interrupt mask" start="6" size="1" />
+      <BitField name="TXERRM" description="Transaction error mask" start="7" size="1" />
+      <BitField name="BBERRM" description="Babble error mask" start="8" size="1" />
+      <BitField name="FRMORM" description="Frame overrun mask" start="9" size="1" />
+      <BitField name="DTERRM" description="Data toggle error mask" start="10" size="1" />
+    </Register>
+    <Register name="OTG_HS_HCINTMSK7" description="OTG_HS host channel-7 interrupt mask register" start="+0x1EC" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRCM" description="Transfer completed mask" start="0" size="1" />
+      <BitField name="CHHM" description="Channel halted mask" start="1" size="1" />
+      <BitField name="AHBERR" description="AHB error" start="2" size="1" />
+      <BitField name="STALLM" description="STALL response received interrupt mask" start="3" size="1" />
+      <BitField name="NAKM" description="NAK response received interrupt mask" start="4" size="1" />
+      <BitField name="ACKM" description="ACK response received/transmitted interrupt mask" start="5" size="1" />
+      <BitField name="NYET" description="response received interrupt mask" start="6" size="1" />
+      <BitField name="TXERRM" description="Transaction error mask" start="7" size="1" />
+      <BitField name="BBERRM" description="Babble error mask" start="8" size="1" />
+      <BitField name="FRMORM" description="Frame overrun mask" start="9" size="1" />
+      <BitField name="DTERRM" description="Data toggle error mask" start="10" size="1" />
+    </Register>
+    <Register name="OTG_HS_HCINTMSK8" description="OTG_HS host channel-8 interrupt mask register" start="+0x20C" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRCM" description="Transfer completed mask" start="0" size="1" />
+      <BitField name="CHHM" description="Channel halted mask" start="1" size="1" />
+      <BitField name="AHBERR" description="AHB error" start="2" size="1" />
+      <BitField name="STALLM" description="STALL response received interrupt mask" start="3" size="1" />
+      <BitField name="NAKM" description="NAK response received interrupt mask" start="4" size="1" />
+      <BitField name="ACKM" description="ACK response received/transmitted interrupt mask" start="5" size="1" />
+      <BitField name="NYET" description="response received interrupt mask" start="6" size="1" />
+      <BitField name="TXERRM" description="Transaction error mask" start="7" size="1" />
+      <BitField name="BBERRM" description="Babble error mask" start="8" size="1" />
+      <BitField name="FRMORM" description="Frame overrun mask" start="9" size="1" />
+      <BitField name="DTERRM" description="Data toggle error mask" start="10" size="1" />
+    </Register>
+    <Register name="OTG_HS_HCINTMSK9" description="OTG_HS host channel-9 interrupt mask register" start="+0x22C" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRCM" description="Transfer completed mask" start="0" size="1" />
+      <BitField name="CHHM" description="Channel halted mask" start="1" size="1" />
+      <BitField name="AHBERR" description="AHB error" start="2" size="1" />
+      <BitField name="STALLM" description="STALL response received interrupt mask" start="3" size="1" />
+      <BitField name="NAKM" description="NAK response received interrupt mask" start="4" size="1" />
+      <BitField name="ACKM" description="ACK response received/transmitted interrupt mask" start="5" size="1" />
+      <BitField name="NYET" description="response received interrupt mask" start="6" size="1" />
+      <BitField name="TXERRM" description="Transaction error mask" start="7" size="1" />
+      <BitField name="BBERRM" description="Babble error mask" start="8" size="1" />
+      <BitField name="FRMORM" description="Frame overrun mask" start="9" size="1" />
+      <BitField name="DTERRM" description="Data toggle error mask" start="10" size="1" />
+    </Register>
+    <Register name="OTG_HS_HCINTMSK10" description="OTG_HS host channel-10 interrupt mask register" start="+0x24C" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRCM" description="Transfer completed mask" start="0" size="1" />
+      <BitField name="CHHM" description="Channel halted mask" start="1" size="1" />
+      <BitField name="AHBERR" description="AHB error" start="2" size="1" />
+      <BitField name="STALLM" description="STALL response received interrupt mask" start="3" size="1" />
+      <BitField name="NAKM" description="NAK response received interrupt mask" start="4" size="1" />
+      <BitField name="ACKM" description="ACK response received/transmitted interrupt mask" start="5" size="1" />
+      <BitField name="NYET" description="response received interrupt mask" start="6" size="1" />
+      <BitField name="TXERRM" description="Transaction error mask" start="7" size="1" />
+      <BitField name="BBERRM" description="Babble error mask" start="8" size="1" />
+      <BitField name="FRMORM" description="Frame overrun mask" start="9" size="1" />
+      <BitField name="DTERRM" description="Data toggle error mask" start="10" size="1" />
+    </Register>
+    <Register name="OTG_HS_HCINTMSK11" description="OTG_HS host channel-11 interrupt mask register" start="+0x26C" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRCM" description="Transfer completed mask" start="0" size="1" />
+      <BitField name="CHHM" description="Channel halted mask" start="1" size="1" />
+      <BitField name="AHBERR" description="AHB error" start="2" size="1" />
+      <BitField name="STALLM" description="STALL response received interrupt mask" start="3" size="1" />
+      <BitField name="NAKM" description="NAK response received interrupt mask" start="4" size="1" />
+      <BitField name="ACKM" description="ACK response received/transmitted interrupt mask" start="5" size="1" />
+      <BitField name="NYET" description="response received interrupt mask" start="6" size="1" />
+      <BitField name="TXERRM" description="Transaction error mask" start="7" size="1" />
+      <BitField name="BBERRM" description="Babble error mask" start="8" size="1" />
+      <BitField name="FRMORM" description="Frame overrun mask" start="9" size="1" />
+      <BitField name="DTERRM" description="Data toggle error mask" start="10" size="1" />
+    </Register>
+    <Register name="OTG_HS_HCTSIZ0" description="OTG_HS host channel-11 transfer size register" start="+0x110" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRSIZ" description="Transfer size" start="0" size="19" />
+      <BitField name="PKTCNT" description="Packet count" start="19" size="10" />
+      <BitField name="DPID" description="Data PID" start="29" size="2" />
+    </Register>
+    <Register name="OTG_HS_HCTSIZ1" description="OTG_HS host channel-1 transfer size register" start="+0x130" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRSIZ" description="Transfer size" start="0" size="19" />
+      <BitField name="PKTCNT" description="Packet count" start="19" size="10" />
+      <BitField name="DPID" description="Data PID" start="29" size="2" />
+    </Register>
+    <Register name="OTG_HS_HCTSIZ2" description="OTG_HS host channel-2 transfer size register" start="+0x150" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRSIZ" description="Transfer size" start="0" size="19" />
+      <BitField name="PKTCNT" description="Packet count" start="19" size="10" />
+      <BitField name="DPID" description="Data PID" start="29" size="2" />
+    </Register>
+    <Register name="OTG_HS_HCTSIZ3" description="OTG_HS host channel-3 transfer size register" start="+0x170" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRSIZ" description="Transfer size" start="0" size="19" />
+      <BitField name="PKTCNT" description="Packet count" start="19" size="10" />
+      <BitField name="DPID" description="Data PID" start="29" size="2" />
+    </Register>
+    <Register name="OTG_HS_HCTSIZ4" description="OTG_HS host channel-4 transfer size register" start="+0x190" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRSIZ" description="Transfer size" start="0" size="19" />
+      <BitField name="PKTCNT" description="Packet count" start="19" size="10" />
+      <BitField name="DPID" description="Data PID" start="29" size="2" />
+    </Register>
+    <Register name="OTG_HS_HCTSIZ5" description="OTG_HS host channel-5 transfer size register" start="+0x1B0" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRSIZ" description="Transfer size" start="0" size="19" />
+      <BitField name="PKTCNT" description="Packet count" start="19" size="10" />
+      <BitField name="DPID" description="Data PID" start="29" size="2" />
+    </Register>
+    <Register name="OTG_HS_HCTSIZ6" description="OTG_HS host channel-6 transfer size register" start="+0x1D0" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRSIZ" description="Transfer size" start="0" size="19" />
+      <BitField name="PKTCNT" description="Packet count" start="19" size="10" />
+      <BitField name="DPID" description="Data PID" start="29" size="2" />
+    </Register>
+    <Register name="OTG_HS_HCTSIZ7" description="OTG_HS host channel-7 transfer size register" start="+0x1F0" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRSIZ" description="Transfer size" start="0" size="19" />
+      <BitField name="PKTCNT" description="Packet count" start="19" size="10" />
+      <BitField name="DPID" description="Data PID" start="29" size="2" />
+    </Register>
+    <Register name="OTG_HS_HCTSIZ8" description="OTG_HS host channel-8 transfer size register" start="+0x210" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRSIZ" description="Transfer size" start="0" size="19" />
+      <BitField name="PKTCNT" description="Packet count" start="19" size="10" />
+      <BitField name="DPID" description="Data PID" start="29" size="2" />
+    </Register>
+    <Register name="OTG_HS_HCTSIZ9" description="OTG_HS host channel-9 transfer size register" start="+0x230" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRSIZ" description="Transfer size" start="0" size="19" />
+      <BitField name="PKTCNT" description="Packet count" start="19" size="10" />
+      <BitField name="DPID" description="Data PID" start="29" size="2" />
+    </Register>
+    <Register name="OTG_HS_HCTSIZ10" description="OTG_HS host channel-10 transfer size register" start="+0x250" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRSIZ" description="Transfer size" start="0" size="19" />
+      <BitField name="PKTCNT" description="Packet count" start="19" size="10" />
+      <BitField name="DPID" description="Data PID" start="29" size="2" />
+    </Register>
+    <Register name="OTG_HS_HCTSIZ11" description="OTG_HS host channel-11 transfer size register" start="+0x270" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRSIZ" description="Transfer size" start="0" size="19" />
+      <BitField name="PKTCNT" description="Packet count" start="19" size="10" />
+      <BitField name="DPID" description="Data PID" start="29" size="2" />
+    </Register>
+    <Register name="OTG_HS_HCDMA0" description="OTG_HS host channel-0 DMA address register" start="+0x114" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAADDR" description="DMA address" start="0" size="32" />
+    </Register>
+    <Register name="OTG_HS_HCDMA1" description="OTG_HS host channel-1 DMA address register" start="+0x134" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAADDR" description="DMA address" start="0" size="32" />
+    </Register>
+    <Register name="OTG_HS_HCDMA2" description="OTG_HS host channel-2 DMA address register" start="+0x154" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAADDR" description="DMA address" start="0" size="32" />
+    </Register>
+    <Register name="OTG_HS_HCDMA3" description="OTG_HS host channel-3 DMA address register" start="+0x174" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAADDR" description="DMA address" start="0" size="32" />
+    </Register>
+    <Register name="OTG_HS_HCDMA4" description="OTG_HS host channel-4 DMA address register" start="+0x194" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAADDR" description="DMA address" start="0" size="32" />
+    </Register>
+    <Register name="OTG_HS_HCDMA5" description="OTG_HS host channel-5 DMA address register" start="+0x1B4" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAADDR" description="DMA address" start="0" size="32" />
+    </Register>
+    <Register name="OTG_HS_HCDMA6" description="OTG_HS host channel-6 DMA address register" start="+0x1D4" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAADDR" description="DMA address" start="0" size="32" />
+    </Register>
+    <Register name="OTG_HS_HCDMA7" description="OTG_HS host channel-7 DMA address register" start="+0x1F4" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAADDR" description="DMA address" start="0" size="32" />
+    </Register>
+    <Register name="OTG_HS_HCDMA8" description="OTG_HS host channel-8 DMA address register" start="+0x214" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAADDR" description="DMA address" start="0" size="32" />
+    </Register>
+    <Register name="OTG_HS_HCDMA9" description="OTG_HS host channel-9 DMA address register" start="+0x234" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAADDR" description="DMA address" start="0" size="32" />
+    </Register>
+    <Register name="OTG_HS_HCDMA10" description="OTG_HS host channel-10 DMA address register" start="+0x254" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAADDR" description="DMA address" start="0" size="32" />
+    </Register>
+    <Register name="OTG_HS_HCDMA11" description="OTG_HS host channel-11 DMA address register" start="+0x274" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAADDR" description="DMA address" start="0" size="32" />
+    </Register>
+    <Register name="OTG_HS_HCCHAR12" description="OTG_HS host channel-12 characteristics register" start="+0x278" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" />
+      <BitField name="EPNUM" description="Endpoint number" start="11" size="4" />
+      <BitField name="EPDIR" description="Endpoint direction" start="15" size="1" />
+      <BitField name="LSDEV" description="Low-speed device" start="17" size="1" />
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" />
+      <BitField name="MC" description="Multi Count (MC) / Error Count (EC)" start="20" size="2" />
+      <BitField name="DAD" description="Device address" start="22" size="7" />
+      <BitField name="ODDFRM" description="Odd frame" start="29" size="1" />
+      <BitField name="CHDIS" description="Channel disable" start="30" size="1" />
+      <BitField name="CHENA" description="Channel enable" start="31" size="1" />
+    </Register>
+    <Register name="OTG_HS_HCSPLT12" description="OTG_HS host channel-12 split control register" start="+0x27C" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="PRTADDR" description="Port address" start="0" size="7" />
+      <BitField name="HUBADDR" description="Hub address" start="7" size="7" />
+      <BitField name="XACTPOS" description="XACTPOS" start="14" size="2" />
+      <BitField name="COMPLSPLT" description="Do complete split" start="16" size="1" />
+      <BitField name="SPLITEN" description="Split enable" start="31" size="1" />
+    </Register>
+    <Register name="OTG_HS_HCINT12" description="OTG_HS host channel-12 interrupt register" start="+0x280" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRC" description="Transfer completed" start="0" size="1" />
+      <BitField name="CHH" description="Channel halted" start="1" size="1" />
+      <BitField name="AHBERR" description="AHB error" start="2" size="1" />
+      <BitField name="STALL" description="STALL response received interrupt" start="3" size="1" />
+      <BitField name="NAK" description="NAK response received interrupt" start="4" size="1" />
+      <BitField name="ACK" description="ACK response received/transmitted interrupt" start="5" size="1" />
+      <BitField name="NYET" description="Response received interrupt" start="6" size="1" />
+      <BitField name="TXERR" description="Transaction error" start="7" size="1" />
+      <BitField name="BBERR" description="Babble error" start="8" size="1" />
+      <BitField name="FRMOR" description="Frame overrun" start="9" size="1" />
+      <BitField name="DTERR" description="Data toggle error" start="10" size="1" />
+    </Register>
+    <Register name="OTG_HS_HCINTMSK12" description="OTG_HS host channel-12 interrupt mask register" start="+0x284" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRCM" description="Transfer completed mask" start="0" size="1" />
+      <BitField name="CHHM" description="Channel halted mask" start="1" size="1" />
+      <BitField name="AHBERR" description="AHB error" start="2" size="1" />
+      <BitField name="STALLM" description="STALL response received interrupt mask" start="3" size="1" />
+      <BitField name="NAKM" description="NAK response received interrupt mask" start="4" size="1" />
+      <BitField name="ACKM" description="ACK response received/transmitted interrupt mask" start="5" size="1" />
+      <BitField name="NYET" description="Response received interrupt" start="6" size="1" />
+      <BitField name="TXERRM" description="Transaction error" start="7" size="1" />
+      <BitField name="BBERRM" description="Babble error" start="8" size="1" />
+      <BitField name="FRMORM" description="Frame overrun mask" start="9" size="1" />
+      <BitField name="DTERRM" description="Data toggle error mask" start="10" size="1" />
+    </Register>
+    <Register name="OTG_HS_HCTSIZ12" description="OTG_HS host channel-12 transfer size register" start="+0x288" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRSIZ" description="Transfer size" start="0" size="19" />
+      <BitField name="PKTCNT" description="Packet count" start="19" size="10" />
+      <BitField name="DPID" description="Data PID" start="29" size="2" />
+    </Register>
+    <Register name="OTG_HS_HCDMA12" description="OTG_HS host channel-12 DMA address register" start="+0x28C" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAADDR" description="DMA address" start="0" size="32" />
+    </Register>
+    <Register name="OTG_HS_HCCHAR13" description="OTG_HS host channel-13 characteristics register" start="+0x290" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" />
+      <BitField name="EPNUM" description="Endpoint number" start="11" size="4" />
+      <BitField name="EPDIR" description="Endpoint direction" start="15" size="1" />
+      <BitField name="LSDEV" description="Low-speed device" start="17" size="1" />
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" />
+      <BitField name="MC" description="Multi Count (MC) / Error Count (EC)" start="20" size="2" />
+      <BitField name="DAD" description="Device address" start="22" size="7" />
+      <BitField name="ODDFRM" description="Odd frame" start="29" size="1" />
+      <BitField name="CHDIS" description="Channel disable" start="30" size="1" />
+      <BitField name="CHENA" description="Channel enable" start="31" size="1" />
+    </Register>
+    <Register name="OTG_HS_HCSPLT13" description="OTG_HS host channel-13 split control register" start="+0x294" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="PRTADDR" description="Port address" start="0" size="7" />
+      <BitField name="HUBADDR" description="Hub address" start="7" size="7" />
+      <BitField name="XACTPOS" description="XACTPOS" start="14" size="2" />
+      <BitField name="COMPLSPLT" description="Do complete split" start="16" size="1" />
+      <BitField name="SPLITEN" description="Split enable" start="31" size="1" />
+    </Register>
+    <Register name="OTG_HS_HCINT13" description="OTG_HS host channel-13 interrupt register" start="+0x298" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRC" description="Transfer completed" start="0" size="1" />
+      <BitField name="CHH" description="Channel halted" start="1" size="1" />
+      <BitField name="AHBERR" description="AHB error" start="2" size="1" />
+      <BitField name="STALL" description="STALL response received interrupt" start="3" size="1" />
+      <BitField name="NAK" description="NAK response received interrupt" start="4" size="1" />
+      <BitField name="ACK" description="ACK response received/transmitted interrupt" start="5" size="1" />
+      <BitField name="NYET" description="Response received interrupt" start="6" size="1" />
+      <BitField name="TXERR" description="Transaction error" start="7" size="1" />
+      <BitField name="BBERR" description="Babble error" start="8" size="1" />
+      <BitField name="FRMOR" description="Frame overrun" start="9" size="1" />
+      <BitField name="DTERR" description="Data toggle error" start="10" size="1" />
+    </Register>
+    <Register name="OTG_HS_HCINTMSK13" description="OTG_HS host channel-13 interrupt mask register" start="+0x29C" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRCM" description="Transfer completed mask" start="0" size="1" />
+      <BitField name="CHHM" description="Channel halted mask" start="1" size="1" />
+      <BitField name="AHBERR" description="AHB error" start="2" size="1" />
+      <BitField name="STALLM" description="STALLM response received interrupt mask" start="3" size="1" />
+      <BitField name="NAKM" description="NAK response received interrupt mask" start="4" size="1" />
+      <BitField name="ACKM" description="ACK response received/transmitted interrupt mask" start="5" size="1" />
+      <BitField name="NYET" description="Response received interrupt" start="6" size="1" />
+      <BitField name="TXERRM" description="Transaction error" start="7" size="1" />
+      <BitField name="BBERRM" description="Babble error" start="8" size="1" />
+      <BitField name="FRMORM" description="Frame overrun mask" start="9" size="1" />
+      <BitField name="DTERRM" description="Data toggle error mask" start="10" size="1" />
+    </Register>
+    <Register name="OTG_HS_HCTSIZ13" description="OTG_HS host channel-13 transfer size register" start="+0x2A0" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRSIZ" description="Transfer size" start="0" size="19" />
+      <BitField name="PKTCNT" description="Packet count" start="19" size="10" />
+      <BitField name="DPID" description="Data PID" start="29" size="2" />
+    </Register>
+    <Register name="OTG_HS_HCDMA13" description="OTG_HS host channel-13 DMA address register" start="+0x2A4" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAADDR" description="DMA address" start="0" size="32" />
+    </Register>
+    <Register name="OTG_HS_HCCHAR14" description="OTG_HS host channel-14 characteristics register" start="+0x2A8" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" />
+      <BitField name="EPNUM" description="Endpoint number" start="11" size="4" />
+      <BitField name="EPDIR" description="Endpoint direction" start="15" size="1" />
+      <BitField name="LSDEV" description="Low-speed device" start="17" size="1" />
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" />
+      <BitField name="MC" description="Multi Count (MC) / Error Count (EC)" start="20" size="2" />
+      <BitField name="DAD" description="Device address" start="22" size="7" />
+      <BitField name="ODDFRM" description="Odd frame" start="29" size="1" />
+      <BitField name="CHDIS" description="Channel disable" start="30" size="1" />
+      <BitField name="CHENA" description="Channel enable" start="31" size="1" />
+    </Register>
+    <Register name="OTG_HS_HCSPLT14" description="OTG_HS host channel-14 split control register" start="+0x2AC" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="PRTADDR" description="Port address" start="0" size="7" />
+      <BitField name="HUBADDR" description="Hub address" start="7" size="7" />
+      <BitField name="XACTPOS" description="XACTPOS" start="14" size="2" />
+      <BitField name="COMPLSPLT" description="Do complete split" start="16" size="1" />
+      <BitField name="SPLITEN" description="Split enable" start="31" size="1" />
+    </Register>
+    <Register name="OTG_HS_HCINT14" description="OTG_HS host channel-14 interrupt register" start="+0x2B0" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRC" description="Transfer completed" start="0" size="1" />
+      <BitField name="CHH" description="Channel halted" start="1" size="1" />
+      <BitField name="AHBERR" description="AHB error" start="2" size="1" />
+      <BitField name="STALL" description="STALL response received interrupt" start="3" size="1" />
+      <BitField name="NAK" description="NAK response received interrupt" start="4" size="1" />
+      <BitField name="ACK" description="ACK response received/transmitted interrupt" start="5" size="1" />
+      <BitField name="NYET" description="Response received interrupt" start="6" size="1" />
+      <BitField name="TXERR" description="Transaction error" start="7" size="1" />
+      <BitField name="BBERR" description="Babble error" start="8" size="1" />
+      <BitField name="FRMOR" description="Frame overrun" start="9" size="1" />
+      <BitField name="DTERR" description="Data toggle error" start="10" size="1" />
+    </Register>
+    <Register name="OTG_HS_HCINTMSK14" description="OTG_HS host channel-14 interrupt mask register" start="+0x2B4" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRCM" description="Transfer completed mask" start="0" size="1" />
+      <BitField name="CHHM" description="Channel halted mask" start="1" size="1" />
+      <BitField name="AHBERR" description="AHB error" start="2" size="1" />
+      <BitField name="STALLM" description="STALL response received interrupt mask" start="3" size="1" />
+      <BitField name="NAKM" description="NAKM response received interrupt mask" start="4" size="1" />
+      <BitField name="ACKM" description="ACKM response received/transmitted interrupt mask" start="5" size="1" />
+      <BitField name="NYET" description="Response received interrupt" start="6" size="1" />
+      <BitField name="TXERRM" description="Transaction error" start="7" size="1" />
+      <BitField name="BBERRM" description="Babble error" start="8" size="1" />
+      <BitField name="FRMORM" description="Frame overrun mask" start="9" size="1" />
+      <BitField name="DTERRM" description="Data toggle error mask" start="10" size="1" />
+    </Register>
+    <Register name="OTG_HS_HCTSIZ14" description="OTG_HS host channel-14 transfer size register" start="+0x2B8" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRSIZ" description="Transfer size" start="0" size="19" />
+      <BitField name="PKTCNT" description="Packet count" start="19" size="10" />
+      <BitField name="DPID" description="Data PID" start="29" size="2" />
+    </Register>
+    <Register name="OTG_HS_HCDMA14" description="OTG_HS host channel-14 DMA address register" start="+0x2BC" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAADDR" description="DMA address" start="0" size="32" />
+    </Register>
+    <Register name="OTG_HS_HCCHAR15" description="OTG_HS host channel-15 characteristics register" start="+0x2C0" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="MPSIZ" description="Maximum packet size" start="0" size="11" />
+      <BitField name="EPNUM" description="Endpoint number" start="11" size="4" />
+      <BitField name="EPDIR" description="Endpoint direction" start="15" size="1" />
+      <BitField name="LSDEV" description="Low-speed device" start="17" size="1" />
+      <BitField name="EPTYP" description="Endpoint type" start="18" size="2" />
+      <BitField name="MC" description="Multi Count (MC) / Error Count (EC)" start="20" size="2" />
+      <BitField name="DAD" description="Device address" start="22" size="7" />
+      <BitField name="ODDFRM" description="Odd frame" start="29" size="1" />
+      <BitField name="CHDIS" description="Channel disable" start="30" size="1" />
+      <BitField name="CHENA" description="Channel enable" start="31" size="1" />
+    </Register>
+    <Register name="OTG_HS_HCSPLT15" description="OTG_HS host channel-15 split control register" start="+0x2C4" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="PRTADDR" description="Port address" start="0" size="7" />
+      <BitField name="HUBADDR" description="Hub address" start="7" size="7" />
+      <BitField name="XACTPOS" description="XACTPOS" start="14" size="2" />
+      <BitField name="COMPLSPLT" description="Do complete split" start="16" size="1" />
+      <BitField name="SPLITEN" description="Split enable" start="31" size="1" />
+    </Register>
+    <Register name="OTG_HS_HCINT15" description="OTG_HS host channel-15 interrupt register" start="+0x2C8" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRC" description="Transfer completed" start="0" size="1" />
+      <BitField name="CHH" description="Channel halted" start="1" size="1" />
+      <BitField name="AHBERR" description="AHB error" start="2" size="1" />
+      <BitField name="STALL" description="STALL response received interrupt" start="3" size="1" />
+      <BitField name="NAK" description="NAK response received interrupt" start="4" size="1" />
+      <BitField name="ACK" description="ACK response received/transmitted interrupt" start="5" size="1" />
+      <BitField name="NYET" description="Response received interrupt" start="6" size="1" />
+      <BitField name="TXERR" description="Transaction error" start="7" size="1" />
+      <BitField name="BBERR" description="Babble error" start="8" size="1" />
+      <BitField name="FRMOR" description="Frame overrun" start="9" size="1" />
+      <BitField name="DTERR" description="Data toggle error" start="10" size="1" />
+    </Register>
+    <Register name="OTG_HS_HCINTMSK15" description="OTG_HS host channel-15 interrupt mask register" start="+0x2CC" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRCM" description="Transfer completed mask" start="0" size="1" />
+      <BitField name="CHHM" description="Channel halted mask" start="1" size="1" />
+      <BitField name="AHBERR" description="AHB error" start="2" size="1" />
+      <BitField name="STALL" description="STALL response received interrupt mask" start="3" size="1" />
+      <BitField name="NAKM" description="NAK response received interrupt mask" start="4" size="1" />
+      <BitField name="ACKM" description="ACK response received/transmitted interrupt mask" start="5" size="1" />
+      <BitField name="NYET" description="Response received interrupt" start="6" size="1" />
+      <BitField name="TXERRM" description="Transaction error" start="7" size="1" />
+      <BitField name="BBERRM" description="Babble error" start="8" size="1" />
+      <BitField name="FRMORM" description="Frame overrun mask" start="9" size="1" />
+      <BitField name="DTERRM" description="Data toggle error mask" start="10" size="1" />
+    </Register>
+    <Register name="OTG_HS_HCTSIZ15" description="OTG_HS host channel-15 transfer size register" start="+0x2D0" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="XFRSIZ" description="Transfer size" start="0" size="19" />
+      <BitField name="PKTCNT" description="Packet count" start="19" size="10" />
+      <BitField name="DPID" description="Data PID" start="29" size="2" />
+    </Register>
+    <Register name="OTG_HS_HCDMA15" description="OTG_HS host channel-15 DMA address register" start="+0x2D4" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAADDR" description="DMA address" start="0" size="32" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="OTG1_HS_PWRCLK" description="USB 1 on the go high speed" start="0x40040E00">
+    <Register name="OTG_HS_PCGCR" description="Power and clock gating control register" start="+0x0" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="STPPCLK" description="Stop PHY clock" start="0" size="1" />
+      <BitField name="GATEHCLK" description="Gate HCLK" start="1" size="1" />
+      <BitField name="PHYSUSP" description="PHY suspended" start="4" size="1" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="OTG2_HS_PWRCLK" description="USB 1 on the go high speed" start="0x40080E00">
+    <Register name="OTG_HS_PCGCR" description="Power and clock gating control register" start="+0x0" size="4" access="Read/Write" reset_value="0x0" reset_mask="0xFFFFFFFF">
+      <BitField name="STPPCLK" description="Stop PHY clock" start="0" size="1" />
+      <BitField name="GATEHCLK" description="Gate HCLK" start="1" size="1" />
+      <BitField name="PHYSUSP" description="PHY suspended" start="4" size="1" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="OctoSPII_O_Manager" description="OctoSPI IO Manager" start="0x5200B400">
+    <Register name="CR" description="OctoSPI IO Manager Control Register" start="+0x0" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MUXEN" description="Multiplexed mode Enable" start="0" size="1" />
+      <BitField name="REQ2ACK_TIME" description="REQ to ACK Time" start="16" size="8" />
+    </Register>
+    <Register name="P1CR" description="OctoSPI IO Manager Port 1 configuration register" start="+0x4" size="4" access="Read/Write" reset_value="0x03010111" reset_mask="0xFFFFFFFF">
+      <BitField name="CLKEN" description="CLK/CLKn Enable for Port n" start="0" size="1" />
+      <BitField name="CLKSRC" description="CLK/CLKn Source for Port n" start="1" size="1" />
+      <BitField name="DQSEN" description="DQSEN" start="4" size="1" />
+      <BitField name="DQSSRC" description="DQSSRC" start="5" size="1" />
+      <BitField name="NCSEN" description="NCSEN" start="8" size="1" />
+      <BitField name="NCSSRC" description="NCSSRC" start="9" size="1" />
+      <BitField name="IOLEN" description="IOLEN" start="16" size="1" />
+      <BitField name="IOLSRC" description="IOLSRC" start="17" size="2" />
+      <BitField name="IOHEN" description="IOHEN" start="24" size="1" />
+      <BitField name="IOHSRC" description="IOHSRC" start="25" size="2" />
+    </Register>
+    <Register name="P2CR" description="OctoSPI IO Manager Port 2 configuration register" start="+0x8" size="4" access="Read/Write" reset_value="0x07050333" reset_mask="0xFFFFFFFF">
+      <BitField name="CLKEN" description="CLKEN" start="0" size="1" />
+      <BitField name="CLKSRC" description="CLKSRC" start="1" size="1" />
+      <BitField name="DQSEN" description="DQSEN" start="4" size="1" />
+      <BitField name="DQSSRC" description="DQSSRC" start="5" size="1" />
+      <BitField name="NCSEN" description="NCSEN" start="8" size="1" />
+      <BitField name="NCSSRC" description="NCSSRC" start="9" size="1" />
+      <BitField name="IOLEN" description="IOLEN" start="16" size="1" />
+      <BitField name="IOLSRC" description="IOLSRC" start="17" size="2" />
+      <BitField name="IOHEN" description="IOHEN" start="24" size="1" />
+      <BitField name="IOHSRC" description="IOHSRC" start="25" size="2" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="PF" description="Processor features" start="0xE000ED78">
+    <Register name="CLIDR" description="Cache Level ID register" start="+0x0" size="4" access="ReadOnly" reset_value="0x09000003" reset_mask="0xFFFFFFFF">
+      <BitField name="CL1" description="CL1" start="0" size="3" />
+      <BitField name="CL2" description="CL2" start="3" size="3" />
+      <BitField name="CL3" description="CL3" start="6" size="3" />
+      <BitField name="CL4" description="CL4" start="9" size="3" />
+      <BitField name="CL5" description="CL5" start="12" size="3" />
+      <BitField name="CL6" description="CL6" start="15" size="3" />
+      <BitField name="CL7" description="CL7" start="18" size="3" />
+      <BitField name="LoUIS" description="LoUIS" start="21" size="3" />
+      <BitField name="LoC" description="LoC" start="24" size="3" />
+      <BitField name="LoU" description="LoU" start="27" size="3" />
+    </Register>
+    <Register name="CTR" description="Cache Type register" start="+0x4" size="4" access="ReadOnly" reset_value="0X8303C003" reset_mask="0xFFFFFFFF">
+      <BitField name="_IminLine" description="IminLine" start="0" size="4" />
+      <BitField name="DMinLine" description="DMinLine" start="16" size="4" />
+      <BitField name="ERG" description="ERG" start="20" size="4" />
+      <BitField name="CWG" description="CWG" start="24" size="4" />
+      <BitField name="Format" description="Format" start="29" size="3" />
+    </Register>
+    <Register name="CCSIDR" description="Cache Size ID register" start="+0x8" size="4" access="ReadOnly" reset_value="0X00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LineSize" description="LineSize" start="0" size="3" />
+      <BitField name="Associativity" description="Associativity" start="3" size="10" />
+      <BitField name="NumSets" description="NumSets" start="13" size="15" />
+      <BitField name="WA" description="WA" start="28" size="1" />
+      <BitField name="RA" description="RA" start="29" size="1" />
+      <BitField name="WB" description="WB" start="30" size="1" />
+      <BitField name="WT" description="WT" start="31" size="1" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="PSSI" description="PSSI register block" start="0x48020400">
+    <Register name="PSSI_CR" description="PSSI control register " start="+0x0" size="4" reset_value="0x40000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CKPOL" description="Parallel data clock polarity This bit configures the capture edge of the parallel clock or the edge used for driving outputs, depending on OUTEN." start="5" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Falling edge active for inputs or rising edge active for outputs" start="0x0" />
+        <Enum name="B_0x1" description="Rising edge active for inputs or falling edge active for outputs." start="0x1" />
+      </BitField>
+      <BitField name="DEPOL" description="Data enable (PSSI_DE) polarity This bit indicates the level on the PSSI_DE pin when the data are not valid on the parallel interface." start="6" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="PSSI_DE active low (0 indicates that data is valid)" start="0x0" />
+        <Enum name="B_0x1" description="PSSI_DE active high (1 indicates that data is valid)" start="0x1" />
+      </BitField>
+      <BitField name="RDYPOL" description="Ready (PSSI_RDY) polarity This bit indicates the level on the PSSI_RDY pin when the data are not valid on the parallel interface." start="8" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="PSSI_RDY active low (0 indicates that the receiver is ready to receive)" start="0x0" />
+        <Enum name="B_0x1" description="PSSI_RDY active high (1 indicates that the receiver is ready to receive)" start="0x1" />
+      </BitField>
+      <BitField name="EDM" description="Extended data mode" start="10" size="2" access="Read/Write">
+        <Enum name="B_0x0" description="Interface captures 8-bit data on every parallel data clock" start="0x0" />
+        <Enum name="B_0x1" description="Reserved, must not be selected" start="0x1" />
+        <Enum name="B_0x2" description="Reserved, must not be selected" start="0x2" />
+        <Enum name="B_0x3" description="The interface captures 16-bit data on every parallel data clock" start="0x3" />
+      </BitField>
+      <BitField name="ENABLE" description="PSSI enable The contents of the FIFO are flushed when ENABLE is cleared to 0. Note: When ENABLE=1, the content of PSSI_CR must not be changed, except for the ENABLE bit itself. All configuration bits can change as soon as ENABLE changes from 0 to 1. The DMA controller and all PSSI configuration registers must be programmed correctly before setting the ENABLE bit to 1. The ENABLE bit and the DCMI ENABLE bit (bit 15 of DCMI_CR) must not be set to 1 at the same time." start="14" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="PSSI disabled" start="0x0" />
+        <Enum name="B_0x1" description="PSSI enabled" start="0x1" />
+      </BitField>
+      <BitField name="DERDYCFG" description="Data enable and ready configuration When the PSSI_RDY function is mapped to the PSSI_DE pin (settings 101 or 111), it is still the RDYPOL bit which determines its polarity. Similarly, when the PSSI_DE function is mapped to the PSSI_RDY pin (settings 110 or 111), it is still the DEPOL bit which determines its polarity." start="18" size="3" access="Read/Write">
+        <Enum name="B_0x0" description="PSSI_DE and PSSI_RDY both disabled" start="0x0" />
+        <Enum name="B_0x1" description="Only PSSI_RDY enabled" start="0x1" />
+        <Enum name="B_0x2" description="Only PSSI_DE enabled" start="0x2" />
+        <Enum name="B_0x3" description="Both PSSI_RDY and PSSI_DE alternate functions enabled" start="0x3" />
+        <Enum name="B_0x4" description="Both PSSI_RDY and PSSI_DE features enabled - bidirectional on PSSI_RDY pin (see )" start="0x4" />
+        <Enum name="B_0x5" description="Only PSSI_RDY function enabled, but mapped to PSSI_DE pin" start="0x5" />
+        <Enum name="B_0x6" description="Only PSSI_DE function enabled, but mapped to PSSI_RDY pin" start="0x6" />
+        <Enum name="B_0x7" description="Both PSSI_RDY and PSSI_DE features enabled - bidirectional on PSSI_DE pin (see )" start="0x7" />
+      </BitField>
+      <BitField name="DMAEN" description="DMA enable bit" start="30" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="DMA transfers are disabled. The user application can directly access the PSSI_DR register when DMA transfers are disabled." start="0x0" />
+        <Enum name="B_0x1" description="DMA transfers are enabled (default configuration). A DMA channel in the general-purpose DMA controller must be configured to perform transfers from/to PSSI_DR." start="0x1" />
+      </BitField>
+      <BitField name="OUTEN" description="Data direction selection bit" start="31" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="Receive mode: data is input synchronously with PSSI_PDCK" start="0x0" />
+        <Enum name="B_0x1" description="Transmit mode: data is output synchronously with PSSI_PDCK" start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="PSSI_SR" description="PSSI status register " start="+0x4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RTT4B" description="FIFO is ready to transfer four bytes" start="2" size="1" access="ReadOnly">
+        <Enum name="B_0x1" description="FIFO is ready for a four-byte (32-bit) transfer. In receive mode, this means that at least four valid data bytes are in the FIFO. In transmit mode, this means that there are at least four bytes free in the FIFO." start="0x1" />
+        <Enum name="B_0x0" description="FIFO is not ready for a four-byte transfer" start="0x0" />
+      </BitField>
+      <BitField name="RTT1B" description="FIFO is ready to transfer one byte" start="3" size="1" access="ReadOnly">
+        <Enum name="B_0x1" description="FIFO is ready for a one byte (32-bit) transfer. In receive mode, this means that at least one valid data byte is in the FIFO. In transmit mode, this means that there is at least one byte free in the FIFO." start="0x1" />
+        <Enum name="B_0x0" description="FIFO is not ready for a 1-byte transfer" start="0x0" />
+      </BitField>
+    </Register>
+    <Register name="PSSI_RIS" description="PSSI raw interrupt status register " start="+0x8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OVR_RIS" description="Data buffer overrun/underrun raw interrupt status This bit is cleared by writing a 1 to the OVR_ISC bit in PSSI_ICR." start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No overrun/underrun occurred" start="0x0" />
+        <Enum name="B_0x1" description="An overrun/underrun occurred: overrun in receive mode, underrun in transmit mode." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="PSSI_IER" description="PSSI interrupt enable register " start="+0xc" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OVR_IE" description="Data buffer overrun/underrun interrupt enable" start="1" size="1" access="Read/Write">
+        <Enum name="B_0x0" description="No interrupt generation" start="0x0" />
+        <Enum name="B_0x1" description="An interrupt is generated if either an overrun or an underrun error occurred." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="PSSI_MIS" description="PSSI masked interrupt status register " start="+0x10" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OVR_MIS" description="Data buffer overrun/underrun masked interrupt status This bit is set to 1 only when PSSI_IER/OVR_IE and PSSI_RIS/OVR_RIS are both set to 1." start="1" size="1" access="ReadOnly">
+        <Enum name="B_0x0" description="No interrupt is generated when an overrun/underrun error occurs" start="0x0" />
+        <Enum name="B_0x1" description="An interrupt is generated if there is either an overrun or an underrun error and the OVR_IE bit is set in PSSI_IER." start="0x1" />
+      </BitField>
+    </Register>
+    <Register name="PSSI_ICR" description="PSSI interrupt clear register " start="+0x14" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OVR_ISC" description="Data buffer overrun/underrun interrupt status clear Writing this bit to 1 clears the OVR_RIS bit in PSSI_RIS." start="1" size="1" access="WriteOnly" />
+    </Register>
+    <Register name="PSSI_DR" description="PSSI data register " start="+0x28" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BYTE0" description="Data byte 0" start="0" size="8" access="Read/Write" />
+      <BitField name="BYTE1" description="Data byte 1" start="8" size="8" access="Read/Write" />
+      <BitField name="BYTE2" description="Data byte 2" start="16" size="8" access="Read/Write" />
+      <BitField name="BYTE3" description="Data byte 3" start="24" size="8" access="Read/Write" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="PWR" description="PWR" start="0x58024800">
+    <Register name="CR1" description="PWR control register 1" start="+0x0" size="4" access="Read/Write" reset_value="0xF000C000" reset_mask="0xFFFFFFFF">
+      <BitField name="LPDS" description="Low-power Deepsleep with SVOS3 (SVOS4 and SVOS5 always use low-power, regardless of the setting of this bit)" start="0" size="1" />
+      <BitField name="PVDE" description="Programmable voltage detector enable" start="4" size="1" />
+      <BitField name="PLS" description="Programmable voltage detector level selection These bits select the voltage threshold detected by the PVD. Note: Refer to Section Electrical characteristics of the product datasheet for more details." start="5" size="3" />
+      <BitField name="DBP" description="Disable backup domain write protection In reset state, the RCC_BDCR register, the RTC registers (including the backup registers), BREN and MOEN bits in PWR_CR2 register, are protected against parasitic write access. This bit must be set to enable write access to these registers." start="8" size="1" />
+      <BitField name="FLPS" description="Flash low-power mode in DStop mode This bit allows to obtain the best trade-off between low-power consumption and restart time when exiting from DStop mode. When it is set, the Flash memory enters low-power mode when D1 domain is in DStop mode." start="9" size="1" />
+      <BitField name="SVOS" description="System Stop mode voltage scaling selection These bits control the VCORE voltage level in system Stop mode, to obtain the best trade-off between power consumption and performance." start="14" size="2" />
+      <BitField name="AVDEN" description="Peripheral voltage monitor on VDDA enable" start="16" size="1" />
+      <BitField name="ALS" description="Analog voltage detector level selection These bits select the voltage threshold detected by the AVD." start="17" size="2" />
+    </Register>
+    <Register name="CSR1" description="PWR control status register 1" start="+0x4" size="4" access="ReadOnly" reset_value="0x00004000" reset_mask="0xFFFFFFFF">
+      <BitField name="PVDO" description="Programmable voltage detect output This bit is set and cleared by hardware. It is valid only if the PVD has been enabled by the PVDE bit. Note: since the PVD is disabled in Standby mode, this bit is equal to 0 after Standby or reset until the PVDE bit is set." start="4" size="1" />
+      <BitField name="ACTVOSRDY" description="Voltage levels ready bit for currently used VOS and SDLEVEL This bit is set to 1 by hardware when the voltage regulator and the SD converter are both disabled and Bypass mode is selected in PWR control register 3 (PWR_CR3)." start="13" size="1" />
+      <BitField name="ACTVOS" description="VOS currently applied for VCORE voltage scaling selection. These bits reflect the last VOS value applied to the PMU." start="14" size="2" />
+      <BitField name="AVDO" description="Analog voltage detector output on VDDA This bit is set and cleared by hardware. It is valid only if AVD on VDDA is enabled by the AVDEN bit. Note: Since the AVD is disabled in Standby mode, this bit is equal to 0 after Standby or reset until the AVDEN bit is set." start="16" size="1" />
+    </Register>
+    <Register name="CR2" description="This register is not reset by wakeup from Standby mode, RESET signal and VDD POR. It is only reset by VSW POR and VSWRST reset. This register shall not be accessed when VSWRST bit in RCC_BDCR register resets the VSW domain.After reset, PWR_CR2 register is write-protected. Prior to modifying its content, the DBP bit in PWR_CR1 register must be set to disable the write protection." start="+0x8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BREN" description="Backup regulator enable When set, the Backup regulator (used to maintain the backup RAM content in Standby and VBAT modes) is enabled. If BREN is reset, the backup regulator is switched off. The backup RAM can still be used in Run and Stop modes. However, its content will be lost in Standby and VBAT modes. If BREN is set, the application must wait till the Backup Regulator Ready flag (BRRDY) is set to indicate that the data written into the SRAM will be maintained in Standby and VBAT modes." start="0" size="1" access="Read/Write" />
+      <BitField name="MONEN" description="VBAT and temperature monitoring enable When set, the VBAT supply and temperature monitoring is enabled." start="4" size="1" access="Read/Write" />
+      <BitField name="BRRDY" description="Backup regulator ready This bit is set by hardware to indicate that the Backup regulator is ready." start="16" size="1" access="ReadOnly" />
+      <BitField name="VBATL" description="VBAT level monitoring versus low threshold" start="20" size="1" access="ReadOnly" />
+      <BitField name="VBATH" description="VBAT level monitoring versus high threshold" start="21" size="1" access="ReadOnly" />
+      <BitField name="TEMPL" description="Temperature level monitoring versus low threshold" start="22" size="1" access="ReadOnly" />
+      <BitField name="TEMPH" description="Temperature level monitoring versus high threshold" start="23" size="1" access="ReadOnly" />
+    </Register>
+    <Register name="CR3" description="Reset only by POR only, not reset by wakeup from Standby mode and RESET pad. The lower byte of this register is written once after POR and shall be written before changing VOS level or ck_sys clock frequency. No limitation applies to the upper bytes.Programming data corresponding to an invalid combination of SDLEVEL, SDEXTHP, SDEN, LDOEN and BYPASS bits (see Table9) will be ignored: data will not be written, the written-once mechanism will lock the register and any further write access will be ignored. The default supply configuration will be kept and the ACTVOSRDY bit in PWR control status register 1 (PWR_CSR1) will go on indicating invalid voltage levels. The system shall be power cycled before writing a new value." start="+0xC" size="4" reset_value="0x00000006" reset_mask="0xFFFFFFFF">
+      <BitField name="BYPASS" description="Power management unit bypass" start="0" size="1" access="Read/Write" />
+      <BitField name="LDOEN" description="Low drop-out regulator enable" start="1" size="1" access="Read/Write" />
+      <BitField name="SDEN" description="SD converter Enable" start="2" size="1" access="Read/Write" />
+      <BitField name="VBE" description="VBAT charging enable" start="8" size="1" access="Read/Write" />
+      <BitField name="VBRS" description="VBAT charging resistor selection" start="9" size="1" access="Read/Write" />
+      <BitField name="USB33DEN" description="VDD33USB voltage level detector enable." start="24" size="1" access="WriteOnly" />
+      <BitField name="USBREGEN" description="USB regulator enable." start="25" size="1" access="Read/Write" />
+      <BitField name="USB33RDY" description="USB supply ready." start="26" size="1" access="ReadOnly" />
+    </Register>
+    <Register name="CPUCR" description="This register allows controlling CPU1 power." start="+0x10" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PDDS_D1" description="D1 domain Power Down Deepsleep selection. This bit allows CPU1 to define the Deepsleep mode for D1 domain." start="0" size="1" access="Read/Write" />
+      <BitField name="PDDS_D2" description="D2 domain Power Down Deepsleep. This bit allows CPU1 to define the Deepsleep mode for D2 domain." start="1" size="1" access="Read/Write" />
+      <BitField name="PDDS_D3" description="System D3 domain Power Down Deepsleep. This bit allows CPU1 to define the Deepsleep mode for System D3 domain." start="2" size="1" access="Read/Write" />
+      <BitField name="STOPF" description="STOP flag This bit is set by hardware and cleared only by any reset or by setting the CPU1 CSSF bit." start="5" size="1" access="ReadOnly" />
+      <BitField name="SBF" description="System Standby flag This bit is set by hardware and cleared only by a POR (Power-on Reset) or by setting the CPU1 CSSF bit" start="6" size="1" access="ReadOnly" />
+      <BitField name="SBF_D1" description="D1 domain DStandby flag This bit is set by hardware and cleared by any system reset or by setting the CPU1 CSSF bit. Once set, this bit can be cleared only when the D1 domain is no longer in DStandby mode." start="7" size="1" access="ReadOnly" />
+      <BitField name="SBF_D2" description="D2 domain DStandby flag This bit is set by hardware and cleared by any system reset or by setting the CPU1 CSSF bit. Once set, this bit can be cleared only when the D2 domain is no longer in DStandby mode." start="8" size="1" access="ReadOnly" />
+      <BitField name="CSSF" description="Clear D1 domain CPU1 Standby, Stop and HOLD flags (always read as 0) This bit is cleared to 0 by hardware." start="9" size="1" access="Read/Write" />
+      <BitField name="RUN_D3" description="Keep system D3 domain in Run mode regardless of the CPU sub-systems modes" start="11" size="1" access="Read/Write" />
+    </Register>
+    <Register name="D3CR" description="This register allows controlling D3 domain power.Following reset VOSRDY will be read 1 by software" start="+0x18" size="4" reset_value="0x00004000" reset_mask="0xFFFFFFFF">
+      <BitField name="VOSRDY" description="VOS Ready bit for VCORE voltage scaling output selection. This bit is set to 1 by hardware when Bypass mode is selected in PWR control register 3 (PWR_CR3)." start="13" size="1" access="ReadOnly" />
+      <BitField name="VOS" description="Voltage scaling selection according to performance These bits control the VCORE voltage level and allow to obtains the best trade-off between power consumption and performance: When increasing the performance, the voltage scaling shall be changed before increasing the system frequency. When decreasing performance, the system frequency shall first be decreased before changing the voltage scaling." start="14" size="2" access="Read/Write" />
+    </Register>
+    <Register name="WKUPCR" description="reset only by system reset, not reset by wakeup from Standby mode5 wait states are required when writing this register (when clearing a WKUPF bit in PWR_WKUPFR, the AHB write access will complete after the WKUPF has been cleared)." start="+0x20" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="WKUPC" description="Clear Wakeup pin flag for WKUP. These bits are always read as 0." start="0" size="6" />
+    </Register>
+    <Register name="WKUPFR" description="reset only by system reset, not reset by wakeup from Standby mode" start="+0x24" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="WKUPF1" description="Wakeup pin WKUPF flag. This bit is set by hardware and cleared only by a Reset pin or by setting the WKUPCn+1 bit in the PWR wakeup clear register (PWR_WKUPCR)." start="0" size="1" />
+      <BitField name="WKUPF2" description="Wakeup pin WKUPF flag. This bit is set by hardware and cleared only by a Reset pin or by setting the WKUPCn+1 bit in the PWR wakeup clear register (PWR_WKUPCR)." start="1" size="1" />
+      <BitField name="WKUPF3" description="Wakeup pin WKUPF flag. This bit is set by hardware and cleared only by a Reset pin or by setting the WKUPCn+1 bit in the PWR wakeup clear register (PWR_WKUPCR)." start="2" size="1" />
+      <BitField name="WKUPF4" description="Wakeup pin WKUPF flag. This bit is set by hardware and cleared only by a Reset pin or by setting the WKUPCn+1 bit in the PWR wakeup clear register (PWR_WKUPCR)." start="3" size="1" />
+      <BitField name="WKUPF5" description="Wakeup pin WKUPF flag. This bit is set by hardware and cleared only by a Reset pin or by setting the WKUPCn+1 bit in the PWR wakeup clear register (PWR_WKUPCR)." start="4" size="1" />
+      <BitField name="WKUPF6" description="Wakeup pin WKUPF flag. This bit is set by hardware and cleared only by a Reset pin or by setting the WKUPCn+1 bit in the PWR wakeup clear register (PWR_WKUPCR)." start="5" size="1" />
+    </Register>
+    <Register name="WKUPEPR" description="Reset only by system reset, not reset by wakeup from Standby mode" start="+0x28" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="WKUPEN1" description="Enable Wakeup Pin WKUPn+1 Each bit is set and cleared by software. Note: An additional wakeup event is detected if WKUPn+1 pin is enabled (by setting the WKUPENn+1 bit) when WKUPn+1 pin level is already high when WKUPPn+1 selects rising edge, or low when WKUPPn+1 selects falling edge." start="0" size="1" />
+      <BitField name="WKUPEN2" description="Enable Wakeup Pin WKUPn+1 Each bit is set and cleared by software. Note: An additional wakeup event is detected if WKUPn+1 pin is enabled (by setting the WKUPENn+1 bit) when WKUPn+1 pin level is already high when WKUPPn+1 selects rising edge, or low when WKUPPn+1 selects falling edge." start="1" size="1" />
+      <BitField name="WKUPEN3" description="Enable Wakeup Pin WKUPn+1 Each bit is set and cleared by software. Note: An additional wakeup event is detected if WKUPn+1 pin is enabled (by setting the WKUPENn+1 bit) when WKUPn+1 pin level is already high when WKUPPn+1 selects rising edge, or low when WKUPPn+1 selects falling edge." start="2" size="1" />
+      <BitField name="WKUPEN4" description="Enable Wakeup Pin WKUPn+1 Each bit is set and cleared by software. Note: An additional wakeup event is detected if WKUPn+1 pin is enabled (by setting the WKUPENn+1 bit) when WKUPn+1 pin level is already high when WKUPPn+1 selects rising edge, or low when WKUPPn+1 selects falling edge." start="3" size="1" />
+      <BitField name="WKUPEN5" description="Enable Wakeup Pin WKUPn+1 Each bit is set and cleared by software. Note: An additional wakeup event is detected if WKUPn+1 pin is enabled (by setting the WKUPENn+1 bit) when WKUPn+1 pin level is already high when WKUPPn+1 selects rising edge, or low when WKUPPn+1 selects falling edge." start="4" size="1" />
+      <BitField name="WKUPEN6" description="Enable Wakeup Pin WKUPn+1 Each bit is set and cleared by software. Note: An additional wakeup event is detected if WKUPn+1 pin is enabled (by setting the WKUPENn+1 bit) when WKUPn+1 pin level is already high when WKUPPn+1 selects rising edge, or low when WKUPPn+1 selects falling edge." start="5" size="1" />
+      <BitField name="WKUPP1" description="Wakeup pin polarity bit for WKUPn-7 These bits define the polarity used for event detection on WKUPn-7 external wakeup pin." start="8" size="1" />
+      <BitField name="WKUPP2" description="Wakeup pin polarity bit for WKUPn-7 These bits define the polarity used for event detection on WKUPn-7 external wakeup pin." start="9" size="1" />
+      <BitField name="WKUPP3" description="Wakeup pin polarity bit for WKUPn-7 These bits define the polarity used for event detection on WKUPn-7 external wakeup pin." start="10" size="1" />
+      <BitField name="WKUPP4" description="Wakeup pin polarity bit for WKUPn-7 These bits define the polarity used for event detection on WKUPn-7 external wakeup pin." start="11" size="1" />
+      <BitField name="WKUPP5" description="Wakeup pin polarity bit for WKUPn-7 These bits define the polarity used for event detection on WKUPn-7 external wakeup pin." start="12" size="1" />
+      <BitField name="WKUPP6" description="Wakeup pin polarity bit for WKUPn-7 These bits define the polarity used for event detection on WKUPn-7 external wakeup pin." start="13" size="1" />
+      <BitField name="WKUPPUPD1" description="Wakeup pin pull configuration" start="16" size="2" />
+      <BitField name="WKUPPUPD2" description="Wakeup pin pull configuration" start="18" size="2" />
+      <BitField name="WKUPPUPD3" description="Wakeup pin pull configuration" start="20" size="2" />
+      <BitField name="WKUPPUPD4" description="Wakeup pin pull configuration" start="22" size="2" />
+      <BitField name="WKUPPUPD5" description="Wakeup pin pull configuration" start="24" size="2" />
+      <BitField name="WKUPPUPD6" description="Wakeup pin pull configuration for WKUP(truncate(n/2)-7) These bits define the I/O pad pull configuration used when WKUPEN(truncate(n/2)-7) = 1. The associated GPIO port pull configuration shall be set to the same value or to 00. The Wakeup pin pull configuration is kept in Standby mode." start="26" size="2" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="RAMECC1" description="ECC controller is associated to each RAM area" start="0x52009000">
+    <Register name="IER" description="RAMECC interrupt enable register" start="+0x0" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="GIE" description="Global interrupt enable" start="0" size="1" />
+      <BitField name="GECCSEIE_" description="Global ECC single error interrupt enable" start="1" size="1" />
+      <BitField name="GECCDEIE" description="Global ECC double error interrupt enable" start="2" size="1" />
+      <BitField name="GECCDEBWIE" description="Global ECC double error on byte write (BW) interrupt enable" start="3" size="1" />
+    </Register>
+    <Register name="M1CR" description="RAMECC monitor x configuration register" start="+0x20" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ECCSEIE" description="ECC single error interrupt enable" start="2" size="1" />
+      <BitField name="ECCDEIE" description="ECC double error interrupt enable" start="3" size="1" />
+      <BitField name="ECCDEBWIE" description="ECC double error on byte write (BW) interrupt enable" start="4" size="1" />
+      <BitField name="ECCELEN" description="ECC error latching enable" start="5" size="1" />
+    </Register>
+    <Register name="M1SR" description="RAMECC monitor x status register" start="+0x24" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ECCSEIE" description="ECC single error interrupt enable" start="2" size="1" />
+      <BitField name="ECCDEIE" description="ECC double error interrupt enable" start="3" size="1" />
+      <BitField name="ECCDEBWIE" description="ECC double error on byte write (BW) interrupt enable" start="4" size="1" />
+      <BitField name="ECCELEN" description="ECC error latching enable" start="5" size="1" />
+    </Register>
+    <Register name="M1FAR" description="RAMECC monitor x failing address register" start="+0x28" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ECCSEIE" description="ECC single error interrupt enable" start="2" size="1" />
+      <BitField name="ECCDEIE" description="ECC double error interrupt enable" start="3" size="1" />
+      <BitField name="ECCDEBWIE" description="ECC double error on byte write (BW) interrupt enable" start="4" size="1" />
+      <BitField name="ECCELEN" description="ECC error latching enable" start="5" size="1" />
+    </Register>
+    <Register name="M1FDRL" description="RAMECC monitor x failing data low register" start="+0x2C" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ECCSEIE" description="ECC single error interrupt enable" start="2" size="1" />
+      <BitField name="ECCDEIE" description="ECC double error interrupt enable" start="3" size="1" />
+      <BitField name="ECCDEBWIE" description="ECC double error on byte write (BW) interrupt enable" start="4" size="1" />
+      <BitField name="ECCELEN" description="ECC error latching enable" start="5" size="1" />
+    </Register>
+    <Register name="M1FDRH" description="RAMECC monitor x failing data high register" start="+0x30" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ECCSEIE" description="ECC single error interrupt enable" start="2" size="1" />
+      <BitField name="ECCDEIE" description="ECC double error interrupt enable" start="3" size="1" />
+      <BitField name="ECCDEBWIE" description="ECC double error on byte write (BW) interrupt enable" start="4" size="1" />
+      <BitField name="ECCELEN" description="ECC error latching enable" start="5" size="1" />
+    </Register>
+    <Register name="M1FECR" description="RAMECC monitor x failing ECC error code register" start="+0x34" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SEDCF" description="ECC single error detected and corrected flag" start="0" size="1" />
+      <BitField name="DEDF" description="ECC double error detected flag" start="1" size="1" />
+      <BitField name="DEBWDF" description="ECC double error on byte write (BW) detected flag" start="2" size="1" />
+    </Register>
+    <Register name="M2CR" description="RAMECC monitor x configuration register" start="+0x40" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SEDCF" description="ECC single error detected and corrected flag" start="0" size="1" />
+      <BitField name="DEDF" description="ECC double error detected flag" start="1" size="1" />
+      <BitField name="DEBWDF" description="ECC double error on byte write (BW) detected flag" start="2" size="1" />
+    </Register>
+    <Register name="M2SR" description="RAMECC monitor x status register" start="+0x44" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SEDCF" description="ECC single error detected and corrected flag" start="0" size="1" />
+      <BitField name="DEDF" description="ECC double error detected flag" start="1" size="1" />
+      <BitField name="DEBWDF" description="ECC double error on byte write (BW) detected flag" start="2" size="1" />
+    </Register>
+    <Register name="M2FAR" description="RAMECC monitor x failing address register" start="+0x48" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SEDCF" description="ECC single error detected and corrected flag" start="0" size="1" />
+      <BitField name="DEDF" description="ECC double error detected flag" start="1" size="1" />
+      <BitField name="DEBWDF" description="ECC double error on byte write (BW) detected flag" start="2" size="1" />
+    </Register>
+    <Register name="M2FDRL" description="RAMECC monitor x failing data low register" start="+0x4C" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SEDCF" description="ECC single error detected and corrected flag" start="0" size="1" />
+      <BitField name="DEDF" description="ECC double error detected flag" start="1" size="1" />
+      <BitField name="DEBWDF" description="ECC double error on byte write (BW) detected flag" start="2" size="1" />
+    </Register>
+    <Register name="M2FDRH" description="RAMECC monitor x failing data high register" start="+0x50" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FADD" description="ECC error failing address" start="0" size="32" />
+    </Register>
+    <Register name="M2FECR" description="RAMECC monitor x failing ECC error code register" start="+0x58" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FADD" description="ECC error failing address" start="0" size="32" />
+    </Register>
+    <Register name="M3CR" description="RAMECC monitor x configuration register" start="+0x60" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FADD" description="ECC error failing address" start="0" size="32" />
+    </Register>
+    <Register name="M3SR" description="RAMECC monitor x status register" start="+0x64" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FADD" description="ECC error failing address" start="0" size="32" />
+    </Register>
+    <Register name="M3FAR" description="RAMECC monitor x failing address register" start="+0x68" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FADD" description="ECC error failing address" start="0" size="32" />
+    </Register>
+    <Register name="M3FDRL" description="RAMECC monitor x failing data low register" start="+0x6C" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FDATAL" description="Failing data low" start="0" size="32" />
+    </Register>
+    <Register name="M3FDRH" description="RAMECC monitor x failing data high register" start="+0x70" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FDATAL" description="Failing data low" start="0" size="32" />
+    </Register>
+    <Register name="M3FECR" description="RAMECC monitor x failing ECC error code register" start="+0x7C" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FDATAL" description="Failing data low" start="0" size="32" />
+    </Register>
+    <Register name="M4CR" description="RAMECC monitor x configuration register" start="+0x80" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FDATAL" description="Failing data low" start="0" size="32" />
+    </Register>
+    <Register name="M4SR" description="RAMECC monitor x status register" start="+0x84" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FDATAL" description="Failing data low" start="0" size="32" />
+    </Register>
+    <Register name="M4FAR" description="RAMECC monitor x failing address register" start="+0x88" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FDATAH" description="Failing data high (64-bit memory)" start="0" size="32" />
+    </Register>
+    <Register name="M4FDRL" description="RAMECC monitor x failing data low register" start="+0x8C" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FDATAH" description="Failing data high (64-bit memory)" start="0" size="32" />
+    </Register>
+    <Register name="M4FDRH" description="RAMECC monitor x failing data high register" start="+0x90" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FDATAH" description="Failing data high (64-bit memory)" start="0" size="32" />
+    </Register>
+    <Register name="M4FECR" description="RAMECC monitor x failing ECC error code register" start="+0x90" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FDATAH" description="Failing data high (64-bit memory)" start="0" size="32" />
+    </Register>
+    <Register name="M5CR" description="RAMECC monitor x configuration register" start="+0xA0" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FEC" description="Failing error code" start="0" size="32" />
+    </Register>
+    <Register name="M5SR" description="RAMECC monitor x status register" start="+0xA4" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FEC" description="Failing error code" start="0" size="32" />
+    </Register>
+    <Register name="M5FAR" description="RAMECC monitor x failing address register" start="+0xA8" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FEC" description="Failing error code" start="0" size="32" />
+    </Register>
+    <Register name="M5FDRL" description="RAMECC monitor x failing data low register" start="+0xAC" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FEC" description="Failing error code" start="0" size="32" />
+    </Register>
+    <Register name="M5FDRH" description="RAMECC monitor x failing data high register" start="+0xB0" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FEC" description="Failing error code" start="0" size="32" />
+    </Register>
+    <Register name="M5FECR" description="RAMECC monitor x failing ECC error code register" start="+0xB4" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FEC" description="Failing error code" start="0" size="32" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="RAMECC2" description="ECC controller is associated to each RAM area" start="0x48023000">
+    <Register name="IER" description="RAMECC interrupt enable register" start="+0x0" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="GIE" description="Global interrupt enable" start="0" size="1" />
+      <BitField name="GECCSEIE_" description="Global ECC single error interrupt enable" start="1" size="1" />
+      <BitField name="GECCDEIE" description="Global ECC double error interrupt enable" start="2" size="1" />
+      <BitField name="GECCDEBWIE" description="Global ECC double error on byte write (BW) interrupt enable" start="3" size="1" />
+    </Register>
+    <Register name="M1CR" description="RAMECC monitor x configuration register" start="+0x20" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ECCSEIE" description="ECC single error interrupt enable" start="2" size="1" />
+      <BitField name="ECCDEIE" description="ECC double error interrupt enable" start="3" size="1" />
+      <BitField name="ECCDEBWIE" description="ECC double error on byte write (BW) interrupt enable" start="4" size="1" />
+      <BitField name="ECCELEN" description="ECC error latching enable" start="5" size="1" />
+    </Register>
+    <Register name="M2CR" description="RAMECC monitor x configuration register" start="+0x40" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ECCSEIE" description="ECC single error interrupt enable" start="2" size="1" />
+      <BitField name="ECCDEIE" description="ECC double error interrupt enable" start="3" size="1" />
+      <BitField name="ECCDEBWIE" description="ECC double error on byte write (BW) interrupt enable" start="4" size="1" />
+      <BitField name="ECCELEN" description="ECC error latching enable" start="5" size="1" />
+    </Register>
+    <Register name="M3CR" description="RAMECC monitor x configuration register" start="+0x60" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ECCSEIE" description="ECC single error interrupt enable" start="2" size="1" />
+      <BitField name="ECCDEIE" description="ECC double error interrupt enable" start="3" size="1" />
+      <BitField name="ECCDEBWIE" description="ECC double error on byte write (BW) interrupt enable" start="4" size="1" />
+      <BitField name="ECCELEN" description="ECC error latching enable" start="5" size="1" />
+    </Register>
+    <Register name="M4CR" description="RAMECC monitor x configuration register" start="+0x80" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ECCSEIE" description="ECC single error interrupt enable" start="2" size="1" />
+      <BitField name="ECCDEIE" description="ECC double error interrupt enable" start="3" size="1" />
+      <BitField name="ECCDEBWIE" description="ECC double error on byte write (BW) interrupt enable" start="4" size="1" />
+      <BitField name="ECCELEN" description="ECC error latching enable" start="5" size="1" />
+    </Register>
+    <Register name="M5CR" description="RAMECC monitor x configuration register" start="+0xA0" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ECCSEIE" description="ECC single error interrupt enable" start="2" size="1" />
+      <BitField name="ECCDEIE" description="ECC double error interrupt enable" start="3" size="1" />
+      <BitField name="ECCDEBWIE" description="ECC double error on byte write (BW) interrupt enable" start="4" size="1" />
+      <BitField name="ECCELEN" description="ECC error latching enable" start="5" size="1" />
+    </Register>
+    <Register name="M1SR" description="RAMECC monitor x status register" start="+0x24" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SEDCF" description="ECC single error detected and corrected flag" start="0" size="1" />
+      <BitField name="DEDF" description="ECC double error detected flag" start="1" size="1" />
+      <BitField name="DEBWDF" description="ECC double error on byte write (BW) detected flag" start="2" size="1" />
+    </Register>
+    <Register name="M2SR" description="RAMECC monitor x status register" start="+0x44" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SEDCF" description="ECC single error detected and corrected flag" start="0" size="1" />
+      <BitField name="DEDF" description="ECC double error detected flag" start="1" size="1" />
+      <BitField name="DEBWDF" description="ECC double error on byte write (BW) detected flag" start="2" size="1" />
+    </Register>
+    <Register name="M3SR" description="RAMECC monitor x status register" start="+0x64" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SEDCF" description="ECC single error detected and corrected flag" start="0" size="1" />
+      <BitField name="DEDF" description="ECC double error detected flag" start="1" size="1" />
+      <BitField name="DEBWDF" description="ECC double error on byte write (BW) detected flag" start="2" size="1" />
+    </Register>
+    <Register name="M4SR" description="RAMECC monitor x status register" start="+0x84" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SEDCF" description="ECC single error detected and corrected flag" start="0" size="1" />
+      <BitField name="DEDF" description="ECC double error detected flag" start="1" size="1" />
+      <BitField name="DEBWDF" description="ECC double error on byte write (BW) detected flag" start="2" size="1" />
+    </Register>
+    <Register name="M5SR" description="RAMECC monitor x status register" start="+0xA4" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SEDCF" description="ECC single error detected and corrected flag" start="0" size="1" />
+      <BitField name="DEDF" description="ECC double error detected flag" start="1" size="1" />
+      <BitField name="DEBWDF" description="ECC double error on byte write (BW) detected flag" start="2" size="1" />
+    </Register>
+    <Register name="M1FAR" description="RAMECC monitor x failing address register" start="+0x28" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FADD" description="ECC error failing address" start="0" size="32" />
+    </Register>
+    <Register name="M2FAR" description="RAMECC monitor x failing address register" start="+0x48" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FADD" description="ECC error failing address" start="0" size="32" />
+    </Register>
+    <Register name="M3FAR" description="RAMECC monitor x failing address register" start="+0x68" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FADD" description="ECC error failing address" start="0" size="32" />
+    </Register>
+    <Register name="M4FAR" description="RAMECC monitor x failing address register" start="+0x88" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FADD" description="ECC error failing address" start="0" size="32" />
+    </Register>
+    <Register name="M5FAR" description="RAMECC monitor x failing address register" start="+0xA8" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FADD" description="ECC error failing address" start="0" size="32" />
+    </Register>
+    <Register name="M1FDRL" description="RAMECC monitor x failing data low register" start="+0x2C" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FDATAL" description="Failing data low" start="0" size="32" />
+    </Register>
+    <Register name="M2FDRL" description="RAMECC monitor x failing data low register" start="+0x4C" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FDATAL" description="Failing data low" start="0" size="32" />
+    </Register>
+    <Register name="M3FDRL" description="RAMECC monitor x failing data low register" start="+0x6C" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FDATAL" description="Failing data low" start="0" size="32" />
+    </Register>
+    <Register name="M4FDRL" description="RAMECC monitor x failing data low register" start="+0x8C" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FDATAL" description="Failing data low" start="0" size="32" />
+    </Register>
+    <Register name="M5FDRL" description="RAMECC monitor x failing data low register" start="+0xAC" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FDATAL" description="Failing data low" start="0" size="32" />
+    </Register>
+    <Register name="M1FDRH" description="RAMECC monitor x failing data high register" start="+0x30" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FDATAH" description="Failing data high (64-bit memory)" start="0" size="32" />
+    </Register>
+    <Register name="M2FDRH" description="RAMECC monitor x failing data high register" start="+0x50" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FDATAH" description="Failing data high (64-bit memory)" start="0" size="32" />
+    </Register>
+    <Register name="M3FDRH" description="RAMECC monitor x failing data high register" start="+0x70" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FDATAH" description="Failing data high (64-bit memory)" start="0" size="32" />
+    </Register>
+    <Register name="M4FDRH" description="RAMECC monitor x failing data high register" start="+0x90" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FDATAH" description="Failing data high (64-bit memory)" start="0" size="32" />
+    </Register>
+    <Register name="M5FDRH" description="RAMECC monitor x failing data high register" start="+0xB0" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FEC" description="Failing error code" start="0" size="32" />
+    </Register>
+    <Register name="M1FECR" description="RAMECC monitor x failing ECC error code register" start="+0x34" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FEC" description="Failing error code" start="0" size="32" />
+    </Register>
+    <Register name="M2FECR" description="RAMECC monitor x failing ECC error code register" start="+0x58" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FEC" description="Failing error code" start="0" size="32" />
+    </Register>
+    <Register name="M3FECR" description="RAMECC monitor x failing ECC error code register" start="+0x7C" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FEC" description="Failing error code" start="0" size="32" />
+    </Register>
+    <Register name="M4FECR" description="RAMECC monitor x failing ECC error code register" start="+0x90" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FEC" description="Failing error code" start="0" size="32" />
+    </Register>
+    <Register name="M5FECR" description="RAMECC monitor x failing ECC error code register" start="+0xB4" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FEC" description="Failing error code" start="0" size="32" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="RAMECC3" description="ECC controller is associated to each RAM area" start="0x58027000">
+    <Register name="IER" description="RAMECC interrupt enable register" start="+0x0" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="GIE" description="Global interrupt enable" start="0" size="1" />
+      <BitField name="GECCSEIE_" description="Global ECC single error interrupt enable" start="1" size="1" />
+      <BitField name="GECCDEIE" description="Global ECC double error interrupt enable" start="2" size="1" />
+      <BitField name="GECCDEBWIE" description="Global ECC double error on byte write (BW) interrupt enable" start="3" size="1" />
+    </Register>
+    <Register name="M1CR" description="RAMECC monitor x configuration register" start="+0x20" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ECCSEIE" description="ECC single error interrupt enable" start="2" size="1" />
+      <BitField name="ECCDEIE" description="ECC double error interrupt enable" start="3" size="1" />
+      <BitField name="ECCDEBWIE" description="ECC double error on byte write (BW) interrupt enable" start="4" size="1" />
+      <BitField name="ECCELEN" description="ECC error latching enable" start="5" size="1" />
+    </Register>
+    <Register name="M2CR" description="RAMECC monitor x configuration register" start="+0x40" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ECCSEIE" description="ECC single error interrupt enable" start="2" size="1" />
+      <BitField name="ECCDEIE" description="ECC double error interrupt enable" start="3" size="1" />
+      <BitField name="ECCDEBWIE" description="ECC double error on byte write (BW) interrupt enable" start="4" size="1" />
+      <BitField name="ECCELEN" description="ECC error latching enable" start="5" size="1" />
+    </Register>
+    <Register name="M1SR" description="RAMECC monitor x status register" start="+0x24" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SEDCF" description="ECC single error detected and corrected flag" start="0" size="1" />
+      <BitField name="DEDF" description="ECC double error detected flag" start="1" size="1" />
+      <BitField name="DEBWDF" description="ECC double error on byte write (BW) detected flag" start="2" size="1" />
+    </Register>
+    <Register name="M2SR" description="RAMECC monitor x status register" start="+0x44" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SEDCF" description="ECC single error detected and corrected flag" start="0" size="1" />
+      <BitField name="DEDF" description="ECC double error detected flag" start="1" size="1" />
+      <BitField name="DEBWDF" description="ECC double error on byte write (BW) detected flag" start="2" size="1" />
+    </Register>
+    <Register name="M1FAR" description="RAMECC monitor x failing address register" start="+0x28" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FADD" description="ECC error failing address" start="0" size="32" />
+    </Register>
+    <Register name="M2FAR" description="RAMECC monitor x failing address register" start="+0x48" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FADD" description="ECC error failing address" start="0" size="32" />
+    </Register>
+    <Register name="M1FDRL" description="RAMECC monitor x failing data low register" start="+0x2C" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FDATAL" description="Failing data low" start="0" size="32" />
+    </Register>
+    <Register name="M2FDRL" description="RAMECC monitor x failing data low register" start="+0x4C" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FDATAL" description="Failing data low" start="0" size="32" />
+    </Register>
+    <Register name="M1FDRH" description="RAMECC monitor x failing data high register" start="+0x30" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FDATAH" description="Failing data high (64-bit memory)" start="0" size="32" />
+    </Register>
+    <Register name="M2FDRH" description="RAMECC monitor x failing data high register" start="+0x50" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FDATAH" description="Failing data high (64-bit memory)" start="0" size="32" />
+    </Register>
+    <Register name="M1FECR" description="RAMECC monitor x failing ECC error code register" start="+0x34" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FEC" description="Failing error code" start="0" size="32" />
+    </Register>
+    <Register name="M2FECR" description="RAMECC monitor x failing ECC error code register" start="+0x58" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FEC" description="Failing error code" start="0" size="32" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="RCC" description="Reset and clock control" start="0x58024400">
+    <Register name="CR" description="clock control register" start="+0x0" size="4" access="Read/Write" reset_value="0x00000083" reset_mask="0xFFFFFFFF">
+      <BitField name="HSION" description="Internal high-speed clock enable" start="0" size="1" />
+      <BitField name="HSIKERON" description="High Speed Internal clock enable in Stop mode" start="1" size="1" />
+      <BitField name="HSIRDY" description="HSI clock ready flag" start="2" size="1" />
+      <BitField name="HSIDIV" description="HSI clock divider" start="3" size="2" />
+      <BitField name="HSIDIVF" description="HSI divider flag" start="5" size="1" />
+      <BitField name="CSION" description="CSI clock enable" start="7" size="1" />
+      <BitField name="CSIRDY" description="CSI clock ready flag" start="8" size="1" />
+      <BitField name="CSIKERON" description="CSI clock enable in Stop mode" start="9" size="1" />
+      <BitField name="RC48ON" description="RC48 clock enable" start="12" size="1" />
+      <BitField name="RC48RDY" description="RC48 clock ready flag" start="13" size="1" />
+      <BitField name="D1CKRDY" description="D1 domain clocks ready flag" start="14" size="1" />
+      <BitField name="D2CKRDY" description="D2 domain clocks ready flag" start="15" size="1" />
+      <BitField name="HSEON" description="HSE clock enable" start="16" size="1" />
+      <BitField name="HSERDY" description="HSE clock ready flag" start="17" size="1" />
+      <BitField name="HSEBYP" description="HSE clock bypass" start="18" size="1" />
+      <BitField name="HSECSSON" description="HSE Clock Security System enable" start="19" size="1" />
+      <BitField name="PLL1ON" description="PLL1 enable" start="24" size="1" />
+      <BitField name="PLL1RDY" description="PLL1 clock ready flag" start="25" size="1" />
+      <BitField name="PLL2ON" description="PLL2 enable" start="26" size="1" />
+      <BitField name="PLL2RDY" description="PLL2 clock ready flag" start="27" size="1" />
+      <BitField name="PLL3ON" description="PLL3 enable" start="28" size="1" />
+      <BitField name="PLL3RDY" description="PLL3 clock ready flag" start="29" size="1" />
+    </Register>
+    <Register name="ICSCR" description="RCC Internal Clock Source Calibration Register" start="+0x4" size="4" reset_value="0x40000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HSICAL" description="HSI clock calibration" start="0" size="12" access="ReadOnly" />
+      <BitField name="HSITRIM" description="HSI clock trimming" start="12" size="6" access="Read/Write" />
+      <BitField name="CSICAL" description="CSI clock calibration" start="18" size="8" access="ReadOnly" />
+      <BitField name="CSITRIM" description="CSI clock trimming" start="26" size="5" access="Read/Write" />
+    </Register>
+    <Register name="CRRCR" description="RCC Clock Recovery RC Register" start="+0x8" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RC48CAL" description="Internal RC 48 MHz clock calibration" start="0" size="10" />
+    </Register>
+    <Register name="CFGR" description="RCC Clock Configuration Register" start="+0x10" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SW" description="System clock switch" start="0" size="3" />
+      <BitField name="SWS" description="System clock switch status" start="3" size="3" />
+      <BitField name="STOPWUCK" description="System clock selection after a wake up from system Stop" start="6" size="1" />
+      <BitField name="STOPKERWUCK" description="Kernel clock selection after a wake up from system Stop" start="7" size="1" />
+      <BitField name="RTCPRE" description="HSE division factor for RTC clock" start="8" size="6" />
+      <BitField name="TIMPRE" description="Timers clocks prescaler selection" start="15" size="1" />
+      <BitField name="MCO1PRE" description="MCO1 prescaler" start="18" size="4" />
+      <BitField name="MCO1SEL" description="Micro-controller clock output 1" start="22" size="3" />
+      <BitField name="MCO2PRE" description="MCO2 prescaler" start="25" size="4" />
+      <BitField name="MCO2SEL" description="Micro-controller clock output 2" start="29" size="3" />
+    </Register>
+    <Register name="D1CFGR" description="RCC Domain 1 Clock Configuration Register" start="+0x18" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="HPRE" description="D1 domain AHB prescaler" start="0" size="4" />
+      <BitField name="D1PPRE" description="D1 domain APB3 prescaler" start="4" size="3" />
+      <BitField name="D1CPRE" description="D1 domain Core prescaler" start="8" size="4" />
+    </Register>
+    <Register name="D2CFGR" description="RCC Domain 2 Clock Configuration Register" start="+0x1C" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="D2PPRE1" description="D2 domain APB1 prescaler" start="4" size="3" />
+      <BitField name="D2PPRE2" description="D2 domain APB2 prescaler" start="8" size="3" />
+    </Register>
+    <Register name="D3CFGR" description="RCC Domain 3 Clock Configuration Register" start="+0x20" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="D3PPRE" description="D3 domain APB4 prescaler" start="4" size="3" />
+    </Register>
+    <Register name="PLLCKSELR" description="RCC PLLs Clock Source Selection Register" start="+0x28" size="4" access="Read/Write" reset_value="0x02020200" reset_mask="0xFFFFFFFF">
+      <BitField name="PLLSRC" description="DIVMx and PLLs clock source selection" start="0" size="2" />
+      <BitField name="DIVM1" description="Prescaler for PLL1" start="4" size="6" />
+      <BitField name="DIVM2" description="Prescaler for PLL2" start="12" size="6" />
+      <BitField name="DIVM3" description="Prescaler for PLL3" start="20" size="6" />
+    </Register>
+    <Register name="PLLCFGR" description="RCC PLLs Configuration Register" start="+0x2C" size="4" access="Read/Write" reset_value="0x01FF0000" reset_mask="0xFFFFFFFF">
+      <BitField name="PLL1FRACEN" description="PLL1 fractional latch enable" start="0" size="1" />
+      <BitField name="PLL1VCOSEL" description="PLL1 VCO selection" start="1" size="1" />
+      <BitField name="PLL1RGE" description="PLL1 input frequency range" start="2" size="2" />
+      <BitField name="PLL2FRACEN" description="PLL2 fractional latch enable" start="4" size="1" />
+      <BitField name="PLL2VCOSEL" description="PLL2 VCO selection" start="5" size="1" />
+      <BitField name="PLL2RGE" description="PLL2 input frequency range" start="6" size="2" />
+      <BitField name="PLL3FRACEN" description="PLL3 fractional latch enable" start="8" size="1" />
+      <BitField name="PLL3VCOSEL" description="PLL3 VCO selection" start="9" size="1" />
+      <BitField name="PLL3RGE" description="PLL3 input frequency range" start="10" size="2" />
+      <BitField name="DIVP1EN" description="PLL1 DIVP divider output enable" start="16" size="1" />
+      <BitField name="DIVQ1EN" description="PLL1 DIVQ divider output enable" start="17" size="1" />
+      <BitField name="DIVR1EN" description="PLL1 DIVR divider output enable" start="18" size="1" />
+      <BitField name="DIVP2EN" description="PLL2 DIVP divider output enable" start="19" size="1" />
+      <BitField name="DIVQ2EN" description="PLL2 DIVQ divider output enable" start="20" size="1" />
+      <BitField name="DIVR2EN" description="PLL2 DIVR divider output enable" start="21" size="1" />
+      <BitField name="DIVP3EN" description="PLL3 DIVP divider output enable" start="22" size="1" />
+      <BitField name="DIVQ3EN" description="PLL3 DIVQ divider output enable" start="23" size="1" />
+      <BitField name="DIVR3EN" description="PLL3 DIVR divider output enable" start="24" size="1" />
+    </Register>
+    <Register name="PLL1DIVR" description="RCC PLL1 Dividers Configuration Register" start="+0x30" size="4" access="Read/Write" reset_value="0x01010280" reset_mask="0xFFFFFFFF">
+      <BitField name="DIVN1" description="Multiplication factor for PLL1 VCO" start="0" size="9" />
+      <BitField name="DIVP1" description="PLL1 DIVP division factor" start="9" size="7" />
+      <BitField name="DIVQ1" description="PLL1 DIVQ division factor" start="16" size="7" />
+      <BitField name="DIVR1" description="PLL1 DIVR division factor" start="24" size="7" />
+    </Register>
+    <Register name="PLL1FRACR" description="RCC PLL1 Fractional Divider Register" start="+0x34" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FRACN1" description="Fractional part of the multiplication factor for PLL1 VCO" start="3" size="13" />
+    </Register>
+    <Register name="PLL2DIVR" description="RCC PLL2 Dividers Configuration Register" start="+0x38" size="4" access="Read/Write" reset_value="0x01010280" reset_mask="0xFFFFFFFF">
+      <BitField name="DIVN1" description="Multiplication factor for PLL1 VCO" start="0" size="9" />
+      <BitField name="DIVP1" description="PLL1 DIVP division factor" start="9" size="7" />
+      <BitField name="DIVQ1" description="PLL1 DIVQ division factor" start="16" size="7" />
+      <BitField name="DIVR1" description="PLL1 DIVR division factor" start="24" size="7" />
+    </Register>
+    <Register name="PLL2FRACR" description="RCC PLL2 Fractional Divider Register" start="+0x3C" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FRACN2" description="Fractional part of the multiplication factor for PLL VCO" start="3" size="13" />
+    </Register>
+    <Register name="PLL3DIVR" description="RCC PLL3 Dividers Configuration Register" start="+0x40" size="4" access="Read/Write" reset_value="0x01010280" reset_mask="0xFFFFFFFF">
+      <BitField name="DIVN3" description="Multiplication factor for PLL1 VCO" start="0" size="9" />
+      <BitField name="DIVP3" description="PLL DIVP division factor" start="9" size="7" />
+      <BitField name="DIVQ3" description="PLL DIVQ division factor" start="16" size="7" />
+      <BitField name="DIVR3" description="PLL DIVR division factor" start="24" size="7" />
+    </Register>
+    <Register name="PLL3FRACR" description="RCC PLL3 Fractional Divider Register" start="+0x44" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FRACN3" description="Fractional part of the multiplication factor for PLL3 VCO" start="3" size="13" />
+    </Register>
+    <Register name="D1CCIPR" description="RCC Domain 1 Kernel Clock Configuration Register" start="+0x4C" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FMCSRC" description="FMC kernel clock source selection" start="0" size="2" />
+      <BitField name="QSPISRC" description="QUADSPI kernel clock source selection" start="4" size="2" />
+      <BitField name="SDMMCSRC" description="SDMMC kernel clock source selection" start="16" size="1" />
+      <BitField name="CKPERSRC" description="per_ck clock source selection" start="28" size="2" />
+    </Register>
+    <Register name="D2CCIP1R" description="RCC Domain 2 Kernel Clock Configuration Register" start="+0x50" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SAI1SRC" description="SAI1 and DFSDM1 kernel Aclk clock source selection" start="0" size="3" />
+      <BitField name="SAI23SRC" description="SAI2 and SAI3 kernel clock source selection" start="6" size="3" />
+      <BitField name="SPI123SRC" description="SPI/I2S1,2 and 3 kernel clock source selection" start="12" size="3" />
+      <BitField name="SPI45SRC" description="SPI4 and 5 kernel clock source selection" start="16" size="3" />
+      <BitField name="SPDIFSRC" description="SPDIFRX kernel clock source selection" start="20" size="2" />
+      <BitField name="DFSDM1SRC" description="DFSDM1 kernel Clk clock source selection" start="24" size="1" />
+      <BitField name="FDCANSRC" description="FDCAN kernel clock source selection" start="28" size="2" />
+      <BitField name="SWPSRC" description="SWPMI kernel clock source selection" start="31" size="1" />
+    </Register>
+    <Register name="D2CCIP2R" description="RCC Domain 2 Kernel Clock Configuration Register" start="+0x54" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="USART234578SRC" description="USART2/3, UART4,5, 7/8 (APB1) kernel clock source selection" start="0" size="3" />
+      <BitField name="USART16SRC" description="USART1 and 6 kernel clock source selection" start="3" size="3" />
+      <BitField name="RNGSRC" description="RNG kernel clock source selection" start="8" size="2" />
+      <BitField name="I2C123SRC" description="I2C1,2,3 kernel clock source selection" start="12" size="2" />
+      <BitField name="USBSRC" description="USBOTG 1 and 2 kernel clock source selection" start="20" size="2" />
+      <BitField name="CECSRC" description="HDMI-CEC kernel clock source selection" start="22" size="2" />
+      <BitField name="LPTIM1SRC" description="LPTIM1 kernel clock source selection" start="28" size="3" />
+    </Register>
+    <Register name="D3CCIPR" description="RCC Domain 3 Kernel Clock Configuration Register" start="+0x58" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LPUART1SRC" description="LPUART1 kernel clock source selection" start="0" size="3" />
+      <BitField name="I2C4SRC" description="I2C4 kernel clock source selection" start="8" size="2" />
+      <BitField name="LPTIM2SRC" description="LPTIM2 kernel clock source selection" start="10" size="3" />
+      <BitField name="LPTIM345SRC" description="LPTIM3,4,5 kernel clock source selection" start="13" size="3" />
+      <BitField name="ADCSRC" description="SAR ADC kernel clock source selection" start="16" size="2" />
+      <BitField name="SAI4ASRC" description="Sub-Block A of SAI4 kernel clock source selection" start="21" size="3" />
+      <BitField name="SAI4BSRC" description="Sub-Block B of SAI4 kernel clock source selection" start="24" size="3" />
+      <BitField name="SPI6SRC" description="SPI6 kernel clock source selection" start="28" size="3" />
+    </Register>
+    <Register name="CIER" description="RCC Clock Source Interrupt Enable Register" start="+0x60" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LSIRDYIE" description="LSI ready Interrupt Enable" start="0" size="1" />
+      <BitField name="LSERDYIE" description="LSE ready Interrupt Enable" start="1" size="1" />
+      <BitField name="HSIRDYIE" description="HSI ready Interrupt Enable" start="2" size="1" />
+      <BitField name="HSERDYIE" description="HSE ready Interrupt Enable" start="3" size="1" />
+      <BitField name="CSIRDYIE" description="CSI ready Interrupt Enable" start="4" size="1" />
+      <BitField name="RC48RDYIE" description="RC48 ready Interrupt Enable" start="5" size="1" />
+      <BitField name="PLL1RDYIE" description="PLL1 ready Interrupt Enable" start="6" size="1" />
+      <BitField name="PLL2RDYIE" description="PLL2 ready Interrupt Enable" start="7" size="1" />
+      <BitField name="PLL3RDYIE" description="PLL3 ready Interrupt Enable" start="8" size="1" />
+      <BitField name="LSECSSIE" description="LSE clock security system Interrupt Enable" start="9" size="1" />
+    </Register>
+    <Register name="CIFR" description="RCC Clock Source Interrupt Flag Register" start="+0x64" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LSIRDYF" description="LSI ready Interrupt Flag" start="0" size="1" />
+      <BitField name="LSERDYF" description="LSE ready Interrupt Flag" start="1" size="1" />
+      <BitField name="HSIRDYF" description="HSI ready Interrupt Flag" start="2" size="1" />
+      <BitField name="HSERDYF" description="HSE ready Interrupt Flag" start="3" size="1" />
+      <BitField name="CSIRDY" description="CSI ready Interrupt Flag" start="4" size="1" />
+      <BitField name="RC48RDYF" description="RC48 ready Interrupt Flag" start="5" size="1" />
+      <BitField name="PLL1RDYF" description="PLL1 ready Interrupt Flag" start="6" size="1" />
+      <BitField name="PLL2RDYF" description="PLL2 ready Interrupt Flag" start="7" size="1" />
+      <BitField name="PLL3RDYF" description="PLL3 ready Interrupt Flag" start="8" size="1" />
+      <BitField name="LSECSSF" description="LSE clock security system Interrupt Flag" start="9" size="1" />
+      <BitField name="HSECSSF" description="HSE clock security system Interrupt Flag" start="10" size="1" />
+    </Register>
+    <Register name="CICR" description="RCC Clock Source Interrupt Clear Register" start="+0x68" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LSIRDYC" description="LSI ready Interrupt Clear" start="0" size="1" />
+      <BitField name="LSERDYC" description="LSE ready Interrupt Clear" start="1" size="1" />
+      <BitField name="HSIRDYC" description="HSI ready Interrupt Clear" start="2" size="1" />
+      <BitField name="HSERDYC" description="HSE ready Interrupt Clear" start="3" size="1" />
+      <BitField name="HSE_ready_Interrupt_Clear" description="CSI ready Interrupt Clear" start="4" size="1" />
+      <BitField name="RC48RDYC" description="RC48 ready Interrupt Clear" start="5" size="1" />
+      <BitField name="PLL1RDYC" description="PLL1 ready Interrupt Clear" start="6" size="1" />
+      <BitField name="PLL2RDYC" description="PLL2 ready Interrupt Clear" start="7" size="1" />
+      <BitField name="PLL3RDYC" description="PLL3 ready Interrupt Clear" start="8" size="1" />
+      <BitField name="LSECSSC" description="LSE clock security system Interrupt Clear" start="9" size="1" />
+      <BitField name="HSECSSC" description="HSE clock security system Interrupt Clear" start="10" size="1" />
+    </Register>
+    <Register name="BDCR" description="RCC Backup Domain Control Register" start="+0x70" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LSEON" description="LSE oscillator enabled" start="0" size="1" />
+      <BitField name="LSERDY" description="LSE oscillator ready" start="1" size="1" />
+      <BitField name="LSEBYP" description="LSE oscillator bypass" start="2" size="1" />
+      <BitField name="LSEDRV" description="LSE oscillator driving capability" start="3" size="2" />
+      <BitField name="LSECSSON" description="LSE clock security system enable" start="5" size="1" />
+      <BitField name="LSECSSD" description="LSE clock security system failure detection" start="6" size="1" />
+      <BitField name="RTCSRC" description="RTC clock source selection" start="8" size="2" />
+      <BitField name="RTCEN" description="RTC clock enable" start="15" size="1" />
+      <BitField name="VSWRST" description="VSwitch domain software reset" start="16" size="1" />
+    </Register>
+    <Register name="CSR" description="RCC Clock Control and Status Register" start="+0x74" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LSION" description="LSI oscillator enable" start="0" size="1" />
+      <BitField name="LSIRDY" description="LSI oscillator ready" start="1" size="1" />
+    </Register>
+    <Register name="AHB3RSTR" description="RCC AHB3 Reset Register" start="+0x7C" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MDMARST" description="MDMA block reset" start="0" size="1" />
+      <BitField name="DMA2DRST" description="DMA2D block reset" start="4" size="1" />
+      <BitField name="JPGDECRST" description="JPGDEC block reset" start="5" size="1" />
+      <BitField name="FMCRST" description="FMC block reset" start="12" size="1" />
+      <BitField name="QSPIRST" description="QUADSPI and QUADSPI delay block reset" start="14" size="1" />
+      <BitField name="SDMMC1RST" description="SDMMC1 and SDMMC1 delay block reset" start="16" size="1" />
+      <BitField name="CPURST" description="CPU reset" start="31" size="1" />
+    </Register>
+    <Register name="AHB1RSTR" description="RCC AHB1 Peripheral Reset Register" start="+0x80" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DMA1RST" description="DMA1 block reset" start="0" size="1" />
+      <BitField name="DMA2RST" description="DMA2 block reset" start="1" size="1" />
+      <BitField name="ADC12RST" description="ADC1&amp;2 block reset" start="5" size="1" />
+      <BitField name="ETH1MACRST" description="ETH1MAC block reset" start="15" size="1" />
+      <BitField name="USB1OTGRST" description="USB1OTG block reset" start="25" size="1" />
+      <BitField name="USB2OTGRST" description="USB2OTG block reset" start="27" size="1" />
+    </Register>
+    <Register name="AHB2RSTR" description="RCC AHB2 Peripheral Reset Register" start="+0x84" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CAMITFRST" description="CAMITF block reset" start="0" size="1" />
+      <BitField name="CRYPTRST" description="Cryptography block reset" start="4" size="1" />
+      <BitField name="HASHRST" description="Hash block reset" start="5" size="1" />
+      <BitField name="RNGRST" description="Random Number Generator block reset" start="6" size="1" />
+      <BitField name="SDMMC2RST" description="SDMMC2 and SDMMC2 Delay block reset" start="9" size="1" />
+    </Register>
+    <Register name="AHB4RSTR" description="RCC AHB4 Peripheral Reset Register" start="+0x88" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="GPIOARST" description="GPIO block reset" start="0" size="1" />
+      <BitField name="GPIOBRST" description="GPIO block reset" start="1" size="1" />
+      <BitField name="GPIOCRST" description="GPIO block reset" start="2" size="1" />
+      <BitField name="GPIODRST" description="GPIO block reset" start="3" size="1" />
+      <BitField name="GPIOERST" description="GPIO block reset" start="4" size="1" />
+      <BitField name="GPIOFRST" description="GPIO block reset" start="5" size="1" />
+      <BitField name="GPIOGRST" description="GPIO block reset" start="6" size="1" />
+      <BitField name="GPIOHRST" description="GPIO block reset" start="7" size="1" />
+      <BitField name="GPIOIRST" description="GPIO block reset" start="8" size="1" />
+      <BitField name="GPIOJRST" description="GPIO block reset" start="9" size="1" />
+      <BitField name="GPIOKRST" description="GPIO block reset" start="10" size="1" />
+      <BitField name="CRCRST" description="CRC block reset" start="19" size="1" />
+      <BitField name="BDMARST" description="BDMA block reset" start="21" size="1" />
+      <BitField name="ADC3RST" description="ADC3 block reset" start="24" size="1" />
+      <BitField name="HSEMRST" description="HSEM block reset" start="25" size="1" />
+    </Register>
+    <Register name="APB3RSTR" description="RCC APB3 Peripheral Reset Register" start="+0x8C" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LTDCRST" description="LTDC block reset" start="3" size="1" />
+    </Register>
+    <Register name="APB1LRSTR" description="RCC APB1 Peripheral Reset Register" start="+0x90" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TIM2RST" description="TIM block reset" start="0" size="1" />
+      <BitField name="TIM3RST" description="TIM block reset" start="1" size="1" />
+      <BitField name="TIM4RST" description="TIM block reset" start="2" size="1" />
+      <BitField name="TIM5RST" description="TIM block reset" start="3" size="1" />
+      <BitField name="TIM6RST" description="TIM block reset" start="4" size="1" />
+      <BitField name="TIM7RST" description="TIM block reset" start="5" size="1" />
+      <BitField name="TIM12RST" description="TIM block reset" start="6" size="1" />
+      <BitField name="TIM13RST" description="TIM block reset" start="7" size="1" />
+      <BitField name="TIM14RST" description="TIM block reset" start="8" size="1" />
+      <BitField name="LPTIM1RST" description="TIM block reset" start="9" size="1" />
+      <BitField name="SPI2RST" description="SPI2 block reset" start="14" size="1" />
+      <BitField name="SPI3RST" description="SPI3 block reset" start="15" size="1" />
+      <BitField name="SPDIFRXRST" description="SPDIFRX block reset" start="16" size="1" />
+      <BitField name="USART2RST" description="USART2 block reset" start="17" size="1" />
+      <BitField name="USART3RST" description="USART3 block reset" start="18" size="1" />
+      <BitField name="UART4RST" description="UART4 block reset" start="19" size="1" />
+      <BitField name="UART5RST" description="UART5 block reset" start="20" size="1" />
+      <BitField name="I2C1RST" description="I2C1 block reset" start="21" size="1" />
+      <BitField name="I2C2RST" description="I2C2 block reset" start="22" size="1" />
+      <BitField name="I2C3RST" description="I2C3 block reset" start="23" size="1" />
+      <BitField name="HDMICECRST" description="HDMI-CEC block reset" start="27" size="1" />
+      <BitField name="DAC12RST" description="DAC1 and 2 Blocks Reset" start="29" size="1" />
+      <BitField name="USART7RST" description="USART7 block reset" start="30" size="1" />
+      <BitField name="USART8RST" description="USART8 block reset" start="31" size="1" />
+    </Register>
+    <Register name="APB1HRSTR" description="RCC APB1 Peripheral Reset Register" start="+0x94" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CRSRST" description="Clock Recovery System reset" start="1" size="1" />
+      <BitField name="SWPRST" description="SWPMI block reset" start="2" size="1" />
+      <BitField name="OPAMPRST" description="OPAMP block reset" start="4" size="1" />
+      <BitField name="MDIOSRST" description="MDIOS block reset" start="5" size="1" />
+      <BitField name="FDCANRST" description="FDCAN block reset" start="8" size="1" />
+    </Register>
+    <Register name="APB2RSTR" description="RCC APB2 Peripheral Reset Register" start="+0x98" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TIM1RST" description="TIM1 block reset" start="0" size="1" />
+      <BitField name="TIM8RST" description="TIM8 block reset" start="1" size="1" />
+      <BitField name="USART1RST" description="USART1 block reset" start="4" size="1" />
+      <BitField name="USART6RST" description="USART6 block reset" start="5" size="1" />
+      <BitField name="SPI1RST" description="SPI1 block reset" start="12" size="1" />
+      <BitField name="SPI4RST" description="SPI4 block reset" start="13" size="1" />
+      <BitField name="TIM15RST" description="TIM15 block reset" start="16" size="1" />
+      <BitField name="TIM16RST" description="TIM16 block reset" start="17" size="1" />
+      <BitField name="TIM17RST" description="TIM17 block reset" start="18" size="1" />
+      <BitField name="SPI5RST" description="SPI5 block reset" start="20" size="1" />
+      <BitField name="SAI1RST" description="SAI1 block reset" start="22" size="1" />
+      <BitField name="SAI2RST" description="SAI2 block reset" start="23" size="1" />
+      <BitField name="SAI3RST" description="SAI3 block reset" start="24" size="1" />
+      <BitField name="DFSDM1RST" description="DFSDM1 block reset" start="28" size="1" />
+    </Register>
+    <Register name="APB4RSTR" description="RCC APB4 Peripheral Reset Register" start="+0x9C" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SYSCFGRST" description="SYSCFG block reset" start="1" size="1" />
+      <BitField name="LPUART1RST" description="LPUART1 block reset" start="3" size="1" />
+      <BitField name="SPI6RST" description="SPI6 block reset" start="5" size="1" />
+      <BitField name="I2C4RST" description="I2C4 block reset" start="7" size="1" />
+      <BitField name="LPTIM2RST" description="LPTIM2 block reset" start="9" size="1" />
+      <BitField name="LPTIM3RST" description="LPTIM3 block reset" start="10" size="1" />
+      <BitField name="LPTIM4RST" description="LPTIM4 block reset" start="11" size="1" />
+      <BitField name="LPTIM5RST" description="LPTIM5 block reset" start="12" size="1" />
+      <BitField name="COMP12RST" description="COMP12 Blocks Reset" start="14" size="1" />
+      <BitField name="VREFRST" description="VREF block reset" start="15" size="1" />
+      <BitField name="SAI4RST" description="SAI4 block reset" start="21" size="1" />
+    </Register>
+    <Register name="GCR" description="RCC Global Control Register" start="+0xA0" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="WW1RSC" description="WWDG1 reset scope control" start="0" size="1" />
+    </Register>
+    <Register name="D3AMR" description="RCC D3 Autonomous mode Register" start="+0xA8" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BDMAAMEN" description="BDMA and DMAMUX Autonomous mode enable" start="0" size="1" />
+      <BitField name="LPUART1AMEN" description="LPUART1 Autonomous mode enable" start="3" size="1" />
+      <BitField name="SPI6AMEN" description="SPI6 Autonomous mode enable" start="5" size="1" />
+      <BitField name="I2C4AMEN" description="I2C4 Autonomous mode enable" start="7" size="1" />
+      <BitField name="LPTIM2AMEN" description="LPTIM2 Autonomous mode enable" start="9" size="1" />
+      <BitField name="LPTIM3AMEN" description="LPTIM3 Autonomous mode enable" start="10" size="1" />
+      <BitField name="LPTIM4AMEN" description="LPTIM4 Autonomous mode enable" start="11" size="1" />
+      <BitField name="LPTIM5AMEN" description="LPTIM5 Autonomous mode enable" start="12" size="1" />
+      <BitField name="COMP12AMEN" description="COMP12 Autonomous mode enable" start="14" size="1" />
+      <BitField name="VREFAMEN" description="VREF Autonomous mode enable" start="15" size="1" />
+      <BitField name="RTCAMEN" description="RTC Autonomous mode enable" start="16" size="1" />
+      <BitField name="CRCAMEN" description="CRC Autonomous mode enable" start="19" size="1" />
+      <BitField name="SAI4AMEN" description="SAI4 Autonomous mode enable" start="21" size="1" />
+      <BitField name="ADC3AMEN" description="ADC3 Autonomous mode enable" start="24" size="1" />
+      <BitField name="BKPSRAMAMEN" description="Backup RAM Autonomous mode enable" start="28" size="1" />
+      <BitField name="SRAM4AMEN" description="SRAM4 Autonomous mode enable" start="29" size="1" />
+    </Register>
+    <Register name="RSR" description="RCC Reset Status Register" start="+0xD0" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RMVF" description="Remove reset flag" start="16" size="1" />
+      <BitField name="CPURSTF" description="CPU reset flag" start="17" size="1" />
+      <BitField name="D1RSTF" description="D1 domain power switch reset flag" start="19" size="1" />
+      <BitField name="D2RSTF" description="D2 domain power switch reset flag" start="20" size="1" />
+      <BitField name="BORRSTF" description="BOR reset flag" start="21" size="1" />
+      <BitField name="PINRSTF" description="Pin reset flag (NRST)" start="22" size="1" />
+      <BitField name="PORRSTF" description="POR/PDR reset flag" start="23" size="1" />
+      <BitField name="SFTRSTF" description="System reset from CPU reset flag" start="24" size="1" />
+      <BitField name="IWDG1RSTF" description="Independent Watchdog reset flag" start="26" size="1" />
+      <BitField name="WWDG1RSTF" description="Window Watchdog reset flag" start="28" size="1" />
+      <BitField name="LPWRRSTF" description="Reset due to illegal D1 DStandby or CPU CStop flag" start="30" size="1" />
+    </Register>
+    <Register name="C1_RSR" description="RCC Reset Status Register" start="+0x130" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RMVF" description="Remove reset flag" start="16" size="1" />
+      <BitField name="CPURSTF" description="CPU reset flag" start="17" size="1" />
+      <BitField name="D1RSTF" description="D1 domain power switch reset flag" start="19" size="1" />
+      <BitField name="D2RSTF" description="D2 domain power switch reset flag" start="20" size="1" />
+      <BitField name="BORRSTF" description="BOR reset flag" start="21" size="1" />
+      <BitField name="PINRSTF" description="Pin reset flag (NRST)" start="22" size="1" />
+      <BitField name="PORRSTF" description="POR/PDR reset flag" start="23" size="1" />
+      <BitField name="SFTRSTF" description="System reset from CPU reset flag" start="24" size="1" />
+      <BitField name="IWDG1RSTF" description="Independent Watchdog reset flag" start="26" size="1" />
+      <BitField name="WWDG1RSTF" description="Window Watchdog reset flag" start="28" size="1" />
+      <BitField name="LPWRRSTF" description="Reset due to illegal D1 DStandby or CPU CStop flag" start="30" size="1" />
+    </Register>
+    <Register name="C1_AHB3ENR" description="RCC AHB3 Clock Register" start="+0x134" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MDMAEN" description="MDMA Peripheral Clock Enable" start="0" size="1" />
+      <BitField name="DMA2DEN" description="DMA2D Peripheral Clock Enable" start="4" size="1" />
+      <BitField name="JPGDECEN" description="JPGDEC Peripheral Clock Enable" start="5" size="1" />
+      <BitField name="FMCEN" description="FMC Peripheral Clocks Enable" start="12" size="1" />
+      <BitField name="QSPIEN" description="QUADSPI and QUADSPI Delay Clock Enable" start="14" size="1" />
+      <BitField name="SDMMC1EN" description="SDMMC1 and SDMMC1 Delay Clock Enable" start="16" size="1" />
+    </Register>
+    <Register name="AHB3ENR" description="RCC AHB3 Clock Register" start="+0xD4" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MDMAEN" description="MDMA Peripheral Clock Enable" start="0" size="1" />
+      <BitField name="DMA2DEN" description="DMA2D Peripheral Clock Enable" start="4" size="1" />
+      <BitField name="JPGDECEN" description="JPGDEC Peripheral Clock Enable" start="5" size="1" />
+      <BitField name="FMCEN" description="FMC Peripheral Clocks Enable" start="12" size="1" />
+      <BitField name="QSPIEN" description="QUADSPI and QUADSPI Delay Clock Enable" start="14" size="1" />
+      <BitField name="SDMMC1EN" description="SDMMC1 and SDMMC1 Delay Clock Enable" start="16" size="1" />
+    </Register>
+    <Register name="AHB1ENR" description="RCC AHB1 Clock Register" start="+0xD8" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DMA1EN" description="DMA1 Clock Enable" start="0" size="1" />
+      <BitField name="DMA2EN" description="DMA2 Clock Enable" start="1" size="1" />
+      <BitField name="ADC12EN" description="ADC1/2 Peripheral Clocks Enable" start="5" size="1" />
+      <BitField name="ETH1MACEN" description="Ethernet MAC bus interface Clock Enable" start="15" size="1" />
+      <BitField name="ETH1TXEN" description="Ethernet Transmission Clock Enable" start="16" size="1" />
+      <BitField name="ETH1RXEN" description="Ethernet Reception Clock Enable" start="17" size="1" />
+      <BitField name="USB1OTGEN" description="USB1OTG Peripheral Clocks Enable" start="25" size="1" />
+      <BitField name="USB1ULPIEN" description="USB_PHY1 Clocks Enable" start="26" size="1" />
+      <BitField name="USB2OTGEN" description="USB2OTG Peripheral Clocks Enable" start="27" size="1" />
+      <BitField name="USB2ULPIEN" description="USB_PHY2 Clocks Enable" start="28" size="1" />
+    </Register>
+    <Register name="C1_AHB1ENR" description="RCC AHB1 Clock Register" start="+0x138" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DMA1EN" description="DMA1 Clock Enable" start="0" size="1" />
+      <BitField name="DMA2EN" description="DMA2 Clock Enable" start="1" size="1" />
+      <BitField name="ADC12EN" description="ADC1/2 Peripheral Clocks Enable" start="5" size="1" />
+      <BitField name="ETH1MACEN" description="Ethernet MAC bus interface Clock Enable" start="15" size="1" />
+      <BitField name="ETH1TXEN" description="Ethernet Transmission Clock Enable" start="16" size="1" />
+      <BitField name="ETH1RXEN" description="Ethernet Reception Clock Enable" start="17" size="1" />
+      <BitField name="USB1OTGEN" description="USB1OTG Peripheral Clocks Enable" start="25" size="1" />
+      <BitField name="USB1ULPIEN" description="USB_PHY1 Clocks Enable" start="26" size="1" />
+      <BitField name="USB2OTGEN" description="USB2OTG Peripheral Clocks Enable" start="27" size="1" />
+      <BitField name="USB2ULPIEN" description="USB_PHY2 Clocks Enable" start="28" size="1" />
+    </Register>
+    <Register name="C1_AHB2ENR" description="RCC AHB2 Clock Register" start="+0x13C" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CAMITFEN" description="CAMITF peripheral clock enable" start="0" size="1" />
+      <BitField name="CRYPTEN" description="CRYPT peripheral clock enable" start="4" size="1" />
+      <BitField name="HASHEN" description="HASH peripheral clock enable" start="5" size="1" />
+      <BitField name="RNGEN" description="RNG peripheral clocks enable" start="6" size="1" />
+      <BitField name="SDMMC2EN" description="SDMMC2 and SDMMC2 delay clock enable" start="9" size="1" />
+      <BitField name="SRAM1EN" description="SRAM1 block enable" start="29" size="1" />
+      <BitField name="SRAM2EN" description="SRAM2 block enable" start="30" size="1" />
+      <BitField name="SRAM3EN" description="SRAM3 block enable" start="31" size="1" />
+    </Register>
+    <Register name="AHB2ENR" description="RCC AHB2 Clock Register" start="+0xDC" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CAMITFEN" description="CAMITF peripheral clock enable" start="0" size="1" />
+      <BitField name="CRYPTEN" description="CRYPT peripheral clock enable" start="4" size="1" />
+      <BitField name="HASHEN" description="HASH peripheral clock enable" start="5" size="1" />
+      <BitField name="RNGEN" description="RNG peripheral clocks enable" start="6" size="1" />
+      <BitField name="SDMMC2EN" description="SDMMC2 and SDMMC2 delay clock enable" start="9" size="1" />
+      <BitField name="SRAM1EN" description="SRAM1 block enable" start="29" size="1" />
+      <BitField name="SRAM2EN" description="SRAM2 block enable" start="30" size="1" />
+      <BitField name="SRAM3EN" description="SRAM3 block enable" start="31" size="1" />
+    </Register>
+    <Register name="AHB4ENR" description="RCC AHB4 Clock Register" start="+0xE0" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="GPIOAEN" description="0GPIO peripheral clock enable" start="0" size="1" />
+      <BitField name="GPIOBEN" description="0GPIO peripheral clock enable" start="1" size="1" />
+      <BitField name="GPIOCEN" description="0GPIO peripheral clock enable" start="2" size="1" />
+      <BitField name="GPIODEN" description="0GPIO peripheral clock enable" start="3" size="1" />
+      <BitField name="GPIOEEN" description="0GPIO peripheral clock enable" start="4" size="1" />
+      <BitField name="GPIOFEN" description="0GPIO peripheral clock enable" start="5" size="1" />
+      <BitField name="GPIOGEN" description="0GPIO peripheral clock enable" start="6" size="1" />
+      <BitField name="GPIOHEN" description="0GPIO peripheral clock enable" start="7" size="1" />
+      <BitField name="GPIOIEN" description="0GPIO peripheral clock enable" start="8" size="1" />
+      <BitField name="GPIOJEN" description="0GPIO peripheral clock enable" start="9" size="1" />
+      <BitField name="GPIOKEN" description="0GPIO peripheral clock enable" start="10" size="1" />
+      <BitField name="CRCEN" description="CRC peripheral clock enable" start="19" size="1" />
+      <BitField name="BDMAEN" description="BDMA and DMAMUX2 Clock Enable" start="21" size="1" />
+      <BitField name="ADC3EN" description="ADC3 Peripheral Clocks Enable" start="24" size="1" />
+      <BitField name="HSEMEN" description="HSEM peripheral clock enable" start="25" size="1" />
+      <BitField name="BKPRAMEN" description="Backup RAM Clock Enable" start="28" size="1" />
+    </Register>
+    <Register name="C1_AHB4ENR" description="RCC AHB4 Clock Register" start="+0x140" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="GPIOAEN" description="0GPIO peripheral clock enable" start="0" size="1" />
+      <BitField name="GPIOBEN" description="0GPIO peripheral clock enable" start="1" size="1" />
+      <BitField name="GPIOCEN" description="0GPIO peripheral clock enable" start="2" size="1" />
+      <BitField name="GPIODEN" description="0GPIO peripheral clock enable" start="3" size="1" />
+      <BitField name="GPIOEEN" description="0GPIO peripheral clock enable" start="4" size="1" />
+      <BitField name="GPIOFEN" description="0GPIO peripheral clock enable" start="5" size="1" />
+      <BitField name="GPIOGEN" description="0GPIO peripheral clock enable" start="6" size="1" />
+      <BitField name="GPIOHEN" description="0GPIO peripheral clock enable" start="7" size="1" />
+      <BitField name="GPIOIEN" description="0GPIO peripheral clock enable" start="8" size="1" />
+      <BitField name="GPIOJEN" description="0GPIO peripheral clock enable" start="9" size="1" />
+      <BitField name="GPIOKEN" description="0GPIO peripheral clock enable" start="10" size="1" />
+      <BitField name="CRCEN" description="CRC peripheral clock enable" start="19" size="1" />
+      <BitField name="BDMAEN" description="BDMA and DMAMUX2 Clock Enable" start="21" size="1" />
+      <BitField name="ADC3EN" description="ADC3 Peripheral Clocks Enable" start="24" size="1" />
+      <BitField name="HSEMEN" description="HSEM peripheral clock enable" start="25" size="1" />
+      <BitField name="BKPRAMEN" description="Backup RAM Clock Enable" start="28" size="1" />
+    </Register>
+    <Register name="C1_APB3ENR" description="RCC APB3 Clock Register" start="+0x144" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LTDCEN" description="LTDC peripheral clock enable" start="3" size="1" />
+      <BitField name="WWDG1EN" description="WWDG1 Clock Enable" start="6" size="1" />
+    </Register>
+    <Register name="APB3ENR" description="RCC APB3 Clock Register" start="+0xE4" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LTDCEN" description="LTDC peripheral clock enable" start="3" size="1" />
+      <BitField name="WWDG1EN" description="WWDG1 Clock Enable" start="6" size="1" />
+    </Register>
+    <Register name="APB1LENR" description="RCC APB1 Clock Register" start="+0xE8" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TIM2EN" description="TIM peripheral clock enable" start="0" size="1" />
+      <BitField name="TIM3EN" description="TIM peripheral clock enable" start="1" size="1" />
+      <BitField name="TIM4EN" description="TIM peripheral clock enable" start="2" size="1" />
+      <BitField name="TIM5EN" description="TIM peripheral clock enable" start="3" size="1" />
+      <BitField name="TIM6EN" description="TIM peripheral clock enable" start="4" size="1" />
+      <BitField name="TIM7EN" description="TIM peripheral clock enable" start="5" size="1" />
+      <BitField name="TIM12EN" description="TIM peripheral clock enable" start="6" size="1" />
+      <BitField name="TIM13EN" description="TIM peripheral clock enable" start="7" size="1" />
+      <BitField name="TIM14EN" description="TIM peripheral clock enable" start="8" size="1" />
+      <BitField name="LPTIM1EN" description="LPTIM1 Peripheral Clocks Enable" start="9" size="1" />
+      <BitField name="SPI2EN" description="SPI2 Peripheral Clocks Enable" start="14" size="1" />
+      <BitField name="SPI3EN" description="SPI3 Peripheral Clocks Enable" start="15" size="1" />
+      <BitField name="SPDIFRXEN" description="SPDIFRX Peripheral Clocks Enable" start="16" size="1" />
+      <BitField name="USART2EN" description="USART2 Peripheral Clocks Enable" start="17" size="1" />
+      <BitField name="USART3EN" description="USART3 Peripheral Clocks Enable" start="18" size="1" />
+      <BitField name="UART4EN" description="UART4 Peripheral Clocks Enable" start="19" size="1" />
+      <BitField name="UART5EN" description="UART5 Peripheral Clocks Enable" start="20" size="1" />
+      <BitField name="I2C1EN" description="I2C1 Peripheral Clocks Enable" start="21" size="1" />
+      <BitField name="I2C2EN" description="I2C2 Peripheral Clocks Enable" start="22" size="1" />
+      <BitField name="I2C3EN" description="I2C3 Peripheral Clocks Enable" start="23" size="1" />
+      <BitField name="HDMICECEN" description="HDMI-CEC peripheral clock enable" start="27" size="1" />
+      <BitField name="DAC12EN" description="DAC1&amp;2 peripheral clock enable" start="29" size="1" />
+      <BitField name="USART7EN" description="USART7 Peripheral Clocks Enable" start="30" size="1" />
+      <BitField name="USART8EN" description="USART8 Peripheral Clocks Enable" start="31" size="1" />
+    </Register>
+    <Register name="C1_APB1LENR" description="RCC APB1 Clock Register" start="+0x148" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TIM2EN" description="TIM peripheral clock enable" start="0" size="1" />
+      <BitField name="TIM3EN" description="TIM peripheral clock enable" start="1" size="1" />
+      <BitField name="TIM4EN" description="TIM peripheral clock enable" start="2" size="1" />
+      <BitField name="TIM5EN" description="TIM peripheral clock enable" start="3" size="1" />
+      <BitField name="TIM6EN" description="TIM peripheral clock enable" start="4" size="1" />
+      <BitField name="TIM7EN" description="TIM peripheral clock enable" start="5" size="1" />
+      <BitField name="TIM12EN" description="TIM peripheral clock enable" start="6" size="1" />
+      <BitField name="TIM13EN" description="TIM peripheral clock enable" start="7" size="1" />
+      <BitField name="TIM14EN" description="TIM peripheral clock enable" start="8" size="1" />
+      <BitField name="LPTIM1EN" description="LPTIM1 Peripheral Clocks Enable" start="9" size="1" />
+      <BitField name="SPI2EN" description="SPI2 Peripheral Clocks Enable" start="14" size="1" />
+      <BitField name="SPI3EN" description="SPI3 Peripheral Clocks Enable" start="15" size="1" />
+      <BitField name="SPDIFRXEN" description="SPDIFRX Peripheral Clocks Enable" start="16" size="1" />
+      <BitField name="USART2EN" description="USART2 Peripheral Clocks Enable" start="17" size="1" />
+      <BitField name="USART3EN" description="USART3 Peripheral Clocks Enable" start="18" size="1" />
+      <BitField name="UART4EN" description="UART4 Peripheral Clocks Enable" start="19" size="1" />
+      <BitField name="UART5EN" description="UART5 Peripheral Clocks Enable" start="20" size="1" />
+      <BitField name="I2C1EN" description="I2C1 Peripheral Clocks Enable" start="21" size="1" />
+      <BitField name="I2C2EN" description="I2C2 Peripheral Clocks Enable" start="22" size="1" />
+      <BitField name="I2C3EN" description="I2C3 Peripheral Clocks Enable" start="23" size="1" />
+      <BitField name="HDMICECEN" description="HDMI-CEC peripheral clock enable" start="27" size="1" />
+      <BitField name="DAC12EN" description="DAC1&amp;2 peripheral clock enable" start="29" size="1" />
+      <BitField name="USART7EN" description="USART7 Peripheral Clocks Enable" start="30" size="1" />
+      <BitField name="USART8EN" description="USART8 Peripheral Clocks Enable" start="31" size="1" />
+    </Register>
+    <Register name="APB1HENR" description="RCC APB1 Clock Register" start="+0xEC" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CRSEN" description="Clock Recovery System peripheral clock enable" start="1" size="1" />
+      <BitField name="SWPEN" description="SWPMI Peripheral Clocks Enable" start="2" size="1" />
+      <BitField name="OPAMPEN" description="OPAMP peripheral clock enable" start="4" size="1" />
+      <BitField name="MDIOSEN" description="MDIOS peripheral clock enable" start="5" size="1" />
+      <BitField name="FDCANEN" description="FDCAN Peripheral Clocks Enable" start="8" size="1" />
+    </Register>
+    <Register name="C1_APB1HENR" description="RCC APB1 Clock Register" start="+0x14C" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CRSEN" description="Clock Recovery System peripheral clock enable" start="1" size="1" />
+      <BitField name="SWPEN" description="SWPMI Peripheral Clocks Enable" start="2" size="1" />
+      <BitField name="OPAMPEN" description="OPAMP peripheral clock enable" start="4" size="1" />
+      <BitField name="MDIOSEN" description="MDIOS peripheral clock enable" start="5" size="1" />
+      <BitField name="FDCANEN" description="FDCAN Peripheral Clocks Enable" start="8" size="1" />
+    </Register>
+    <Register name="C1_APB2ENR" description="RCC APB2 Clock Register" start="+0x150" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TIM1EN" description="TIM1 peripheral clock enable" start="0" size="1" />
+      <BitField name="TIM8EN" description="TIM8 peripheral clock enable" start="1" size="1" />
+      <BitField name="USART1EN" description="USART1 Peripheral Clocks Enable" start="4" size="1" />
+      <BitField name="USART6EN" description="USART6 Peripheral Clocks Enable" start="5" size="1" />
+      <BitField name="SPI1EN" description="SPI1 Peripheral Clocks Enable" start="12" size="1" />
+      <BitField name="SPI4EN" description="SPI4 Peripheral Clocks Enable" start="13" size="1" />
+      <BitField name="TIM16EN" description="TIM16 peripheral clock enable" start="17" size="1" />
+      <BitField name="TIM15EN" description="TIM15 peripheral clock enable" start="16" size="1" />
+      <BitField name="TIM17EN" description="TIM17 peripheral clock enable" start="18" size="1" />
+      <BitField name="SPI5EN" description="SPI5 Peripheral Clocks Enable" start="20" size="1" />
+      <BitField name="SAI1EN" description="SAI1 Peripheral Clocks Enable" start="22" size="1" />
+      <BitField name="SAI2EN" description="SAI2 Peripheral Clocks Enable" start="23" size="1" />
+      <BitField name="SAI3EN" description="SAI3 Peripheral Clocks Enable" start="24" size="1" />
+      <BitField name="DFSDM1EN" description="DFSDM1 Peripheral Clocks Enable" start="28" size="1" />
+    </Register>
+    <Register name="APB2ENR" description="RCC APB2 Clock Register" start="+0xF0" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TIM1EN" description="TIM1 peripheral clock enable" start="0" size="1" />
+      <BitField name="TIM8EN" description="TIM8 peripheral clock enable" start="1" size="1" />
+      <BitField name="USART1EN" description="USART1 Peripheral Clocks Enable" start="4" size="1" />
+      <BitField name="USART6EN" description="USART6 Peripheral Clocks Enable" start="5" size="1" />
+      <BitField name="SPI1EN" description="SPI1 Peripheral Clocks Enable" start="12" size="1" />
+      <BitField name="SPI4EN" description="SPI4 Peripheral Clocks Enable" start="13" size="1" />
+      <BitField name="TIM16EN" description="TIM16 peripheral clock enable" start="17" size="1" />
+      <BitField name="TIM15EN" description="TIM15 peripheral clock enable" start="16" size="1" />
+      <BitField name="TIM17EN" description="TIM17 peripheral clock enable" start="18" size="1" />
+      <BitField name="SPI5EN" description="SPI5 Peripheral Clocks Enable" start="20" size="1" />
+      <BitField name="SAI1EN" description="SAI1 Peripheral Clocks Enable" start="22" size="1" />
+      <BitField name="SAI2EN" description="SAI2 Peripheral Clocks Enable" start="23" size="1" />
+      <BitField name="SAI3EN" description="SAI3 Peripheral Clocks Enable" start="24" size="1" />
+      <BitField name="DFSDM1EN" description="DFSDM1 Peripheral Clocks Enable" start="28" size="1" />
+    </Register>
+    <Register name="APB4ENR" description="RCC APB4 Clock Register" start="+0xF4" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SYSCFGEN" description="SYSCFG peripheral clock enable" start="1" size="1" />
+      <BitField name="LPUART1EN" description="LPUART1 Peripheral Clocks Enable" start="3" size="1" />
+      <BitField name="SPI6EN" description="SPI6 Peripheral Clocks Enable" start="5" size="1" />
+      <BitField name="I2C4EN" description="I2C4 Peripheral Clocks Enable" start="7" size="1" />
+      <BitField name="LPTIM2EN" description="LPTIM2 Peripheral Clocks Enable" start="9" size="1" />
+      <BitField name="LPTIM3EN" description="LPTIM3 Peripheral Clocks Enable" start="10" size="1" />
+      <BitField name="LPTIM4EN" description="LPTIM4 Peripheral Clocks Enable" start="11" size="1" />
+      <BitField name="LPTIM5EN" description="LPTIM5 Peripheral Clocks Enable" start="12" size="1" />
+      <BitField name="COMP12EN" description="COMP1/2 peripheral clock enable" start="14" size="1" />
+      <BitField name="VREFEN" description="VREF peripheral clock enable" start="15" size="1" />
+      <BitField name="RTCAPBEN" description="RTC APB Clock Enable" start="16" size="1" />
+      <BitField name="SAI4EN" description="SAI4 Peripheral Clocks Enable" start="21" size="1" />
+    </Register>
+    <Register name="C1_APB4ENR" description="RCC APB4 Clock Register" start="+0x154" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SYSCFGEN" description="SYSCFG peripheral clock enable" start="1" size="1" />
+      <BitField name="LPUART1EN" description="LPUART1 Peripheral Clocks Enable" start="3" size="1" />
+      <BitField name="SPI6EN" description="SPI6 Peripheral Clocks Enable" start="5" size="1" />
+      <BitField name="I2C4EN" description="I2C4 Peripheral Clocks Enable" start="7" size="1" />
+      <BitField name="LPTIM2EN" description="LPTIM2 Peripheral Clocks Enable" start="9" size="1" />
+      <BitField name="LPTIM3EN" description="LPTIM3 Peripheral Clocks Enable" start="10" size="1" />
+      <BitField name="LPTIM4EN" description="LPTIM4 Peripheral Clocks Enable" start="11" size="1" />
+      <BitField name="LPTIM5EN" description="LPTIM5 Peripheral Clocks Enable" start="12" size="1" />
+      <BitField name="COMP12EN" description="COMP1/2 peripheral clock enable" start="14" size="1" />
+      <BitField name="VREFEN" description="VREF peripheral clock enable" start="15" size="1" />
+      <BitField name="RTCAPBEN" description="RTC APB Clock Enable" start="16" size="1" />
+      <BitField name="SAI4EN" description="SAI4 Peripheral Clocks Enable" start="21" size="1" />
+    </Register>
+    <Register name="C1_AHB3LPENR" description="RCC AHB3 Sleep Clock Register" start="+0x15C" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MDMALPEN" description="MDMA Clock Enable During CSleep Mode" start="0" size="1" />
+      <BitField name="DMA2DLPEN" description="DMA2D Clock Enable During CSleep Mode" start="4" size="1" />
+      <BitField name="JPGDECLPEN" description="JPGDEC Clock Enable During CSleep Mode" start="5" size="1" />
+      <BitField name="FLITFLPEN" description="FLITF Clock Enable During CSleep Mode" start="8" size="1" />
+      <BitField name="FMCLPEN" description="FMC Peripheral Clocks Enable During CSleep Mode" start="12" size="1" />
+      <BitField name="QSPILPEN" description="QUADSPI and QUADSPI Delay Clock Enable During CSleep Mode" start="14" size="1" />
+      <BitField name="SDMMC1LPEN" description="SDMMC1 and SDMMC1 Delay Clock Enable During CSleep Mode" start="16" size="1" />
+      <BitField name="D1DTCM1LPEN" description="D1DTCM1 Block Clock Enable During CSleep mode" start="28" size="1" />
+      <BitField name="DTCM2LPEN" description="D1 DTCM2 Block Clock Enable During CSleep mode" start="29" size="1" />
+      <BitField name="ITCMLPEN" description="D1ITCM Block Clock Enable During CSleep mode" start="30" size="1" />
+      <BitField name="AXISRAMLPEN" description="AXISRAM Block Clock Enable During CSleep mode" start="31" size="1" />
+    </Register>
+    <Register name="AHB3LPENR" description="RCC AHB3 Sleep Clock Register" start="+0xFC" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MDMALPEN" description="MDMA Clock Enable During CSleep Mode" start="0" size="1" />
+      <BitField name="DMA2DLPEN" description="DMA2D Clock Enable During CSleep Mode" start="4" size="1" />
+      <BitField name="JPGDECLPEN" description="JPGDEC Clock Enable During CSleep Mode" start="5" size="1" />
+      <BitField name="FLITFLPEN" description="FLITF Clock Enable During CSleep Mode" start="8" size="1" />
+      <BitField name="FMCLPEN" description="FMC Peripheral Clocks Enable During CSleep Mode" start="12" size="1" />
+      <BitField name="QSPILPEN" description="QUADSPI and QUADSPI Delay Clock Enable During CSleep Mode" start="14" size="1" />
+      <BitField name="SDMMC1LPEN" description="SDMMC1 and SDMMC1 Delay Clock Enable During CSleep Mode" start="16" size="1" />
+      <BitField name="D1DTCM1LPEN" description="D1DTCM1 Block Clock Enable During CSleep mode" start="28" size="1" />
+      <BitField name="DTCM2LPEN" description="D1 DTCM2 Block Clock Enable During CSleep mode" start="29" size="1" />
+      <BitField name="ITCMLPEN" description="D1ITCM Block Clock Enable During CSleep mode" start="30" size="1" />
+      <BitField name="AXISRAMLPEN" description="AXISRAM Block Clock Enable During CSleep mode" start="31" size="1" />
+    </Register>
+    <Register name="AHB1LPENR" description="RCC AHB1 Sleep Clock Register" start="+0x100" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DMA1LPEN" description="DMA1 Clock Enable During CSleep Mode" start="0" size="1" />
+      <BitField name="DMA2LPEN" description="DMA2 Clock Enable During CSleep Mode" start="1" size="1" />
+      <BitField name="ADC12LPEN" description="ADC1/2 Peripheral Clocks Enable During CSleep Mode" start="5" size="1" />
+      <BitField name="ETH1MACLPEN" description="Ethernet MAC bus interface Clock Enable During CSleep Mode" start="15" size="1" />
+      <BitField name="ETH1TXLPEN" description="Ethernet Transmission Clock Enable During CSleep Mode" start="16" size="1" />
+      <BitField name="ETH1RXLPEN" description="Ethernet Reception Clock Enable During CSleep Mode" start="17" size="1" />
+      <BitField name="USB1OTGLPEN" description="USB1OTG peripheral clock enable during CSleep mode" start="25" size="1" />
+      <BitField name="USB1ULPILPEN" description="USB_PHY1 clock enable during CSleep mode" start="26" size="1" />
+      <BitField name="USB2OTGLPEN" description="USB2OTG peripheral clock enable during CSleep mode" start="27" size="1" />
+      <BitField name="USB2ULPILPEN" description="USB_PHY2 clocks enable during CSleep mode" start="28" size="1" />
+    </Register>
+    <Register name="C1_AHB1LPENR" description="RCC AHB1 Sleep Clock Register" start="+0x160" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DMA1LPEN" description="DMA1 Clock Enable During CSleep Mode" start="0" size="1" />
+      <BitField name="DMA2LPEN" description="DMA2 Clock Enable During CSleep Mode" start="1" size="1" />
+      <BitField name="ADC12LPEN" description="ADC1/2 Peripheral Clocks Enable During CSleep Mode" start="5" size="1" />
+      <BitField name="ETH1MACLPEN" description="Ethernet MAC bus interface Clock Enable During CSleep Mode" start="15" size="1" />
+      <BitField name="ETH1TXLPEN" description="Ethernet Transmission Clock Enable During CSleep Mode" start="16" size="1" />
+      <BitField name="ETH1RXLPEN" description="Ethernet Reception Clock Enable During CSleep Mode" start="17" size="1" />
+      <BitField name="USB1OTGLPEN" description="USB1OTG peripheral clock enable during CSleep mode" start="25" size="1" />
+      <BitField name="USB1ULPILPEN" description="USB_PHY1 clock enable during CSleep mode" start="26" size="1" />
+      <BitField name="USB2OTGLPEN" description="USB2OTG peripheral clock enable during CSleep mode" start="27" size="1" />
+      <BitField name="USB2ULPILPEN" description="USB_PHY2 clocks enable during CSleep mode" start="28" size="1" />
+    </Register>
+    <Register name="C1_AHB2LPENR" description="RCC AHB2 Sleep Clock Register" start="+0x164" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CAMITFLPEN" description="CAMITF peripheral clock enable during CSleep mode" start="0" size="1" />
+      <BitField name="CRYPTLPEN" description="CRYPT peripheral clock enable during CSleep mode" start="4" size="1" />
+      <BitField name="HASHLPEN" description="HASH peripheral clock enable during CSleep mode" start="5" size="1" />
+      <BitField name="SDMMC2LPEN" description="SDMMC2 and SDMMC2 Delay Clock Enable During CSleep Mode" start="9" size="1" />
+      <BitField name="RNGLPEN" description="RNG peripheral clock enable during CSleep mode" start="6" size="1" />
+      <BitField name="SRAM1LPEN" description="SRAM1 Clock Enable During CSleep Mode" start="29" size="1" />
+      <BitField name="SRAM2LPEN" description="SRAM2 Clock Enable During CSleep Mode" start="30" size="1" />
+      <BitField name="SRAM3LPEN" description="SRAM3 Clock Enable During CSleep Mode" start="31" size="1" />
+    </Register>
+    <Register name="AHB2LPENR" description="RCC AHB2 Sleep Clock Register" start="+0x104" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CAMITFLPEN" description="CAMITF peripheral clock enable during CSleep mode" start="0" size="1" />
+      <BitField name="CRYPTLPEN" description="CRYPT peripheral clock enable during CSleep mode" start="4" size="1" />
+      <BitField name="HASHLPEN" description="HASH peripheral clock enable during CSleep mode" start="5" size="1" />
+      <BitField name="SDMMC2LPEN" description="SDMMC2 and SDMMC2 Delay Clock Enable During CSleep Mode" start="9" size="1" />
+      <BitField name="RNGLPEN" description="RNG peripheral clock enable during CSleep mode" start="6" size="1" />
+      <BitField name="SRAM1LPEN" description="SRAM1 Clock Enable During CSleep Mode" start="29" size="1" />
+      <BitField name="SRAM2LPEN" description="SRAM2 Clock Enable During CSleep Mode" start="30" size="1" />
+      <BitField name="SRAM3LPEN" description="SRAM3 Clock Enable During CSleep Mode" start="31" size="1" />
+    </Register>
+    <Register name="AHB4LPENR" description="RCC AHB4 Sleep Clock Register" start="+0x108" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="GPIOALPEN" description="GPIO peripheral clock enable during CSleep mode" start="0" size="1" />
+      <BitField name="GPIOBLPEN" description="GPIO peripheral clock enable during CSleep mode" start="1" size="1" />
+      <BitField name="GPIOCLPEN" description="GPIO peripheral clock enable during CSleep mode" start="2" size="1" />
+      <BitField name="GPIODLPEN" description="GPIO peripheral clock enable during CSleep mode" start="3" size="1" />
+      <BitField name="GPIOELPEN" description="GPIO peripheral clock enable during CSleep mode" start="4" size="1" />
+      <BitField name="GPIOFLPEN" description="GPIO peripheral clock enable during CSleep mode" start="5" size="1" />
+      <BitField name="GPIOGLPEN" description="GPIO peripheral clock enable during CSleep mode" start="6" size="1" />
+      <BitField name="GPIOHLPEN" description="GPIO peripheral clock enable during CSleep mode" start="7" size="1" />
+      <BitField name="GPIOILPEN" description="GPIO peripheral clock enable during CSleep mode" start="8" size="1" />
+      <BitField name="GPIOJLPEN" description="GPIO peripheral clock enable during CSleep mode" start="9" size="1" />
+      <BitField name="GPIOKLPEN" description="GPIO peripheral clock enable during CSleep mode" start="10" size="1" />
+      <BitField name="CRCLPEN" description="CRC peripheral clock enable during CSleep mode" start="19" size="1" />
+      <BitField name="BDMALPEN" description="BDMA Clock Enable During CSleep Mode" start="21" size="1" />
+      <BitField name="ADC3LPEN" description="ADC3 Peripheral Clocks Enable During CSleep Mode" start="24" size="1" />
+      <BitField name="BKPRAMLPEN" description="Backup RAM Clock Enable During CSleep Mode" start="28" size="1" />
+      <BitField name="SRAM4LPEN" description="SRAM4 Clock Enable During CSleep Mode" start="29" size="1" />
+    </Register>
+    <Register name="C1_AHB4LPENR" description="RCC AHB4 Sleep Clock Register" start="+0x168" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="GPIOALPEN" description="GPIO peripheral clock enable during CSleep mode" start="0" size="1" />
+      <BitField name="GPIOBLPEN" description="GPIO peripheral clock enable during CSleep mode" start="1" size="1" />
+      <BitField name="GPIOCLPEN" description="GPIO peripheral clock enable during CSleep mode" start="2" size="1" />
+      <BitField name="GPIODLPEN" description="GPIO peripheral clock enable during CSleep mode" start="3" size="1" />
+      <BitField name="GPIOELPEN" description="GPIO peripheral clock enable during CSleep mode" start="4" size="1" />
+      <BitField name="GPIOFLPEN" description="GPIO peripheral clock enable during CSleep mode" start="5" size="1" />
+      <BitField name="GPIOGLPEN" description="GPIO peripheral clock enable during CSleep mode" start="6" size="1" />
+      <BitField name="GPIOHLPEN" description="GPIO peripheral clock enable during CSleep mode" start="7" size="1" />
+      <BitField name="GPIOILPEN" description="GPIO peripheral clock enable during CSleep mode" start="8" size="1" />
+      <BitField name="GPIOJLPEN" description="GPIO peripheral clock enable during CSleep mode" start="9" size="1" />
+      <BitField name="GPIOKLPEN" description="GPIO peripheral clock enable during CSleep mode" start="10" size="1" />
+      <BitField name="CRCLPEN" description="CRC peripheral clock enable during CSleep mode" start="19" size="1" />
+      <BitField name="BDMALPEN" description="BDMA Clock Enable During CSleep Mode" start="21" size="1" />
+      <BitField name="ADC3LPEN" description="ADC3 Peripheral Clocks Enable During CSleep Mode" start="24" size="1" />
+      <BitField name="BKPRAMLPEN" description="Backup RAM Clock Enable During CSleep Mode" start="28" size="1" />
+      <BitField name="SRAM4LPEN" description="SRAM4 Clock Enable During CSleep Mode" start="29" size="1" />
+    </Register>
+    <Register name="C1_APB3LPENR" description="RCC APB3 Sleep Clock Register" start="+0x16C" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LTDCLPEN" description="LTDC peripheral clock enable during CSleep mode" start="3" size="1" />
+      <BitField name="WWDG1LPEN" description="WWDG1 Clock Enable During CSleep Mode" start="6" size="1" />
+    </Register>
+    <Register name="APB3LPENR" description="RCC APB3 Sleep Clock Register" start="+0x10C" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="LTDCLPEN" description="LTDC peripheral clock enable during CSleep mode" start="3" size="1" />
+      <BitField name="WWDG1LPEN" description="WWDG1 Clock Enable During CSleep Mode" start="6" size="1" />
+    </Register>
+    <Register name="APB1LLPENR" description="RCC APB1 Low Sleep Clock Register" start="+0x110" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TIM2LPEN" description="TIM2 peripheral clock enable during CSleep mode" start="0" size="1" />
+      <BitField name="TIM3LPEN" description="TIM3 peripheral clock enable during CSleep mode" start="1" size="1" />
+      <BitField name="TIM4LPEN" description="TIM4 peripheral clock enable during CSleep mode" start="2" size="1" />
+      <BitField name="TIM5LPEN" description="TIM5 peripheral clock enable during CSleep mode" start="3" size="1" />
+      <BitField name="TIM6LPEN" description="TIM6 peripheral clock enable during CSleep mode" start="4" size="1" />
+      <BitField name="TIM7LPEN" description="TIM7 peripheral clock enable during CSleep mode" start="5" size="1" />
+      <BitField name="TIM12LPEN" description="TIM12 peripheral clock enable during CSleep mode" start="6" size="1" />
+      <BitField name="TIM13LPEN" description="TIM13 peripheral clock enable during CSleep mode" start="7" size="1" />
+      <BitField name="TIM14LPEN" description="TIM14 peripheral clock enable during CSleep mode" start="8" size="1" />
+      <BitField name="LPTIM1LPEN" description="LPTIM1 Peripheral Clocks Enable During CSleep Mode" start="9" size="1" />
+      <BitField name="SPI2LPEN" description="SPI2 Peripheral Clocks Enable During CSleep Mode" start="14" size="1" />
+      <BitField name="SPI3LPEN" description="SPI3 Peripheral Clocks Enable During CSleep Mode" start="15" size="1" />
+      <BitField name="SPDIFRXLPEN" description="SPDIFRX Peripheral Clocks Enable During CSleep Mode" start="16" size="1" />
+      <BitField name="USART2LPEN" description="USART2 Peripheral Clocks Enable During CSleep Mode" start="17" size="1" />
+      <BitField name="USART3LPEN" description="USART3 Peripheral Clocks Enable During CSleep Mode" start="18" size="1" />
+      <BitField name="UART4LPEN" description="UART4 Peripheral Clocks Enable During CSleep Mode" start="19" size="1" />
+      <BitField name="UART5LPEN" description="UART5 Peripheral Clocks Enable During CSleep Mode" start="20" size="1" />
+      <BitField name="I2C1LPEN" description="I2C1 Peripheral Clocks Enable During CSleep Mode" start="21" size="1" />
+      <BitField name="I2C2LPEN" description="I2C2 Peripheral Clocks Enable During CSleep Mode" start="22" size="1" />
+      <BitField name="I2C3LPEN" description="I2C3 Peripheral Clocks Enable During CSleep Mode" start="23" size="1" />
+      <BitField name="HDMICECLPEN" description="HDMI-CEC Peripheral Clocks Enable During CSleep Mode" start="27" size="1" />
+      <BitField name="DAC12LPEN" description="DAC1/2 peripheral clock enable during CSleep mode" start="29" size="1" />
+      <BitField name="USART7LPEN" description="USART7 Peripheral Clocks Enable During CSleep Mode" start="30" size="1" />
+      <BitField name="USART8LPEN" description="USART8 Peripheral Clocks Enable During CSleep Mode" start="31" size="1" />
+    </Register>
+    <Register name="C1_APB1LLPENR" description="RCC APB1 Low Sleep Clock Register" start="+0x170" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TIM2LPEN" description="TIM2 peripheral clock enable during CSleep mode" start="0" size="1" />
+      <BitField name="TIM3LPEN" description="TIM3 peripheral clock enable during CSleep mode" start="1" size="1" />
+      <BitField name="TIM4LPEN" description="TIM4 peripheral clock enable during CSleep mode" start="2" size="1" />
+      <BitField name="TIM5LPEN" description="TIM5 peripheral clock enable during CSleep mode" start="3" size="1" />
+      <BitField name="TIM6LPEN" description="TIM6 peripheral clock enable during CSleep mode" start="4" size="1" />
+      <BitField name="TIM7LPEN" description="TIM7 peripheral clock enable during CSleep mode" start="5" size="1" />
+      <BitField name="TIM12LPEN" description="TIM12 peripheral clock enable during CSleep mode" start="6" size="1" />
+      <BitField name="TIM13LPEN" description="TIM13 peripheral clock enable during CSleep mode" start="7" size="1" />
+      <BitField name="TIM14LPEN" description="TIM14 peripheral clock enable during CSleep mode" start="8" size="1" />
+      <BitField name="LPTIM1LPEN" description="LPTIM1 Peripheral Clocks Enable During CSleep Mode" start="9" size="1" />
+      <BitField name="SPI2LPEN" description="SPI2 Peripheral Clocks Enable During CSleep Mode" start="14" size="1" />
+      <BitField name="SPI3LPEN" description="SPI3 Peripheral Clocks Enable During CSleep Mode" start="15" size="1" />
+      <BitField name="SPDIFRXLPEN" description="SPDIFRX Peripheral Clocks Enable During CSleep Mode" start="16" size="1" />
+      <BitField name="USART2LPEN" description="USART2 Peripheral Clocks Enable During CSleep Mode" start="17" size="1" />
+      <BitField name="USART3LPEN" description="USART3 Peripheral Clocks Enable During CSleep Mode" start="18" size="1" />
+      <BitField name="UART4LPEN" description="UART4 Peripheral Clocks Enable During CSleep Mode" start="19" size="1" />
+      <BitField name="UART5LPEN" description="UART5 Peripheral Clocks Enable During CSleep Mode" start="20" size="1" />
+      <BitField name="I2C1LPEN" description="I2C1 Peripheral Clocks Enable During CSleep Mode" start="21" size="1" />
+      <BitField name="I2C2LPEN" description="I2C2 Peripheral Clocks Enable During CSleep Mode" start="22" size="1" />
+      <BitField name="I2C3LPEN" description="I2C3 Peripheral Clocks Enable During CSleep Mode" start="23" size="1" />
+      <BitField name="HDMICECLPEN" description="HDMI-CEC Peripheral Clocks Enable During CSleep Mode" start="27" size="1" />
+      <BitField name="DAC12LPEN" description="DAC1/2 peripheral clock enable during CSleep mode" start="29" size="1" />
+      <BitField name="USART7LPEN" description="USART7 Peripheral Clocks Enable During CSleep Mode" start="30" size="1" />
+      <BitField name="USART8LPEN" description="USART8 Peripheral Clocks Enable During CSleep Mode" start="31" size="1" />
+    </Register>
+    <Register name="C1_APB1HLPENR" description="RCC APB1 High Sleep Clock Register" start="+0x174" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CRSLPEN" description="Clock Recovery System peripheral clock enable during CSleep mode" start="1" size="1" />
+      <BitField name="SWPLPEN" description="SWPMI Peripheral Clocks Enable During CSleep Mode" start="2" size="1" />
+      <BitField name="OPAMPLPEN" description="OPAMP peripheral clock enable during CSleep mode" start="4" size="1" />
+      <BitField name="MDIOSLPEN" description="MDIOS peripheral clock enable during CSleep mode" start="5" size="1" />
+      <BitField name="FDCANLPEN" description="FDCAN Peripheral Clocks Enable During CSleep Mode" start="8" size="1" />
+    </Register>
+    <Register name="APB1HLPENR" description="RCC APB1 High Sleep Clock Register" start="+0x114" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CRSLPEN" description="Clock Recovery System peripheral clock enable during CSleep mode" start="1" size="1" />
+      <BitField name="SWPLPEN" description="SWPMI Peripheral Clocks Enable During CSleep Mode" start="2" size="1" />
+      <BitField name="OPAMPLPEN" description="OPAMP peripheral clock enable during CSleep mode" start="4" size="1" />
+      <BitField name="MDIOSLPEN" description="MDIOS peripheral clock enable during CSleep mode" start="5" size="1" />
+      <BitField name="FDCANLPEN" description="FDCAN Peripheral Clocks Enable During CSleep Mode" start="8" size="1" />
+    </Register>
+    <Register name="APB2LPENR" description="RCC APB2 Sleep Clock Register" start="+0x118" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TIM1LPEN" description="TIM1 peripheral clock enable during CSleep mode" start="0" size="1" />
+      <BitField name="TIM8LPEN" description="TIM8 peripheral clock enable during CSleep mode" start="1" size="1" />
+      <BitField name="USART1LPEN" description="USART1 Peripheral Clocks Enable During CSleep Mode" start="4" size="1" />
+      <BitField name="USART6LPEN" description="USART6 Peripheral Clocks Enable During CSleep Mode" start="5" size="1" />
+      <BitField name="SPI1LPEN" description="SPI1 Peripheral Clocks Enable During CSleep Mode" start="12" size="1" />
+      <BitField name="SPI4LPEN" description="SPI4 Peripheral Clocks Enable During CSleep Mode" start="13" size="1" />
+      <BitField name="TIM15LPEN" description="TIM15 peripheral clock enable during CSleep mode" start="16" size="1" />
+      <BitField name="TIM16LPEN" description="TIM16 peripheral clock enable during CSleep mode" start="17" size="1" />
+      <BitField name="TIM17LPEN" description="TIM17 peripheral clock enable during CSleep mode" start="18" size="1" />
+      <BitField name="SPI5LPEN" description="SPI5 Peripheral Clocks Enable During CSleep Mode" start="20" size="1" />
+      <BitField name="SAI1LPEN" description="SAI1 Peripheral Clocks Enable During CSleep Mode" start="22" size="1" />
+      <BitField name="SAI2LPEN" description="SAI2 Peripheral Clocks Enable During CSleep Mode" start="23" size="1" />
+      <BitField name="SAI3LPEN" description="SAI3 Peripheral Clocks Enable During CSleep Mode" start="24" size="1" />
+      <BitField name="DFSDM1LPEN" description="DFSDM1 Peripheral Clocks Enable During CSleep Mode" start="28" size="1" />
+    </Register>
+    <Register name="C1_APB2LPENR" description="RCC APB2 Sleep Clock Register" start="+0x178" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TIM1LPEN" description="TIM1 peripheral clock enable during CSleep mode" start="0" size="1" />
+      <BitField name="TIM8LPEN" description="TIM8 peripheral clock enable during CSleep mode" start="1" size="1" />
+      <BitField name="USART1LPEN" description="USART1 Peripheral Clocks Enable During CSleep Mode" start="4" size="1" />
+      <BitField name="USART6LPEN" description="USART6 Peripheral Clocks Enable During CSleep Mode" start="5" size="1" />
+      <BitField name="SPI1LPEN" description="SPI1 Peripheral Clocks Enable During CSleep Mode" start="12" size="1" />
+      <BitField name="SPI4LPEN" description="SPI4 Peripheral Clocks Enable During CSleep Mode" start="13" size="1" />
+      <BitField name="TIM15LPEN" description="TIM15 peripheral clock enable during CSleep mode" start="16" size="1" />
+      <BitField name="TIM16LPEN" description="TIM16 peripheral clock enable during CSleep mode" start="17" size="1" />
+      <BitField name="TIM17LPEN" description="TIM17 peripheral clock enable during CSleep mode" start="18" size="1" />
+      <BitField name="SPI5LPEN" description="SPI5 Peripheral Clocks Enable During CSleep Mode" start="20" size="1" />
+      <BitField name="SAI1LPEN" description="SAI1 Peripheral Clocks Enable During CSleep Mode" start="22" size="1" />
+      <BitField name="SAI2LPEN" description="SAI2 Peripheral Clocks Enable During CSleep Mode" start="23" size="1" />
+      <BitField name="SAI3LPEN" description="SAI3 Peripheral Clocks Enable During CSleep Mode" start="24" size="1" />
+      <BitField name="DFSDM1LPEN" description="DFSDM1 Peripheral Clocks Enable During CSleep Mode" start="28" size="1" />
+    </Register>
+    <Register name="C1_APB4LPENR" description="RCC APB4 Sleep Clock Register" start="+0x17C" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SYSCFGLPEN" description="SYSCFG peripheral clock enable during CSleep mode" start="1" size="1" />
+      <BitField name="LPUART1LPEN" description="LPUART1 Peripheral Clocks Enable During CSleep Mode" start="3" size="1" />
+      <BitField name="SPI6LPEN" description="SPI6 Peripheral Clocks Enable During CSleep Mode" start="5" size="1" />
+      <BitField name="I2C4LPEN" description="I2C4 Peripheral Clocks Enable During CSleep Mode" start="7" size="1" />
+      <BitField name="LPTIM2LPEN" description="LPTIM2 Peripheral Clocks Enable During CSleep Mode" start="9" size="1" />
+      <BitField name="LPTIM3LPEN" description="LPTIM3 Peripheral Clocks Enable During CSleep Mode" start="10" size="1" />
+      <BitField name="LPTIM4LPEN" description="LPTIM4 Peripheral Clocks Enable During CSleep Mode" start="11" size="1" />
+      <BitField name="LPTIM5LPEN" description="LPTIM5 Peripheral Clocks Enable During CSleep Mode" start="12" size="1" />
+      <BitField name="COMP12LPEN" description="COMP1/2 peripheral clock enable during CSleep mode" start="14" size="1" />
+      <BitField name="VREFLPEN" description="VREF peripheral clock enable during CSleep mode" start="15" size="1" />
+      <BitField name="RTCAPBLPEN" description="RTC APB Clock Enable During CSleep Mode" start="16" size="1" />
+      <BitField name="SAI4LPEN" description="SAI4 Peripheral Clocks Enable During CSleep Mode" start="21" size="1" />
+    </Register>
+    <Register name="APB4LPENR" description="RCC APB4 Sleep Clock Register" start="+0x11C" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SYSCFGLPEN" description="SYSCFG peripheral clock enable during CSleep mode" start="1" size="1" />
+      <BitField name="LPUART1LPEN" description="LPUART1 Peripheral Clocks Enable During CSleep Mode" start="3" size="1" />
+      <BitField name="SPI6LPEN" description="SPI6 Peripheral Clocks Enable During CSleep Mode" start="5" size="1" />
+      <BitField name="I2C4LPEN" description="I2C4 Peripheral Clocks Enable During CSleep Mode" start="7" size="1" />
+      <BitField name="LPTIM2LPEN" description="LPTIM2 Peripheral Clocks Enable During CSleep Mode" start="9" size="1" />
+      <BitField name="LPTIM3LPEN" description="LPTIM3 Peripheral Clocks Enable During CSleep Mode" start="10" size="1" />
+      <BitField name="LPTIM4LPEN" description="LPTIM4 Peripheral Clocks Enable During CSleep Mode" start="11" size="1" />
+      <BitField name="LPTIM5LPEN" description="LPTIM5 Peripheral Clocks Enable During CSleep Mode" start="12" size="1" />
+      <BitField name="COMP12LPEN" description="COMP1/2 peripheral clock enable during CSleep mode" start="14" size="1" />
+      <BitField name="VREFLPEN" description="VREF peripheral clock enable during CSleep mode" start="15" size="1" />
+      <BitField name="RTCAPBLPEN" description="RTC APB Clock Enable During CSleep Mode" start="16" size="1" />
+      <BitField name="SAI4LPEN" description="SAI4 Peripheral Clocks Enable During CSleep Mode" start="21" size="1" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="RNG" description="RNG" start="0x48021800">
+    <Register name="CR" description="RNG control register" start="+0x0" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RNGEN" description="Random number generator enable" start="2" size="1" />
+      <BitField name="IE" description="Interrupt enable" start="3" size="1" />
+      <BitField name="CED" description="Clock error detection Note: The clock error detection can be used only when ck_rc48 or ck_pll1_q (ck_pll1_q = 48MHz) source is selected otherwise, CED bit must be equal to 1. The clock error detection cannot be enabled nor disabled on the fly when RNG peripheral is enabled, to enable or disable CED the RNG must be disabled." start="5" size="1" />
+    </Register>
+    <Register name="SR" description="RNG status register" start="+0x4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DRDY" description="Data ready Note: If IE=1 in RNG_CR, an interrupt is generated when DRDY=1. It can rise when the peripheral is disabled. When the output buffer becomes empty (after reading RNG_DR), this bit returns to 0 until a new random value is generated." start="0" size="1" access="ReadOnly" />
+      <BitField name="CECS" description="Clock error current status Note: This bit is meaningless if CED (Clock error detection) bit in RNG_CR is equal to 1." start="1" size="1" access="ReadOnly" />
+      <BitField name="SECS" description="Seed error current status ** More than 64 consecutive bits at the same value (0 or 1) ** More than 32 consecutive alternances of 0 and 1 (0101010101...01)" start="2" size="1" access="ReadOnly" />
+      <BitField name="CEIS" description="Clock error interrupt status This bit is set at the same time as CECS. It is cleared by writing it to 0. An interrupt is pending if IE = 1 in the RNG_CR register. Note: This bit is meaningless if CED (Clock error detection) bit in RNG_CR is equal to 1." start="5" size="1" access="Read/Write" />
+      <BitField name="SEIS" description="Seed error interrupt status This bit is set at the same time as SECS. It is cleared by writing it to 0. ** More than 64 consecutive bits at the same value (0 or 1) ** More than 32 consecutive alternances of 0 and 1 (0101010101...01) An interrupt is pending if IE = 1 in the RNG_CR register." start="6" size="1" access="Read/Write" />
+    </Register>
+    <Register name="DR" description="The RNG_DR register is a read-only register that delivers a 32-bit random value when read. The content of this register is valid when DRDY= 1, even if RNGEN=0." start="+0x8" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RNDATA" description="Random data 32-bit random data which are valid when DRDY=1." start="0" size="32" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="RTC" description="RTC" start="0x58004000">
+    <Register name="RTC_TR" description="The RTC_TR is the calendar time shadow register. This register must be written in initialization mode only. Refer to Calendar initialization and configuration on page9 and Reading the calendar on page10.This register is write protected. The write access procedure is described in RTC register write protection on page9." start="+0x0" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SU" description="Second units in BCD format" start="0" size="4" />
+      <BitField name="ST" description="Second tens in BCD format" start="4" size="3" />
+      <BitField name="MNU" description="Minute units in BCD format" start="8" size="4" />
+      <BitField name="MNT" description="Minute tens in BCD format" start="12" size="3" />
+      <BitField name="HU" description="Hour units in BCD format" start="16" size="4" />
+      <BitField name="HT" description="Hour tens in BCD format" start="20" size="2" />
+      <BitField name="PM" description="AM/PM notation" start="22" size="1" />
+    </Register>
+    <Register name="RTC_DR" description="The RTC_DR is the calendar date shadow register. This register must be written in initialization mode only. Refer to Calendar initialization and configuration on page9 and Reading the calendar on page10.This register is write protected. The write access procedure is described in RTC register write protection on page9." start="+0x4" size="4" access="Read/Write" reset_value="0x00002101" reset_mask="0xFFFFFFFF">
+      <BitField name="DU" description="Date units in BCD format" start="0" size="4" />
+      <BitField name="DT" description="Date tens in BCD format" start="4" size="2" />
+      <BitField name="MU" description="Month units in BCD format" start="8" size="4" />
+      <BitField name="MT" description="Month tens in BCD format" start="12" size="1" />
+      <BitField name="WDU" description="Week day units" start="13" size="3" />
+      <BitField name="YU" description="Year units in BCD format" start="16" size="4" />
+      <BitField name="YT" description="Year tens in BCD format" start="20" size="4" />
+    </Register>
+    <Register name="RTC_CR" description="RTC control register" start="+0x8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="WUCKSEL" description="Wakeup clock selection" start="0" size="3" access="Read/Write" />
+      <BitField name="TSEDGE" description="Time-stamp event active edge TSE must be reset when TSEDGE is changed to avoid unwanted TSF setting." start="3" size="1" access="Read/Write" />
+      <BitField name="REFCKON" description="RTC_REFIN reference clock detection enable (50 or 60Hz) Note: PREDIV_S must be 0x00FF." start="4" size="1" access="Read/Write" />
+      <BitField name="BYPSHAD" description="Bypass the shadow registers Note: If the frequency of the APB clock is less than seven times the frequency of RTCCLK, BYPSHAD must be set to 1." start="5" size="1" access="Read/Write" />
+      <BitField name="FMT" description="Hour format" start="6" size="1" access="Read/Write" />
+      <BitField name="ALRAE" description="Alarm A enable" start="8" size="1" access="Read/Write" />
+      <BitField name="ALRBE" description="Alarm B enable" start="9" size="1" access="Read/Write" />
+      <BitField name="WUTE" description="Wakeup timer enable" start="10" size="1" access="Read/Write" />
+      <BitField name="TSE" description="timestamp enable" start="11" size="1" access="Read/Write" />
+      <BitField name="ALRAIE" description="Alarm A interrupt enable" start="12" size="1" access="Read/Write" />
+      <BitField name="ALRBIE" description="Alarm B interrupt enable" start="13" size="1" access="Read/Write" />
+      <BitField name="WUTIE" description="Wakeup timer interrupt enable" start="14" size="1" access="Read/Write" />
+      <BitField name="TSIE" description="Time-stamp interrupt enable" start="15" size="1" access="Read/Write" />
+      <BitField name="ADD1H" description="Add 1 hour (summer time change) When this bit is set outside initialization mode, 1 hour is added to the calendar time. This bit is always read as 0." start="16" size="1" access="WriteOnly" />
+      <BitField name="SUB1H" description="Subtract 1 hour (winter time change) When this bit is set outside initialization mode, 1 hour is subtracted to the calendar time if the current hour is not 0. This bit is always read as 0. Setting this bit has no effect when current hour is 0." start="17" size="1" access="WriteOnly" />
+      <BitField name="BKP" description="Backup This bit can be written by the user to memorize whether the daylight saving time change has been performed or not." start="18" size="1" access="Read/Write" />
+      <BitField name="COSEL" description="Calibration output selection When COE=1, this bit selects which signal is output on RTC_CALIB. These frequencies are valid for RTCCLK at 32.768 kHz and prescalers at their default values (PREDIV_A=127 and PREDIV_S=255). Refer to Section24.3.15: Calibration clock output" start="19" size="1" access="Read/Write" />
+      <BitField name="POL" description="Output polarity This bit is used to configure the polarity of RTC_ALARM output" start="20" size="1" access="Read/Write" />
+      <BitField name="OSEL" description="Output selection These bits are used to select the flag to be routed to RTC_ALARM output" start="21" size="2" access="Read/Write" />
+      <BitField name="COE" description="Calibration output enable This bit enables the RTC_CALIB output" start="23" size="1" access="Read/Write" />
+      <BitField name="ITSE" description="timestamp on internal event enable" start="24" size="1" access="Read/Write" />
+    </Register>
+    <Register name="RTC_ISR" description="This register is write protected (except for RTC_ISR[13:8] bits). The write access procedure is described in RTC register write protection on page9." start="+0xC" size="4" reset_value="0x00000007" reset_mask="0xFFFFFFFF">
+      <BitField name="ALRAWF" description="Alarm A write flag This bit is set by hardware when Alarm A values can be changed, after the ALRAE bit has been set to 0 in RTC_CR. It is cleared by hardware in initialization mode." start="0" size="1" access="ReadOnly" />
+      <BitField name="ALRBWF" description="Alarm B write flag This bit is set by hardware when Alarm B values can be changed, after the ALRBE bit has been set to 0 in RTC_CR. It is cleared by hardware in initialization mode." start="1" size="1" access="ReadOnly" />
+      <BitField name="WUTWF" description="Wakeup timer write flag This bit is set by hardware up to 2 RTCCLK cycles after the WUTE bit has been set to 0 in RTC_CR, and is cleared up to 2 RTCCLK cycles after the WUTE bit has been set to 1. The wakeup timer values can be changed when WUTE bit is cleared and WUTWF is set." start="2" size="1" access="ReadOnly" />
+      <BitField name="SHPF" description="Shift operation pending This flag is set by hardware as soon as a shift operation is initiated by a write to the RTC_SHIFTR register. It is cleared by hardware when the corresponding shift operation has been executed. Writing to the SHPF bit has no effect." start="3" size="1" access="ReadOnly" />
+      <BitField name="INITS" description="Initialization status flag This bit is set by hardware when the calendar year field is different from 0 (Backup domain reset state)." start="4" size="1" access="ReadOnly" />
+      <BitField name="RSF" description="Registers synchronization flag This bit is set by hardware each time the calendar registers are copied into the shadow registers (RTC_SSRx, RTC_TRx and RTC_DRx). This bit is cleared by hardware in initialization mode, while a shift operation is pending (SHPF=1), or when in bypass shadow register mode (BYPSHAD=1). This bit can also be cleared by software. It is cleared either by software or by hardware in initialization mode." start="5" size="1" access="Read/Write" />
+      <BitField name="INITF" description="Initialization flag When this bit is set to 1, the RTC is in initialization state, and the time, date and prescaler registers can be updated." start="6" size="1" access="ReadOnly" />
+      <BitField name="INIT" description="Initialization mode" start="7" size="1" access="Read/Write" />
+      <BitField name="ALRAF" description="Alarm A flag This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm A register (RTC_ALRMAR). This flag is cleared by software by writing 0." start="8" size="1" access="Read/Write" />
+      <BitField name="ALRBF" description="Alarm B flag This flag is set by hardware when the time/date registers (RTC_TR and RTC_DR) match the Alarm B register (RTC_ALRMBR). This flag is cleared by software by writing 0." start="9" size="1" access="Read/Write" />
+      <BitField name="WUTF" description="Wakeup timer flag This flag is set by hardware when the wakeup auto-reload counter reaches 0. This flag is cleared by software by writing 0. This flag must be cleared by software at least 1.5 RTCCLK periods before WUTF is set to 1 again." start="10" size="1" access="Read/Write" />
+      <BitField name="TSF" description="Time-stamp flag This flag is set by hardware when a time-stamp event occurs. This flag is cleared by software by writing 0." start="11" size="1" access="Read/Write" />
+      <BitField name="TSOVF" description="Time-stamp overflow flag This flag is set by hardware when a time-stamp event occurs while TSF is already set. This flag is cleared by software by writing 0. It is recommended to check and then clear TSOVF only after clearing the TSF bit. Otherwise, an overflow might not be noticed if a time-stamp event occurs immediately before the TSF bit is cleared." start="12" size="1" access="Read/Write" />
+      <BitField name="TAMP1F" description="RTC_TAMP1 detection flag This flag is set by hardware when a tamper detection event is detected on the RTC_TAMP1 input. It is cleared by software writing 0" start="13" size="1" access="Read/Write" />
+      <BitField name="TAMP2F" description="RTC_TAMP2 detection flag This flag is set by hardware when a tamper detection event is detected on the RTC_TAMP2 input. It is cleared by software writing 0" start="14" size="1" access="Read/Write" />
+      <BitField name="TAMP3F" description="RTC_TAMP3 detection flag This flag is set by hardware when a tamper detection event is detected on the RTC_TAMP3 input. It is cleared by software writing 0" start="15" size="1" access="Read/Write" />
+      <BitField name="RECALPF" description="Recalibration pending Flag The RECALPF status flag is automatically set to 1 when software writes to the RTC_CALR register, indicating that the RTC_CALR register is blocked. When the new calibration settings are taken into account, this bit returns to 0. Refer to Re-calibration on-the-fly." start="16" size="1" access="ReadOnly" />
+      <BitField name="ITSF" description="Internal tTime-stamp flag" start="17" size="1" access="Read/Write" />
+    </Register>
+    <Register name="RTC_PRER" description="This register must be written in initialization mode only. The initialization must be performed in two separate write accesses. Refer to Calendar initialization and configuration on page9.This register is write protected. The write access procedure is described in RTC register write protection on page9." start="+0x10" size="4" access="Read/Write" reset_value="0x007F00FF" reset_mask="0xFFFFFFFF">
+      <BitField name="PREDIV_S" description="Synchronous prescaler factor This is the synchronous division factor: ck_spre frequency = ck_apre frequency/(PREDIV_S+1)" start="0" size="15" />
+      <BitField name="PREDIV_A" description="Asynchronous prescaler factor This is the asynchronous division factor: ck_apre frequency = RTCCLK frequency/(PREDIV_A+1)" start="16" size="7" />
+    </Register>
+    <Register name="RTC_WUTR" description="This register can be written only when WUTWF is set to 1 in RTC_ISR.This register is write protected. The write access procedure is described in RTC register write protection on page9." start="+0x14" size="4" access="Read/Write" reset_value="0x0000FFFF" reset_mask="0xFFFFFFFF">
+      <BitField name="WUT" description="Wakeup auto-reload value bits When the wakeup timer is enabled (WUTE set to 1), the WUTF flag is set every (WUT[15:0] + 1) ck_wut cycles. The ck_wut period is selected through WUCKSEL[2:0] bits of the RTC_CR register When WUCKSEL[2] = 1, the wakeup timer becomes 17-bits and WUCKSEL[1] effectively becomes WUT[16] the most-significant bit to be reloaded into the timer. The first assertion of WUTF occurs (WUT+1) ck_wut cycles after WUTE is set. Setting WUT[15:0] to 0x0000 with WUCKSEL[2:0] =011 (RTCCLK/2) is forbidden." start="0" size="16" />
+    </Register>
+    <Register name="RTC_ALRMAR" description="This register can be written only when ALRAWF is set to 1 in RTC_ISR, or in initialization mode.This register is write protected. The write access procedure is described in RTC register write protection on page9." start="+0x1C" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SU" description="Second units in BCD format." start="0" size="4" />
+      <BitField name="ST" description="Second tens in BCD format." start="4" size="3" />
+      <BitField name="MSK1" description="Alarm A seconds mask" start="7" size="1" />
+      <BitField name="MNU" description="Minute units in BCD format." start="8" size="4" />
+      <BitField name="MNT" description="Minute tens in BCD format." start="12" size="3" />
+      <BitField name="MSK2" description="Alarm A minutes mask" start="15" size="1" />
+      <BitField name="HU" description="Hour units in BCD format." start="16" size="4" />
+      <BitField name="HT" description="Hour tens in BCD format." start="20" size="2" />
+      <BitField name="PM" description="AM/PM notation" start="22" size="1" />
+      <BitField name="MSK3" description="Alarm A hours mask" start="23" size="1" />
+      <BitField name="DU" description="Date units or day in BCD format." start="24" size="4" />
+      <BitField name="DT" description="Date tens in BCD format." start="28" size="2" />
+      <BitField name="WDSEL" description="Week day selection" start="30" size="1" />
+      <BitField name="MSK4" description="Alarm A date mask" start="31" size="1" />
+    </Register>
+    <Register name="RTC_ALRMBR" description="This register can be written only when ALRBWF is set to 1 in RTC_ISR, or in initialization mode.This register is write protected. The write access procedure is described in RTC register write protection on page9." start="+0x20" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SU" description="Second units in BCD format" start="0" size="4" />
+      <BitField name="ST" description="Second tens in BCD format" start="4" size="3" />
+      <BitField name="MSK1" description="Alarm B seconds mask" start="7" size="1" />
+      <BitField name="MNU" description="Minute units in BCD format" start="8" size="4" />
+      <BitField name="MNT" description="Minute tens in BCD format" start="12" size="3" />
+      <BitField name="MSK2" description="Alarm B minutes mask" start="15" size="1" />
+      <BitField name="HU" description="Hour units in BCD format" start="16" size="4" />
+      <BitField name="HT" description="Hour tens in BCD format" start="20" size="2" />
+      <BitField name="PM" description="AM/PM notation" start="22" size="1" />
+      <BitField name="MSK3" description="Alarm B hours mask" start="23" size="1" />
+      <BitField name="DU" description="Date units or day in BCD format" start="24" size="4" />
+      <BitField name="DT" description="Date tens in BCD format" start="28" size="2" />
+      <BitField name="WDSEL" description="Week day selection" start="30" size="1" />
+      <BitField name="MSK4" description="Alarm B date mask" start="31" size="1" />
+    </Register>
+    <Register name="RTC_WPR" description="RTC write protection register" start="+0x24" size="4" access="WriteOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="KEY" description="Write protection key This byte is written by software. Reading this byte always returns 0x00. Refer to RTC register write protection for a description of how to unlock RTC register write protection." start="0" size="8" />
+    </Register>
+    <Register name="RTC_SSR" description="RTC sub second register" start="+0x28" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SS" description="Sub second value SS[15:0] is the value in the synchronous prescaler counter. The fraction of a second is given by the formula below: Second fraction = (PREDIV_S - SS) / (PREDIV_S + 1) Note: SS can be larger than PREDIV_S only after a shift operation. In that case, the correct time/date is one second less than as indicated by RTC_TR/RTC_DR." start="0" size="16" />
+    </Register>
+    <Register name="RTC_SHIFTR" description="This register is write protected. The write access procedure is described in RTC register write protection on page9." start="+0x2C" size="4" access="WriteOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SUBFS" description="Subtract a fraction of a second These bits are write only and is always read as zero. Writing to this bit has no effect when a shift operation is pending (when SHPF=1, in RTC_ISR). The value which is written to SUBFS is added to the synchronous prescaler counter. Since this counter counts down, this operation effectively subtracts from (delays) the clock by: Delay (seconds) = SUBFS / (PREDIV_S + 1) A fraction of a second can effectively be added to the clock (advancing the clock) when the ADD1S function is used in conjunction with SUBFS, effectively advancing the clock by: Advance (seconds) = (1 - (SUBFS / (PREDIV_S + 1))). Note: Writing to SUBFS causes RSF to be cleared. Software can then wait until RSF=1 to be sure that the shadow registers have been updated with the shifted time." start="0" size="15" />
+      <BitField name="ADD1S" description="Add one second This bit is write only and is always read as zero. Writing to this bit has no effect when a shift operation is pending (when SHPF=1, in RTC_ISR). This function is intended to be used with SUBFS (see description below) in order to effectively add a fraction of a second to the clock in an atomic operation." start="31" size="1" />
+    </Register>
+    <Register name="RTC_TSTR" description="The content of this register is valid only when TSF is set to 1 in RTC_ISR. It is cleared when TSF bit is reset." start="+0x30" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SU" description="Second units in BCD format." start="0" size="4" />
+      <BitField name="ST" description="Second tens in BCD format." start="4" size="3" />
+      <BitField name="MNU" description="Minute units in BCD format." start="8" size="4" />
+      <BitField name="MNT" description="Minute tens in BCD format." start="12" size="3" />
+      <BitField name="HU" description="Hour units in BCD format." start="16" size="4" />
+      <BitField name="HT" description="Hour tens in BCD format." start="20" size="2" />
+      <BitField name="PM" description="AM/PM notation" start="22" size="1" />
+    </Register>
+    <Register name="RTC_TSDR" description="The content of this register is valid only when TSF is set to 1 in RTC_ISR. It is cleared when TSF bit is reset." start="+0x34" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DU" description="Date units in BCD format" start="0" size="4" />
+      <BitField name="DT" description="Date tens in BCD format" start="4" size="2" />
+      <BitField name="MU" description="Month units in BCD format" start="8" size="4" />
+      <BitField name="MT" description="Month tens in BCD format" start="12" size="1" />
+      <BitField name="WDU" description="Week day units" start="13" size="3" />
+    </Register>
+    <Register name="RTC_TSSSR" description="The content of this register is valid only when RTC_ISR/TSF is set. It is cleared when the RTC_ISR/TSF bit is reset." start="+0x38" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SS" description="Sub second value SS[15:0] is the value of the synchronous prescaler counter when the timestamp event occurred." start="0" size="16" />
+    </Register>
+    <Register name="RTC_CALR" description="This register is write protected. The write access procedure is described in RTC register write protection on page9." start="+0x3C" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CALM" description="Calibration minus The frequency of the calendar is reduced by masking CALM out of 220 RTCCLK pulses (32 seconds if the input frequency is 32768 Hz). This decreases the frequency of the calendar with a resolution of 0.9537 ppm. To increase the frequency of the calendar, this feature should be used in conjunction with CALP. See Section24.3.12: RTC smooth digital calibration on page13." start="0" size="9" />
+      <BitField name="CALW16" description="Use a 16-second calibration cycle period When CALW16 is set to 1, the 16-second calibration cycle period is selected.This bit must not be set to 1 if CALW8=1. Note: CALM[0] is stuck at 0 when CALW16= 1. Refer to Section24.3.12: RTC smooth digital calibration." start="13" size="1" />
+      <BitField name="CALW8" description="Use an 8-second calibration cycle period When CALW8 is set to 1, the 8-second calibration cycle period is selected. Note: CALM[1:0] are stuck at 00; when CALW8= 1. Refer to Section24.3.12: RTC smooth digital calibration." start="14" size="1" />
+      <BitField name="CALP" description="Increase frequency of RTC by 488.5 ppm This feature is intended to be used in conjunction with CALM, which lowers the frequency of the calendar with a fine resolution. if the input frequency is 32768 Hz, the number of RTCCLK pulses added during a 32-second window is calculated as follows: (512 * CALP) - CALM. Refer to Section24.3.12: RTC smooth digital calibration." start="15" size="1" />
+    </Register>
+    <Register name="RTC_TAMPCR" description="RTC tamper and alternate function configuration register" start="+0x40" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TAMP1E" description="RTC_TAMP1 input detection enable" start="0" size="1" />
+      <BitField name="TAMP1TRG" description="Active level for RTC_TAMP1 input If TAMPFLT != 00 if TAMPFLT = 00:" start="1" size="1" />
+      <BitField name="TAMPIE" description="Tamper interrupt enable" start="2" size="1" />
+      <BitField name="TAMP2E" description="RTC_TAMP2 input detection enable" start="3" size="1" />
+      <BitField name="TAMP2TRG" description="Active level for RTC_TAMP2 input if TAMPFLT != 00: if TAMPFLT = 00:" start="4" size="1" />
+      <BitField name="TAMP3E" description="RTC_TAMP3 detection enable" start="5" size="1" />
+      <BitField name="TAMP3TRG" description="Active level for RTC_TAMP3 input if TAMPFLT != 00: if TAMPFLT = 00:" start="6" size="1" />
+      <BitField name="TAMPTS" description="Activate timestamp on tamper detection event TAMPTS is valid even if TSE=0 in the RTC_CR register." start="7" size="1" />
+      <BitField name="TAMPFREQ" description="Tamper sampling frequency Determines the frequency at which each of the RTC_TAMPx inputs are sampled." start="8" size="3" />
+      <BitField name="TAMPFLT" description="RTC_TAMPx filter count These bits determines the number of consecutive samples at the specified level (TAMP*TRG) needed to activate a Tamper event. TAMPFLT is valid for each of the RTC_TAMPx inputs." start="11" size="2" />
+      <BitField name="TAMPPRCH" description="RTC_TAMPx precharge duration These bit determines the duration of time during which the pull-up/is activated before each sample. TAMPPRCH is valid for each of the RTC_TAMPx inputs." start="13" size="2" />
+      <BitField name="TAMPPUDIS" description="RTC_TAMPx pull-up disable This bit determines if each of the RTC_TAMPx pins are pre-charged before each sample." start="15" size="1" />
+      <BitField name="TAMP1IE" description="Tamper 1 interrupt enable" start="16" size="1" />
+      <BitField name="TAMP1NOERASE" description="Tamper 1 no erase" start="17" size="1" />
+      <BitField name="TAMP1MF" description="Tamper 1 mask flag" start="18" size="1" />
+      <BitField name="TAMP2IE" description="Tamper 2 interrupt enable" start="19" size="1" />
+      <BitField name="TAMP2NOERASE" description="Tamper 2 no erase" start="20" size="1" />
+      <BitField name="TAMP2MF" description="Tamper 2 mask flag" start="21" size="1" />
+      <BitField name="TAMP3IE" description="Tamper 3 interrupt enable" start="22" size="1" />
+      <BitField name="TAMP3NOERASE" description="Tamper 3 no erase" start="23" size="1" />
+      <BitField name="TAMP3MF" description="Tamper 3 mask flag" start="24" size="1" />
+    </Register>
+    <Register name="RTC_ALRMASSR" description="This register can be written only when ALRAE is reset in RTC_CR register, or in initialization mode.This register is write protected. The write access procedure is described in RTC register write protection on page9" start="+0x44" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SS" description="Sub seconds value This value is compared with the contents of the synchronous prescaler counter to determine if Alarm A is to be activated. Only bits 0 up MASKSS-1 are compared." start="0" size="15" />
+      <BitField name="MASKSS" description="Mask the most-significant bits starting at this bit ... The overflow bits of the synchronous counter (bits 15) is never compared. This bit can be different from 0 only after a shift operation." start="24" size="4" />
+    </Register>
+    <Register name="RTC_ALRMBSSR" description="This register can be written only when ALRBE is reset in RTC_CR register, or in initialization mode.This register is write protected.The write access procedure is described in Section: RTC register write protection." start="+0x48" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SS" description="Sub seconds value This value is compared with the contents of the synchronous prescaler counter to determine if Alarm B is to be activated. Only bits 0 up to MASKSS-1 are compared." start="0" size="15" />
+      <BitField name="MASKSS" description="Mask the most-significant bits starting at this bit ... The overflow bits of the synchronous counter (bits 15) is never compared. This bit can be different from 0 only after a shift operation." start="24" size="4" />
+    </Register>
+    <Register name="RTC_BKP0R" description="RTC backup registers" start="+0x50" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BKP" description="The application can write or read data to and from these registers. They are powered-on by VBAT when VDD is switched off, so that they are not reset by System reset, and their contents remain valid when the device operates in low-power mode. This register is reset on a tamper detection event, as long as TAMPxF=1. or when the Flash readout protection is disabled." start="0" size="32" />
+    </Register>
+    <Register name="RTC_BKP1R" description="RTC backup registers" start="+0x54" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BKP" description="The application can write or read data to and from these registers. They are powered-on by VBAT when VDD is switched off, so that they are not reset by System reset, and their contents remain valid when the device operates in low-power mode. This register is reset on a tamper detection event, as long as TAMPxF=1. or when the Flash readout protection is disabled." start="0" size="32" />
+    </Register>
+    <Register name="RTC_BKP2R" description="RTC backup registers" start="+0x58" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BKP" description="The application can write or read data to and from these registers. They are powered-on by VBAT when VDD is switched off, so that they are not reset by System reset, and their contents remain valid when the device operates in low-power mode. This register is reset on a tamper detection event, as long as TAMPxF=1. or when the Flash readout protection is disabled." start="0" size="32" />
+    </Register>
+    <Register name="RTC_BKP3R" description="RTC backup registers" start="+0x5C" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BKP" description="The application can write or read data to and from these registers. They are powered-on by VBAT when VDD is switched off, so that they are not reset by System reset, and their contents remain valid when the device operates in low-power mode. This register is reset on a tamper detection event, as long as TAMPxF=1. or when the Flash readout protection is disabled." start="0" size="32" />
+    </Register>
+    <Register name="RTC_BKP4R" description="RTC backup registers" start="+0x60" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BKP" description="The application can write or read data to and from these registers. They are powered-on by VBAT when VDD is switched off, so that they are not reset by System reset, and their contents remain valid when the device operates in low-power mode. This register is reset on a tamper detection event, as long as TAMPxF=1. or when the Flash readout protection is disabled." start="0" size="32" />
+    </Register>
+    <Register name="RTC_BKP5R" description="RTC backup registers" start="+0x64" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BKP" description="The application can write or read data to and from these registers. They are powered-on by VBAT when VDD is switched off, so that they are not reset by System reset, and their contents remain valid when the device operates in low-power mode. This register is reset on a tamper detection event, as long as TAMPxF=1. or when the Flash readout protection is disabled." start="0" size="32" />
+    </Register>
+    <Register name="RTC_BKP6R" description="RTC backup registers" start="+0x68" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BKP" description="The application can write or read data to and from these registers. They are powered-on by VBAT when VDD is switched off, so that they are not reset by System reset, and their contents remain valid when the device operates in low-power mode. This register is reset on a tamper detection event, as long as TAMPxF=1. or when the Flash readout protection is disabled." start="0" size="32" />
+    </Register>
+    <Register name="RTC_BKP7R" description="RTC backup registers" start="+0x6C" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BKP" description="The application can write or read data to and from these registers. They are powered-on by VBAT when VDD is switched off, so that they are not reset by System reset, and their contents remain valid when the device operates in low-power mode. This register is reset on a tamper detection event, as long as TAMPxF=1. or when the Flash readout protection is disabled." start="0" size="32" />
+    </Register>
+    <Register name="RTC_BKP8R" description="RTC backup registers" start="+0x70" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BKP" description="The application can write or read data to and from these registers. They are powered-on by VBAT when VDD is switched off, so that they are not reset by System reset, and their contents remain valid when the device operates in low-power mode. This register is reset on a tamper detection event, as long as TAMPxF=1. or when the Flash readout protection is disabled." start="0" size="32" />
+    </Register>
+    <Register name="RTC_BKP9R" description="RTC backup registers" start="+0x74" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BKP" description="The application can write or read data to and from these registers. They are powered-on by VBAT when VDD is switched off, so that they are not reset by System reset, and their contents remain valid when the device operates in low-power mode. This register is reset on a tamper detection event, as long as TAMPxF=1. or when the Flash readout protection is disabled." start="0" size="32" />
+    </Register>
+    <Register name="RTC_BKP10R" description="RTC backup registers" start="+0x78" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BKP" description="The application can write or read data to and from these registers. They are powered-on by VBAT when VDD is switched off, so that they are not reset by System reset, and their contents remain valid when the device operates in low-power mode. This register is reset on a tamper detection event, as long as TAMPxF=1. or when the Flash readout protection is disabled." start="0" size="32" />
+    </Register>
+    <Register name="RTC_BKP11R" description="RTC backup registers" start="+0x7C" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BKP" description="The application can write or read data to and from these registers. They are powered-on by VBAT when VDD is switched off, so that they are not reset by System reset, and their contents remain valid when the device operates in low-power mode. This register is reset on a tamper detection event, as long as TAMPxF=1. or when the Flash readout protection is disabled." start="0" size="32" />
+    </Register>
+    <Register name="RTC_BKP12R" description="RTC backup registers" start="+0x80" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BKP" description="The application can write or read data to and from these registers. They are powered-on by VBAT when VDD is switched off, so that they are not reset by System reset, and their contents remain valid when the device operates in low-power mode. This register is reset on a tamper detection event, as long as TAMPxF=1. or when the Flash readout protection is disabled." start="0" size="32" />
+    </Register>
+    <Register name="RTC_BKP13R" description="RTC backup registers" start="+0x84" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BKP" description="The application can write or read data to and from these registers. They are powered-on by VBAT when VDD is switched off, so that they are not reset by System reset, and their contents remain valid when the device operates in low-power mode. This register is reset on a tamper detection event, as long as TAMPxF=1. or when the Flash readout protection is disabled." start="0" size="32" />
+    </Register>
+    <Register name="RTC_BKP14R" description="RTC backup registers" start="+0x88" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BKP" description="The application can write or read data to and from these registers. They are powered-on by VBAT when VDD is switched off, so that they are not reset by System reset, and their contents remain valid when the device operates in low-power mode. This register is reset on a tamper detection event, as long as TAMPxF=1. or when the Flash readout protection is disabled." start="0" size="32" />
+    </Register>
+    <Register name="RTC_BKP15R" description="RTC backup registers" start="+0x8C" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BKP" description="The application can write or read data to and from these registers. They are powered-on by VBAT when VDD is switched off, so that they are not reset by System reset, and their contents remain valid when the device operates in low-power mode. This register is reset on a tamper detection event, as long as TAMPxF=1. or when the Flash readout protection is disabled." start="0" size="32" />
+    </Register>
+    <Register name="RTC_OR" description="RTC option register" start="+0x4C" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RTC_ALARM_TYPE" description="RTC_ALARM output type on PC13" start="0" size="1" />
+      <BitField name="RTC_OUT_RMP" description="RTC_OUT remap" start="1" size="1" />
+    </Register>
+    <Register name="RTC_BKP16R" description="RTC backup registers" start="+0x90" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BKP" description="The application can write or read data to and from these registers. They are powered-on by VBAT when VDD is switched off, so that they are not reset by System reset, and their contents remain valid when the device operates in low-power mode. This register is reset on a tamper detection event, as long as TAMPxF=1. or when the Flash readout protection is disabled." start="0" size="32" />
+    </Register>
+    <Register name="RTC_BKP17R" description="RTC backup registers" start="+0x94" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BKP" description="The application can write or read data to and from these registers. They are powered-on by VBAT when VDD is switched off, so that they are not reset by System reset, and their contents remain valid when the device operates in low-power mode. This register is reset on a tamper detection event, as long as TAMPxF=1. or when the Flash readout protection is disabled." start="0" size="32" />
+    </Register>
+    <Register name="RTC_BKP18R" description="RTC backup registers" start="+0x98" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BKP" description="The application can write or read data to and from these registers. They are powered-on by VBAT when VDD is switched off, so that they are not reset by System reset, and their contents remain valid when the device operates in low-power mode. This register is reset on a tamper detection event, as long as TAMPxF=1. or when the Flash readout protection is disabled." start="0" size="32" />
+    </Register>
+    <Register name="RTC_BKP19R" description="RTC backup registers" start="+0x9C" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BKP" description="The application can write or read data to and from these registers. They are powered-on by VBAT when VDD is switched off, so that they are not reset by System reset, and their contents remain valid when the device operates in low-power mode. This register is reset on a tamper detection event, as long as TAMPxF=1. or when the Flash readout protection is disabled." start="0" size="32" />
+    </Register>
+    <Register name="RTC_BKP20R" description="RTC backup registers" start="+0xA0" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BKP" description="The application can write or read data to and from these registers. They are powered-on by VBAT when VDD is switched off, so that they are not reset by System reset, and their contents remain valid when the device operates in low-power mode. This register is reset on a tamper detection event, as long as TAMPxF=1. or when the Flash readout protection is disabled." start="0" size="32" />
+    </Register>
+    <Register name="RTC_BKP21R" description="RTC backup registers" start="+0xA4" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BKP" description="The application can write or read data to and from these registers. They are powered-on by VBAT when VDD is switched off, so that they are not reset by System reset, and their contents remain valid when the device operates in low-power mode. This register is reset on a tamper detection event, as long as TAMPxF=1. or when the Flash readout protection is disabled." start="0" size="32" />
+    </Register>
+    <Register name="RTC_BKP22R" description="RTC backup registers" start="+0xA8" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BKP" description="The application can write or read data to and from these registers. They are powered-on by VBAT when VDD is switched off, so that they are not reset by System reset, and their contents remain valid when the device operates in low-power mode. This register is reset on a tamper detection event, as long as TAMPxF=1. or when the Flash readout protection is disabled." start="0" size="32" />
+    </Register>
+    <Register name="RTC_BKP23R" description="RTC backup registers" start="+0xAC" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BKP" description="The application can write or read data to and from these registers. They are powered-on by VBAT when VDD is switched off, so that they are not reset by System reset, and their contents remain valid when the device operates in low-power mode. This register is reset on a tamper detection event, as long as TAMPxF=1. or when the Flash readout protection is disabled." start="0" size="32" />
+    </Register>
+    <Register name="RTC_BKP24R" description="RTC backup registers" start="+0xB0" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BKP" description="The application can write or read data to and from these registers. They are powered-on by VBAT when VDD is switched off, so that they are not reset by System reset, and their contents remain valid when the device operates in low-power mode. This register is reset on a tamper detection event, as long as TAMPxF=1. or when the Flash readout protection is disabled." start="0" size="32" />
+    </Register>
+    <Register name="RTC_BKP25R" description="RTC backup registers" start="+0xB4" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BKP" description="The application can write or read data to and from these registers. They are powered-on by VBAT when VDD is switched off, so that they are not reset by System reset, and their contents remain valid when the device operates in low-power mode. This register is reset on a tamper detection event, as long as TAMPxF=1. or when the Flash readout protection is disabled." start="0" size="32" />
+    </Register>
+    <Register name="RTC_BKP26R" description="RTC backup registers" start="+0xB8" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BKP" description="The application can write or read data to and from these registers. They are powered-on by VBAT when VDD is switched off, so that they are not reset by System reset, and their contents remain valid when the device operates in low-power mode. This register is reset on a tamper detection event, as long as TAMPxF=1. or when the Flash readout protection is disabled." start="0" size="32" />
+    </Register>
+    <Register name="RTC_BKP27R" description="RTC backup registers" start="+0xBC" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BKP" description="The application can write or read data to and from these registers. They are powered-on by VBAT when VDD is switched off, so that they are not reset by System reset, and their contents remain valid when the device operates in low-power mode. This register is reset on a tamper detection event, as long as TAMPxF=1. or when the Flash readout protection is disabled." start="0" size="32" />
+    </Register>
+    <Register name="RTC_BKP28R" description="RTC backup registers" start="+0xC0" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BKP" description="The application can write or read data to and from these registers. They are powered-on by VBAT when VDD is switched off, so that they are not reset by System reset, and their contents remain valid when the device operates in low-power mode. This register is reset on a tamper detection event, as long as TAMPxF=1. or when the Flash readout protection is disabled." start="0" size="32" />
+    </Register>
+    <Register name="RTC_BKP29R" description="RTC backup registers" start="+0xC4" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BKP" description="The application can write or read data to and from these registers. They are powered-on by VBAT when VDD is switched off, so that they are not reset by System reset, and their contents remain valid when the device operates in low-power mode. This register is reset on a tamper detection event, as long as TAMPxF=1. or when the Flash readout protection is disabled." start="0" size="32" />
+    </Register>
+    <Register name="RTC_BKP30R" description="RTC backup registers" start="+0xC8" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BKP" description="The application can write or read data to and from these registers. They are powered-on by VBAT when VDD is switched off, so that they are not reset by System reset, and their contents remain valid when the device operates in low-power mode. This register is reset on a tamper detection event, as long as TAMPxF=1. or when the Flash readout protection is disabled." start="0" size="32" />
+    </Register>
+    <Register name="RTC_BKP31R" description="RTC backup registers" start="+0xCC" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BKP" description="The application can write or read data to and from these registers. They are powered-on by VBAT when VDD is switched off, so that they are not reset by System reset, and their contents remain valid when the device operates in low-power mode. This register is reset on a tamper detection event, as long as TAMPxF=1. or when the Flash readout protection is disabled." start="0" size="32" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="SAI1" description="SAI" start="0x40015800">
+    <Register name="SAI_GCR" description="Global configuration register" start="+0x0" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SYNCOUT" description="Synchronization outputs These bits are set and cleared by software." start="4" size="2" />
+      <BitField name="SYNCIN" description="Synchronization inputs" start="0" size="2" />
+    </Register>
+    <Register name="SAI_ACR1" description="Configuration register 1" start="+0x4" size="4" access="Read/Write" reset_value="0x00000040" reset_mask="0xFFFFFFFF">
+      <BitField name="MODE" description="SAIx audio block mode immediately" start="0" size="2" />
+      <BitField name="PRTCFG" description="Protocol configuration. These bits are set and cleared by software. These bits have to be configured when the audio block is disabled." start="2" size="2" />
+      <BitField name="DS" description="Data size. These bits are set and cleared by software. These bits are ignored when the SPDIF protocols are selected (bit PRTCFG[1:0]), because the frame and the data size are fixed in such case. When the companding mode is selected through COMP[1:0] bits, DS[1:0] are ignored since the data size is fixed to 8 bits by the algorithm. These bits must be configured when the audio block is disabled." start="5" size="3" />
+      <BitField name="LSBFIRST" description="Least significant bit first. This bit is set and cleared by software. It must be configured when the audio block is disabled. This bit has no meaning in AC97 audio protocol since AC97 data are always transferred with the MSB first. This bit has no meaning in SPDIF audio protocol since in SPDIF data are always transferred with LSB first." start="8" size="1" />
+      <BitField name="CKSTR" description="Clock strobing edge. This bit is set and cleared by software. It must be configured when the audio block is disabled. This bit has no meaning in SPDIF audio protocol." start="9" size="1" />
+      <BitField name="SYNCEN" description="Synchronization enable. These bits are set and cleared by software. They must be configured when the audio sub-block is disabled. Note: The audio sub-block should be configured as asynchronous when SPDIF mode is enabled." start="10" size="2" />
+      <BitField name="MONO" description="Mono mode. This bit is set and cleared by software. It is meaningful only when the number of slots is equal to 2. When the mono mode is selected, slot 0 data are duplicated on slot 1 when the audio block operates as a transmitter. In reception mode, the slot1 is discarded and only the data received from slot 0 are stored. Refer to Section: Mono/stereo mode for more details." start="12" size="1" />
+      <BitField name="OUTDRIV" description="Output drive. This bit is set and cleared by software. Note: This bit has to be set before enabling the audio block and after the audio block configuration." start="13" size="1" />
+      <BitField name="SAIXEN" description="Audio block enable where x is A or B. This bit is set by software. To switch off the audio block, the application software must program this bit to 0 and poll the bit till it reads back 0, meaning that the block is completely disabled. Before setting this bit to 1, check that it is set to 0, otherwise the enable command will not be taken into account. This bit allows to control the state of SAIx audio block. If it is disabled when an audio frame transfer is ongoing, the ongoing transfer completes and the cell is fully disabled at the end of this audio frame transfer. Note: When SAIx block is configured in master mode, the clock must be present on the input of SAIx before setting SAIXEN bit." start="16" size="1" />
+      <BitField name="DMAEN" description="DMA enable. This bit is set and cleared by software. Note: Since the audio block defaults to operate as a transmitter after reset, the MODE[1:0] bits must be configured before setting DMAEN to avoid a DMA request in receiver mode." start="17" size="1" />
+      <BitField name="NOMCK" description="No divider" start="19" size="1" />
+      <BitField name="MCKDIV" description="Master clock divider. These bits are set and cleared by software. These bits are meaningless when the audio block operates in slave mode. They have to be configured when the audio block is disabled. Others: the master clock frequency is calculated accordingly to the following formula:" start="20" size="4" />
+      <BitField name="OSR" description="Oversampling ratio for master clock" start="26" size="1" />
+    </Register>
+    <Register name="SAI_ACR2" description="Configuration register 2" start="+0x8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FTH" description="FIFO threshold. This bit is set and cleared by software." start="0" size="3" access="Read/Write" />
+      <BitField name="FFLUSH" description="FIFO flush. This bit is set by software. It is always read as 0. This bit should be configured when the SAI is disabled." start="3" size="1" access="WriteOnly" />
+      <BitField name="TRIS" description="Tristate management on data line. This bit is set and cleared by software. It is meaningful only if the audio block is configured as a transmitter. This bit is not used when the audio block is configured in SPDIF mode. It should be configured when SAI is disabled. Refer to Section: Output data line management on an inactive slot for more details." start="4" size="1" access="Read/Write" />
+      <BitField name="MUTE" description="Mute. This bit is set and cleared by software. It is meaningful only when the audio block operates as a transmitter. The MUTE value is linked to value of MUTEVAL if the number of slots is lower or equal to 2, or equal to 0 if it is greater than 2. Refer to Section: Mute mode for more details. Note: This bit is meaningless and should not be used for SPDIF audio blocks." start="5" size="1" access="Read/Write" />
+      <BitField name="MUTEVAL" description="Mute value. This bit is set and cleared by software.It must be written before enabling the audio block: SAIXEN. This bit is meaningful only when the audio block operates as a transmitter, the number of slots is lower or equal to 2 and the MUTE bit is set. If more slots are declared, the bit value sent during the transmission in mute mode is equal to 0, whatever the value of MUTEVAL. if the number of slot is lower or equal to 2 and MUTEVAL = 1, the MUTE value transmitted for each slot is the one sent during the previous frame. Refer to Section: Mute mode for more details. Note: This bit is meaningless and should not be used for SPDIF audio blocks." start="6" size="1" access="Read/Write" />
+      <BitField name="MUTECNT" description="Mute counter. These bits are set and cleared by software. They are used only in reception mode. The value set in these bits is compared to the number of consecutive mute frames detected in reception. When the number of mute frames is equal to this value, the flag MUTEDET will be set and an interrupt will be generated if bit MUTEDETIE is set. Refer to Section: Mute mode for more details." start="7" size="6" access="Read/Write" />
+      <BitField name="CPL" description="Complement bit. This bit is set and cleared by software. It defines the type of complement to be used for companding mode Note: This bit has effect only when the companding mode is -Law algorithm or A-Law algorithm." start="13" size="1" access="Read/Write" />
+      <BitField name="COMP" description="Companding mode. These bits are set and cleared by software. The -Law and the A-Law log are a part of the CCITT G.711 recommendation, the type of complement that will be used depends on CPL bit. The data expansion or data compression are determined by the state of bit MODE[0]. The data compression is applied if the audio block is configured as a transmitter. The data expansion is automatically applied when the audio block is configured as a receiver. Refer to Section: Companding mode for more details. Note: Companding mode is applicable only when TDM is selected." start="14" size="2" access="Read/Write" />
+    </Register>
+    <Register name="SAI_AFRCR" description="This register has no meaning in AC97 and SPDIF audio protocol" start="+0xC" size="4" reset_value="0x00000007" reset_mask="0xFFFFFFFF">
+      <BitField name="FRL" description="Frame length. These bits are set and cleared by software. They define the audio frame length expressed in number of SCK clock cycles: the number of bits in the frame is equal to FRL[7:0] + 1. The minimum number of bits to transfer in an audio frame must be equal to 8, otherwise the audio block will behaves in an unexpected way. This is the case when the data size is 8 bits and only one slot 0 is defined in NBSLOT[4:0] of SAI_xSLOTR register (NBSLOT[3:0] = 0000). In master mode, if the master clock (available on MCLK_x pin) is used, the frame length should be aligned with a number equal to a power of 2, ranging from 8 to 256. When the master clock is not used (NODIV = 1), it is recommended to program the frame length to an value ranging from 8 to 256. These bits are meaningless and are not used in AC97 or SPDIF audio block configuration." start="0" size="8" access="Read/Write" />
+      <BitField name="FSALL" description="Frame synchronization active level length. These bits are set and cleared by software. They specify the length in number of bit clock (SCK) + 1 (FSALL[6:0] + 1) of the active level of the FS signal in the audio frame These bits are meaningless and are not used in AC97 or SPDIF audio block configuration. They must be configured when the audio block is disabled." start="8" size="7" access="Read/Write" />
+      <BitField name="FSDEF" description="Frame synchronization definition. This bit is set and cleared by software. When the bit is set, the number of slots defined in the SAI_xSLOTR register has to be even. It means that half of this number of slots will be dedicated to the left channel and the other slots for the right channel (e.g: this bit has to be set for I2S or MSB/LSB-justified protocols...). This bit is meaningless and is not used in AC97 or SPDIF audio block configuration. It must be configured when the audio block is disabled." start="16" size="1" access="ReadOnly" />
+      <BitField name="FSPOL" description="Frame synchronization polarity. This bit is set and cleared by software. It is used to configure the level of the start of frame on the FS signal. It is meaningless and is not used in AC97 or SPDIF audio block configuration. This bit must be configured when the audio block is disabled." start="17" size="1" access="Read/Write" />
+      <BitField name="FSOFF" description="Frame synchronization offset. This bit is set and cleared by software. It is meaningless and is not used in AC97 or SPDIF audio block configuration. This bit must be configured when the audio block is disabled." start="18" size="1" access="Read/Write" />
+    </Register>
+    <Register name="SAI_ASLOTR" description="This register has no meaning in AC97 and SPDIF audio protocol" start="+0x10" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FBOFF" description="First bit offset These bits are set and cleared by software. The value set in this bitfield defines the position of the first data transfer bit in the slot. It represents an offset value. In transmission mode, the bits outside the data field are forced to 0. In reception mode, the extra received bits are discarded. These bits must be set when the audio block is disabled. They are ignored in AC97 or SPDIF mode." start="0" size="5" />
+      <BitField name="SLOTSZ" description="Slot size This bits is set and cleared by software. The slot size must be higher or equal to the data size. If this condition is not respected, the behavior of the SAI will be undetermined. Refer to Section: Output data line management on an inactive slot for information on how to drive SD line. These bits must be set when the audio block is disabled. They are ignored in AC97 or SPDIF mode." start="6" size="2" />
+      <BitField name="NBSLOT" description="Number of slots in an audio frame. These bits are set and cleared by software. The value set in this bitfield represents the number of slots + 1 in the audio frame (including the number of inactive slots). The maximum number of slots is 16. The number of slots should be even if FSDEF bit in the SAI_xFRCR register is set. The number of slots must be configured when the audio block is disabled. They are ignored in AC97 or SPDIF mode." start="8" size="4" />
+      <BitField name="SLOTEN" description="Slot enable. These bits are set and cleared by software. Each SLOTEN bit corresponds to a slot position from 0 to 15 (maximum 16 slots). The slot must be enabled when the audio block is disabled. They are ignored in AC97 or SPDIF mode." start="16" size="16" />
+    </Register>
+    <Register name="SAI_AIM" description="Interrupt mask register 2" start="+0x14" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OVRUDRIE" description="Overrun/underrun interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt is generated if the OVRUDR bit in the SAI_xSR register is set." start="0" size="1" />
+      <BitField name="MUTEDETIE" description="Mute detection interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt is generated if the MUTEDET bit in the SAI_xSR register is set. This bit has a meaning only if the audio block is configured in receiver mode." start="1" size="1" />
+      <BitField name="WCKCFGIE" description="Wrong clock configuration interrupt enable. This bit is set and cleared by software. This bit is taken into account only if the audio block is configured as a master (MODE[1] = 0) and NODIV = 0. It generates an interrupt if the WCKCFG flag in the SAI_xSR register is set. Note: This bit is used only in TDM mode and is meaningless in other modes." start="2" size="1" />
+      <BitField name="FREQIE" description="FIFO request interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt is generated if the FREQ bit in the SAI_xSR register is set. Since the audio block defaults to operate as a transmitter after reset, the MODE bit must be configured before setting FREQIE to avoid a parasitic interruption in receiver mode," start="3" size="1" />
+      <BitField name="CNRDYIE" description="Codec not ready interrupt enable (AC97). This bit is set and cleared by software. When the interrupt is enabled, the audio block detects in the slot 0 (tag0) of the AC97 frame if the Codec connected to this line is ready or not. If it is not ready, the CNRDY flag in the SAI_xSR register is set and an interruption i generated. This bit has a meaning only if the AC97 mode is selected through PRTCFG[1:0] bits and the audio block is operates as a receiver." start="4" size="1" />
+      <BitField name="AFSDETIE" description="Anticipated frame synchronization detection interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt will be generated if the AFSDET bit in the SAI_xSR register is set. This bit is meaningless in AC97, SPDIF mode or when the audio block operates as a master." start="5" size="1" />
+      <BitField name="LFSDETIE" description="Late frame synchronization detection interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt will be generated if the LFSDET bit is set in the SAI_xSR register. This bit is meaningless in AC97, SPDIF mode or when the audio block operates as a master." start="6" size="1" />
+    </Register>
+    <Register name="SAI_ASR" description="Status register" start="+0x18" size="4" access="ReadOnly" reset_value="0x00000008" reset_mask="0xFFFFFFFF">
+      <BitField name="OVRUDR" description="Overrun / underrun. This bit is read only. The overrun and underrun conditions can occur only when the audio block is configured as a receiver and a transmitter, respectively. It can generate an interrupt if OVRUDRIE bit is set in SAI_xIM register. This flag is cleared when the software sets COVRUDR bit in SAI_xCLRFR register." start="0" size="1" />
+      <BitField name="MUTEDET" description="Mute detection. This bit is read only. This flag is set if consecutive 0 values are received in each slot of a given audio frame and for a consecutive number of audio frames (set in the MUTECNT bit in the SAI_xCR2 register). It can generate an interrupt if MUTEDETIE bit is set in SAI_xIM register. This flag is cleared when the software sets bit CMUTEDET in the SAI_xCLRFR register." start="1" size="1" />
+      <BitField name="WCKCFG" description="Wrong clock configuration flag. This bit is read only. This bit is used only when the audio block operates in master mode (MODE[1] = 0) and NODIV = 0. It can generate an interrupt if WCKCFGIE bit is set in SAI_xIM register. This flag is cleared when the software sets CWCKCFG bit in SAI_xCLRFR register." start="2" size="1" />
+      <BitField name="FREQ" description="FIFO request. This bit is read only. The request depends on the audio block configuration: If the block is configured in transmission mode, the FIFO request is related to a write request operation in the SAI_xDR. If the block configured in reception, the FIFO request related to a read request operation from the SAI_xDR. This flag can generate an interrupt if FREQIE bit is set in SAI_xIM register." start="3" size="1" />
+      <BitField name="CNRDY" description="Codec not ready. This bit is read only. This bit is used only when the AC97 audio protocol is selected in the SAI_xCR1 register and configured in receiver mode. It can generate an interrupt if CNRDYIE bit is set in SAI_xIM register. This flag is cleared when the software sets CCNRDY bit in SAI_xCLRFR register." start="4" size="1" />
+      <BitField name="AFSDET" description="Anticipated frame synchronization detection. This bit is read only. This flag can be set only if the audio block is configured in slave mode. It is not used in AC97or SPDIF mode. It can generate an interrupt if AFSDETIE bit is set in SAI_xIM register. This flag is cleared when the software sets CAFSDET bit in SAI_xCLRFR register." start="5" size="1" />
+      <BitField name="LFSDET" description="Late frame synchronization detection. This bit is read only. This flag can be set only if the audio block is configured in slave mode. It is not used in AC97 or SPDIF mode. It can generate an interrupt if LFSDETIE bit is set in the SAI_xIM register. This flag is cleared when the software sets bit CLFSDET in SAI_xCLRFR register" start="6" size="1" />
+      <BitField name="FLVL" description="FIFO level threshold. This bit is read only. The FIFO level threshold flag is managed only by hardware and its setting depends on SAI block configuration (transmitter or receiver mode). If the SAI block is configured as transmitter: If SAI block is configured as receiver:" start="16" size="3" />
+    </Register>
+    <Register name="SAI_ACLRFR" description="Clear flag register" start="+0x1C" size="4" access="WriteOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="COVRUDR" description="Clear overrun / underrun. This bit is write only. Programming this bit to 1 clears the OVRUDR flag in the SAI_xSR register. Reading this bit always returns the value 0." start="0" size="1" />
+      <BitField name="CMUTEDET" description="Mute detection flag. This bit is write only. Programming this bit to 1 clears the MUTEDET flag in the SAI_xSR register. Reading this bit always returns the value 0." start="1" size="1" />
+      <BitField name="CWCKCFG" description="Clear wrong clock configuration flag. This bit is write only. Programming this bit to 1 clears the WCKCFG flag in the SAI_xSR register. This bit is used only when the audio block is set as master (MODE[1] = 0) and NODIV = 0 in the SAI_xCR1 register. Reading this bit always returns the value 0." start="2" size="1" />
+      <BitField name="CCNRDY" description="Clear Codec not ready flag. This bit is write only. Programming this bit to 1 clears the CNRDY flag in the SAI_xSR register. This bit is used only when the AC97 audio protocol is selected in the SAI_xCR1 register. Reading this bit always returns the value 0." start="4" size="1" />
+      <BitField name="CAFSDET" description="Clear anticipated frame synchronization detection flag. This bit is write only. Programming this bit to 1 clears the AFSDET flag in the SAI_xSR register. It is not used in AC97or SPDIF mode. Reading this bit always returns the value 0." start="5" size="1" />
+      <BitField name="CLFSDET" description="Clear late frame synchronization detection flag. This bit is write only. Programming this bit to 1 clears the LFSDET flag in the SAI_xSR register. This bit is not used in AC97or SPDIF mode Reading this bit always returns the value 0." start="6" size="1" />
+    </Register>
+    <Register name="SAI_ADR" description="Data register" start="+0x20" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DATA" description="Data A write to this register loads the FIFO provided the FIFO is not full. A read from this register empties the FIFO if the FIFO is not empty." start="0" size="32" />
+    </Register>
+    <Register name="SAI_BCR1" description="Configuration register 1" start="+0x24" size="4" access="Read/Write" reset_value="0x00000040" reset_mask="0xFFFFFFFF">
+      <BitField name="MODE" description="SAIx audio block mode immediately" start="0" size="2" />
+      <BitField name="PRTCFG" description="Protocol configuration. These bits are set and cleared by software. These bits have to be configured when the audio block is disabled." start="2" size="2" />
+      <BitField name="DS" description="Data size. These bits are set and cleared by software. These bits are ignored when the SPDIF protocols are selected (bit PRTCFG[1:0]), because the frame and the data size are fixed in such case. When the companding mode is selected through COMP[1:0] bits, DS[1:0] are ignored since the data size is fixed to 8 bits by the algorithm. These bits must be configured when the audio block is disabled." start="5" size="3" />
+      <BitField name="LSBFIRST" description="Least significant bit first. This bit is set and cleared by software. It must be configured when the audio block is disabled. This bit has no meaning in AC97 audio protocol since AC97 data are always transferred with the MSB first. This bit has no meaning in SPDIF audio protocol since in SPDIF data are always transferred with LSB first." start="8" size="1" />
+      <BitField name="CKSTR" description="Clock strobing edge. This bit is set and cleared by software. It must be configured when the audio block is disabled. This bit has no meaning in SPDIF audio protocol." start="9" size="1" />
+      <BitField name="SYNCEN" description="Synchronization enable. These bits are set and cleared by software. They must be configured when the audio sub-block is disabled. Note: The audio sub-block should be configured as asynchronous when SPDIF mode is enabled." start="10" size="2" />
+      <BitField name="MONO" description="Mono mode. This bit is set and cleared by software. It is meaningful only when the number of slots is equal to 2. When the mono mode is selected, slot 0 data are duplicated on slot 1 when the audio block operates as a transmitter. In reception mode, the slot1 is discarded and only the data received from slot 0 are stored. Refer to Section: Mono/stereo mode for more details." start="12" size="1" />
+      <BitField name="OUTDRIV" description="Output drive. This bit is set and cleared by software. Note: This bit has to be set before enabling the audio block and after the audio block configuration." start="13" size="1" />
+      <BitField name="SAIXEN" description="Audio block enable where x is A or B. This bit is set by software. To switch off the audio block, the application software must program this bit to 0 and poll the bit till it reads back 0, meaning that the block is completely disabled. Before setting this bit to 1, check that it is set to 0, otherwise the enable command will not be taken into account. This bit allows to control the state of SAIx audio block. If it is disabled when an audio frame transfer is ongoing, the ongoing transfer completes and the cell is fully disabled at the end of this audio frame transfer. Note: When SAIx block is configured in master mode, the clock must be present on the input of SAIx before setting SAIXEN bit." start="16" size="1" />
+      <BitField name="DMAEN" description="DMA enable. This bit is set and cleared by software. Note: Since the audio block defaults to operate as a transmitter after reset, the MODE[1:0] bits must be configured before setting DMAEN to avoid a DMA request in receiver mode." start="17" size="1" />
+      <BitField name="NOMCK" description="No divider" start="19" size="1" />
+      <BitField name="MCKDIV" description="Master clock divider. These bits are set and cleared by software. These bits are meaningless when the audio block operates in slave mode. They have to be configured when the audio block is disabled. Others: the master clock frequency is calculated accordingly to the following formula:" start="20" size="4" />
+      <BitField name="OSR" description="Oversampling ratio for master clock" start="26" size="1" />
+    </Register>
+    <Register name="SAI_BCR2" description="Configuration register 2" start="+0x28" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FTH" description="FIFO threshold. This bit is set and cleared by software." start="0" size="3" access="Read/Write" />
+      <BitField name="FFLUSH" description="FIFO flush. This bit is set by software. It is always read as 0. This bit should be configured when the SAI is disabled." start="3" size="1" access="WriteOnly" />
+      <BitField name="TRIS" description="Tristate management on data line. This bit is set and cleared by software. It is meaningful only if the audio block is configured as a transmitter. This bit is not used when the audio block is configured in SPDIF mode. It should be configured when SAI is disabled. Refer to Section: Output data line management on an inactive slot for more details." start="4" size="1" access="Read/Write" />
+      <BitField name="MUTE" description="Mute. This bit is set and cleared by software. It is meaningful only when the audio block operates as a transmitter. The MUTE value is linked to value of MUTEVAL if the number of slots is lower or equal to 2, or equal to 0 if it is greater than 2. Refer to Section: Mute mode for more details. Note: This bit is meaningless and should not be used for SPDIF audio blocks." start="5" size="1" access="Read/Write" />
+      <BitField name="MUTEVAL" description="Mute value. This bit is set and cleared by software.It must be written before enabling the audio block: SAIXEN. This bit is meaningful only when the audio block operates as a transmitter, the number of slots is lower or equal to 2 and the MUTE bit is set. If more slots are declared, the bit value sent during the transmission in mute mode is equal to 0, whatever the value of MUTEVAL. if the number of slot is lower or equal to 2 and MUTEVAL = 1, the MUTE value transmitted for each slot is the one sent during the previous frame. Refer to Section: Mute mode for more details. Note: This bit is meaningless and should not be used for SPDIF audio blocks." start="6" size="1" access="Read/Write" />
+      <BitField name="MUTECNT" description="Mute counter. These bits are set and cleared by software. They are used only in reception mode. The value set in these bits is compared to the number of consecutive mute frames detected in reception. When the number of mute frames is equal to this value, the flag MUTEDET will be set and an interrupt will be generated if bit MUTEDETIE is set. Refer to Section: Mute mode for more details." start="7" size="6" access="Read/Write" />
+      <BitField name="CPL" description="Complement bit. This bit is set and cleared by software. It defines the type of complement to be used for companding mode Note: This bit has effect only when the companding mode is -Law algorithm or A-Law algorithm." start="13" size="1" access="Read/Write" />
+      <BitField name="COMP" description="Companding mode. These bits are set and cleared by software. The -Law and the A-Law log are a part of the CCITT G.711 recommendation, the type of complement that will be used depends on CPL bit. The data expansion or data compression are determined by the state of bit MODE[0]. The data compression is applied if the audio block is configured as a transmitter. The data expansion is automatically applied when the audio block is configured as a receiver. Refer to Section: Companding mode for more details. Note: Companding mode is applicable only when TDM is selected." start="14" size="2" access="Read/Write" />
+    </Register>
+    <Register name="SAI_BFRCR" description="This register has no meaning in AC97 and SPDIF audio protocol" start="+0x2C" size="4" reset_value="0x00000007" reset_mask="0xFFFFFFFF">
+      <BitField name="FRL" description="Frame length. These bits are set and cleared by software. They define the audio frame length expressed in number of SCK clock cycles: the number of bits in the frame is equal to FRL[7:0] + 1. The minimum number of bits to transfer in an audio frame must be equal to 8, otherwise the audio block will behaves in an unexpected way. This is the case when the data size is 8 bits and only one slot 0 is defined in NBSLOT[4:0] of SAI_xSLOTR register (NBSLOT[3:0] = 0000). In master mode, if the master clock (available on MCLK_x pin) is used, the frame length should be aligned with a number equal to a power of 2, ranging from 8 to 256. When the master clock is not used (NODIV = 1), it is recommended to program the frame length to an value ranging from 8 to 256. These bits are meaningless and are not used in AC97 or SPDIF audio block configuration." start="0" size="8" access="Read/Write" />
+      <BitField name="FSALL" description="Frame synchronization active level length. These bits are set and cleared by software. They specify the length in number of bit clock (SCK) + 1 (FSALL[6:0] + 1) of the active level of the FS signal in the audio frame These bits are meaningless and are not used in AC97 or SPDIF audio block configuration. They must be configured when the audio block is disabled." start="8" size="7" access="Read/Write" />
+      <BitField name="FSDEF" description="Frame synchronization definition. This bit is set and cleared by software. When the bit is set, the number of slots defined in the SAI_xSLOTR register has to be even. It means that half of this number of slots will be dedicated to the left channel and the other slots for the right channel (e.g: this bit has to be set for I2S or MSB/LSB-justified protocols...). This bit is meaningless and is not used in AC97 or SPDIF audio block configuration. It must be configured when the audio block is disabled." start="16" size="1" access="ReadOnly" />
+      <BitField name="FSPOL" description="Frame synchronization polarity. This bit is set and cleared by software. It is used to configure the level of the start of frame on the FS signal. It is meaningless and is not used in AC97 or SPDIF audio block configuration. This bit must be configured when the audio block is disabled." start="17" size="1" access="Read/Write" />
+      <BitField name="FSOFF" description="Frame synchronization offset. This bit is set and cleared by software. It is meaningless and is not used in AC97 or SPDIF audio block configuration. This bit must be configured when the audio block is disabled." start="18" size="1" access="Read/Write" />
+    </Register>
+    <Register name="SAI_BSLOTR" description="This register has no meaning in AC97 and SPDIF audio protocol" start="+0x30" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FBOFF" description="First bit offset These bits are set and cleared by software. The value set in this bitfield defines the position of the first data transfer bit in the slot. It represents an offset value. In transmission mode, the bits outside the data field are forced to 0. In reception mode, the extra received bits are discarded. These bits must be set when the audio block is disabled. They are ignored in AC97 or SPDIF mode." start="0" size="5" />
+      <BitField name="SLOTSZ" description="Slot size This bits is set and cleared by software. The slot size must be higher or equal to the data size. If this condition is not respected, the behavior of the SAI will be undetermined. Refer to Section: Output data line management on an inactive slot for information on how to drive SD line. These bits must be set when the audio block is disabled. They are ignored in AC97 or SPDIF mode." start="6" size="2" />
+      <BitField name="NBSLOT" description="Number of slots in an audio frame. These bits are set and cleared by software. The value set in this bitfield represents the number of slots + 1 in the audio frame (including the number of inactive slots). The maximum number of slots is 16. The number of slots should be even if FSDEF bit in the SAI_xFRCR register is set. The number of slots must be configured when the audio block is disabled. They are ignored in AC97 or SPDIF mode." start="8" size="4" />
+      <BitField name="SLOTEN" description="Slot enable. These bits are set and cleared by software. Each SLOTEN bit corresponds to a slot position from 0 to 15 (maximum 16 slots). The slot must be enabled when the audio block is disabled. They are ignored in AC97 or SPDIF mode." start="16" size="16" />
+    </Register>
+    <Register name="SAI_BIM" description="Interrupt mask register 2" start="+0x34" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OVRUDRIE" description="Overrun/underrun interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt is generated if the OVRUDR bit in the SAI_xSR register is set." start="0" size="1" />
+      <BitField name="MUTEDETIE" description="Mute detection interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt is generated if the MUTEDET bit in the SAI_xSR register is set. This bit has a meaning only if the audio block is configured in receiver mode." start="1" size="1" />
+      <BitField name="WCKCFGIE" description="Wrong clock configuration interrupt enable. This bit is set and cleared by software. This bit is taken into account only if the audio block is configured as a master (MODE[1] = 0) and NODIV = 0. It generates an interrupt if the WCKCFG flag in the SAI_xSR register is set. Note: This bit is used only in TDM mode and is meaningless in other modes." start="2" size="1" />
+      <BitField name="FREQIE" description="FIFO request interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt is generated if the FREQ bit in the SAI_xSR register is set. Since the audio block defaults to operate as a transmitter after reset, the MODE bit must be configured before setting FREQIE to avoid a parasitic interruption in receiver mode," start="3" size="1" />
+      <BitField name="CNRDYIE" description="Codec not ready interrupt enable (AC97). This bit is set and cleared by software. When the interrupt is enabled, the audio block detects in the slot 0 (tag0) of the AC97 frame if the Codec connected to this line is ready or not. If it is not ready, the CNRDY flag in the SAI_xSR register is set and an interruption i generated. This bit has a meaning only if the AC97 mode is selected through PRTCFG[1:0] bits and the audio block is operates as a receiver." start="4" size="1" />
+      <BitField name="AFSDETIE" description="Anticipated frame synchronization detection interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt will be generated if the AFSDET bit in the SAI_xSR register is set. This bit is meaningless in AC97, SPDIF mode or when the audio block operates as a master." start="5" size="1" />
+      <BitField name="LFSDETIE" description="Late frame synchronization detection interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt will be generated if the LFSDET bit is set in the SAI_xSR register. This bit is meaningless in AC97, SPDIF mode or when the audio block operates as a master." start="6" size="1" />
+    </Register>
+    <Register name="SAI_BSR" description="Status register" start="+0x38" size="4" access="ReadOnly" reset_value="0x00000008" reset_mask="0xFFFFFFFF">
+      <BitField name="OVRUDR" description="Overrun / underrun. This bit is read only. The overrun and underrun conditions can occur only when the audio block is configured as a receiver and a transmitter, respectively. It can generate an interrupt if OVRUDRIE bit is set in SAI_xIM register. This flag is cleared when the software sets COVRUDR bit in SAI_xCLRFR register." start="0" size="1" />
+      <BitField name="MUTEDET" description="Mute detection. This bit is read only. This flag is set if consecutive 0 values are received in each slot of a given audio frame and for a consecutive number of audio frames (set in the MUTECNT bit in the SAI_xCR2 register). It can generate an interrupt if MUTEDETIE bit is set in SAI_xIM register. This flag is cleared when the software sets bit CMUTEDET in the SAI_xCLRFR register." start="1" size="1" />
+      <BitField name="WCKCFG" description="Wrong clock configuration flag. This bit is read only. This bit is used only when the audio block operates in master mode (MODE[1] = 0) and NODIV = 0. It can generate an interrupt if WCKCFGIE bit is set in SAI_xIM register. This flag is cleared when the software sets CWCKCFG bit in SAI_xCLRFR register." start="2" size="1" />
+      <BitField name="FREQ" description="FIFO request. This bit is read only. The request depends on the audio block configuration: If the block is configured in transmission mode, the FIFO request is related to a write request operation in the SAI_xDR. If the block configured in reception, the FIFO request related to a read request operation from the SAI_xDR. This flag can generate an interrupt if FREQIE bit is set in SAI_xIM register." start="3" size="1" />
+      <BitField name="CNRDY" description="Codec not ready. This bit is read only. This bit is used only when the AC97 audio protocol is selected in the SAI_xCR1 register and configured in receiver mode. It can generate an interrupt if CNRDYIE bit is set in SAI_xIM register. This flag is cleared when the software sets CCNRDY bit in SAI_xCLRFR register." start="4" size="1" />
+      <BitField name="AFSDET" description="Anticipated frame synchronization detection. This bit is read only. This flag can be set only if the audio block is configured in slave mode. It is not used in AC97or SPDIF mode. It can generate an interrupt if AFSDETIE bit is set in SAI_xIM register. This flag is cleared when the software sets CAFSDET bit in SAI_xCLRFR register." start="5" size="1" />
+      <BitField name="LFSDET" description="Late frame synchronization detection. This bit is read only. This flag can be set only if the audio block is configured in slave mode. It is not used in AC97 or SPDIF mode. It can generate an interrupt if LFSDETIE bit is set in the SAI_xIM register. This flag is cleared when the software sets bit CLFSDET in SAI_xCLRFR register" start="6" size="1" />
+      <BitField name="FLVL" description="FIFO level threshold. This bit is read only. The FIFO level threshold flag is managed only by hardware and its setting depends on SAI block configuration (transmitter or receiver mode). If the SAI block is configured as transmitter: If SAI block is configured as receiver:" start="16" size="3" />
+    </Register>
+    <Register name="SAI_BCLRFR" description="Clear flag register" start="+0x3C" size="4" access="WriteOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="COVRUDR" description="Clear overrun / underrun. This bit is write only. Programming this bit to 1 clears the OVRUDR flag in the SAI_xSR register. Reading this bit always returns the value 0." start="0" size="1" />
+      <BitField name="CMUTEDET" description="Mute detection flag. This bit is write only. Programming this bit to 1 clears the MUTEDET flag in the SAI_xSR register. Reading this bit always returns the value 0." start="1" size="1" />
+      <BitField name="CWCKCFG" description="Clear wrong clock configuration flag. This bit is write only. Programming this bit to 1 clears the WCKCFG flag in the SAI_xSR register. This bit is used only when the audio block is set as master (MODE[1] = 0) and NODIV = 0 in the SAI_xCR1 register. Reading this bit always returns the value 0." start="2" size="1" />
+      <BitField name="CCNRDY" description="Clear Codec not ready flag. This bit is write only. Programming this bit to 1 clears the CNRDY flag in the SAI_xSR register. This bit is used only when the AC97 audio protocol is selected in the SAI_xCR1 register. Reading this bit always returns the value 0." start="4" size="1" />
+      <BitField name="CAFSDET" description="Clear anticipated frame synchronization detection flag. This bit is write only. Programming this bit to 1 clears the AFSDET flag in the SAI_xSR register. It is not used in AC97or SPDIF mode. Reading this bit always returns the value 0." start="5" size="1" />
+      <BitField name="CLFSDET" description="Clear late frame synchronization detection flag. This bit is write only. Programming this bit to 1 clears the LFSDET flag in the SAI_xSR register. This bit is not used in AC97or SPDIF mode Reading this bit always returns the value 0." start="6" size="1" />
+    </Register>
+    <Register name="SAI_BDR" description="Data register" start="+0x40" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DATA" description="Data A write to this register loads the FIFO provided the FIFO is not full. A read from this register empties the FIFO if the FIFO is not empty." start="0" size="32" />
+    </Register>
+    <Register name="SAI_PDMCR" description="PDM control register" start="+0x44" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PDMEN" description="PDM enable" start="0" size="1" />
+      <BitField name="MICNBR" description="Number of microphones" start="4" size="2" />
+      <BitField name="CKEN1" description="Clock enable of bitstream clock number 1" start="8" size="1" />
+      <BitField name="CKEN2" description="Clock enable of bitstream clock number 2" start="9" size="1" />
+      <BitField name="CKEN3" description="Clock enable of bitstream clock number 3" start="10" size="1" />
+      <BitField name="CKEN4" description="Clock enable of bitstream clock number 4" start="11" size="1" />
+    </Register>
+    <Register name="SAI_PDMDLY" description="PDM delay register" start="+0x48" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DLYM1L" description="Delay line adjust for first microphone of pair 1" start="0" size="3" />
+      <BitField name="DLYM1R" description="Delay line adjust for second microphone of pair 1" start="4" size="3" />
+      <BitField name="DLYM2L" description="Delay line for first microphone of pair 2" start="8" size="3" />
+      <BitField name="DLYM2R" description="Delay line for second microphone of pair 2" start="12" size="3" />
+      <BitField name="DLYM3L" description="Delay line for first microphone of pair 3" start="16" size="3" />
+      <BitField name="DLYM3R" description="Delay line for second microphone of pair 3" start="20" size="3" />
+      <BitField name="DLYM4L" description="Delay line for first microphone of pair 4" start="24" size="3" />
+      <BitField name="DLYM4R" description="Delay line for second microphone of pair 4" start="28" size="3" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="SAI4" description="SAI" start="0x58005400">
+    <Register name="SAI_GCR" description="Global configuration register" start="+0x0" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SYNCOUT" description="Synchronization outputs These bits are set and cleared by software." start="4" size="2" />
+      <BitField name="SYNCIN" description="Synchronization inputs" start="0" size="2" />
+    </Register>
+    <Register name="SAI_ACR1" description="Configuration register 1" start="+0x4" size="4" access="Read/Write" reset_value="0x00000040" reset_mask="0xFFFFFFFF">
+      <BitField name="MODE" description="SAIx audio block mode immediately" start="0" size="2" />
+      <BitField name="PRTCFG" description="Protocol configuration. These bits are set and cleared by software. These bits have to be configured when the audio block is disabled." start="2" size="2" />
+      <BitField name="DS" description="Data size. These bits are set and cleared by software. These bits are ignored when the SPDIF protocols are selected (bit PRTCFG[1:0]), because the frame and the data size are fixed in such case. When the companding mode is selected through COMP[1:0] bits, DS[1:0] are ignored since the data size is fixed to 8 bits by the algorithm. These bits must be configured when the audio block is disabled." start="5" size="3" />
+      <BitField name="LSBFIRST" description="Least significant bit first. This bit is set and cleared by software. It must be configured when the audio block is disabled. This bit has no meaning in AC97 audio protocol since AC97 data are always transferred with the MSB first. This bit has no meaning in SPDIF audio protocol since in SPDIF data are always transferred with LSB first." start="8" size="1" />
+      <BitField name="CKSTR" description="Clock strobing edge. This bit is set and cleared by software. It must be configured when the audio block is disabled. This bit has no meaning in SPDIF audio protocol." start="9" size="1" />
+      <BitField name="SYNCEN" description="Synchronization enable. These bits are set and cleared by software. They must be configured when the audio sub-block is disabled. Note: The audio sub-block should be configured as asynchronous when SPDIF mode is enabled." start="10" size="2" />
+      <BitField name="MONO" description="Mono mode. This bit is set and cleared by software. It is meaningful only when the number of slots is equal to 2. When the mono mode is selected, slot 0 data are duplicated on slot 1 when the audio block operates as a transmitter. In reception mode, the slot1 is discarded and only the data received from slot 0 are stored. Refer to Section: Mono/stereo mode for more details." start="12" size="1" />
+      <BitField name="OUTDRIV" description="Output drive. This bit is set and cleared by software. Note: This bit has to be set before enabling the audio block and after the audio block configuration." start="13" size="1" />
+      <BitField name="SAIXEN" description="Audio block enable where x is A or B. This bit is set by software. To switch off the audio block, the application software must program this bit to 0 and poll the bit till it reads back 0, meaning that the block is completely disabled. Before setting this bit to 1, check that it is set to 0, otherwise the enable command will not be taken into account. This bit allows to control the state of SAIx audio block. If it is disabled when an audio frame transfer is ongoing, the ongoing transfer completes and the cell is fully disabled at the end of this audio frame transfer. Note: When SAIx block is configured in master mode, the clock must be present on the input of SAIx before setting SAIXEN bit." start="16" size="1" />
+      <BitField name="DMAEN" description="DMA enable. This bit is set and cleared by software. Note: Since the audio block defaults to operate as a transmitter after reset, the MODE[1:0] bits must be configured before setting DMAEN to avoid a DMA request in receiver mode." start="17" size="1" />
+      <BitField name="NOMCK" description="No divider" start="19" size="1" />
+      <BitField name="MCKDIV" description="Master clock divider. These bits are set and cleared by software. These bits are meaningless when the audio block operates in slave mode. They have to be configured when the audio block is disabled. Others: the master clock frequency is calculated accordingly to the following formula:" start="20" size="4" />
+      <BitField name="OSR" description="Oversampling ratio for master clock" start="26" size="1" />
+    </Register>
+    <Register name="SAI_ACR2" description="Configuration register 2" start="+0x8" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FTH" description="FIFO threshold. This bit is set and cleared by software." start="0" size="3" access="Read/Write" />
+      <BitField name="FFLUSH" description="FIFO flush. This bit is set by software. It is always read as 0. This bit should be configured when the SAI is disabled." start="3" size="1" access="WriteOnly" />
+      <BitField name="TRIS" description="Tristate management on data line. This bit is set and cleared by software. It is meaningful only if the audio block is configured as a transmitter. This bit is not used when the audio block is configured in SPDIF mode. It should be configured when SAI is disabled. Refer to Section: Output data line management on an inactive slot for more details." start="4" size="1" access="Read/Write" />
+      <BitField name="MUTE" description="Mute. This bit is set and cleared by software. It is meaningful only when the audio block operates as a transmitter. The MUTE value is linked to value of MUTEVAL if the number of slots is lower or equal to 2, or equal to 0 if it is greater than 2. Refer to Section: Mute mode for more details. Note: This bit is meaningless and should not be used for SPDIF audio blocks." start="5" size="1" access="Read/Write" />
+      <BitField name="MUTEVAL" description="Mute value. This bit is set and cleared by software.It must be written before enabling the audio block: SAIXEN. This bit is meaningful only when the audio block operates as a transmitter, the number of slots is lower or equal to 2 and the MUTE bit is set. If more slots are declared, the bit value sent during the transmission in mute mode is equal to 0, whatever the value of MUTEVAL. if the number of slot is lower or equal to 2 and MUTEVAL = 1, the MUTE value transmitted for each slot is the one sent during the previous frame. Refer to Section: Mute mode for more details. Note: This bit is meaningless and should not be used for SPDIF audio blocks." start="6" size="1" access="Read/Write" />
+      <BitField name="MUTECNT" description="Mute counter. These bits are set and cleared by software. They are used only in reception mode. The value set in these bits is compared to the number of consecutive mute frames detected in reception. When the number of mute frames is equal to this value, the flag MUTEDET will be set and an interrupt will be generated if bit MUTEDETIE is set. Refer to Section: Mute mode for more details." start="7" size="6" access="Read/Write" />
+      <BitField name="CPL" description="Complement bit. This bit is set and cleared by software. It defines the type of complement to be used for companding mode Note: This bit has effect only when the companding mode is -Law algorithm or A-Law algorithm." start="13" size="1" access="Read/Write" />
+      <BitField name="COMP" description="Companding mode. These bits are set and cleared by software. The -Law and the A-Law log are a part of the CCITT G.711 recommendation, the type of complement that will be used depends on CPL bit. The data expansion or data compression are determined by the state of bit MODE[0]. The data compression is applied if the audio block is configured as a transmitter. The data expansion is automatically applied when the audio block is configured as a receiver. Refer to Section: Companding mode for more details. Note: Companding mode is applicable only when TDM is selected." start="14" size="2" access="Read/Write" />
+    </Register>
+    <Register name="SAI_AFRCR" description="This register has no meaning in AC97 and SPDIF audio protocol" start="+0xC" size="4" reset_value="0x00000007" reset_mask="0xFFFFFFFF">
+      <BitField name="FRL" description="Frame length. These bits are set and cleared by software. They define the audio frame length expressed in number of SCK clock cycles: the number of bits in the frame is equal to FRL[7:0] + 1. The minimum number of bits to transfer in an audio frame must be equal to 8, otherwise the audio block will behaves in an unexpected way. This is the case when the data size is 8 bits and only one slot 0 is defined in NBSLOT[4:0] of SAI_xSLOTR register (NBSLOT[3:0] = 0000). In master mode, if the master clock (available on MCLK_x pin) is used, the frame length should be aligned with a number equal to a power of 2, ranging from 8 to 256. When the master clock is not used (NODIV = 1), it is recommended to program the frame length to an value ranging from 8 to 256. These bits are meaningless and are not used in AC97 or SPDIF audio block configuration." start="0" size="8" access="Read/Write" />
+      <BitField name="FSALL" description="Frame synchronization active level length. These bits are set and cleared by software. They specify the length in number of bit clock (SCK) + 1 (FSALL[6:0] + 1) of the active level of the FS signal in the audio frame These bits are meaningless and are not used in AC97 or SPDIF audio block configuration. They must be configured when the audio block is disabled." start="8" size="7" access="Read/Write" />
+      <BitField name="FSDEF" description="Frame synchronization definition. This bit is set and cleared by software. When the bit is set, the number of slots defined in the SAI_xSLOTR register has to be even. It means that half of this number of slots will be dedicated to the left channel and the other slots for the right channel (e.g: this bit has to be set for I2S or MSB/LSB-justified protocols...). This bit is meaningless and is not used in AC97 or SPDIF audio block configuration. It must be configured when the audio block is disabled." start="16" size="1" access="ReadOnly" />
+      <BitField name="FSPOL" description="Frame synchronization polarity. This bit is set and cleared by software. It is used to configure the level of the start of frame on the FS signal. It is meaningless and is not used in AC97 or SPDIF audio block configuration. This bit must be configured when the audio block is disabled." start="17" size="1" access="Read/Write" />
+      <BitField name="FSOFF" description="Frame synchronization offset. This bit is set and cleared by software. It is meaningless and is not used in AC97 or SPDIF audio block configuration. This bit must be configured when the audio block is disabled." start="18" size="1" access="Read/Write" />
+    </Register>
+    <Register name="SAI_ASLOTR" description="This register has no meaning in AC97 and SPDIF audio protocol" start="+0x10" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FBOFF" description="First bit offset These bits are set and cleared by software. The value set in this bitfield defines the position of the first data transfer bit in the slot. It represents an offset value. In transmission mode, the bits outside the data field are forced to 0. In reception mode, the extra received bits are discarded. These bits must be set when the audio block is disabled. They are ignored in AC97 or SPDIF mode." start="0" size="5" />
+      <BitField name="SLOTSZ" description="Slot size This bits is set and cleared by software. The slot size must be higher or equal to the data size. If this condition is not respected, the behavior of the SAI will be undetermined. Refer to Section: Output data line management on an inactive slot for information on how to drive SD line. These bits must be set when the audio block is disabled. They are ignored in AC97 or SPDIF mode." start="6" size="2" />
+      <BitField name="NBSLOT" description="Number of slots in an audio frame. These bits are set and cleared by software. The value set in this bitfield represents the number of slots + 1 in the audio frame (including the number of inactive slots). The maximum number of slots is 16. The number of slots should be even if FSDEF bit in the SAI_xFRCR register is set. The number of slots must be configured when the audio block is disabled. They are ignored in AC97 or SPDIF mode." start="8" size="4" />
+      <BitField name="SLOTEN" description="Slot enable. These bits are set and cleared by software. Each SLOTEN bit corresponds to a slot position from 0 to 15 (maximum 16 slots). The slot must be enabled when the audio block is disabled. They are ignored in AC97 or SPDIF mode." start="16" size="16" />
+    </Register>
+    <Register name="SAI_AIM" description="Interrupt mask register 2" start="+0x14" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OVRUDRIE" description="Overrun/underrun interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt is generated if the OVRUDR bit in the SAI_xSR register is set." start="0" size="1" />
+      <BitField name="MUTEDETIE" description="Mute detection interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt is generated if the MUTEDET bit in the SAI_xSR register is set. This bit has a meaning only if the audio block is configured in receiver mode." start="1" size="1" />
+      <BitField name="WCKCFGIE" description="Wrong clock configuration interrupt enable. This bit is set and cleared by software. This bit is taken into account only if the audio block is configured as a master (MODE[1] = 0) and NODIV = 0. It generates an interrupt if the WCKCFG flag in the SAI_xSR register is set. Note: This bit is used only in TDM mode and is meaningless in other modes." start="2" size="1" />
+      <BitField name="FREQIE" description="FIFO request interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt is generated if the FREQ bit in the SAI_xSR register is set. Since the audio block defaults to operate as a transmitter after reset, the MODE bit must be configured before setting FREQIE to avoid a parasitic interruption in receiver mode," start="3" size="1" />
+      <BitField name="CNRDYIE" description="Codec not ready interrupt enable (AC97). This bit is set and cleared by software. When the interrupt is enabled, the audio block detects in the slot 0 (tag0) of the AC97 frame if the Codec connected to this line is ready or not. If it is not ready, the CNRDY flag in the SAI_xSR register is set and an interruption i generated. This bit has a meaning only if the AC97 mode is selected through PRTCFG[1:0] bits and the audio block is operates as a receiver." start="4" size="1" />
+      <BitField name="AFSDETIE" description="Anticipated frame synchronization detection interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt will be generated if the AFSDET bit in the SAI_xSR register is set. This bit is meaningless in AC97, SPDIF mode or when the audio block operates as a master." start="5" size="1" />
+      <BitField name="LFSDETIE" description="Late frame synchronization detection interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt will be generated if the LFSDET bit is set in the SAI_xSR register. This bit is meaningless in AC97, SPDIF mode or when the audio block operates as a master." start="6" size="1" />
+    </Register>
+    <Register name="SAI_ASR" description="Status register" start="+0x18" size="4" access="ReadOnly" reset_value="0x00000008" reset_mask="0xFFFFFFFF">
+      <BitField name="OVRUDR" description="Overrun / underrun. This bit is read only. The overrun and underrun conditions can occur only when the audio block is configured as a receiver and a transmitter, respectively. It can generate an interrupt if OVRUDRIE bit is set in SAI_xIM register. This flag is cleared when the software sets COVRUDR bit in SAI_xCLRFR register." start="0" size="1" />
+      <BitField name="MUTEDET" description="Mute detection. This bit is read only. This flag is set if consecutive 0 values are received in each slot of a given audio frame and for a consecutive number of audio frames (set in the MUTECNT bit in the SAI_xCR2 register). It can generate an interrupt if MUTEDETIE bit is set in SAI_xIM register. This flag is cleared when the software sets bit CMUTEDET in the SAI_xCLRFR register." start="1" size="1" />
+      <BitField name="WCKCFG" description="Wrong clock configuration flag. This bit is read only. This bit is used only when the audio block operates in master mode (MODE[1] = 0) and NODIV = 0. It can generate an interrupt if WCKCFGIE bit is set in SAI_xIM register. This flag is cleared when the software sets CWCKCFG bit in SAI_xCLRFR register." start="2" size="1" />
+      <BitField name="FREQ" description="FIFO request. This bit is read only. The request depends on the audio block configuration: If the block is configured in transmission mode, the FIFO request is related to a write request operation in the SAI_xDR. If the block configured in reception, the FIFO request related to a read request operation from the SAI_xDR. This flag can generate an interrupt if FREQIE bit is set in SAI_xIM register." start="3" size="1" />
+      <BitField name="CNRDY" description="Codec not ready. This bit is read only. This bit is used only when the AC97 audio protocol is selected in the SAI_xCR1 register and configured in receiver mode. It can generate an interrupt if CNRDYIE bit is set in SAI_xIM register. This flag is cleared when the software sets CCNRDY bit in SAI_xCLRFR register." start="4" size="1" />
+      <BitField name="AFSDET" description="Anticipated frame synchronization detection. This bit is read only. This flag can be set only if the audio block is configured in slave mode. It is not used in AC97or SPDIF mode. It can generate an interrupt if AFSDETIE bit is set in SAI_xIM register. This flag is cleared when the software sets CAFSDET bit in SAI_xCLRFR register." start="5" size="1" />
+      <BitField name="LFSDET" description="Late frame synchronization detection. This bit is read only. This flag can be set only if the audio block is configured in slave mode. It is not used in AC97 or SPDIF mode. It can generate an interrupt if LFSDETIE bit is set in the SAI_xIM register. This flag is cleared when the software sets bit CLFSDET in SAI_xCLRFR register" start="6" size="1" />
+      <BitField name="FLVL" description="FIFO level threshold. This bit is read only. The FIFO level threshold flag is managed only by hardware and its setting depends on SAI block configuration (transmitter or receiver mode). If the SAI block is configured as transmitter: If SAI block is configured as receiver:" start="16" size="3" />
+    </Register>
+    <Register name="SAI_ACLRFR" description="Clear flag register" start="+0x1C" size="4" access="WriteOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="COVRUDR" description="Clear overrun / underrun. This bit is write only. Programming this bit to 1 clears the OVRUDR flag in the SAI_xSR register. Reading this bit always returns the value 0." start="0" size="1" />
+      <BitField name="CMUTEDET" description="Mute detection flag. This bit is write only. Programming this bit to 1 clears the MUTEDET flag in the SAI_xSR register. Reading this bit always returns the value 0." start="1" size="1" />
+      <BitField name="CWCKCFG" description="Clear wrong clock configuration flag. This bit is write only. Programming this bit to 1 clears the WCKCFG flag in the SAI_xSR register. This bit is used only when the audio block is set as master (MODE[1] = 0) and NODIV = 0 in the SAI_xCR1 register. Reading this bit always returns the value 0." start="2" size="1" />
+      <BitField name="CCNRDY" description="Clear Codec not ready flag. This bit is write only. Programming this bit to 1 clears the CNRDY flag in the SAI_xSR register. This bit is used only when the AC97 audio protocol is selected in the SAI_xCR1 register. Reading this bit always returns the value 0." start="4" size="1" />
+      <BitField name="CAFSDET" description="Clear anticipated frame synchronization detection flag. This bit is write only. Programming this bit to 1 clears the AFSDET flag in the SAI_xSR register. It is not used in AC97or SPDIF mode. Reading this bit always returns the value 0." start="5" size="1" />
+      <BitField name="CLFSDET" description="Clear late frame synchronization detection flag. This bit is write only. Programming this bit to 1 clears the LFSDET flag in the SAI_xSR register. This bit is not used in AC97or SPDIF mode Reading this bit always returns the value 0." start="6" size="1" />
+    </Register>
+    <Register name="SAI_ADR" description="Data register" start="+0x20" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DATA" description="Data A write to this register loads the FIFO provided the FIFO is not full. A read from this register empties the FIFO if the FIFO is not empty." start="0" size="32" />
+    </Register>
+    <Register name="SAI_BCR1" description="Configuration register 1" start="+0x24" size="4" access="Read/Write" reset_value="0x00000040" reset_mask="0xFFFFFFFF">
+      <BitField name="MODE" description="SAIx audio block mode immediately" start="0" size="2" />
+      <BitField name="PRTCFG" description="Protocol configuration. These bits are set and cleared by software. These bits have to be configured when the audio block is disabled." start="2" size="2" />
+      <BitField name="DS" description="Data size. These bits are set and cleared by software. These bits are ignored when the SPDIF protocols are selected (bit PRTCFG[1:0]), because the frame and the data size are fixed in such case. When the companding mode is selected through COMP[1:0] bits, DS[1:0] are ignored since the data size is fixed to 8 bits by the algorithm. These bits must be configured when the audio block is disabled." start="5" size="3" />
+      <BitField name="LSBFIRST" description="Least significant bit first. This bit is set and cleared by software. It must be configured when the audio block is disabled. This bit has no meaning in AC97 audio protocol since AC97 data are always transferred with the MSB first. This bit has no meaning in SPDIF audio protocol since in SPDIF data are always transferred with LSB first." start="8" size="1" />
+      <BitField name="CKSTR" description="Clock strobing edge. This bit is set and cleared by software. It must be configured when the audio block is disabled. This bit has no meaning in SPDIF audio protocol." start="9" size="1" />
+      <BitField name="SYNCEN" description="Synchronization enable. These bits are set and cleared by software. They must be configured when the audio sub-block is disabled. Note: The audio sub-block should be configured as asynchronous when SPDIF mode is enabled." start="10" size="2" />
+      <BitField name="MONO" description="Mono mode. This bit is set and cleared by software. It is meaningful only when the number of slots is equal to 2. When the mono mode is selected, slot 0 data are duplicated on slot 1 when the audio block operates as a transmitter. In reception mode, the slot1 is discarded and only the data received from slot 0 are stored. Refer to Section: Mono/stereo mode for more details." start="12" size="1" />
+      <BitField name="OUTDRIV" description="Output drive. This bit is set and cleared by software. Note: This bit has to be set before enabling the audio block and after the audio block configuration." start="13" size="1" />
+      <BitField name="SAIXEN" description="Audio block enable where x is A or B. This bit is set by software. To switch off the audio block, the application software must program this bit to 0 and poll the bit till it reads back 0, meaning that the block is completely disabled. Before setting this bit to 1, check that it is set to 0, otherwise the enable command will not be taken into account. This bit allows to control the state of SAIx audio block. If it is disabled when an audio frame transfer is ongoing, the ongoing transfer completes and the cell is fully disabled at the end of this audio frame transfer. Note: When SAIx block is configured in master mode, the clock must be present on the input of SAIx before setting SAIXEN bit." start="16" size="1" />
+      <BitField name="DMAEN" description="DMA enable. This bit is set and cleared by software. Note: Since the audio block defaults to operate as a transmitter after reset, the MODE[1:0] bits must be configured before setting DMAEN to avoid a DMA request in receiver mode." start="17" size="1" />
+      <BitField name="NOMCK" description="No divider" start="19" size="1" />
+      <BitField name="MCKDIV" description="Master clock divider. These bits are set and cleared by software. These bits are meaningless when the audio block operates in slave mode. They have to be configured when the audio block is disabled. Others: the master clock frequency is calculated accordingly to the following formula:" start="20" size="4" />
+      <BitField name="OSR" description="Oversampling ratio for master clock" start="26" size="1" />
+    </Register>
+    <Register name="SAI_BCR2" description="Configuration register 2" start="+0x28" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FTH" description="FIFO threshold. This bit is set and cleared by software." start="0" size="3" access="Read/Write" />
+      <BitField name="FFLUSH" description="FIFO flush. This bit is set by software. It is always read as 0. This bit should be configured when the SAI is disabled." start="3" size="1" access="WriteOnly" />
+      <BitField name="TRIS" description="Tristate management on data line. This bit is set and cleared by software. It is meaningful only if the audio block is configured as a transmitter. This bit is not used when the audio block is configured in SPDIF mode. It should be configured when SAI is disabled. Refer to Section: Output data line management on an inactive slot for more details." start="4" size="1" access="Read/Write" />
+      <BitField name="MUTE" description="Mute. This bit is set and cleared by software. It is meaningful only when the audio block operates as a transmitter. The MUTE value is linked to value of MUTEVAL if the number of slots is lower or equal to 2, or equal to 0 if it is greater than 2. Refer to Section: Mute mode for more details. Note: This bit is meaningless and should not be used for SPDIF audio blocks." start="5" size="1" access="Read/Write" />
+      <BitField name="MUTEVAL" description="Mute value. This bit is set and cleared by software.It must be written before enabling the audio block: SAIXEN. This bit is meaningful only when the audio block operates as a transmitter, the number of slots is lower or equal to 2 and the MUTE bit is set. If more slots are declared, the bit value sent during the transmission in mute mode is equal to 0, whatever the value of MUTEVAL. if the number of slot is lower or equal to 2 and MUTEVAL = 1, the MUTE value transmitted for each slot is the one sent during the previous frame. Refer to Section: Mute mode for more details. Note: This bit is meaningless and should not be used for SPDIF audio blocks." start="6" size="1" access="Read/Write" />
+      <BitField name="MUTECNT" description="Mute counter. These bits are set and cleared by software. They are used only in reception mode. The value set in these bits is compared to the number of consecutive mute frames detected in reception. When the number of mute frames is equal to this value, the flag MUTEDET will be set and an interrupt will be generated if bit MUTEDETIE is set. Refer to Section: Mute mode for more details." start="7" size="6" access="Read/Write" />
+      <BitField name="CPL" description="Complement bit. This bit is set and cleared by software. It defines the type of complement to be used for companding mode Note: This bit has effect only when the companding mode is -Law algorithm or A-Law algorithm." start="13" size="1" access="Read/Write" />
+      <BitField name="COMP" description="Companding mode. These bits are set and cleared by software. The -Law and the A-Law log are a part of the CCITT G.711 recommendation, the type of complement that will be used depends on CPL bit. The data expansion or data compression are determined by the state of bit MODE[0]. The data compression is applied if the audio block is configured as a transmitter. The data expansion is automatically applied when the audio block is configured as a receiver. Refer to Section: Companding mode for more details. Note: Companding mode is applicable only when TDM is selected." start="14" size="2" access="Read/Write" />
+    </Register>
+    <Register name="SAI_BFRCR" description="This register has no meaning in AC97 and SPDIF audio protocol" start="+0x2C" size="4" reset_value="0x00000007" reset_mask="0xFFFFFFFF">
+      <BitField name="FRL" description="Frame length. These bits are set and cleared by software. They define the audio frame length expressed in number of SCK clock cycles: the number of bits in the frame is equal to FRL[7:0] + 1. The minimum number of bits to transfer in an audio frame must be equal to 8, otherwise the audio block will behaves in an unexpected way. This is the case when the data size is 8 bits and only one slot 0 is defined in NBSLOT[4:0] of SAI_xSLOTR register (NBSLOT[3:0] = 0000). In master mode, if the master clock (available on MCLK_x pin) is used, the frame length should be aligned with a number equal to a power of 2, ranging from 8 to 256. When the master clock is not used (NODIV = 1), it is recommended to program the frame length to an value ranging from 8 to 256. These bits are meaningless and are not used in AC97 or SPDIF audio block configuration." start="0" size="8" access="Read/Write" />
+      <BitField name="FSALL" description="Frame synchronization active level length. These bits are set and cleared by software. They specify the length in number of bit clock (SCK) + 1 (FSALL[6:0] + 1) of the active level of the FS signal in the audio frame These bits are meaningless and are not used in AC97 or SPDIF audio block configuration. They must be configured when the audio block is disabled." start="8" size="7" access="Read/Write" />
+      <BitField name="FSDEF" description="Frame synchronization definition. This bit is set and cleared by software. When the bit is set, the number of slots defined in the SAI_xSLOTR register has to be even. It means that half of this number of slots will be dedicated to the left channel and the other slots for the right channel (e.g: this bit has to be set for I2S or MSB/LSB-justified protocols...). This bit is meaningless and is not used in AC97 or SPDIF audio block configuration. It must be configured when the audio block is disabled." start="16" size="1" access="ReadOnly" />
+      <BitField name="FSPOL" description="Frame synchronization polarity. This bit is set and cleared by software. It is used to configure the level of the start of frame on the FS signal. It is meaningless and is not used in AC97 or SPDIF audio block configuration. This bit must be configured when the audio block is disabled." start="17" size="1" access="Read/Write" />
+      <BitField name="FSOFF" description="Frame synchronization offset. This bit is set and cleared by software. It is meaningless and is not used in AC97 or SPDIF audio block configuration. This bit must be configured when the audio block is disabled." start="18" size="1" access="Read/Write" />
+    </Register>
+    <Register name="SAI_BSLOTR" description="This register has no meaning in AC97 and SPDIF audio protocol" start="+0x30" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FBOFF" description="First bit offset These bits are set and cleared by software. The value set in this bitfield defines the position of the first data transfer bit in the slot. It represents an offset value. In transmission mode, the bits outside the data field are forced to 0. In reception mode, the extra received bits are discarded. These bits must be set when the audio block is disabled. They are ignored in AC97 or SPDIF mode." start="0" size="5" />
+      <BitField name="SLOTSZ" description="Slot size This bits is set and cleared by software. The slot size must be higher or equal to the data size. If this condition is not respected, the behavior of the SAI will be undetermined. Refer to Section: Output data line management on an inactive slot for information on how to drive SD line. These bits must be set when the audio block is disabled. They are ignored in AC97 or SPDIF mode." start="6" size="2" />
+      <BitField name="NBSLOT" description="Number of slots in an audio frame. These bits are set and cleared by software. The value set in this bitfield represents the number of slots + 1 in the audio frame (including the number of inactive slots). The maximum number of slots is 16. The number of slots should be even if FSDEF bit in the SAI_xFRCR register is set. The number of slots must be configured when the audio block is disabled. They are ignored in AC97 or SPDIF mode." start="8" size="4" />
+      <BitField name="SLOTEN" description="Slot enable. These bits are set and cleared by software. Each SLOTEN bit corresponds to a slot position from 0 to 15 (maximum 16 slots). The slot must be enabled when the audio block is disabled. They are ignored in AC97 or SPDIF mode." start="16" size="16" />
+    </Register>
+    <Register name="SAI_BIM" description="Interrupt mask register 2" start="+0x34" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OVRUDRIE" description="Overrun/underrun interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt is generated if the OVRUDR bit in the SAI_xSR register is set." start="0" size="1" />
+      <BitField name="MUTEDETIE" description="Mute detection interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt is generated if the MUTEDET bit in the SAI_xSR register is set. This bit has a meaning only if the audio block is configured in receiver mode." start="1" size="1" />
+      <BitField name="WCKCFGIE" description="Wrong clock configuration interrupt enable. This bit is set and cleared by software. This bit is taken into account only if the audio block is configured as a master (MODE[1] = 0) and NODIV = 0. It generates an interrupt if the WCKCFG flag in the SAI_xSR register is set. Note: This bit is used only in TDM mode and is meaningless in other modes." start="2" size="1" />
+      <BitField name="FREQIE" description="FIFO request interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt is generated if the FREQ bit in the SAI_xSR register is set. Since the audio block defaults to operate as a transmitter after reset, the MODE bit must be configured before setting FREQIE to avoid a parasitic interruption in receiver mode," start="3" size="1" />
+      <BitField name="CNRDYIE" description="Codec not ready interrupt enable (AC97). This bit is set and cleared by software. When the interrupt is enabled, the audio block detects in the slot 0 (tag0) of the AC97 frame if the Codec connected to this line is ready or not. If it is not ready, the CNRDY flag in the SAI_xSR register is set and an interruption i generated. This bit has a meaning only if the AC97 mode is selected through PRTCFG[1:0] bits and the audio block is operates as a receiver." start="4" size="1" />
+      <BitField name="AFSDETIE" description="Anticipated frame synchronization detection interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt will be generated if the AFSDET bit in the SAI_xSR register is set. This bit is meaningless in AC97, SPDIF mode or when the audio block operates as a master." start="5" size="1" />
+      <BitField name="LFSDETIE" description="Late frame synchronization detection interrupt enable. This bit is set and cleared by software. When this bit is set, an interrupt will be generated if the LFSDET bit is set in the SAI_xSR register. This bit is meaningless in AC97, SPDIF mode or when the audio block operates as a master." start="6" size="1" />
+    </Register>
+    <Register name="SAI_BSR" description="Status register" start="+0x38" size="4" access="ReadOnly" reset_value="0x00000008" reset_mask="0xFFFFFFFF">
+      <BitField name="OVRUDR" description="Overrun / underrun. This bit is read only. The overrun and underrun conditions can occur only when the audio block is configured as a receiver and a transmitter, respectively. It can generate an interrupt if OVRUDRIE bit is set in SAI_xIM register. This flag is cleared when the software sets COVRUDR bit in SAI_xCLRFR register." start="0" size="1" />
+      <BitField name="MUTEDET" description="Mute detection. This bit is read only. This flag is set if consecutive 0 values are received in each slot of a given audio frame and for a consecutive number of audio frames (set in the MUTECNT bit in the SAI_xCR2 register). It can generate an interrupt if MUTEDETIE bit is set in SAI_xIM register. This flag is cleared when the software sets bit CMUTEDET in the SAI_xCLRFR register." start="1" size="1" />
+      <BitField name="WCKCFG" description="Wrong clock configuration flag. This bit is read only. This bit is used only when the audio block operates in master mode (MODE[1] = 0) and NODIV = 0. It can generate an interrupt if WCKCFGIE bit is set in SAI_xIM register. This flag is cleared when the software sets CWCKCFG bit in SAI_xCLRFR register." start="2" size="1" />
+      <BitField name="FREQ" description="FIFO request. This bit is read only. The request depends on the audio block configuration: If the block is configured in transmission mode, the FIFO request is related to a write request operation in the SAI_xDR. If the block configured in reception, the FIFO request related to a read request operation from the SAI_xDR. This flag can generate an interrupt if FREQIE bit is set in SAI_xIM register." start="3" size="1" />
+      <BitField name="CNRDY" description="Codec not ready. This bit is read only. This bit is used only when the AC97 audio protocol is selected in the SAI_xCR1 register and configured in receiver mode. It can generate an interrupt if CNRDYIE bit is set in SAI_xIM register. This flag is cleared when the software sets CCNRDY bit in SAI_xCLRFR register." start="4" size="1" />
+      <BitField name="AFSDET" description="Anticipated frame synchronization detection. This bit is read only. This flag can be set only if the audio block is configured in slave mode. It is not used in AC97or SPDIF mode. It can generate an interrupt if AFSDETIE bit is set in SAI_xIM register. This flag is cleared when the software sets CAFSDET bit in SAI_xCLRFR register." start="5" size="1" />
+      <BitField name="LFSDET" description="Late frame synchronization detection. This bit is read only. This flag can be set only if the audio block is configured in slave mode. It is not used in AC97 or SPDIF mode. It can generate an interrupt if LFSDETIE bit is set in the SAI_xIM register. This flag is cleared when the software sets bit CLFSDET in SAI_xCLRFR register" start="6" size="1" />
+      <BitField name="FLVL" description="FIFO level threshold. This bit is read only. The FIFO level threshold flag is managed only by hardware and its setting depends on SAI block configuration (transmitter or receiver mode). If the SAI block is configured as transmitter: If SAI block is configured as receiver:" start="16" size="3" />
+    </Register>
+    <Register name="SAI_BCLRFR" description="Clear flag register" start="+0x3C" size="4" access="WriteOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="COVRUDR" description="Clear overrun / underrun. This bit is write only. Programming this bit to 1 clears the OVRUDR flag in the SAI_xSR register. Reading this bit always returns the value 0." start="0" size="1" />
+      <BitField name="CMUTEDET" description="Mute detection flag. This bit is write only. Programming this bit to 1 clears the MUTEDET flag in the SAI_xSR register. Reading this bit always returns the value 0." start="1" size="1" />
+      <BitField name="CWCKCFG" description="Clear wrong clock configuration flag. This bit is write only. Programming this bit to 1 clears the WCKCFG flag in the SAI_xSR register. This bit is used only when the audio block is set as master (MODE[1] = 0) and NODIV = 0 in the SAI_xCR1 register. Reading this bit always returns the value 0." start="2" size="1" />
+      <BitField name="CCNRDY" description="Clear Codec not ready flag. This bit is write only. Programming this bit to 1 clears the CNRDY flag in the SAI_xSR register. This bit is used only when the AC97 audio protocol is selected in the SAI_xCR1 register. Reading this bit always returns the value 0." start="4" size="1" />
+      <BitField name="CAFSDET" description="Clear anticipated frame synchronization detection flag. This bit is write only. Programming this bit to 1 clears the AFSDET flag in the SAI_xSR register. It is not used in AC97or SPDIF mode. Reading this bit always returns the value 0." start="5" size="1" />
+      <BitField name="CLFSDET" description="Clear late frame synchronization detection flag. This bit is write only. Programming this bit to 1 clears the LFSDET flag in the SAI_xSR register. This bit is not used in AC97or SPDIF mode Reading this bit always returns the value 0." start="6" size="1" />
+    </Register>
+    <Register name="SAI_BDR" description="Data register" start="+0x40" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DATA" description="Data A write to this register loads the FIFO provided the FIFO is not full. A read from this register empties the FIFO if the FIFO is not empty." start="0" size="32" />
+    </Register>
+    <Register name="SAI_PDMCR" description="PDM control register" start="+0x44" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PDMEN" description="PDM enable" start="0" size="1" />
+      <BitField name="MICNBR" description="Number of microphones" start="4" size="2" />
+      <BitField name="CKEN1" description="Clock enable of bitstream clock number 1" start="8" size="1" />
+      <BitField name="CKEN2" description="Clock enable of bitstream clock number 2" start="9" size="1" />
+      <BitField name="CKEN3" description="Clock enable of bitstream clock number 3" start="10" size="1" />
+      <BitField name="CKEN4" description="Clock enable of bitstream clock number 4" start="11" size="1" />
+    </Register>
+    <Register name="SAI_PDMDLY" description="PDM delay register" start="+0x48" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DLYM1L" description="Delay line adjust for first microphone of pair 1" start="0" size="3" />
+      <BitField name="DLYM1R" description="Delay line adjust for second microphone of pair 1" start="4" size="3" />
+      <BitField name="DLYM2L" description="Delay line for first microphone of pair 2" start="8" size="3" />
+      <BitField name="DLYM2R" description="Delay line for second microphone of pair 2" start="12" size="3" />
+      <BitField name="DLYM3L" description="Delay line for first microphone of pair 3" start="16" size="3" />
+      <BitField name="DLYM3R" description="Delay line for second microphone of pair 3" start="20" size="3" />
+      <BitField name="DLYM4L" description="Delay line for first microphone of pair 4" start="24" size="3" />
+      <BitField name="DLYM4R" description="Delay line for second microphone of pair 4" start="28" size="3" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="SCB" description="System control block" start="0xE000ED00">
+    <Register name="CPUID" description="CPUID base register" start="+0x0" size="4" access="ReadOnly" reset_value="0x410FC241" reset_mask="0xFFFFFFFF">
+      <BitField name="Revision" description="Revision number" start="0" size="4" />
+      <BitField name="PartNo" description="Part number of the processor" start="4" size="12" />
+      <BitField name="Constant" description="Reads as 0xF" start="16" size="4" />
+      <BitField name="Variant" description="Variant number" start="20" size="4" />
+      <BitField name="Implementer" description="Implementer code" start="24" size="8" />
+    </Register>
+    <Register name="ICSR" description="Interrupt control and state register" start="+0x4" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="VECTACTIVE" description="Active vector" start="0" size="9" />
+      <BitField name="RETTOBASE" description="Return to base level" start="11" size="1" />
+      <BitField name="VECTPENDING" description="Pending vector" start="12" size="7" />
+      <BitField name="ISRPENDING" description="Interrupt pending flag" start="22" size="1" />
+      <BitField name="PENDSTCLR" description="SysTick exception clear-pending bit" start="25" size="1" />
+      <BitField name="PENDSTSET" description="SysTick exception set-pending bit" start="26" size="1" />
+      <BitField name="PENDSVCLR" description="PendSV clear-pending bit" start="27" size="1" />
+      <BitField name="PENDSVSET" description="PendSV set-pending bit" start="28" size="1" />
+      <BitField name="NMIPENDSET" description="NMI set-pending bit." start="31" size="1" />
+    </Register>
+    <Register name="VTOR" description="Vector table offset register" start="+0x8" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TBLOFF" description="Vector table base offset field" start="9" size="21" />
+    </Register>
+    <Register name="AIRCR" description="Application interrupt and reset control register" start="+0xC" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="VECTRESET" description="VECTRESET" start="0" size="1" />
+      <BitField name="VECTCLRACTIVE" description="VECTCLRACTIVE" start="1" size="1" />
+      <BitField name="SYSRESETREQ" description="SYSRESETREQ" start="2" size="1" />
+      <BitField name="PRIGROUP" description="PRIGROUP" start="8" size="3" />
+      <BitField name="ENDIANESS" description="ENDIANESS" start="15" size="1" />
+      <BitField name="VECTKEYSTAT" description="Register key" start="16" size="16" />
+    </Register>
+    <Register name="SCR" description="System control register" start="+0x10" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SLEEPONEXIT" description="SLEEPONEXIT" start="1" size="1" />
+      <BitField name="SLEEPDEEP" description="SLEEPDEEP" start="2" size="1" />
+      <BitField name="SEVEONPEND" description="Send Event on Pending bit" start="4" size="1" />
+    </Register>
+    <Register name="CCR" description="Configuration and control register" start="+0x14" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="NONBASETHRDENA" description="Configures how the processor enters Thread mode" start="0" size="1" />
+      <BitField name="USERSETMPEND" description="USERSETMPEND" start="1" size="1" />
+      <BitField name="UNALIGN__TRP" description="UNALIGN_ TRP" start="3" size="1" />
+      <BitField name="DIV_0_TRP" description="DIV_0_TRP" start="4" size="1" />
+      <BitField name="BFHFNMIGN" description="BFHFNMIGN" start="8" size="1" />
+      <BitField name="STKALIGN" description="STKALIGN" start="9" size="1" />
+      <BitField name="DC" description="DC" start="16" size="1" />
+      <BitField name="IC" description="IC" start="17" size="1" />
+      <BitField name="BP" description="BP" start="18" size="1" />
+    </Register>
+    <Register name="SHPR1" description="System handler priority registers" start="+0x18" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PRI_4" description="Priority of system handler 4" start="0" size="8" />
+      <BitField name="PRI_5" description="Priority of system handler 5" start="8" size="8" />
+      <BitField name="PRI_6" description="Priority of system handler 6" start="16" size="8" />
+    </Register>
+    <Register name="SHPR2" description="System handler priority registers" start="+0x1C" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PRI_11" description="Priority of system handler 11" start="24" size="8" />
+    </Register>
+    <Register name="SHPR3" description="System handler priority registers" start="+0x20" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PRI_14" description="Priority of system handler 14" start="16" size="8" />
+      <BitField name="PRI_15" description="Priority of system handler 15" start="24" size="8" />
+    </Register>
+    <Register name="SHCSR" description="System handler control and state register" start="+0x24" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MEMFAULTACT" description="Memory management fault exception active bit" start="0" size="1" />
+      <BitField name="BUSFAULTACT" description="Bus fault exception active bit" start="1" size="1" />
+      <BitField name="USGFAULTACT" description="Usage fault exception active bit" start="3" size="1" />
+      <BitField name="SVCALLACT" description="SVC call active bit" start="7" size="1" />
+      <BitField name="MONITORACT" description="Debug monitor active bit" start="8" size="1" />
+      <BitField name="PENDSVACT" description="PendSV exception active bit" start="10" size="1" />
+      <BitField name="SYSTICKACT" description="SysTick exception active bit" start="11" size="1" />
+      <BitField name="USGFAULTPENDED" description="Usage fault exception pending bit" start="12" size="1" />
+      <BitField name="MEMFAULTPENDED" description="Memory management fault exception pending bit" start="13" size="1" />
+      <BitField name="BUSFAULTPENDED" description="Bus fault exception pending bit" start="14" size="1" />
+      <BitField name="SVCALLPENDED" description="SVC call pending bit" start="15" size="1" />
+      <BitField name="MEMFAULTENA" description="Memory management fault enable bit" start="16" size="1" />
+      <BitField name="BUSFAULTENA" description="Bus fault enable bit" start="17" size="1" />
+      <BitField name="USGFAULTENA" description="Usage fault enable bit" start="18" size="1" />
+    </Register>
+    <Register name="CFSR_UFSR_BFSR_MMFSR" description="Configurable fault status register" start="+0x28" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IACCVIOL" description="IACCVIOL" start="0" size="1" />
+      <BitField name="DACCVIOL" description="DACCVIOL" start="1" size="1" />
+      <BitField name="MUNSTKERR" description="MUNSTKERR" start="3" size="1" />
+      <BitField name="MSTKERR" description="MSTKERR" start="4" size="1" />
+      <BitField name="MLSPERR" description="MLSPERR" start="5" size="1" />
+      <BitField name="MMARVALID" description="MMARVALID" start="7" size="1" />
+      <BitField name="IBUSERR" description="Instruction bus error" start="8" size="1" />
+      <BitField name="PRECISERR" description="Precise data bus error" start="9" size="1" />
+      <BitField name="IMPRECISERR" description="Imprecise data bus error" start="10" size="1" />
+      <BitField name="UNSTKERR" description="Bus fault on unstacking for a return from exception" start="11" size="1" />
+      <BitField name="STKERR" description="Bus fault on stacking for exception entry" start="12" size="1" />
+      <BitField name="LSPERR" description="Bus fault on floating-point lazy state preservation" start="13" size="1" />
+      <BitField name="BFARVALID" description="Bus Fault Address Register (BFAR) valid flag" start="15" size="1" />
+      <BitField name="UNDEFINSTR" description="Undefined instruction usage fault" start="16" size="1" />
+      <BitField name="INVSTATE" description="Invalid state usage fault" start="17" size="1" />
+      <BitField name="INVPC" description="Invalid PC load usage fault" start="18" size="1" />
+      <BitField name="NOCP" description="No coprocessor usage fault." start="19" size="1" />
+      <BitField name="UNALIGNED" description="Unaligned access usage fault" start="24" size="1" />
+      <BitField name="DIVBYZERO" description="Divide by zero usage fault" start="25" size="1" />
+    </Register>
+    <Register name="HFSR" description="Hard fault status register" start="+0x2C" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="VECTTBL" description="Vector table hard fault" start="1" size="1" />
+      <BitField name="FORCED" description="Forced hard fault" start="30" size="1" />
+      <BitField name="DEBUG_VT" description="Reserved for Debug use" start="31" size="1" />
+    </Register>
+    <Register name="MMFAR" description="Memory management fault address register" start="+0x34" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ADDRESS" description="Memory management fault address" start="0" size="32" />
+    </Register>
+    <Register name="BFAR" description="Bus fault address register" start="+0x38" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ADDRESS" description="Bus fault address" start="0" size="32" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="SCB_ACTRL" description="System control block ACTLR" start="0xE000E008">
+    <Register name="ACTRL" description="Auxiliary control register" start="+0x0" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DISFOLD" description="DISFOLD" start="2" size="1" />
+      <BitField name="FPEXCODIS" description="FPEXCODIS" start="10" size="1" />
+      <BitField name="DISRAMODE" description="DISRAMODE" start="11" size="1" />
+      <BitField name="DISITMATBFLUSH" description="DISITMATBFLUSH" start="12" size="1" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="SDMMC1" description="SDMMC1" start="0x52007000">
+    <Register name="SDMMC_POWER" description="SDMMC power control register" start="+0x0" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PWRCTRL" description="SDMMC state control bits. These bits can only be written when the SDMMC is not in the power-on state (PWRCTRL?11). These bits are used to define the functional state of the SDMMC signals: Any further write will be ignored, PWRCTRL value will keep 11." start="0" size="2" />
+      <BitField name="VSWITCH" description="Voltage switch sequence start. This bit is used to start the timing critical section of the voltage switch sequence:" start="2" size="1" />
+      <BitField name="VSWITCHEN" description="Voltage switch procedure enable. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). This bit is used to stop the SDMMC_CK after the voltage switch command response:" start="3" size="1" />
+      <BitField name="DIRPOL" description="Data and command direction signals polarity selection. This bit can only be written when the SDMMC is in the power-off state (PWRCTRL = 00)." start="4" size="1" />
+    </Register>
+    <Register name="SDMMC_CLKCR" description="The SDMMC_CLKCR register controls the SDMMC_CK output clock, the SDMMC_RX_CLK receive clock, and the bus width." start="+0x4" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CLKDIV" description="Clock divide factor This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0). This field defines the divide factor between the input clock (SDMMCCLK) and the output clock (SDMMC_CK): SDMMC_CK frequency = SDMMCCLK / [2 * CLKDIV]. 0xx: etc.. xxx: etc.." start="0" size="10" />
+      <BitField name="PWRSAV" description="Power saving configuration bit This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0) For power saving, the SDMMC_CK clock output can be disabled when the bus is idle by setting PWRSAV:" start="12" size="1" />
+      <BitField name="WIDBUS" description="Wide bus mode enable bit This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0)" start="14" size="2" />
+      <BitField name="NEGEDGE" description="SDMMC_CK dephasing selection bit for data and Command. This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0). When clock division = 1 (CLKDIV = 0), this bit has no effect. Data and Command change on SDMMC_CK falling edge. When clock division &amp;gt;1 (CLKDIV &amp;gt; 0) &amp;amp; DDR = 0: - SDMMC_CK edge occurs on SDMMCCLK rising edge. When clock division &gt;1 (CLKDIV &gt; 0) &amp; DDR = 1: - Data changed on the SDMMCCLK falling edge succeeding a SDMMC_CK edge. - SDMMC_CK edge occurs on SDMMCCLK rising edge. - Data changed on the SDMMC_CK falling edge succeeding a SDMMC_CK edge. - SDMMC_CK edge occurs on SDMMCCLK rising edge." start="16" size="1" />
+      <BitField name="HWFC_EN" description="Hardware flow control enable This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0) When Hardware flow control is enabled, the meaning of the TXFIFOE and RXFIFOF flags change, please see SDMMC status register definition in Section56.8.11." start="17" size="1" />
+      <BitField name="DDR" description="Data rate signaling selection This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0) DDR rate shall only be selected with 4-bit or 8-bit wide bus mode. (WIDBUS &amp;gt; 00). DDR = 1 has no effect when WIDBUS = 00 (1-bit wide bus). DDR rate shall only be selected with clock division &amp;gt;1. (CLKDIV &amp;gt; 0)" start="18" size="1" />
+      <BitField name="BUSSPEED" description="Bus speed mode selection between DS, HS, SDR12, SDR25 and SDR50, DDR50, SDR104. This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0)" start="19" size="1" />
+      <BitField name="SELCLKRX" description="Receive clock selection. These bits can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0)" start="20" size="2" />
+    </Register>
+    <Register name="SDMMC_ARGR" description="The SDMMC_ARGR register contains a 32-bit command argument, which is sent to a card as part of a command message." start="+0x8" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CMDARG" description="Command argument. These bits can only be written by firmware when CPSM is disabled (CPSMEN = 0). Command argument sent to a card as part of a command message. If a command contains an argument, it must be loaded into this register before writing a command to the command register." start="0" size="32" />
+    </Register>
+    <Register name="SDMMC_CMDR" description="The SDMMC_CMDR register contains the command index and command type bits. The command index is sent to a card as part of a command message. The command type bits control the command path state machine (CPSM)." start="+0xC" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CMDINDEX" description="Command index. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). The command index is sent to the card as part of a command message." start="0" size="6" />
+      <BitField name="CMDTRANS" description="The CPSM treats the command as a data transfer command, stops the interrupt period, and signals DataEnable to the DPSM This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). If this bit is set, the CPSM issues an end of interrupt period and issues DataEnable signal to the DPSM when the command is sent." start="6" size="1" />
+      <BitField name="CMDSTOP" description="The CPSM treats the command as a Stop Transmission command and signals Abort to the DPSM. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). If this bit is set, the CPSM issues the Abort signal to the DPSM when the command is sent." start="7" size="1" />
+      <BitField name="WAITRESP" description="Wait for response bits. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). They are used to configure whether the CPSM is to wait for a response, and if yes, which kind of response." start="8" size="2" />
+      <BitField name="WAITINT" description="CPSM waits for interrupt request. If this bit is set, the CPSM disables command timeout and waits for an card interrupt request (Response). If this bit is cleared in the CPSM Wait state, will cause the abort of the interrupt mode." start="10" size="1" />
+      <BitField name="WAITPEND" description="CPSM Waits for end of data transfer (CmdPend internal signal) from DPSM. This bit when set, the CPSM waits for the end of data transfer trigger before it starts sending a command. WAITPEND is only taken into account when DTMODE = MMC stream data transfer, WIDBUS = 1-bit wide bus mode, DPSMACT = 1 and DTDIR = from host to card." start="11" size="1" />
+      <BitField name="CPSMEN" description="Command path state machine (CPSM) Enable bit This bit is written 1 by firmware, and cleared by hardware when the CPSM enters the Idle state. If this bit is set, the CPSM is enabled. When DTEN = 1, no command will be transfered nor boot procedure will be started. CPSMEN is cleared to 0." start="12" size="1" />
+      <BitField name="DTHOLD" description="Hold new data block transmission and reception in the DPSM. If this bit is set, the DPSM will not move from the Wait_S state to the Send state or from the Wait_R state to the Receive state." start="13" size="1" />
+      <BitField name="BOOTMODE" description="Select the boot mode procedure to be used. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0)" start="14" size="1" />
+      <BitField name="BOOTEN" description="Enable boot mode procedure." start="15" size="1" />
+      <BitField name="CMDSUSPEND" description="The CPSM treats the command as a Suspend or Resume command and signals interrupt period start/end. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). CMDSUSPEND = 1 and CMDTRANS = 0 Suspend command, start interrupt period when response bit BS=0. CMDSUSPEND = 1 and CMDTRANS = 1 Resume command with data, end interrupt period when response bit DF=1." start="16" size="1" />
+    </Register>
+    <Register name="SDMMC_RESP1R" description="The SDMMC_RESP1/2/3/4R registers contain the status of a card, which is part of the received response." start="+0x14" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CARDSTATUS1" description="see Table 432" start="0" size="32" />
+    </Register>
+    <Register name="SDMMC_RESP2R" description="The SDMMC_RESP1/2/3/4R registers contain the status of a card, which is part of the received response." start="+0x18" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CARDSTATUS2" description="see Table404." start="0" size="32" />
+    </Register>
+    <Register name="SDMMC_RESP3R" description="The SDMMC_RESP1/2/3/4R registers contain the status of a card, which is part of the received response." start="+0x1C" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CARDSTATUS3" description="see Table404." start="0" size="32" />
+    </Register>
+    <Register name="SDMMC_RESP4R" description="The SDMMC_RESP1/2/3/4R registers contain the status of a card, which is part of the received response." start="+0x20" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CARDSTATUS4" description="see Table404." start="0" size="32" />
+    </Register>
+    <Register name="SDMMC_DTIMER" description="The SDMMC_DTIMER register contains the data timeout period, in card bus clock periods. A counter loads the value from the SDMMC_DTIMER register, and starts decrementing when the data path state machine (DPSM) enters the Wait_R or Busy state. If the timer reaches 0 while the DPSM is in either of these states, the timeout status flag is set." start="+0x24" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DATATIME" description="Data and R1b busy timeout period This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0). Data and R1b busy timeout period expressed in card bus clock periods." start="0" size="32" />
+    </Register>
+    <Register name="SDMMC_DLENR" description="The SDMMC_DLENR register contains the number of data bytes to be transferred. The value is loaded into the data counter when data transfer starts." start="+0x28" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DATALENGTH" description="Data length value This register can only be written by firmware when DPSM is inactive (DPSMACT = 0). Number of data bytes to be transferred. When DDR = 1 DATALENGTH is truncated to a multiple of 2. (The last odd byte is not transfered) When DATALENGTH = 0 no data will be transfered, when requested by a CPSMEN and CMDTRANS = 1 also no command will be transfered. DTEN and CPSMEN are cleared to 0." start="0" size="25" />
+    </Register>
+    <Register name="SDMMC_DCTRL" description="The SDMMC_DCTRL register control the data path state machine (DPSM)." start="+0x2C" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DTEN" description="Data transfer enable bit This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). This bit is cleared by Hardware when data transfer completes. This bit shall only be used to transfer data when no associated data transfer command is used, i.e. shall not be used with SD or eMMC cards." start="0" size="1" />
+      <BitField name="DTDIR" description="Data transfer direction selection This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)." start="1" size="1" />
+      <BitField name="DTMODE" description="Data transfer mode selection. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)." start="2" size="2" />
+      <BitField name="DBLOCKSIZE" description="Data block size This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). Define the data block length when the block data transfer mode is selected: When DATALENGTH is not a multiple of DBLOCKSIZE, the transfered data is truncated at a multiple of DBLOCKSIZE. (Any remain data will not be transfered.) When DDR = 1, DBLOCKSIZE = 0000 shall not be used. (No data will be transfered)" start="4" size="4" />
+      <BitField name="RWSTART" description="Read wait start. If this bit is set, read wait operation starts." start="8" size="1" />
+      <BitField name="RWSTOP" description="Read wait stop This bit is written by firmware and auto cleared by hardware when the DPSM moves from the READ_WAIT state to the WAIT_R or IDLE state." start="9" size="1" />
+      <BitField name="RWMOD" description="Read wait mode. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)." start="10" size="1" />
+      <BitField name="SDIOEN" description="SD I/O interrupt enable functions This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). If this bit is set, the DPSM enables the SD I/O card specific interrupt operation." start="11" size="1" />
+      <BitField name="BOOTACKEN" description="Enable the reception of the boot acknowledgment. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)." start="12" size="1" />
+      <BitField name="FIFORST" description="FIFO reset, will flush any remaining data. This bit can only be written by firmware when IDMAEN= 0 and DPSM is active (DPSMACT = 1). This bit will only take effect when a transfer error or transfer hold occurs." start="13" size="1" />
+    </Register>
+    <Register name="SDMMC_DCNTR" description="The SDMMC_DCNTR register loads the value from the data length register (see SDMMC_DLENR) when the DPSM moves from the Idle state to the Wait_R or Wait_S state. As data is transferred, the counter decrements the value until it reaches 0. The DPSM then moves to the Idle state and when there has been no error, the data status end flag (DATAEND) is set." start="+0x30" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DATACOUNT" description="Data count value When read, the number of remaining data bytes to be transferred is returned. Write has no effect." start="0" size="25" />
+    </Register>
+    <Register name="SDMMC_STAR" description="The SDMMC_STAR register is a read-only register. It contains two types of flag:Static flags (bits [29,21,11:0]): these bits remain asserted until they are cleared by writing to the SDMMC interrupt Clear register (see SDMMC_ICR)Dynamic flags (bits [20:12]): these bits change state depending on the state of the underlying logic (for example, FIFO full and empty flags are asserted and de-asserted as data while written to the FIFO)" start="+0x34" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCRCFAIL" description="Command response received (CRC check failed). Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR." start="0" size="1" />
+      <BitField name="DCRCFAIL" description="Data block sent/received (CRC check failed). Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR." start="1" size="1" />
+      <BitField name="CTIMEOUT" description="Command response timeout. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. The Command Timeout period has a fixed value of 64 SDMMC_CK clock periods." start="2" size="1" />
+      <BitField name="DTIMEOUT" description="Data timeout. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR." start="3" size="1" />
+      <BitField name="TXUNDERR" description="Transmit FIFO underrun error or IDMA read transfer error. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR." start="4" size="1" />
+      <BitField name="RXOVERR" description="Received FIFO overrun error or IDMA write transfer error. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR." start="5" size="1" />
+      <BitField name="CMDREND" description="Command response received (CRC check passed, or no CRC). Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR." start="6" size="1" />
+      <BitField name="CMDSENT" description="Command sent (no response required). Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR." start="7" size="1" />
+      <BitField name="DATAEND" description="Data transfer ended correctly. (data counter, DATACOUNT is zero and no errors occur). Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR." start="8" size="1" />
+      <BitField name="DHOLD" description="Data transfer Hold. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR." start="9" size="1" />
+      <BitField name="DBCKEND" description="Data block sent/received. (CRC check passed) and DPSM moves to the READWAIT state. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR." start="10" size="1" />
+      <BitField name="DABORT" description="Data transfer aborted by CMD12. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR." start="11" size="1" />
+      <BitField name="DPSMACT" description="Data path state machine active, i.e. not in Idle state. This is a hardware status flag only, does not generate an interrupt." start="12" size="1" />
+      <BitField name="CPSMACT" description="Command path state machine active, i.e. not in Idle state. This is a hardware status flag only, does not generate an interrupt." start="13" size="1" />
+      <BitField name="TXFIFOHE" description="Transmit FIFO half empty At least half the number of words can be written into the FIFO. This bit is cleared when the FIFO becomes half+1 full." start="14" size="1" />
+      <BitField name="RXFIFOHF" description="Receive FIFO half full There are at least half the number of words in the FIFO. This bit is cleared when the FIFO becomes half+1 empty." start="15" size="1" />
+      <BitField name="TXFIFOF" description="Transmit FIFO full This is a hardware status flag only, does not generate an interrupt. This bit is cleared when one FIFO location becomes empty." start="16" size="1" />
+      <BitField name="RXFIFOF" description="Receive FIFO full This bit is cleared when one FIFO location becomes empty." start="17" size="1" />
+      <BitField name="TXFIFOE" description="Transmit FIFO empty This bit is cleared when one FIFO location becomes full." start="18" size="1" />
+      <BitField name="RXFIFOE" description="Receive FIFO empty This is a hardware status flag only, does not generate an interrupt. This bit is cleared when one FIFO location becomes full." start="19" size="1" />
+      <BitField name="BUSYD0" description="Inverted value of SDMMC_D0 line (Busy), sampled at the end of a CMD response and a second time 2 SDMMC_CK cycles after the CMD response. This bit is reset to not busy when the SDMMCD0 line changes from busy to not busy. This bit does not signal busy due to data transfer. This is a hardware status flag only, it does not generate an interrupt." start="20" size="1" />
+      <BitField name="BUSYD0END" description="end of SDMMC_D0 Busy following a CMD response detected. This indicates only end of busy following a CMD response. This bit does not signal busy due to data transfer. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR." start="21" size="1" />
+      <BitField name="SDIOIT" description="SDIO interrupt received. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR." start="22" size="1" />
+      <BitField name="ACKFAIL" description="Boot acknowledgment received (boot acknowledgment check fail). Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR." start="23" size="1" />
+      <BitField name="ACKTIMEOUT" description="Boot acknowledgment timeout. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR." start="24" size="1" />
+      <BitField name="VSWEND" description="Voltage switch critical timing section completion. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR." start="25" size="1" />
+      <BitField name="CKSTOP" description="SDMMC_CK stopped in Voltage switch procedure. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR." start="26" size="1" />
+      <BitField name="IDMATE" description="IDMA transfer error. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR." start="27" size="1" />
+      <BitField name="IDMABTC" description="IDMA buffer transfer complete. interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR." start="28" size="1" />
+    </Register>
+    <Register name="SDMMC_ICR" description="The SDMMC_ICR register is a write-only register. Writing a bit with 1 clears the corresponding bit in the SDMMC_STAR status register." start="+0x38" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCRCFAILC" description="CCRCFAIL flag clear bit Set by software to clear the CCRCFAIL flag." start="0" size="1" />
+      <BitField name="DCRCFAILC" description="DCRCFAIL flag clear bit Set by software to clear the DCRCFAIL flag." start="1" size="1" />
+      <BitField name="CTIMEOUTC" description="CTIMEOUT flag clear bit Set by software to clear the CTIMEOUT flag." start="2" size="1" />
+      <BitField name="DTIMEOUTC" description="DTIMEOUT flag clear bit Set by software to clear the DTIMEOUT flag." start="3" size="1" />
+      <BitField name="TXUNDERRC" description="TXUNDERR flag clear bit Set by software to clear TXUNDERR flag." start="4" size="1" />
+      <BitField name="RXOVERRC" description="RXOVERR flag clear bit Set by software to clear the RXOVERR flag." start="5" size="1" />
+      <BitField name="CMDRENDC" description="CMDREND flag clear bit Set by software to clear the CMDREND flag." start="6" size="1" />
+      <BitField name="CMDSENTC" description="CMDSENT flag clear bit Set by software to clear the CMDSENT flag." start="7" size="1" />
+      <BitField name="DATAENDC" description="DATAEND flag clear bit Set by software to clear the DATAEND flag." start="8" size="1" />
+      <BitField name="DHOLDC" description="DHOLD flag clear bit Set by software to clear the DHOLD flag." start="9" size="1" />
+      <BitField name="DBCKENDC" description="DBCKEND flag clear bit Set by software to clear the DBCKEND flag." start="10" size="1" />
+      <BitField name="DABORTC" description="DABORT flag clear bit Set by software to clear the DABORT flag." start="11" size="1" />
+      <BitField name="BUSYD0ENDC" description="BUSYD0END flag clear bit Set by software to clear the BUSYD0END flag." start="21" size="1" />
+      <BitField name="SDIOITC" description="SDIOIT flag clear bit Set by software to clear the SDIOIT flag." start="22" size="1" />
+      <BitField name="ACKFAILC" description="ACKFAIL flag clear bit Set by software to clear the ACKFAIL flag." start="23" size="1" />
+      <BitField name="ACKTIMEOUTC" description="ACKTIMEOUT flag clear bit Set by software to clear the ACKTIMEOUT flag." start="24" size="1" />
+      <BitField name="VSWENDC" description="VSWEND flag clear bit Set by software to clear the VSWEND flag." start="25" size="1" />
+      <BitField name="CKSTOPC" description="CKSTOP flag clear bit Set by software to clear the CKSTOP flag." start="26" size="1" />
+      <BitField name="IDMATEC" description="IDMA transfer error clear bit Set by software to clear the IDMATE flag." start="27" size="1" />
+      <BitField name="IDMABTCC" description="IDMA buffer transfer complete clear bit Set by software to clear the IDMABTC flag." start="28" size="1" />
+    </Register>
+    <Register name="SDMMC_MASKR" description="The interrupt mask register determines which status flags generate an interrupt request by setting the corresponding bit to 1." start="+0x3C" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCRCFAILIE" description="Command CRC fail interrupt enable Set and cleared by software to enable/disable interrupt caused by command CRC failure." start="0" size="1" />
+      <BitField name="DCRCFAILIE" description="Data CRC fail interrupt enable Set and cleared by software to enable/disable interrupt caused by data CRC failure." start="1" size="1" />
+      <BitField name="CTIMEOUTIE" description="Command timeout interrupt enable Set and cleared by software to enable/disable interrupt caused by command timeout." start="2" size="1" />
+      <BitField name="DTIMEOUTIE" description="Data timeout interrupt enable Set and cleared by software to enable/disable interrupt caused by data timeout." start="3" size="1" />
+      <BitField name="TXUNDERRIE" description="Tx FIFO underrun error interrupt enable Set and cleared by software to enable/disable interrupt caused by Tx FIFO underrun error." start="4" size="1" />
+      <BitField name="RXOVERRIE" description="Rx FIFO overrun error interrupt enable Set and cleared by software to enable/disable interrupt caused by Rx FIFO overrun error." start="5" size="1" />
+      <BitField name="CMDRENDIE" description="Command response received interrupt enable Set and cleared by software to enable/disable interrupt caused by receiving command response." start="6" size="1" />
+      <BitField name="CMDSENTIE" description="Command sent interrupt enable Set and cleared by software to enable/disable interrupt caused by sending command." start="7" size="1" />
+      <BitField name="DATAENDIE" description="Data end interrupt enable Set and cleared by software to enable/disable interrupt caused by data end." start="8" size="1" />
+      <BitField name="DHOLDIE" description="Data hold interrupt enable Set and cleared by software to enable/disable the interrupt generated when sending new data is hold in the DPSM Wait_S state." start="9" size="1" />
+      <BitField name="DBCKENDIE" description="Data block end interrupt enable Set and cleared by software to enable/disable interrupt caused by data block end." start="10" size="1" />
+      <BitField name="DABORTIE" description="Data transfer aborted interrupt enable Set and cleared by software to enable/disable interrupt caused by a data transfer being aborted." start="11" size="1" />
+      <BitField name="TXFIFOHEIE" description="Tx FIFO half empty interrupt enable Set and cleared by software to enable/disable interrupt caused by Tx FIFO half empty." start="14" size="1" />
+      <BitField name="RXFIFOHFIE" description="Rx FIFO half full interrupt enable Set and cleared by software to enable/disable interrupt caused by Rx FIFO half full." start="15" size="1" />
+      <BitField name="RXFIFOFIE" description="Rx FIFO full interrupt enable Set and cleared by software to enable/disable interrupt caused by Rx FIFO full." start="17" size="1" />
+      <BitField name="TXFIFOEIE" description="Tx FIFO empty interrupt enable Set and cleared by software to enable/disable interrupt caused by Tx FIFO empty." start="18" size="1" />
+      <BitField name="BUSYD0ENDIE" description="BUSYD0END interrupt enable Set and cleared by software to enable/disable the interrupt generated when SDMMC_D0 signal changes from busy to NOT busy following a CMD response." start="21" size="1" />
+      <BitField name="SDIOITIE" description="SDIO mode interrupt received interrupt enable Set and cleared by software to enable/disable the interrupt generated when receiving the SDIO mode interrupt." start="22" size="1" />
+      <BitField name="ACKFAILIE" description="Acknowledgment Fail interrupt enable Set and cleared by software to enable/disable interrupt caused by acknowledgment Fail." start="23" size="1" />
+      <BitField name="ACKTIMEOUTIE" description="Acknowledgment timeout interrupt enable Set and cleared by software to enable/disable interrupt caused by acknowledgment timeout." start="24" size="1" />
+      <BitField name="VSWENDIE" description="Voltage switch critical timing section completion interrupt enable Set and cleared by software to enable/disable the interrupt generated when voltage switch critical timing section completion." start="25" size="1" />
+      <BitField name="CKSTOPIE" description="Voltage Switch clock stopped interrupt enable Set and cleared by software to enable/disable interrupt caused by Voltage Switch clock stopped." start="26" size="1" />
+      <BitField name="IDMABTCIE" description="IDMA buffer transfer complete interrupt enable Set and cleared by software to enable/disable the interrupt generated when the IDMA has transferred all data belonging to a memory buffer." start="28" size="1" />
+    </Register>
+    <Register name="SDMMC_ACKTIMER" description="The SDMMC_ACKTIMER register contains the acknowledgment timeout period, in SDMMC_CK bus clock periods. A counter loads the value from the SDMMC_ACKTIMER register, and starts decrementing when the data path state machine (DPSM) enters the Wait_Ack state. If the timer reaches 0 while the DPSM is in this states, the acknowledgment timeout status flag is set." start="+0x40" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ACKTIME" description="Boot acknowledgment timeout period This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). Boot acknowledgment timeout period expressed in card bus clock periods." start="0" size="25" />
+    </Register>
+    <Register name="SDMMC_IDMACTRLR" description="The receive and transmit FIFOs can be read or written as 32-bit wide registers. The FIFOs contain 32 entries on 32 sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO." start="+0x50" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IDMAEN" description="IDMA enable This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)." start="0" size="1" />
+      <BitField name="IDMABMODE" description="Buffer mode selection. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)." start="1" size="1" />
+      <BitField name="IDMABACT" description="Double buffer mode active buffer indication This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). When IDMA is enabled this bit is toggled by hardware." start="2" size="1" />
+    </Register>
+    <Register name="SDMMC_IDMABSIZER" description="The SDMMC_IDMABSIZER register contains the buffers size when in double buffer configuration." start="+0x54" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IDMABNDT" description="Number of transfers per buffer. This 8-bit value shall be multiplied by 8 to get the size of the buffer in 32-bit words and by 32 to get the size of the buffer in bytes. Example: IDMABNDT = 0x01: buffer size = 8 words = 32 bytes. These bits can only be written by firmware when DPSM is inactive (DPSMACT = 0)." start="5" size="8" />
+    </Register>
+    <Register name="SDMMC_IDMABASE0R" description="The SDMMC_IDMABASE0R register contains the memory buffer base address in single buffer configuration and the buffer 0 base address in double buffer configuration." start="+0x58" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IDMABASE0" description="Buffer 0 memory base address bits [31:2], shall be word aligned (bit [1:0] are always 0 and read only). This register can be written by firmware when DPSM is inactive (DPSMACT = 0), and can dynamically be written by firmware when DPSM active (DPSMACT = 1) and memory buffer 0 is inactive (IDMABACT = 1)." start="0" size="32" />
+    </Register>
+    <Register name="SDMMC_IDMABASE1R" description="The SDMMC_IDMABASE1R register contains the double buffer configuration second buffer memory base address." start="+0x5C" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IDMABASE1" description="Buffer 1 memory base address, shall be word aligned (bit [1:0] are always 0 and read only). This register can be written by firmware when DPSM is inactive (DPSMACT = 0), and can dynamically be written by firmware when DPSM active (DPSMACT = 1) and memory buffer 1 is inactive (IDMABACT = 0)." start="0" size="32" />
+    </Register>
+    <Register name="SDMMC_FIFOR" description="The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO.When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated." start="+0x80" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FIFODATA" description="Receive and transmit FIFO data This register can only be read or written by firmware when the DPSM is active (DPSMACT=1). The FIFO data occupies 16 entries of 32-bit words." start="0" size="32" />
+    </Register>
+    <Register name="SDMMC_RESPCMDR" description="SDMMC command response register" start="+0x10" size="4" access="ReadOnly" reset_value="0xA3C5DD01" reset_mask="0xFFFFFFFF">
+      <BitField name="RESPCMD" description="Response command index" start="0" size="6" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="SDMMC2" description="SDMMC1" start="0x48022400">
+    <Register name="SDMMC_POWER" description="SDMMC power control register" start="+0x0" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PWRCTRL" description="SDMMC state control bits. These bits can only be written when the SDMMC is not in the power-on state (PWRCTRL?11). These bits are used to define the functional state of the SDMMC signals: Any further write will be ignored, PWRCTRL value will keep 11." start="0" size="2" />
+      <BitField name="VSWITCH" description="Voltage switch sequence start. This bit is used to start the timing critical section of the voltage switch sequence:" start="2" size="1" />
+      <BitField name="VSWITCHEN" description="Voltage switch procedure enable. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). This bit is used to stop the SDMMC_CK after the voltage switch command response:" start="3" size="1" />
+      <BitField name="DIRPOL" description="Data and command direction signals polarity selection. This bit can only be written when the SDMMC is in the power-off state (PWRCTRL = 00)." start="4" size="1" />
+    </Register>
+    <Register name="SDMMC_CLKCR" description="The SDMMC_CLKCR register controls the SDMMC_CK output clock, the SDMMC_RX_CLK receive clock, and the bus width." start="+0x4" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CLKDIV" description="Clock divide factor This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0). This field defines the divide factor between the input clock (SDMMCCLK) and the output clock (SDMMC_CK): SDMMC_CK frequency = SDMMCCLK / [2 * CLKDIV]. 0xx: etc.. xxx: etc.." start="0" size="10" />
+      <BitField name="PWRSAV" description="Power saving configuration bit This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0) For power saving, the SDMMC_CK clock output can be disabled when the bus is idle by setting PWRSAV:" start="12" size="1" />
+      <BitField name="WIDBUS" description="Wide bus mode enable bit This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0)" start="14" size="2" />
+      <BitField name="NEGEDGE" description="SDMMC_CK dephasing selection bit for data and Command. This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0). When clock division = 1 (CLKDIV = 0), this bit has no effect. Data and Command change on SDMMC_CK falling edge. When clock division &amp;gt;1 (CLKDIV &amp;gt; 0) &amp;amp; DDR = 0: - SDMMC_CK edge occurs on SDMMCCLK rising edge. When clock division &gt;1 (CLKDIV &gt; 0) &amp; DDR = 1: - Data changed on the SDMMCCLK falling edge succeeding a SDMMC_CK edge. - SDMMC_CK edge occurs on SDMMCCLK rising edge. - Data changed on the SDMMC_CK falling edge succeeding a SDMMC_CK edge. - SDMMC_CK edge occurs on SDMMCCLK rising edge." start="16" size="1" />
+      <BitField name="HWFC_EN" description="Hardware flow control enable This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0) When Hardware flow control is enabled, the meaning of the TXFIFOE and RXFIFOF flags change, please see SDMMC status register definition in Section56.8.11." start="17" size="1" />
+      <BitField name="DDR" description="Data rate signaling selection This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0) DDR rate shall only be selected with 4-bit or 8-bit wide bus mode. (WIDBUS &amp;gt; 00). DDR = 1 has no effect when WIDBUS = 00 (1-bit wide bus). DDR rate shall only be selected with clock division &amp;gt;1. (CLKDIV &amp;gt; 0)" start="18" size="1" />
+      <BitField name="BUSSPEED" description="Bus speed mode selection between DS, HS, SDR12, SDR25 and SDR50, DDR50, SDR104. This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0)" start="19" size="1" />
+      <BitField name="SELCLKRX" description="Receive clock selection. These bits can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0)" start="20" size="2" />
+    </Register>
+    <Register name="SDMMC_ARGR" description="The SDMMC_ARGR register contains a 32-bit command argument, which is sent to a card as part of a command message." start="+0x8" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CMDARG" description="Command argument. These bits can only be written by firmware when CPSM is disabled (CPSMEN = 0). Command argument sent to a card as part of a command message. If a command contains an argument, it must be loaded into this register before writing a command to the command register." start="0" size="32" />
+    </Register>
+    <Register name="SDMMC_CMDR" description="The SDMMC_CMDR register contains the command index and command type bits. The command index is sent to a card as part of a command message. The command type bits control the command path state machine (CPSM)." start="+0xC" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CMDINDEX" description="Command index. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). The command index is sent to the card as part of a command message." start="0" size="6" />
+      <BitField name="CMDTRANS" description="The CPSM treats the command as a data transfer command, stops the interrupt period, and signals DataEnable to the DPSM This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). If this bit is set, the CPSM issues an end of interrupt period and issues DataEnable signal to the DPSM when the command is sent." start="6" size="1" />
+      <BitField name="CMDSTOP" description="The CPSM treats the command as a Stop Transmission command and signals Abort to the DPSM. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). If this bit is set, the CPSM issues the Abort signal to the DPSM when the command is sent." start="7" size="1" />
+      <BitField name="WAITRESP" description="Wait for response bits. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). They are used to configure whether the CPSM is to wait for a response, and if yes, which kind of response." start="8" size="2" />
+      <BitField name="WAITINT" description="CPSM waits for interrupt request. If this bit is set, the CPSM disables command timeout and waits for an card interrupt request (Response). If this bit is cleared in the CPSM Wait state, will cause the abort of the interrupt mode." start="10" size="1" />
+      <BitField name="WAITPEND" description="CPSM Waits for end of data transfer (CmdPend internal signal) from DPSM. This bit when set, the CPSM waits for the end of data transfer trigger before it starts sending a command. WAITPEND is only taken into account when DTMODE = MMC stream data transfer, WIDBUS = 1-bit wide bus mode, DPSMACT = 1 and DTDIR = from host to card." start="11" size="1" />
+      <BitField name="CPSMEN" description="Command path state machine (CPSM) Enable bit This bit is written 1 by firmware, and cleared by hardware when the CPSM enters the Idle state. If this bit is set, the CPSM is enabled. When DTEN = 1, no command will be transfered nor boot procedure will be started. CPSMEN is cleared to 0." start="12" size="1" />
+      <BitField name="DTHOLD" description="Hold new data block transmission and reception in the DPSM. If this bit is set, the DPSM will not move from the Wait_S state to the Send state or from the Wait_R state to the Receive state." start="13" size="1" />
+      <BitField name="BOOTMODE" description="Select the boot mode procedure to be used. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0)" start="14" size="1" />
+      <BitField name="BOOTEN" description="Enable boot mode procedure." start="15" size="1" />
+      <BitField name="CMDSUSPEND" description="The CPSM treats the command as a Suspend or Resume command and signals interrupt period start/end. This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). CMDSUSPEND = 1 and CMDTRANS = 0 Suspend command, start interrupt period when response bit BS=0. CMDSUSPEND = 1 and CMDTRANS = 1 Resume command with data, end interrupt period when response bit DF=1." start="16" size="1" />
+    </Register>
+    <Register name="SDMMC_RESP1R" description="The SDMMC_RESP1/2/3/4R registers contain the status of a card, which is part of the received response." start="+0x14" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CARDSTATUS1" description="see Table 432" start="0" size="32" />
+    </Register>
+    <Register name="SDMMC_RESP2R" description="The SDMMC_RESP1/2/3/4R registers contain the status of a card, which is part of the received response." start="+0x18" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CARDSTATUS2" description="see Table404." start="0" size="32" />
+    </Register>
+    <Register name="SDMMC_RESP3R" description="The SDMMC_RESP1/2/3/4R registers contain the status of a card, which is part of the received response." start="+0x1C" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CARDSTATUS3" description="see Table404." start="0" size="32" />
+    </Register>
+    <Register name="SDMMC_RESP4R" description="The SDMMC_RESP1/2/3/4R registers contain the status of a card, which is part of the received response." start="+0x20" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CARDSTATUS4" description="see Table404." start="0" size="32" />
+    </Register>
+    <Register name="SDMMC_DTIMER" description="The SDMMC_DTIMER register contains the data timeout period, in card bus clock periods. A counter loads the value from the SDMMC_DTIMER register, and starts decrementing when the data path state machine (DPSM) enters the Wait_R or Busy state. If the timer reaches 0 while the DPSM is in either of these states, the timeout status flag is set." start="+0x24" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DATATIME" description="Data and R1b busy timeout period This bit can only be written when the CPSM and DPSM are not active (CPSMACT = 0 and DPSMACT = 0). Data and R1b busy timeout period expressed in card bus clock periods." start="0" size="32" />
+    </Register>
+    <Register name="SDMMC_DLENR" description="The SDMMC_DLENR register contains the number of data bytes to be transferred. The value is loaded into the data counter when data transfer starts." start="+0x28" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DATALENGTH" description="Data length value This register can only be written by firmware when DPSM is inactive (DPSMACT = 0). Number of data bytes to be transferred. When DDR = 1 DATALENGTH is truncated to a multiple of 2. (The last odd byte is not transfered) When DATALENGTH = 0 no data will be transfered, when requested by a CPSMEN and CMDTRANS = 1 also no command will be transfered. DTEN and CPSMEN are cleared to 0." start="0" size="25" />
+    </Register>
+    <Register name="SDMMC_DCTRL" description="The SDMMC_DCTRL register control the data path state machine (DPSM)." start="+0x2C" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DTEN" description="Data transfer enable bit This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). This bit is cleared by Hardware when data transfer completes. This bit shall only be used to transfer data when no associated data transfer command is used, i.e. shall not be used with SD or eMMC cards." start="0" size="1" />
+      <BitField name="DTDIR" description="Data transfer direction selection This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)." start="1" size="1" />
+      <BitField name="DTMODE" description="Data transfer mode selection. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)." start="2" size="2" />
+      <BitField name="DBLOCKSIZE" description="Data block size This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). Define the data block length when the block data transfer mode is selected: When DATALENGTH is not a multiple of DBLOCKSIZE, the transfered data is truncated at a multiple of DBLOCKSIZE. (Any remain data will not be transfered.) When DDR = 1, DBLOCKSIZE = 0000 shall not be used. (No data will be transfered)" start="4" size="4" />
+      <BitField name="RWSTART" description="Read wait start. If this bit is set, read wait operation starts." start="8" size="1" />
+      <BitField name="RWSTOP" description="Read wait stop This bit is written by firmware and auto cleared by hardware when the DPSM moves from the READ_WAIT state to the WAIT_R or IDLE state." start="9" size="1" />
+      <BitField name="RWMOD" description="Read wait mode. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)." start="10" size="1" />
+      <BitField name="SDIOEN" description="SD I/O interrupt enable functions This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). If this bit is set, the DPSM enables the SD I/O card specific interrupt operation." start="11" size="1" />
+      <BitField name="BOOTACKEN" description="Enable the reception of the boot acknowledgment. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)." start="12" size="1" />
+      <BitField name="FIFORST" description="FIFO reset, will flush any remaining data. This bit can only be written by firmware when IDMAEN= 0 and DPSM is active (DPSMACT = 1). This bit will only take effect when a transfer error or transfer hold occurs." start="13" size="1" />
+    </Register>
+    <Register name="SDMMC_DCNTR" description="The SDMMC_DCNTR register loads the value from the data length register (see SDMMC_DLENR) when the DPSM moves from the Idle state to the Wait_R or Wait_S state. As data is transferred, the counter decrements the value until it reaches 0. The DPSM then moves to the Idle state and when there has been no error, the data status end flag (DATAEND) is set." start="+0x30" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DATACOUNT" description="Data count value When read, the number of remaining data bytes to be transferred is returned. Write has no effect." start="0" size="25" />
+    </Register>
+    <Register name="SDMMC_STAR" description="The SDMMC_STAR register is a read-only register. It contains two types of flag:Static flags (bits [29,21,11:0]): these bits remain asserted until they are cleared by writing to the SDMMC interrupt Clear register (see SDMMC_ICR)Dynamic flags (bits [20:12]): these bits change state depending on the state of the underlying logic (for example, FIFO full and empty flags are asserted and de-asserted as data while written to the FIFO)" start="+0x34" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCRCFAIL" description="Command response received (CRC check failed). Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR." start="0" size="1" />
+      <BitField name="DCRCFAIL" description="Data block sent/received (CRC check failed). Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR." start="1" size="1" />
+      <BitField name="CTIMEOUT" description="Command response timeout. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR. The Command Timeout period has a fixed value of 64 SDMMC_CK clock periods." start="2" size="1" />
+      <BitField name="DTIMEOUT" description="Data timeout. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR." start="3" size="1" />
+      <BitField name="TXUNDERR" description="Transmit FIFO underrun error or IDMA read transfer error. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR." start="4" size="1" />
+      <BitField name="RXOVERR" description="Received FIFO overrun error or IDMA write transfer error. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR." start="5" size="1" />
+      <BitField name="CMDREND" description="Command response received (CRC check passed, or no CRC). Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR." start="6" size="1" />
+      <BitField name="CMDSENT" description="Command sent (no response required). Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR." start="7" size="1" />
+      <BitField name="DATAEND" description="Data transfer ended correctly. (data counter, DATACOUNT is zero and no errors occur). Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR." start="8" size="1" />
+      <BitField name="DHOLD" description="Data transfer Hold. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR." start="9" size="1" />
+      <BitField name="DBCKEND" description="Data block sent/received. (CRC check passed) and DPSM moves to the READWAIT state. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR." start="10" size="1" />
+      <BitField name="DABORT" description="Data transfer aborted by CMD12. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR." start="11" size="1" />
+      <BitField name="DPSMACT" description="Data path state machine active, i.e. not in Idle state. This is a hardware status flag only, does not generate an interrupt." start="12" size="1" />
+      <BitField name="CPSMACT" description="Command path state machine active, i.e. not in Idle state. This is a hardware status flag only, does not generate an interrupt." start="13" size="1" />
+      <BitField name="TXFIFOHE" description="Transmit FIFO half empty At least half the number of words can be written into the FIFO. This bit is cleared when the FIFO becomes half+1 full." start="14" size="1" />
+      <BitField name="RXFIFOHF" description="Receive FIFO half full There are at least half the number of words in the FIFO. This bit is cleared when the FIFO becomes half+1 empty." start="15" size="1" />
+      <BitField name="TXFIFOF" description="Transmit FIFO full This is a hardware status flag only, does not generate an interrupt. This bit is cleared when one FIFO location becomes empty." start="16" size="1" />
+      <BitField name="RXFIFOF" description="Receive FIFO full This bit is cleared when one FIFO location becomes empty." start="17" size="1" />
+      <BitField name="TXFIFOE" description="Transmit FIFO empty This bit is cleared when one FIFO location becomes full." start="18" size="1" />
+      <BitField name="RXFIFOE" description="Receive FIFO empty This is a hardware status flag only, does not generate an interrupt. This bit is cleared when one FIFO location becomes full." start="19" size="1" />
+      <BitField name="BUSYD0" description="Inverted value of SDMMC_D0 line (Busy), sampled at the end of a CMD response and a second time 2 SDMMC_CK cycles after the CMD response. This bit is reset to not busy when the SDMMCD0 line changes from busy to not busy. This bit does not signal busy due to data transfer. This is a hardware status flag only, it does not generate an interrupt." start="20" size="1" />
+      <BitField name="BUSYD0END" description="end of SDMMC_D0 Busy following a CMD response detected. This indicates only end of busy following a CMD response. This bit does not signal busy due to data transfer. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR." start="21" size="1" />
+      <BitField name="SDIOIT" description="SDIO interrupt received. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR." start="22" size="1" />
+      <BitField name="ACKFAIL" description="Boot acknowledgment received (boot acknowledgment check fail). Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR." start="23" size="1" />
+      <BitField name="ACKTIMEOUT" description="Boot acknowledgment timeout. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR." start="24" size="1" />
+      <BitField name="VSWEND" description="Voltage switch critical timing section completion. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR." start="25" size="1" />
+      <BitField name="CKSTOP" description="SDMMC_CK stopped in Voltage switch procedure. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR." start="26" size="1" />
+      <BitField name="IDMATE" description="IDMA transfer error. Interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR." start="27" size="1" />
+      <BitField name="IDMABTC" description="IDMA buffer transfer complete. interrupt flag is cleared by writing corresponding interrupt clear bit in SDMMC_ICR." start="28" size="1" />
+    </Register>
+    <Register name="SDMMC_ICR" description="The SDMMC_ICR register is a write-only register. Writing a bit with 1 clears the corresponding bit in the SDMMC_STAR status register." start="+0x38" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCRCFAILC" description="CCRCFAIL flag clear bit Set by software to clear the CCRCFAIL flag." start="0" size="1" />
+      <BitField name="DCRCFAILC" description="DCRCFAIL flag clear bit Set by software to clear the DCRCFAIL flag." start="1" size="1" />
+      <BitField name="CTIMEOUTC" description="CTIMEOUT flag clear bit Set by software to clear the CTIMEOUT flag." start="2" size="1" />
+      <BitField name="DTIMEOUTC" description="DTIMEOUT flag clear bit Set by software to clear the DTIMEOUT flag." start="3" size="1" />
+      <BitField name="TXUNDERRC" description="TXUNDERR flag clear bit Set by software to clear TXUNDERR flag." start="4" size="1" />
+      <BitField name="RXOVERRC" description="RXOVERR flag clear bit Set by software to clear the RXOVERR flag." start="5" size="1" />
+      <BitField name="CMDRENDC" description="CMDREND flag clear bit Set by software to clear the CMDREND flag." start="6" size="1" />
+      <BitField name="CMDSENTC" description="CMDSENT flag clear bit Set by software to clear the CMDSENT flag." start="7" size="1" />
+      <BitField name="DATAENDC" description="DATAEND flag clear bit Set by software to clear the DATAEND flag." start="8" size="1" />
+      <BitField name="DHOLDC" description="DHOLD flag clear bit Set by software to clear the DHOLD flag." start="9" size="1" />
+      <BitField name="DBCKENDC" description="DBCKEND flag clear bit Set by software to clear the DBCKEND flag." start="10" size="1" />
+      <BitField name="DABORTC" description="DABORT flag clear bit Set by software to clear the DABORT flag." start="11" size="1" />
+      <BitField name="BUSYD0ENDC" description="BUSYD0END flag clear bit Set by software to clear the BUSYD0END flag." start="21" size="1" />
+      <BitField name="SDIOITC" description="SDIOIT flag clear bit Set by software to clear the SDIOIT flag." start="22" size="1" />
+      <BitField name="ACKFAILC" description="ACKFAIL flag clear bit Set by software to clear the ACKFAIL flag." start="23" size="1" />
+      <BitField name="ACKTIMEOUTC" description="ACKTIMEOUT flag clear bit Set by software to clear the ACKTIMEOUT flag." start="24" size="1" />
+      <BitField name="VSWENDC" description="VSWEND flag clear bit Set by software to clear the VSWEND flag." start="25" size="1" />
+      <BitField name="CKSTOPC" description="CKSTOP flag clear bit Set by software to clear the CKSTOP flag." start="26" size="1" />
+      <BitField name="IDMATEC" description="IDMA transfer error clear bit Set by software to clear the IDMATE flag." start="27" size="1" />
+      <BitField name="IDMABTCC" description="IDMA buffer transfer complete clear bit Set by software to clear the IDMABTC flag." start="28" size="1" />
+    </Register>
+    <Register name="SDMMC_MASKR" description="The interrupt mask register determines which status flags generate an interrupt request by setting the corresponding bit to 1." start="+0x3C" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCRCFAILIE" description="Command CRC fail interrupt enable Set and cleared by software to enable/disable interrupt caused by command CRC failure." start="0" size="1" />
+      <BitField name="DCRCFAILIE" description="Data CRC fail interrupt enable Set and cleared by software to enable/disable interrupt caused by data CRC failure." start="1" size="1" />
+      <BitField name="CTIMEOUTIE" description="Command timeout interrupt enable Set and cleared by software to enable/disable interrupt caused by command timeout." start="2" size="1" />
+      <BitField name="DTIMEOUTIE" description="Data timeout interrupt enable Set and cleared by software to enable/disable interrupt caused by data timeout." start="3" size="1" />
+      <BitField name="TXUNDERRIE" description="Tx FIFO underrun error interrupt enable Set and cleared by software to enable/disable interrupt caused by Tx FIFO underrun error." start="4" size="1" />
+      <BitField name="RXOVERRIE" description="Rx FIFO overrun error interrupt enable Set and cleared by software to enable/disable interrupt caused by Rx FIFO overrun error." start="5" size="1" />
+      <BitField name="CMDRENDIE" description="Command response received interrupt enable Set and cleared by software to enable/disable interrupt caused by receiving command response." start="6" size="1" />
+      <BitField name="CMDSENTIE" description="Command sent interrupt enable Set and cleared by software to enable/disable interrupt caused by sending command." start="7" size="1" />
+      <BitField name="DATAENDIE" description="Data end interrupt enable Set and cleared by software to enable/disable interrupt caused by data end." start="8" size="1" />
+      <BitField name="DHOLDIE" description="Data hold interrupt enable Set and cleared by software to enable/disable the interrupt generated when sending new data is hold in the DPSM Wait_S state." start="9" size="1" />
+      <BitField name="DBCKENDIE" description="Data block end interrupt enable Set and cleared by software to enable/disable interrupt caused by data block end." start="10" size="1" />
+      <BitField name="DABORTIE" description="Data transfer aborted interrupt enable Set and cleared by software to enable/disable interrupt caused by a data transfer being aborted." start="11" size="1" />
+      <BitField name="TXFIFOHEIE" description="Tx FIFO half empty interrupt enable Set and cleared by software to enable/disable interrupt caused by Tx FIFO half empty." start="14" size="1" />
+      <BitField name="RXFIFOHFIE" description="Rx FIFO half full interrupt enable Set and cleared by software to enable/disable interrupt caused by Rx FIFO half full." start="15" size="1" />
+      <BitField name="RXFIFOFIE" description="Rx FIFO full interrupt enable Set and cleared by software to enable/disable interrupt caused by Rx FIFO full." start="17" size="1" />
+      <BitField name="TXFIFOEIE" description="Tx FIFO empty interrupt enable Set and cleared by software to enable/disable interrupt caused by Tx FIFO empty." start="18" size="1" />
+      <BitField name="BUSYD0ENDIE" description="BUSYD0END interrupt enable Set and cleared by software to enable/disable the interrupt generated when SDMMC_D0 signal changes from busy to NOT busy following a CMD response." start="21" size="1" />
+      <BitField name="SDIOITIE" description="SDIO mode interrupt received interrupt enable Set and cleared by software to enable/disable the interrupt generated when receiving the SDIO mode interrupt." start="22" size="1" />
+      <BitField name="ACKFAILIE" description="Acknowledgment Fail interrupt enable Set and cleared by software to enable/disable interrupt caused by acknowledgment Fail." start="23" size="1" />
+      <BitField name="ACKTIMEOUTIE" description="Acknowledgment timeout interrupt enable Set and cleared by software to enable/disable interrupt caused by acknowledgment timeout." start="24" size="1" />
+      <BitField name="VSWENDIE" description="Voltage switch critical timing section completion interrupt enable Set and cleared by software to enable/disable the interrupt generated when voltage switch critical timing section completion." start="25" size="1" />
+      <BitField name="CKSTOPIE" description="Voltage Switch clock stopped interrupt enable Set and cleared by software to enable/disable interrupt caused by Voltage Switch clock stopped." start="26" size="1" />
+      <BitField name="IDMABTCIE" description="IDMA buffer transfer complete interrupt enable Set and cleared by software to enable/disable the interrupt generated when the IDMA has transferred all data belonging to a memory buffer." start="28" size="1" />
+    </Register>
+    <Register name="SDMMC_ACKTIMER" description="The SDMMC_ACKTIMER register contains the acknowledgment timeout period, in SDMMC_CK bus clock periods. A counter loads the value from the SDMMC_ACKTIMER register, and starts decrementing when the data path state machine (DPSM) enters the Wait_Ack state. If the timer reaches 0 while the DPSM is in this states, the acknowledgment timeout status flag is set." start="+0x40" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ACKTIME" description="Boot acknowledgment timeout period This bit can only be written by firmware when CPSM is disabled (CPSMEN = 0). Boot acknowledgment timeout period expressed in card bus clock periods." start="0" size="25" />
+    </Register>
+    <Register name="SDMMC_IDMACTRLR" description="The receive and transmit FIFOs can be read or written as 32-bit wide registers. The FIFOs contain 32 entries on 32 sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO." start="+0x50" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IDMAEN" description="IDMA enable This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)." start="0" size="1" />
+      <BitField name="IDMABMODE" description="Buffer mode selection. This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0)." start="1" size="1" />
+      <BitField name="IDMABACT" description="Double buffer mode active buffer indication This bit can only be written by firmware when DPSM is inactive (DPSMACT = 0). When IDMA is enabled this bit is toggled by hardware." start="2" size="1" />
+    </Register>
+    <Register name="SDMMC_IDMABSIZER" description="The SDMMC_IDMABSIZER register contains the buffers size when in double buffer configuration." start="+0x54" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IDMABNDT" description="Number of transfers per buffer. This 8-bit value shall be multiplied by 8 to get the size of the buffer in 32-bit words and by 32 to get the size of the buffer in bytes. Example: IDMABNDT = 0x01: buffer size = 8 words = 32 bytes. These bits can only be written by firmware when DPSM is inactive (DPSMACT = 0)." start="5" size="8" />
+    </Register>
+    <Register name="SDMMC_IDMABASE0R" description="The SDMMC_IDMABASE0R register contains the memory buffer base address in single buffer configuration and the buffer 0 base address in double buffer configuration." start="+0x58" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IDMABASE0" description="Buffer 0 memory base address bits [31:2], shall be word aligned (bit [1:0] are always 0 and read only). This register can be written by firmware when DPSM is inactive (DPSMACT = 0), and can dynamically be written by firmware when DPSM active (DPSMACT = 1) and memory buffer 0 is inactive (IDMABACT = 1)." start="0" size="32" />
+    </Register>
+    <Register name="SDMMC_IDMABASE1R" description="The SDMMC_IDMABASE1R register contains the double buffer configuration second buffer memory base address." start="+0x5C" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IDMABASE1" description="Buffer 1 memory base address, shall be word aligned (bit [1:0] are always 0 and read only). This register can be written by firmware when DPSM is inactive (DPSMACT = 0), and can dynamically be written by firmware when DPSM active (DPSMACT = 1) and memory buffer 1 is inactive (IDMABACT = 0)." start="0" size="32" />
+    </Register>
+    <Register name="SDMMC_FIFOR" description="The receive and transmit FIFOs can be only read or written as word (32-bit) wide registers. The FIFOs contain 16 entries on sequential addresses. This allows the CPU to use its load and store multiple operands to read from/write to the FIFO.When accessing SDMMC_FIFOR with half word or byte access an AHB bus fault is generated." start="+0x80" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FIFODATA" description="Receive and transmit FIFO data This register can only be read or written by firmware when the DPSM is active (DPSMACT=1). The FIFO data occupies 16 entries of 32-bit words." start="0" size="32" />
+    </Register>
+    <Register name="SDMMC_RESPCMDR" description="SDMMC command response register" start="+0x10" size="4" access="ReadOnly" reset_value="0xA3C5DD01" reset_mask="0xFFFFFFFF">
+      <BitField name="RESPCMD" description="Response command index" start="0" size="6" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="SPDIFRX" description="Receiver Interface" start="0x40004000">
+    <Register name="CR" description="Control register" start="+0x0" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SPDIFRXEN" description="Peripheral Block Enable" start="0" size="2" />
+      <BitField name="RXDMAEN" description="Receiver DMA ENable for data flow" start="2" size="1" />
+      <BitField name="RXSTEO" description="STerEO Mode" start="3" size="1" />
+      <BitField name="DRFMT" description="RX Data format" start="4" size="2" />
+      <BitField name="PMSK" description="Mask Parity error bit" start="6" size="1" />
+      <BitField name="VMSK" description="Mask of Validity bit" start="7" size="1" />
+      <BitField name="CUMSK" description="Mask of channel status and user bits" start="8" size="1" />
+      <BitField name="PTMSK" description="Mask of Preamble Type bits" start="9" size="1" />
+      <BitField name="CBDMAEN" description="Control Buffer DMA ENable for control flow" start="10" size="1" />
+      <BitField name="CHSEL" description="Channel Selection" start="11" size="1" />
+      <BitField name="NBTR" description="Maximum allowed re-tries during synchronization phase" start="12" size="2" />
+      <BitField name="WFA" description="Wait For Activity" start="14" size="1" />
+      <BitField name="INSEL" description="input selection" start="16" size="3" />
+      <BitField name="CKSEN" description="Symbol Clock Enable" start="20" size="1" />
+      <BitField name="CKSBKPEN" description="Backup Symbol Clock Enable" start="21" size="1" />
+    </Register>
+    <Register name="IMR" description="Interrupt mask register" start="+0x4" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RXNEIE" description="RXNE interrupt enable" start="0" size="1" />
+      <BitField name="CSRNEIE" description="Control Buffer Ready Interrupt Enable" start="1" size="1" />
+      <BitField name="PERRIE" description="Parity error interrupt enable" start="2" size="1" />
+      <BitField name="OVRIE" description="Overrun error Interrupt Enable" start="3" size="1" />
+      <BitField name="SBLKIE" description="Synchronization Block Detected Interrupt Enable" start="4" size="1" />
+      <BitField name="SYNCDIE" description="Synchronization Done" start="5" size="1" />
+      <BitField name="IFEIE" description="Serial Interface Error Interrupt Enable" start="6" size="1" />
+    </Register>
+    <Register name="SR" description="Status register" start="+0x8" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RXNE" description="Read data register not empty" start="0" size="1" />
+      <BitField name="CSRNE" description="Control Buffer register is not empty" start="1" size="1" />
+      <BitField name="PERR" description="Parity error" start="2" size="1" />
+      <BitField name="OVR" description="Overrun error" start="3" size="1" />
+      <BitField name="SBD" description="Synchronization Block Detected" start="4" size="1" />
+      <BitField name="SYNCD" description="Synchronization Done" start="5" size="1" />
+      <BitField name="FERR" description="Framing error" start="6" size="1" />
+      <BitField name="SERR" description="Synchronization error" start="7" size="1" />
+      <BitField name="TERR" description="Time-out error" start="8" size="1" />
+      <BitField name="WIDTH5" description="Duration of 5 symbols counted with SPDIF_CLK" start="16" size="15" />
+    </Register>
+    <Register name="IFCR" description="Interrupt Flag Clear register" start="+0xC" size="4" access="WriteOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PERRCF" description="Clears the Parity error flag" start="2" size="1" />
+      <BitField name="OVRCF" description="Clears the Overrun error flag" start="3" size="1" />
+      <BitField name="SBDCF" description="Clears the Synchronization Block Detected flag" start="4" size="1" />
+      <BitField name="SYNCDCF" description="Clears the Synchronization Done flag" start="5" size="1" />
+    </Register>
+    <Register name="FMT0_DR" description="Data input register" start="+0x10" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="DR" description="Parity Error bit" start="0" size="24" />
+      <BitField name="PE" description="Parity Error bit" start="24" size="1" />
+      <BitField name="V" description="Validity bit" start="25" size="1" />
+      <BitField name="U" description="User bit" start="26" size="1" />
+      <BitField name="C" description="Channel Status bit" start="27" size="1" />
+      <BitField name="PT" description="Preamble Type" start="28" size="2" />
+    </Register>
+    <Register name="CSR" description="Channel Status register" start="+0x14" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="USR" description="User data information" start="0" size="16" />
+      <BitField name="CS" description="Channel A status information" start="16" size="8" />
+      <BitField name="SOB" description="Start Of Block" start="24" size="1" />
+    </Register>
+    <Register name="DIR" description="Debug Information register" start="+0x18" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="THI" description="Threshold HIGH" start="0" size="13" />
+      <BitField name="TLO" description="Threshold LOW" start="16" size="13" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="SPI1" description="Serial peripheral interface" start="0x40013000">
+    <Register name="CR1" description="control register 1" start="+0x0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IOLOCK" description="Locking the AF configuration of associated IOs" start="16" size="1" access="ReadOnly" />
+      <BitField name="TCRCI" description="CRC calculation initialization pattern control for transmitter" start="15" size="1" access="Read/Write" />
+      <BitField name="RCRCI" description="CRC calculation initialization pattern control for receiver" start="14" size="1" access="Read/Write" />
+      <BitField name="CRC33_17" description="32-bit CRC polynomial configuration" start="13" size="1" access="Read/Write" />
+      <BitField name="SSI" description="Internal SS signal input level" start="12" size="1" access="Read/Write" />
+      <BitField name="HDDIR" description="Rx/Tx direction at Half-duplex mode" start="11" size="1" access="Read/Write" />
+      <BitField name="CSUSP" description="Master SUSPend request" start="10" size="1" access="WriteOnly" />
+      <BitField name="CSTART" description="Master transfer start" start="9" size="1" access="ReadOnly" />
+      <BitField name="MASRX" description="Master automatic SUSP in Receive mode" start="8" size="1" access="Read/Write" />
+      <BitField name="SPE" description="Serial Peripheral Enable" start="0" size="1" access="Read/Write" />
+    </Register>
+    <Register name="CR2" description="control register 2" start="+0x4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TSER" description="Number of data transfer extension to be reload into TSIZE just when a previous" start="16" size="16" access="ReadOnly" />
+      <BitField name="TSIZE" description="Number of data at current transfer" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="CFG1" description="configuration register 1" start="+0x8" size="4" access="Read/Write" reset_value="0x00070007" reset_mask="0xFFFFFFFF">
+      <BitField name="MBR" description="Master baud rate" start="28" size="3" />
+      <BitField name="CRCEN" description="Hardware CRC computation enable" start="22" size="1" />
+      <BitField name="CRCSIZE" description="Length of CRC frame to be transacted and compared" start="16" size="5" />
+      <BitField name="TXDMAEN" description="Tx DMA stream enable" start="15" size="1" />
+      <BitField name="RXDMAEN" description="Rx DMA stream enable" start="14" size="1" />
+      <BitField name="UDRDET" description="Detection of underrun condition at slave transmitter" start="11" size="2" />
+      <BitField name="UDRCFG" description="Behavior of slave transmitter at underrun condition" start="9" size="2" />
+      <BitField name="FTHVL" description="threshold level" start="5" size="4" />
+      <BitField name="DSIZE" description="Number of bits in at single SPI data frame" start="0" size="5" />
+    </Register>
+    <Register name="CFG2" description="configuration register 2" start="+0xC" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AFCNTR" description="Alternate function GPIOs control" start="31" size="1" />
+      <BitField name="SSOM" description="SS output management in master mode" start="30" size="1" />
+      <BitField name="SSOE" description="SS output enable" start="29" size="1" />
+      <BitField name="SSIOP" description="SS input/output polarity" start="28" size="1" />
+      <BitField name="SSM" description="Software management of SS signal input" start="26" size="1" />
+      <BitField name="CPOL" description="Clock polarity" start="25" size="1" />
+      <BitField name="CPHA" description="Clock phase" start="24" size="1" />
+      <BitField name="LSBFRST" description="Data frame format" start="23" size="1" />
+      <BitField name="MASTER" description="SPI Master" start="22" size="1" />
+      <BitField name="SP" description="Serial Protocol" start="19" size="3" />
+      <BitField name="COMM" description="SPI Communication Mode" start="17" size="2" />
+      <BitField name="IOSWP" description="Swap functionality of MISO and MOSI pins" start="15" size="1" />
+      <BitField name="MIDI" description="Master Inter-Data Idleness" start="4" size="4" />
+      <BitField name="MSSI" description="Master SS Idleness" start="0" size="4" />
+    </Register>
+    <Register name="IER" description="Interrupt Enable Register" start="+0x10" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TSERFIE" description="Additional number of transactions reload interrupt enable" start="10" size="1" access="Read/Write" />
+      <BitField name="MODFIE" description="Mode Fault interrupt enable" start="9" size="1" access="Read/Write" />
+      <BitField name="TIFREIE" description="TIFRE interrupt enable" start="8" size="1" access="Read/Write" />
+      <BitField name="CRCEIE" description="CRC Interrupt enable" start="7" size="1" access="Read/Write" />
+      <BitField name="OVRIE" description="OVR interrupt enable" start="6" size="1" access="Read/Write" />
+      <BitField name="UDRIE" description="UDR interrupt enable" start="5" size="1" access="Read/Write" />
+      <BitField name="TXTFIE" description="TXTFIE interrupt enable" start="4" size="1" access="Read/Write" />
+      <BitField name="EOTIE" description="EOT, SUSP and TXC interrupt enable" start="3" size="1" access="Read/Write" />
+      <BitField name="DPXPIE" description="DXP interrupt enabled" start="2" size="1" access="ReadOnly" />
+      <BitField name="TXPIE" description="TXP interrupt enable" start="1" size="1" access="ReadOnly" />
+      <BitField name="RXPIE" description="RXP Interrupt Enable" start="0" size="1" access="Read/Write" />
+    </Register>
+    <Register name="SR" description="Status Register" start="+0x14" size="4" access="ReadOnly" reset_value="0x00001002" reset_mask="0xFFFFFFFF">
+      <BitField name="CTSIZE" description="Number of data frames remaining in current TSIZE session" start="16" size="16" />
+      <BitField name="RXWNE" description="RxFIFO Word Not Empty" start="15" size="1" />
+      <BitField name="RXPLVL" description="RxFIFO Packing LeVeL" start="13" size="2" />
+      <BitField name="TXC" description="TxFIFO transmission complete" start="12" size="1" />
+      <BitField name="SUSP" description="SUSPend" start="11" size="1" />
+      <BitField name="TSERF" description="Additional number of SPI data to be transacted was reload" start="10" size="1" />
+      <BitField name="MODF" description="Mode Fault" start="9" size="1" />
+      <BitField name="TIFRE" description="TI frame format error" start="8" size="1" />
+      <BitField name="CRCE" description="CRC Error" start="7" size="1" />
+      <BitField name="OVR" description="Overrun" start="6" size="1" />
+      <BitField name="UDR" description="Underrun at slave transmission mode" start="5" size="1" />
+      <BitField name="TXTF" description="Transmission Transfer Filled" start="4" size="1" />
+      <BitField name="EOT" description="End Of Transfer" start="3" size="1" />
+      <BitField name="DXP" description="Duplex Packet" start="2" size="1" />
+      <BitField name="TXP" description="Tx-Packet space available" start="1" size="1" />
+      <BitField name="RXP" description="Rx-Packet available" start="0" size="1" />
+    </Register>
+    <Register name="IFCR" description="Interrupt/Status Flags Clear Register" start="+0x18" size="4" access="WriteOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SUSPC" description="SUSPend flag clear" start="11" size="1" />
+      <BitField name="TSERFC" description="TSERFC flag clear" start="10" size="1" />
+      <BitField name="MODFC" description="Mode Fault flag clear" start="9" size="1" />
+      <BitField name="TIFREC" description="TI frame format error flag clear" start="8" size="1" />
+      <BitField name="CRCEC" description="CRC Error flag clear" start="7" size="1" />
+      <BitField name="OVRC" description="Overrun flag clear" start="6" size="1" />
+      <BitField name="UDRC" description="Underrun flag clear" start="5" size="1" />
+      <BitField name="TXTFC" description="Transmission Transfer Filled flag clear" start="4" size="1" />
+      <BitField name="EOTC" description="End Of Transfer flag clear" start="3" size="1" />
+    </Register>
+    <Register name="TXDR" description="Transmit Data Register" start="+0x20" size="4" access="WriteOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TXDR" description="Transmit data register" start="0" size="32" />
+    </Register>
+    <Register name="RXDR" description="Receive Data Register" start="+0x30" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RXDR" description="Receive data register" start="0" size="32" />
+    </Register>
+    <Register name="CRCPOLY" description="Polynomial Register" start="+0x40" size="4" access="Read/Write" reset_value="0x00000107" reset_mask="0xFFFFFFFF">
+      <BitField name="CRCPOLY" description="CRC polynomial register" start="0" size="32" />
+    </Register>
+    <Register name="TXCRC" description="Transmitter CRC Register" start="+0x44" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TXCRC" description="CRC register for transmitter" start="0" size="32" />
+    </Register>
+    <Register name="RXCRC" description="Receiver CRC Register" start="+0x48" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RXCRC" description="CRC register for receiver" start="0" size="32" />
+    </Register>
+    <Register name="UDRDR" description="Underrun Data Register" start="+0x4C" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="UDRDR" description="Data at slave underrun condition" start="0" size="32" />
+    </Register>
+    <Register name="I2SCFGR" description="configuration register" start="+0x50" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MCKOE" description="Master clock output enable" start="25" size="1" />
+      <BitField name="ODD" description="Odd factor for the prescaler" start="24" size="1" />
+      <BitField name="I2SDIV" description="I2S linear prescaler" start="16" size="8" />
+      <BitField name="DATFMT" description="Data format" start="14" size="1" />
+      <BitField name="WSINV" description="Fixed channel length in SLAVE" start="13" size="1" />
+      <BitField name="FIXCH" description="Word select inversion" start="12" size="1" />
+      <BitField name="CKPOL" description="Serial audio clock polarity" start="11" size="1" />
+      <BitField name="CHLEN" description="Channel length (number of bits per audio channel)" start="10" size="1" />
+      <BitField name="DATLEN" description="Data length to be transferred" start="8" size="2" />
+      <BitField name="PCMSYNC" description="PCM frame synchronization" start="7" size="1" />
+      <BitField name="I2SSTD" description="I2S standard selection" start="4" size="2" />
+      <BitField name="I2SCFG" description="I2S configuration mode" start="1" size="3" />
+      <BitField name="I2SMOD" description="I2S mode selection" start="0" size="1" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="SPI2" description="Serial peripheral interface" start="0x40003800">
+    <Register name="CR1" description="control register 1" start="+0x0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IOLOCK" description="Locking the AF configuration of associated IOs" start="16" size="1" access="ReadOnly" />
+      <BitField name="TCRCI" description="CRC calculation initialization pattern control for transmitter" start="15" size="1" access="Read/Write" />
+      <BitField name="RCRCI" description="CRC calculation initialization pattern control for receiver" start="14" size="1" access="Read/Write" />
+      <BitField name="CRC33_17" description="32-bit CRC polynomial configuration" start="13" size="1" access="Read/Write" />
+      <BitField name="SSI" description="Internal SS signal input level" start="12" size="1" access="Read/Write" />
+      <BitField name="HDDIR" description="Rx/Tx direction at Half-duplex mode" start="11" size="1" access="Read/Write" />
+      <BitField name="CSUSP" description="Master SUSPend request" start="10" size="1" access="WriteOnly" />
+      <BitField name="CSTART" description="Master transfer start" start="9" size="1" access="ReadOnly" />
+      <BitField name="MASRX" description="Master automatic SUSP in Receive mode" start="8" size="1" access="Read/Write" />
+      <BitField name="SPE" description="Serial Peripheral Enable" start="0" size="1" access="Read/Write" />
+    </Register>
+    <Register name="CR2" description="control register 2" start="+0x4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TSER" description="Number of data transfer extension to be reload into TSIZE just when a previous" start="16" size="16" access="ReadOnly" />
+      <BitField name="TSIZE" description="Number of data at current transfer" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="CFG1" description="configuration register 1" start="+0x8" size="4" access="Read/Write" reset_value="0x00070007" reset_mask="0xFFFFFFFF">
+      <BitField name="MBR" description="Master baud rate" start="28" size="3" />
+      <BitField name="CRCEN" description="Hardware CRC computation enable" start="22" size="1" />
+      <BitField name="CRCSIZE" description="Length of CRC frame to be transacted and compared" start="16" size="5" />
+      <BitField name="TXDMAEN" description="Tx DMA stream enable" start="15" size="1" />
+      <BitField name="RXDMAEN" description="Rx DMA stream enable" start="14" size="1" />
+      <BitField name="UDRDET" description="Detection of underrun condition at slave transmitter" start="11" size="2" />
+      <BitField name="UDRCFG" description="Behavior of slave transmitter at underrun condition" start="9" size="2" />
+      <BitField name="FTHVL" description="threshold level" start="5" size="4" />
+      <BitField name="DSIZE" description="Number of bits in at single SPI data frame" start="0" size="5" />
+    </Register>
+    <Register name="CFG2" description="configuration register 2" start="+0xC" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AFCNTR" description="Alternate function GPIOs control" start="31" size="1" />
+      <BitField name="SSOM" description="SS output management in master mode" start="30" size="1" />
+      <BitField name="SSOE" description="SS output enable" start="29" size="1" />
+      <BitField name="SSIOP" description="SS input/output polarity" start="28" size="1" />
+      <BitField name="SSM" description="Software management of SS signal input" start="26" size="1" />
+      <BitField name="CPOL" description="Clock polarity" start="25" size="1" />
+      <BitField name="CPHA" description="Clock phase" start="24" size="1" />
+      <BitField name="LSBFRST" description="Data frame format" start="23" size="1" />
+      <BitField name="MASTER" description="SPI Master" start="22" size="1" />
+      <BitField name="SP" description="Serial Protocol" start="19" size="3" />
+      <BitField name="COMM" description="SPI Communication Mode" start="17" size="2" />
+      <BitField name="IOSWP" description="Swap functionality of MISO and MOSI pins" start="15" size="1" />
+      <BitField name="MIDI" description="Master Inter-Data Idleness" start="4" size="4" />
+      <BitField name="MSSI" description="Master SS Idleness" start="0" size="4" />
+    </Register>
+    <Register name="IER" description="Interrupt Enable Register" start="+0x10" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TSERFIE" description="Additional number of transactions reload interrupt enable" start="10" size="1" access="Read/Write" />
+      <BitField name="MODFIE" description="Mode Fault interrupt enable" start="9" size="1" access="Read/Write" />
+      <BitField name="TIFREIE" description="TIFRE interrupt enable" start="8" size="1" access="Read/Write" />
+      <BitField name="CRCEIE" description="CRC Interrupt enable" start="7" size="1" access="Read/Write" />
+      <BitField name="OVRIE" description="OVR interrupt enable" start="6" size="1" access="Read/Write" />
+      <BitField name="UDRIE" description="UDR interrupt enable" start="5" size="1" access="Read/Write" />
+      <BitField name="TXTFIE" description="TXTFIE interrupt enable" start="4" size="1" access="Read/Write" />
+      <BitField name="EOTIE" description="EOT, SUSP and TXC interrupt enable" start="3" size="1" access="Read/Write" />
+      <BitField name="DPXPIE" description="DXP interrupt enabled" start="2" size="1" access="ReadOnly" />
+      <BitField name="TXPIE" description="TXP interrupt enable" start="1" size="1" access="ReadOnly" />
+      <BitField name="RXPIE" description="RXP Interrupt Enable" start="0" size="1" access="Read/Write" />
+    </Register>
+    <Register name="SR" description="Status Register" start="+0x14" size="4" access="ReadOnly" reset_value="0x00001002" reset_mask="0xFFFFFFFF">
+      <BitField name="CTSIZE" description="Number of data frames remaining in current TSIZE session" start="16" size="16" />
+      <BitField name="RXWNE" description="RxFIFO Word Not Empty" start="15" size="1" />
+      <BitField name="RXPLVL" description="RxFIFO Packing LeVeL" start="13" size="2" />
+      <BitField name="TXC" description="TxFIFO transmission complete" start="12" size="1" />
+      <BitField name="SUSP" description="SUSPend" start="11" size="1" />
+      <BitField name="TSERF" description="Additional number of SPI data to be transacted was reload" start="10" size="1" />
+      <BitField name="MODF" description="Mode Fault" start="9" size="1" />
+      <BitField name="TIFRE" description="TI frame format error" start="8" size="1" />
+      <BitField name="CRCE" description="CRC Error" start="7" size="1" />
+      <BitField name="OVR" description="Overrun" start="6" size="1" />
+      <BitField name="UDR" description="Underrun at slave transmission mode" start="5" size="1" />
+      <BitField name="TXTF" description="Transmission Transfer Filled" start="4" size="1" />
+      <BitField name="EOT" description="End Of Transfer" start="3" size="1" />
+      <BitField name="DXP" description="Duplex Packet" start="2" size="1" />
+      <BitField name="TXP" description="Tx-Packet space available" start="1" size="1" />
+      <BitField name="RXP" description="Rx-Packet available" start="0" size="1" />
+    </Register>
+    <Register name="IFCR" description="Interrupt/Status Flags Clear Register" start="+0x18" size="4" access="WriteOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SUSPC" description="SUSPend flag clear" start="11" size="1" />
+      <BitField name="TSERFC" description="TSERFC flag clear" start="10" size="1" />
+      <BitField name="MODFC" description="Mode Fault flag clear" start="9" size="1" />
+      <BitField name="TIFREC" description="TI frame format error flag clear" start="8" size="1" />
+      <BitField name="CRCEC" description="CRC Error flag clear" start="7" size="1" />
+      <BitField name="OVRC" description="Overrun flag clear" start="6" size="1" />
+      <BitField name="UDRC" description="Underrun flag clear" start="5" size="1" />
+      <BitField name="TXTFC" description="Transmission Transfer Filled flag clear" start="4" size="1" />
+      <BitField name="EOTC" description="End Of Transfer flag clear" start="3" size="1" />
+    </Register>
+    <Register name="TXDR" description="Transmit Data Register" start="+0x20" size="4" access="WriteOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TXDR" description="Transmit data register" start="0" size="32" />
+    </Register>
+    <Register name="RXDR" description="Receive Data Register" start="+0x30" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RXDR" description="Receive data register" start="0" size="32" />
+    </Register>
+    <Register name="CRCPOLY" description="Polynomial Register" start="+0x40" size="4" access="Read/Write" reset_value="0x00000107" reset_mask="0xFFFFFFFF">
+      <BitField name="CRCPOLY" description="CRC polynomial register" start="0" size="32" />
+    </Register>
+    <Register name="TXCRC" description="Transmitter CRC Register" start="+0x44" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TXCRC" description="CRC register for transmitter" start="0" size="32" />
+    </Register>
+    <Register name="RXCRC" description="Receiver CRC Register" start="+0x48" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RXCRC" description="CRC register for receiver" start="0" size="32" />
+    </Register>
+    <Register name="UDRDR" description="Underrun Data Register" start="+0x4C" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="UDRDR" description="Data at slave underrun condition" start="0" size="32" />
+    </Register>
+    <Register name="I2SCFGR" description="configuration register" start="+0x50" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MCKOE" description="Master clock output enable" start="25" size="1" />
+      <BitField name="ODD" description="Odd factor for the prescaler" start="24" size="1" />
+      <BitField name="I2SDIV" description="I2S linear prescaler" start="16" size="8" />
+      <BitField name="DATFMT" description="Data format" start="14" size="1" />
+      <BitField name="WSINV" description="Fixed channel length in SLAVE" start="13" size="1" />
+      <BitField name="FIXCH" description="Word select inversion" start="12" size="1" />
+      <BitField name="CKPOL" description="Serial audio clock polarity" start="11" size="1" />
+      <BitField name="CHLEN" description="Channel length (number of bits per audio channel)" start="10" size="1" />
+      <BitField name="DATLEN" description="Data length to be transferred" start="8" size="2" />
+      <BitField name="PCMSYNC" description="PCM frame synchronization" start="7" size="1" />
+      <BitField name="I2SSTD" description="I2S standard selection" start="4" size="2" />
+      <BitField name="I2SCFG" description="I2S configuration mode" start="1" size="3" />
+      <BitField name="I2SMOD" description="I2S mode selection" start="0" size="1" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="SPI3" description="Serial peripheral interface" start="0x40003C00">
+    <Register name="CR1" description="control register 1" start="+0x0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IOLOCK" description="Locking the AF configuration of associated IOs" start="16" size="1" access="ReadOnly" />
+      <BitField name="TCRCI" description="CRC calculation initialization pattern control for transmitter" start="15" size="1" access="Read/Write" />
+      <BitField name="RCRCI" description="CRC calculation initialization pattern control for receiver" start="14" size="1" access="Read/Write" />
+      <BitField name="CRC33_17" description="32-bit CRC polynomial configuration" start="13" size="1" access="Read/Write" />
+      <BitField name="SSI" description="Internal SS signal input level" start="12" size="1" access="Read/Write" />
+      <BitField name="HDDIR" description="Rx/Tx direction at Half-duplex mode" start="11" size="1" access="Read/Write" />
+      <BitField name="CSUSP" description="Master SUSPend request" start="10" size="1" access="WriteOnly" />
+      <BitField name="CSTART" description="Master transfer start" start="9" size="1" access="ReadOnly" />
+      <BitField name="MASRX" description="Master automatic SUSP in Receive mode" start="8" size="1" access="Read/Write" />
+      <BitField name="SPE" description="Serial Peripheral Enable" start="0" size="1" access="Read/Write" />
+    </Register>
+    <Register name="CR2" description="control register 2" start="+0x4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TSER" description="Number of data transfer extension to be reload into TSIZE just when a previous" start="16" size="16" access="ReadOnly" />
+      <BitField name="TSIZE" description="Number of data at current transfer" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="CFG1" description="configuration register 1" start="+0x8" size="4" access="Read/Write" reset_value="0x00070007" reset_mask="0xFFFFFFFF">
+      <BitField name="MBR" description="Master baud rate" start="28" size="3" />
+      <BitField name="CRCEN" description="Hardware CRC computation enable" start="22" size="1" />
+      <BitField name="CRCSIZE" description="Length of CRC frame to be transacted and compared" start="16" size="5" />
+      <BitField name="TXDMAEN" description="Tx DMA stream enable" start="15" size="1" />
+      <BitField name="RXDMAEN" description="Rx DMA stream enable" start="14" size="1" />
+      <BitField name="UDRDET" description="Detection of underrun condition at slave transmitter" start="11" size="2" />
+      <BitField name="UDRCFG" description="Behavior of slave transmitter at underrun condition" start="9" size="2" />
+      <BitField name="FTHVL" description="threshold level" start="5" size="4" />
+      <BitField name="DSIZE" description="Number of bits in at single SPI data frame" start="0" size="5" />
+    </Register>
+    <Register name="CFG2" description="configuration register 2" start="+0xC" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AFCNTR" description="Alternate function GPIOs control" start="31" size="1" />
+      <BitField name="SSOM" description="SS output management in master mode" start="30" size="1" />
+      <BitField name="SSOE" description="SS output enable" start="29" size="1" />
+      <BitField name="SSIOP" description="SS input/output polarity" start="28" size="1" />
+      <BitField name="SSM" description="Software management of SS signal input" start="26" size="1" />
+      <BitField name="CPOL" description="Clock polarity" start="25" size="1" />
+      <BitField name="CPHA" description="Clock phase" start="24" size="1" />
+      <BitField name="LSBFRST" description="Data frame format" start="23" size="1" />
+      <BitField name="MASTER" description="SPI Master" start="22" size="1" />
+      <BitField name="SP" description="Serial Protocol" start="19" size="3" />
+      <BitField name="COMM" description="SPI Communication Mode" start="17" size="2" />
+      <BitField name="IOSWP" description="Swap functionality of MISO and MOSI pins" start="15" size="1" />
+      <BitField name="MIDI" description="Master Inter-Data Idleness" start="4" size="4" />
+      <BitField name="MSSI" description="Master SS Idleness" start="0" size="4" />
+    </Register>
+    <Register name="IER" description="Interrupt Enable Register" start="+0x10" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TSERFIE" description="Additional number of transactions reload interrupt enable" start="10" size="1" access="Read/Write" />
+      <BitField name="MODFIE" description="Mode Fault interrupt enable" start="9" size="1" access="Read/Write" />
+      <BitField name="TIFREIE" description="TIFRE interrupt enable" start="8" size="1" access="Read/Write" />
+      <BitField name="CRCEIE" description="CRC Interrupt enable" start="7" size="1" access="Read/Write" />
+      <BitField name="OVRIE" description="OVR interrupt enable" start="6" size="1" access="Read/Write" />
+      <BitField name="UDRIE" description="UDR interrupt enable" start="5" size="1" access="Read/Write" />
+      <BitField name="TXTFIE" description="TXTFIE interrupt enable" start="4" size="1" access="Read/Write" />
+      <BitField name="EOTIE" description="EOT, SUSP and TXC interrupt enable" start="3" size="1" access="Read/Write" />
+      <BitField name="DPXPIE" description="DXP interrupt enabled" start="2" size="1" access="ReadOnly" />
+      <BitField name="TXPIE" description="TXP interrupt enable" start="1" size="1" access="ReadOnly" />
+      <BitField name="RXPIE" description="RXP Interrupt Enable" start="0" size="1" access="Read/Write" />
+    </Register>
+    <Register name="SR" description="Status Register" start="+0x14" size="4" access="ReadOnly" reset_value="0x00001002" reset_mask="0xFFFFFFFF">
+      <BitField name="CTSIZE" description="Number of data frames remaining in current TSIZE session" start="16" size="16" />
+      <BitField name="RXWNE" description="RxFIFO Word Not Empty" start="15" size="1" />
+      <BitField name="RXPLVL" description="RxFIFO Packing LeVeL" start="13" size="2" />
+      <BitField name="TXC" description="TxFIFO transmission complete" start="12" size="1" />
+      <BitField name="SUSP" description="SUSPend" start="11" size="1" />
+      <BitField name="TSERF" description="Additional number of SPI data to be transacted was reload" start="10" size="1" />
+      <BitField name="MODF" description="Mode Fault" start="9" size="1" />
+      <BitField name="TIFRE" description="TI frame format error" start="8" size="1" />
+      <BitField name="CRCE" description="CRC Error" start="7" size="1" />
+      <BitField name="OVR" description="Overrun" start="6" size="1" />
+      <BitField name="UDR" description="Underrun at slave transmission mode" start="5" size="1" />
+      <BitField name="TXTF" description="Transmission Transfer Filled" start="4" size="1" />
+      <BitField name="EOT" description="End Of Transfer" start="3" size="1" />
+      <BitField name="DXP" description="Duplex Packet" start="2" size="1" />
+      <BitField name="TXP" description="Tx-Packet space available" start="1" size="1" />
+      <BitField name="RXP" description="Rx-Packet available" start="0" size="1" />
+    </Register>
+    <Register name="IFCR" description="Interrupt/Status Flags Clear Register" start="+0x18" size="4" access="WriteOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SUSPC" description="SUSPend flag clear" start="11" size="1" />
+      <BitField name="TSERFC" description="TSERFC flag clear" start="10" size="1" />
+      <BitField name="MODFC" description="Mode Fault flag clear" start="9" size="1" />
+      <BitField name="TIFREC" description="TI frame format error flag clear" start="8" size="1" />
+      <BitField name="CRCEC" description="CRC Error flag clear" start="7" size="1" />
+      <BitField name="OVRC" description="Overrun flag clear" start="6" size="1" />
+      <BitField name="UDRC" description="Underrun flag clear" start="5" size="1" />
+      <BitField name="TXTFC" description="Transmission Transfer Filled flag clear" start="4" size="1" />
+      <BitField name="EOTC" description="End Of Transfer flag clear" start="3" size="1" />
+    </Register>
+    <Register name="TXDR" description="Transmit Data Register" start="+0x20" size="4" access="WriteOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TXDR" description="Transmit data register" start="0" size="32" />
+    </Register>
+    <Register name="RXDR" description="Receive Data Register" start="+0x30" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RXDR" description="Receive data register" start="0" size="32" />
+    </Register>
+    <Register name="CRCPOLY" description="Polynomial Register" start="+0x40" size="4" access="Read/Write" reset_value="0x00000107" reset_mask="0xFFFFFFFF">
+      <BitField name="CRCPOLY" description="CRC polynomial register" start="0" size="32" />
+    </Register>
+    <Register name="TXCRC" description="Transmitter CRC Register" start="+0x44" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TXCRC" description="CRC register for transmitter" start="0" size="32" />
+    </Register>
+    <Register name="RXCRC" description="Receiver CRC Register" start="+0x48" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RXCRC" description="CRC register for receiver" start="0" size="32" />
+    </Register>
+    <Register name="UDRDR" description="Underrun Data Register" start="+0x4C" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="UDRDR" description="Data at slave underrun condition" start="0" size="32" />
+    </Register>
+    <Register name="I2SCFGR" description="configuration register" start="+0x50" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MCKOE" description="Master clock output enable" start="25" size="1" />
+      <BitField name="ODD" description="Odd factor for the prescaler" start="24" size="1" />
+      <BitField name="I2SDIV" description="I2S linear prescaler" start="16" size="8" />
+      <BitField name="DATFMT" description="Data format" start="14" size="1" />
+      <BitField name="WSINV" description="Fixed channel length in SLAVE" start="13" size="1" />
+      <BitField name="FIXCH" description="Word select inversion" start="12" size="1" />
+      <BitField name="CKPOL" description="Serial audio clock polarity" start="11" size="1" />
+      <BitField name="CHLEN" description="Channel length (number of bits per audio channel)" start="10" size="1" />
+      <BitField name="DATLEN" description="Data length to be transferred" start="8" size="2" />
+      <BitField name="PCMSYNC" description="PCM frame synchronization" start="7" size="1" />
+      <BitField name="I2SSTD" description="I2S standard selection" start="4" size="2" />
+      <BitField name="I2SCFG" description="I2S configuration mode" start="1" size="3" />
+      <BitField name="I2SMOD" description="I2S mode selection" start="0" size="1" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="SPI4" description="Serial peripheral interface" start="0x40013400">
+    <Register name="CR1" description="control register 1" start="+0x0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IOLOCK" description="Locking the AF configuration of associated IOs" start="16" size="1" access="ReadOnly" />
+      <BitField name="TCRCI" description="CRC calculation initialization pattern control for transmitter" start="15" size="1" access="Read/Write" />
+      <BitField name="RCRCI" description="CRC calculation initialization pattern control for receiver" start="14" size="1" access="Read/Write" />
+      <BitField name="CRC33_17" description="32-bit CRC polynomial configuration" start="13" size="1" access="Read/Write" />
+      <BitField name="SSI" description="Internal SS signal input level" start="12" size="1" access="Read/Write" />
+      <BitField name="HDDIR" description="Rx/Tx direction at Half-duplex mode" start="11" size="1" access="Read/Write" />
+      <BitField name="CSUSP" description="Master SUSPend request" start="10" size="1" access="WriteOnly" />
+      <BitField name="CSTART" description="Master transfer start" start="9" size="1" access="ReadOnly" />
+      <BitField name="MASRX" description="Master automatic SUSP in Receive mode" start="8" size="1" access="Read/Write" />
+      <BitField name="SPE" description="Serial Peripheral Enable" start="0" size="1" access="Read/Write" />
+    </Register>
+    <Register name="CR2" description="control register 2" start="+0x4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TSER" description="Number of data transfer extension to be reload into TSIZE just when a previous" start="16" size="16" access="ReadOnly" />
+      <BitField name="TSIZE" description="Number of data at current transfer" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="CFG1" description="configuration register 1" start="+0x8" size="4" access="Read/Write" reset_value="0x00070007" reset_mask="0xFFFFFFFF">
+      <BitField name="MBR" description="Master baud rate" start="28" size="3" />
+      <BitField name="CRCEN" description="Hardware CRC computation enable" start="22" size="1" />
+      <BitField name="CRCSIZE" description="Length of CRC frame to be transacted and compared" start="16" size="5" />
+      <BitField name="TXDMAEN" description="Tx DMA stream enable" start="15" size="1" />
+      <BitField name="RXDMAEN" description="Rx DMA stream enable" start="14" size="1" />
+      <BitField name="UDRDET" description="Detection of underrun condition at slave transmitter" start="11" size="2" />
+      <BitField name="UDRCFG" description="Behavior of slave transmitter at underrun condition" start="9" size="2" />
+      <BitField name="FTHVL" description="threshold level" start="5" size="4" />
+      <BitField name="DSIZE" description="Number of bits in at single SPI data frame" start="0" size="5" />
+    </Register>
+    <Register name="CFG2" description="configuration register 2" start="+0xC" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AFCNTR" description="Alternate function GPIOs control" start="31" size="1" />
+      <BitField name="SSOM" description="SS output management in master mode" start="30" size="1" />
+      <BitField name="SSOE" description="SS output enable" start="29" size="1" />
+      <BitField name="SSIOP" description="SS input/output polarity" start="28" size="1" />
+      <BitField name="SSM" description="Software management of SS signal input" start="26" size="1" />
+      <BitField name="CPOL" description="Clock polarity" start="25" size="1" />
+      <BitField name="CPHA" description="Clock phase" start="24" size="1" />
+      <BitField name="LSBFRST" description="Data frame format" start="23" size="1" />
+      <BitField name="MASTER" description="SPI Master" start="22" size="1" />
+      <BitField name="SP" description="Serial Protocol" start="19" size="3" />
+      <BitField name="COMM" description="SPI Communication Mode" start="17" size="2" />
+      <BitField name="IOSWP" description="Swap functionality of MISO and MOSI pins" start="15" size="1" />
+      <BitField name="MIDI" description="Master Inter-Data Idleness" start="4" size="4" />
+      <BitField name="MSSI" description="Master SS Idleness" start="0" size="4" />
+    </Register>
+    <Register name="IER" description="Interrupt Enable Register" start="+0x10" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TSERFIE" description="Additional number of transactions reload interrupt enable" start="10" size="1" access="Read/Write" />
+      <BitField name="MODFIE" description="Mode Fault interrupt enable" start="9" size="1" access="Read/Write" />
+      <BitField name="TIFREIE" description="TIFRE interrupt enable" start="8" size="1" access="Read/Write" />
+      <BitField name="CRCEIE" description="CRC Interrupt enable" start="7" size="1" access="Read/Write" />
+      <BitField name="OVRIE" description="OVR interrupt enable" start="6" size="1" access="Read/Write" />
+      <BitField name="UDRIE" description="UDR interrupt enable" start="5" size="1" access="Read/Write" />
+      <BitField name="TXTFIE" description="TXTFIE interrupt enable" start="4" size="1" access="Read/Write" />
+      <BitField name="EOTIE" description="EOT, SUSP and TXC interrupt enable" start="3" size="1" access="Read/Write" />
+      <BitField name="DPXPIE" description="DXP interrupt enabled" start="2" size="1" access="ReadOnly" />
+      <BitField name="TXPIE" description="TXP interrupt enable" start="1" size="1" access="ReadOnly" />
+      <BitField name="RXPIE" description="RXP Interrupt Enable" start="0" size="1" access="Read/Write" />
+    </Register>
+    <Register name="SR" description="Status Register" start="+0x14" size="4" access="ReadOnly" reset_value="0x00001002" reset_mask="0xFFFFFFFF">
+      <BitField name="CTSIZE" description="Number of data frames remaining in current TSIZE session" start="16" size="16" />
+      <BitField name="RXWNE" description="RxFIFO Word Not Empty" start="15" size="1" />
+      <BitField name="RXPLVL" description="RxFIFO Packing LeVeL" start="13" size="2" />
+      <BitField name="TXC" description="TxFIFO transmission complete" start="12" size="1" />
+      <BitField name="SUSP" description="SUSPend" start="11" size="1" />
+      <BitField name="TSERF" description="Additional number of SPI data to be transacted was reload" start="10" size="1" />
+      <BitField name="MODF" description="Mode Fault" start="9" size="1" />
+      <BitField name="TIFRE" description="TI frame format error" start="8" size="1" />
+      <BitField name="CRCE" description="CRC Error" start="7" size="1" />
+      <BitField name="OVR" description="Overrun" start="6" size="1" />
+      <BitField name="UDR" description="Underrun at slave transmission mode" start="5" size="1" />
+      <BitField name="TXTF" description="Transmission Transfer Filled" start="4" size="1" />
+      <BitField name="EOT" description="End Of Transfer" start="3" size="1" />
+      <BitField name="DXP" description="Duplex Packet" start="2" size="1" />
+      <BitField name="TXP" description="Tx-Packet space available" start="1" size="1" />
+      <BitField name="RXP" description="Rx-Packet available" start="0" size="1" />
+    </Register>
+    <Register name="IFCR" description="Interrupt/Status Flags Clear Register" start="+0x18" size="4" access="WriteOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SUSPC" description="SUSPend flag clear" start="11" size="1" />
+      <BitField name="TSERFC" description="TSERFC flag clear" start="10" size="1" />
+      <BitField name="MODFC" description="Mode Fault flag clear" start="9" size="1" />
+      <BitField name="TIFREC" description="TI frame format error flag clear" start="8" size="1" />
+      <BitField name="CRCEC" description="CRC Error flag clear" start="7" size="1" />
+      <BitField name="OVRC" description="Overrun flag clear" start="6" size="1" />
+      <BitField name="UDRC" description="Underrun flag clear" start="5" size="1" />
+      <BitField name="TXTFC" description="Transmission Transfer Filled flag clear" start="4" size="1" />
+      <BitField name="EOTC" description="End Of Transfer flag clear" start="3" size="1" />
+    </Register>
+    <Register name="TXDR" description="Transmit Data Register" start="+0x20" size="4" access="WriteOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TXDR" description="Transmit data register" start="0" size="32" />
+    </Register>
+    <Register name="RXDR" description="Receive Data Register" start="+0x30" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RXDR" description="Receive data register" start="0" size="32" />
+    </Register>
+    <Register name="CRCPOLY" description="Polynomial Register" start="+0x40" size="4" access="Read/Write" reset_value="0x00000107" reset_mask="0xFFFFFFFF">
+      <BitField name="CRCPOLY" description="CRC polynomial register" start="0" size="32" />
+    </Register>
+    <Register name="TXCRC" description="Transmitter CRC Register" start="+0x44" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TXCRC" description="CRC register for transmitter" start="0" size="32" />
+    </Register>
+    <Register name="RXCRC" description="Receiver CRC Register" start="+0x48" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RXCRC" description="CRC register for receiver" start="0" size="32" />
+    </Register>
+    <Register name="UDRDR" description="Underrun Data Register" start="+0x4C" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="UDRDR" description="Data at slave underrun condition" start="0" size="32" />
+    </Register>
+    <Register name="I2SCFGR" description="configuration register" start="+0x50" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MCKOE" description="Master clock output enable" start="25" size="1" />
+      <BitField name="ODD" description="Odd factor for the prescaler" start="24" size="1" />
+      <BitField name="I2SDIV" description="I2S linear prescaler" start="16" size="8" />
+      <BitField name="DATFMT" description="Data format" start="14" size="1" />
+      <BitField name="WSINV" description="Fixed channel length in SLAVE" start="13" size="1" />
+      <BitField name="FIXCH" description="Word select inversion" start="12" size="1" />
+      <BitField name="CKPOL" description="Serial audio clock polarity" start="11" size="1" />
+      <BitField name="CHLEN" description="Channel length (number of bits per audio channel)" start="10" size="1" />
+      <BitField name="DATLEN" description="Data length to be transferred" start="8" size="2" />
+      <BitField name="PCMSYNC" description="PCM frame synchronization" start="7" size="1" />
+      <BitField name="I2SSTD" description="I2S standard selection" start="4" size="2" />
+      <BitField name="I2SCFG" description="I2S configuration mode" start="1" size="3" />
+      <BitField name="I2SMOD" description="I2S mode selection" start="0" size="1" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="SPI5" description="Serial peripheral interface" start="0x40015000">
+    <Register name="CR1" description="control register 1" start="+0x0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IOLOCK" description="Locking the AF configuration of associated IOs" start="16" size="1" access="ReadOnly" />
+      <BitField name="TCRCI" description="CRC calculation initialization pattern control for transmitter" start="15" size="1" access="Read/Write" />
+      <BitField name="RCRCI" description="CRC calculation initialization pattern control for receiver" start="14" size="1" access="Read/Write" />
+      <BitField name="CRC33_17" description="32-bit CRC polynomial configuration" start="13" size="1" access="Read/Write" />
+      <BitField name="SSI" description="Internal SS signal input level" start="12" size="1" access="Read/Write" />
+      <BitField name="HDDIR" description="Rx/Tx direction at Half-duplex mode" start="11" size="1" access="Read/Write" />
+      <BitField name="CSUSP" description="Master SUSPend request" start="10" size="1" access="WriteOnly" />
+      <BitField name="CSTART" description="Master transfer start" start="9" size="1" access="ReadOnly" />
+      <BitField name="MASRX" description="Master automatic SUSP in Receive mode" start="8" size="1" access="Read/Write" />
+      <BitField name="SPE" description="Serial Peripheral Enable" start="0" size="1" access="Read/Write" />
+    </Register>
+    <Register name="CR2" description="control register 2" start="+0x4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TSER" description="Number of data transfer extension to be reload into TSIZE just when a previous" start="16" size="16" access="ReadOnly" />
+      <BitField name="TSIZE" description="Number of data at current transfer" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="CFG1" description="configuration register 1" start="+0x8" size="4" access="Read/Write" reset_value="0x00070007" reset_mask="0xFFFFFFFF">
+      <BitField name="MBR" description="Master baud rate" start="28" size="3" />
+      <BitField name="CRCEN" description="Hardware CRC computation enable" start="22" size="1" />
+      <BitField name="CRCSIZE" description="Length of CRC frame to be transacted and compared" start="16" size="5" />
+      <BitField name="TXDMAEN" description="Tx DMA stream enable" start="15" size="1" />
+      <BitField name="RXDMAEN" description="Rx DMA stream enable" start="14" size="1" />
+      <BitField name="UDRDET" description="Detection of underrun condition at slave transmitter" start="11" size="2" />
+      <BitField name="UDRCFG" description="Behavior of slave transmitter at underrun condition" start="9" size="2" />
+      <BitField name="FTHVL" description="threshold level" start="5" size="4" />
+      <BitField name="DSIZE" description="Number of bits in at single SPI data frame" start="0" size="5" />
+    </Register>
+    <Register name="CFG2" description="configuration register 2" start="+0xC" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AFCNTR" description="Alternate function GPIOs control" start="31" size="1" />
+      <BitField name="SSOM" description="SS output management in master mode" start="30" size="1" />
+      <BitField name="SSOE" description="SS output enable" start="29" size="1" />
+      <BitField name="SSIOP" description="SS input/output polarity" start="28" size="1" />
+      <BitField name="SSM" description="Software management of SS signal input" start="26" size="1" />
+      <BitField name="CPOL" description="Clock polarity" start="25" size="1" />
+      <BitField name="CPHA" description="Clock phase" start="24" size="1" />
+      <BitField name="LSBFRST" description="Data frame format" start="23" size="1" />
+      <BitField name="MASTER" description="SPI Master" start="22" size="1" />
+      <BitField name="SP" description="Serial Protocol" start="19" size="3" />
+      <BitField name="COMM" description="SPI Communication Mode" start="17" size="2" />
+      <BitField name="IOSWP" description="Swap functionality of MISO and MOSI pins" start="15" size="1" />
+      <BitField name="MIDI" description="Master Inter-Data Idleness" start="4" size="4" />
+      <BitField name="MSSI" description="Master SS Idleness" start="0" size="4" />
+    </Register>
+    <Register name="IER" description="Interrupt Enable Register" start="+0x10" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TSERFIE" description="Additional number of transactions reload interrupt enable" start="10" size="1" access="Read/Write" />
+      <BitField name="MODFIE" description="Mode Fault interrupt enable" start="9" size="1" access="Read/Write" />
+      <BitField name="TIFREIE" description="TIFRE interrupt enable" start="8" size="1" access="Read/Write" />
+      <BitField name="CRCEIE" description="CRC Interrupt enable" start="7" size="1" access="Read/Write" />
+      <BitField name="OVRIE" description="OVR interrupt enable" start="6" size="1" access="Read/Write" />
+      <BitField name="UDRIE" description="UDR interrupt enable" start="5" size="1" access="Read/Write" />
+      <BitField name="TXTFIE" description="TXTFIE interrupt enable" start="4" size="1" access="Read/Write" />
+      <BitField name="EOTIE" description="EOT, SUSP and TXC interrupt enable" start="3" size="1" access="Read/Write" />
+      <BitField name="DPXPIE" description="DXP interrupt enabled" start="2" size="1" access="ReadOnly" />
+      <BitField name="TXPIE" description="TXP interrupt enable" start="1" size="1" access="ReadOnly" />
+      <BitField name="RXPIE" description="RXP Interrupt Enable" start="0" size="1" access="Read/Write" />
+    </Register>
+    <Register name="SR" description="Status Register" start="+0x14" size="4" access="ReadOnly" reset_value="0x00001002" reset_mask="0xFFFFFFFF">
+      <BitField name="CTSIZE" description="Number of data frames remaining in current TSIZE session" start="16" size="16" />
+      <BitField name="RXWNE" description="RxFIFO Word Not Empty" start="15" size="1" />
+      <BitField name="RXPLVL" description="RxFIFO Packing LeVeL" start="13" size="2" />
+      <BitField name="TXC" description="TxFIFO transmission complete" start="12" size="1" />
+      <BitField name="SUSP" description="SUSPend" start="11" size="1" />
+      <BitField name="TSERF" description="Additional number of SPI data to be transacted was reload" start="10" size="1" />
+      <BitField name="MODF" description="Mode Fault" start="9" size="1" />
+      <BitField name="TIFRE" description="TI frame format error" start="8" size="1" />
+      <BitField name="CRCE" description="CRC Error" start="7" size="1" />
+      <BitField name="OVR" description="Overrun" start="6" size="1" />
+      <BitField name="UDR" description="Underrun at slave transmission mode" start="5" size="1" />
+      <BitField name="TXTF" description="Transmission Transfer Filled" start="4" size="1" />
+      <BitField name="EOT" description="End Of Transfer" start="3" size="1" />
+      <BitField name="DXP" description="Duplex Packet" start="2" size="1" />
+      <BitField name="TXP" description="Tx-Packet space available" start="1" size="1" />
+      <BitField name="RXP" description="Rx-Packet available" start="0" size="1" />
+    </Register>
+    <Register name="IFCR" description="Interrupt/Status Flags Clear Register" start="+0x18" size="4" access="WriteOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SUSPC" description="SUSPend flag clear" start="11" size="1" />
+      <BitField name="TSERFC" description="TSERFC flag clear" start="10" size="1" />
+      <BitField name="MODFC" description="Mode Fault flag clear" start="9" size="1" />
+      <BitField name="TIFREC" description="TI frame format error flag clear" start="8" size="1" />
+      <BitField name="CRCEC" description="CRC Error flag clear" start="7" size="1" />
+      <BitField name="OVRC" description="Overrun flag clear" start="6" size="1" />
+      <BitField name="UDRC" description="Underrun flag clear" start="5" size="1" />
+      <BitField name="TXTFC" description="Transmission Transfer Filled flag clear" start="4" size="1" />
+      <BitField name="EOTC" description="End Of Transfer flag clear" start="3" size="1" />
+    </Register>
+    <Register name="TXDR" description="Transmit Data Register" start="+0x20" size="4" access="WriteOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TXDR" description="Transmit data register" start="0" size="32" />
+    </Register>
+    <Register name="RXDR" description="Receive Data Register" start="+0x30" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RXDR" description="Receive data register" start="0" size="32" />
+    </Register>
+    <Register name="CRCPOLY" description="Polynomial Register" start="+0x40" size="4" access="Read/Write" reset_value="0x00000107" reset_mask="0xFFFFFFFF">
+      <BitField name="CRCPOLY" description="CRC polynomial register" start="0" size="32" />
+    </Register>
+    <Register name="TXCRC" description="Transmitter CRC Register" start="+0x44" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TXCRC" description="CRC register for transmitter" start="0" size="32" />
+    </Register>
+    <Register name="RXCRC" description="Receiver CRC Register" start="+0x48" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RXCRC" description="CRC register for receiver" start="0" size="32" />
+    </Register>
+    <Register name="UDRDR" description="Underrun Data Register" start="+0x4C" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="UDRDR" description="Data at slave underrun condition" start="0" size="32" />
+    </Register>
+    <Register name="I2SCFGR" description="configuration register" start="+0x50" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MCKOE" description="Master clock output enable" start="25" size="1" />
+      <BitField name="ODD" description="Odd factor for the prescaler" start="24" size="1" />
+      <BitField name="I2SDIV" description="I2S linear prescaler" start="16" size="8" />
+      <BitField name="DATFMT" description="Data format" start="14" size="1" />
+      <BitField name="WSINV" description="Fixed channel length in SLAVE" start="13" size="1" />
+      <BitField name="FIXCH" description="Word select inversion" start="12" size="1" />
+      <BitField name="CKPOL" description="Serial audio clock polarity" start="11" size="1" />
+      <BitField name="CHLEN" description="Channel length (number of bits per audio channel)" start="10" size="1" />
+      <BitField name="DATLEN" description="Data length to be transferred" start="8" size="2" />
+      <BitField name="PCMSYNC" description="PCM frame synchronization" start="7" size="1" />
+      <BitField name="I2SSTD" description="I2S standard selection" start="4" size="2" />
+      <BitField name="I2SCFG" description="I2S configuration mode" start="1" size="3" />
+      <BitField name="I2SMOD" description="I2S mode selection" start="0" size="1" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="SPI6" description="Serial peripheral interface" start="0x58001400">
+    <Register name="CR1" description="control register 1" start="+0x0" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IOLOCK" description="Locking the AF configuration of associated IOs" start="16" size="1" access="ReadOnly" />
+      <BitField name="TCRCI" description="CRC calculation initialization pattern control for transmitter" start="15" size="1" access="Read/Write" />
+      <BitField name="RCRCI" description="CRC calculation initialization pattern control for receiver" start="14" size="1" access="Read/Write" />
+      <BitField name="CRC33_17" description="32-bit CRC polynomial configuration" start="13" size="1" access="Read/Write" />
+      <BitField name="SSI" description="Internal SS signal input level" start="12" size="1" access="Read/Write" />
+      <BitField name="HDDIR" description="Rx/Tx direction at Half-duplex mode" start="11" size="1" access="Read/Write" />
+      <BitField name="CSUSP" description="Master SUSPend request" start="10" size="1" access="WriteOnly" />
+      <BitField name="CSTART" description="Master transfer start" start="9" size="1" access="ReadOnly" />
+      <BitField name="MASRX" description="Master automatic SUSP in Receive mode" start="8" size="1" access="Read/Write" />
+      <BitField name="SPE" description="Serial Peripheral Enable" start="0" size="1" access="Read/Write" />
+    </Register>
+    <Register name="CR2" description="control register 2" start="+0x4" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TSER" description="Number of data transfer extension to be reload into TSIZE just when a previous" start="16" size="16" access="ReadOnly" />
+      <BitField name="TSIZE" description="Number of data at current transfer" start="0" size="16" access="Read/Write" />
+    </Register>
+    <Register name="CFG1" description="configuration register 1" start="+0x8" size="4" access="Read/Write" reset_value="0x00070007" reset_mask="0xFFFFFFFF">
+      <BitField name="MBR" description="Master baud rate" start="28" size="3" />
+      <BitField name="CRCEN" description="Hardware CRC computation enable" start="22" size="1" />
+      <BitField name="CRCSIZE" description="Length of CRC frame to be transacted and compared" start="16" size="5" />
+      <BitField name="TXDMAEN" description="Tx DMA stream enable" start="15" size="1" />
+      <BitField name="RXDMAEN" description="Rx DMA stream enable" start="14" size="1" />
+      <BitField name="UDRDET" description="Detection of underrun condition at slave transmitter" start="11" size="2" />
+      <BitField name="UDRCFG" description="Behavior of slave transmitter at underrun condition" start="9" size="2" />
+      <BitField name="FTHVL" description="threshold level" start="5" size="4" />
+      <BitField name="DSIZE" description="Number of bits in at single SPI data frame" start="0" size="5" />
+    </Register>
+    <Register name="CFG2" description="configuration register 2" start="+0xC" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="AFCNTR" description="Alternate function GPIOs control" start="31" size="1" />
+      <BitField name="SSOM" description="SS output management in master mode" start="30" size="1" />
+      <BitField name="SSOE" description="SS output enable" start="29" size="1" />
+      <BitField name="SSIOP" description="SS input/output polarity" start="28" size="1" />
+      <BitField name="SSM" description="Software management of SS signal input" start="26" size="1" />
+      <BitField name="CPOL" description="Clock polarity" start="25" size="1" />
+      <BitField name="CPHA" description="Clock phase" start="24" size="1" />
+      <BitField name="LSBFRST" description="Data frame format" start="23" size="1" />
+      <BitField name="MASTER" description="SPI Master" start="22" size="1" />
+      <BitField name="SP" description="Serial Protocol" start="19" size="3" />
+      <BitField name="COMM" description="SPI Communication Mode" start="17" size="2" />
+      <BitField name="IOSWP" description="Swap functionality of MISO and MOSI pins" start="15" size="1" />
+      <BitField name="MIDI" description="Master Inter-Data Idleness" start="4" size="4" />
+      <BitField name="MSSI" description="Master SS Idleness" start="0" size="4" />
+    </Register>
+    <Register name="IER" description="Interrupt Enable Register" start="+0x10" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TSERFIE" description="Additional number of transactions reload interrupt enable" start="10" size="1" access="Read/Write" />
+      <BitField name="MODFIE" description="Mode Fault interrupt enable" start="9" size="1" access="Read/Write" />
+      <BitField name="TIFREIE" description="TIFRE interrupt enable" start="8" size="1" access="Read/Write" />
+      <BitField name="CRCEIE" description="CRC Interrupt enable" start="7" size="1" access="Read/Write" />
+      <BitField name="OVRIE" description="OVR interrupt enable" start="6" size="1" access="Read/Write" />
+      <BitField name="UDRIE" description="UDR interrupt enable" start="5" size="1" access="Read/Write" />
+      <BitField name="TXTFIE" description="TXTFIE interrupt enable" start="4" size="1" access="Read/Write" />
+      <BitField name="EOTIE" description="EOT, SUSP and TXC interrupt enable" start="3" size="1" access="Read/Write" />
+      <BitField name="DPXPIE" description="DXP interrupt enabled" start="2" size="1" access="ReadOnly" />
+      <BitField name="TXPIE" description="TXP interrupt enable" start="1" size="1" access="ReadOnly" />
+      <BitField name="RXPIE" description="RXP Interrupt Enable" start="0" size="1" access="Read/Write" />
+    </Register>
+    <Register name="SR" description="Status Register" start="+0x14" size="4" access="ReadOnly" reset_value="0x00001002" reset_mask="0xFFFFFFFF">
+      <BitField name="CTSIZE" description="Number of data frames remaining in current TSIZE session" start="16" size="16" />
+      <BitField name="RXWNE" description="RxFIFO Word Not Empty" start="15" size="1" />
+      <BitField name="RXPLVL" description="RxFIFO Packing LeVeL" start="13" size="2" />
+      <BitField name="TXC" description="TxFIFO transmission complete" start="12" size="1" />
+      <BitField name="SUSP" description="SUSPend" start="11" size="1" />
+      <BitField name="TSERF" description="Additional number of SPI data to be transacted was reload" start="10" size="1" />
+      <BitField name="MODF" description="Mode Fault" start="9" size="1" />
+      <BitField name="TIFRE" description="TI frame format error" start="8" size="1" />
+      <BitField name="CRCE" description="CRC Error" start="7" size="1" />
+      <BitField name="OVR" description="Overrun" start="6" size="1" />
+      <BitField name="UDR" description="Underrun at slave transmission mode" start="5" size="1" />
+      <BitField name="TXTF" description="Transmission Transfer Filled" start="4" size="1" />
+      <BitField name="EOT" description="End Of Transfer" start="3" size="1" />
+      <BitField name="DXP" description="Duplex Packet" start="2" size="1" />
+      <BitField name="TXP" description="Tx-Packet space available" start="1" size="1" />
+      <BitField name="RXP" description="Rx-Packet available" start="0" size="1" />
+    </Register>
+    <Register name="IFCR" description="Interrupt/Status Flags Clear Register" start="+0x18" size="4" access="WriteOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SUSPC" description="SUSPend flag clear" start="11" size="1" />
+      <BitField name="TSERFC" description="TSERFC flag clear" start="10" size="1" />
+      <BitField name="MODFC" description="Mode Fault flag clear" start="9" size="1" />
+      <BitField name="TIFREC" description="TI frame format error flag clear" start="8" size="1" />
+      <BitField name="CRCEC" description="CRC Error flag clear" start="7" size="1" />
+      <BitField name="OVRC" description="Overrun flag clear" start="6" size="1" />
+      <BitField name="UDRC" description="Underrun flag clear" start="5" size="1" />
+      <BitField name="TXTFC" description="Transmission Transfer Filled flag clear" start="4" size="1" />
+      <BitField name="EOTC" description="End Of Transfer flag clear" start="3" size="1" />
+    </Register>
+    <Register name="TXDR" description="Transmit Data Register" start="+0x20" size="4" access="WriteOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TXDR" description="Transmit data register" start="0" size="32" />
+    </Register>
+    <Register name="RXDR" description="Receive Data Register" start="+0x30" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RXDR" description="Receive data register" start="0" size="32" />
+    </Register>
+    <Register name="CRCPOLY" description="Polynomial Register" start="+0x40" size="4" access="Read/Write" reset_value="0x00000107" reset_mask="0xFFFFFFFF">
+      <BitField name="CRCPOLY" description="CRC polynomial register" start="0" size="32" />
+    </Register>
+    <Register name="TXCRC" description="Transmitter CRC Register" start="+0x44" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TXCRC" description="CRC register for transmitter" start="0" size="32" />
+    </Register>
+    <Register name="RXCRC" description="Receiver CRC Register" start="+0x48" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RXCRC" description="CRC register for receiver" start="0" size="32" />
+    </Register>
+    <Register name="UDRDR" description="Underrun Data Register" start="+0x4C" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="UDRDR" description="Data at slave underrun condition" start="0" size="32" />
+    </Register>
+    <Register name="I2SCFGR" description="configuration register" start="+0x50" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MCKOE" description="Master clock output enable" start="25" size="1" />
+      <BitField name="ODD" description="Odd factor for the prescaler" start="24" size="1" />
+      <BitField name="I2SDIV" description="I2S linear prescaler" start="16" size="8" />
+      <BitField name="DATFMT" description="Data format" start="14" size="1" />
+      <BitField name="WSINV" description="Fixed channel length in SLAVE" start="13" size="1" />
+      <BitField name="FIXCH" description="Word select inversion" start="12" size="1" />
+      <BitField name="CKPOL" description="Serial audio clock polarity" start="11" size="1" />
+      <BitField name="CHLEN" description="Channel length (number of bits per audio channel)" start="10" size="1" />
+      <BitField name="DATLEN" description="Data length to be transferred" start="8" size="2" />
+      <BitField name="PCMSYNC" description="PCM frame synchronization" start="7" size="1" />
+      <BitField name="I2SSTD" description="I2S standard selection" start="4" size="2" />
+      <BitField name="I2SCFG" description="I2S configuration mode" start="1" size="3" />
+      <BitField name="I2SMOD" description="I2S mode selection" start="0" size="1" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="STK" description="SysTick timer" start="0xE000E010">
+    <Register name="CSR" description="SysTick control and status register" start="+0x0" size="4" access="Read/Write" reset_value="0X00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ENABLE" description="Counter enable" start="0" size="1" />
+      <BitField name="TICKINT" description="SysTick exception request enable" start="1" size="1" />
+      <BitField name="CLKSOURCE" description="Clock source selection" start="2" size="1" />
+      <BitField name="COUNTFLAG" description="COUNTFLAG" start="16" size="1" />
+    </Register>
+    <Register name="RVR" description="SysTick reload value register" start="+0x4" size="4" access="Read/Write" reset_value="0X00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RELOAD" description="RELOAD value" start="0" size="24" />
+    </Register>
+    <Register name="CVR" description="SysTick current value register" start="+0x8" size="4" access="Read/Write" reset_value="0X00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CURRENT" description="Current counter value" start="0" size="24" />
+    </Register>
+    <Register name="CALIB" description="SysTick calibration value register" start="+0xC" size="4" access="Read/Write" reset_value="0X00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TENMS" description="Calibration value" start="0" size="24" />
+      <BitField name="SKEW" description="SKEW flag: Indicates whether the TENMS value is exact" start="30" size="1" />
+      <BitField name="NOREF" description="NOREF flag. Reads as zero" start="31" size="1" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="SWPMI" description="Single Wire Protocol Master Interface" start="0x40008800">
+    <Register name="CR" description="SWPMI Configuration/Control register" start="+0x0" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RXDMA" description="Reception DMA enable" start="0" size="1" />
+      <BitField name="TXDMA" description="Transmission DMA enable" start="1" size="1" />
+      <BitField name="RXMODE" description="Reception buffering mode" start="2" size="1" />
+      <BitField name="TXMODE" description="Transmission buffering mode" start="3" size="1" />
+      <BitField name="LPBK" description="Loopback mode enable" start="4" size="1" />
+      <BitField name="SWPACT" description="Single wire protocol master interface activate" start="5" size="1" />
+      <BitField name="DEACT" description="Single wire protocol master interface deactivate" start="10" size="1" />
+      <BitField name="SWPTEN" description="Single wire protocol master transceiver enable" start="11" size="1" />
+    </Register>
+    <Register name="BRR" description="SWPMI Bitrate register" start="+0x4" size="4" access="Read/Write" reset_value="0x00000001" reset_mask="0xFFFFFFFF">
+      <BitField name="BR" description="Bitrate prescaler" start="0" size="8" />
+    </Register>
+    <Register name="ISR" description="SWPMI Interrupt and Status register" start="+0xC" size="4" access="ReadOnly" reset_value="0x000002C2" reset_mask="0xFFFFFFFF">
+      <BitField name="RXBFF" description="Receive buffer full flag" start="0" size="1" />
+      <BitField name="TXBEF" description="Transmit buffer empty flag" start="1" size="1" />
+      <BitField name="RXBERF" description="Receive CRC error flag" start="2" size="1" />
+      <BitField name="RXOVRF" description="Receive overrun error flag" start="3" size="1" />
+      <BitField name="TXUNRF" description="Transmit underrun error flag" start="4" size="1" />
+      <BitField name="RXNE" description="Receive data register not empty" start="5" size="1" />
+      <BitField name="TXE" description="Transmit data register empty" start="6" size="1" />
+      <BitField name="TCF" description="Transfer complete flag" start="7" size="1" />
+      <BitField name="SRF" description="Slave resume flag" start="8" size="1" />
+      <BitField name="SUSP" description="SUSPEND flag" start="9" size="1" />
+      <BitField name="DEACTF" description="DEACTIVATED flag" start="10" size="1" />
+      <BitField name="RDYF" description="transceiver ready flag" start="11" size="1" />
+    </Register>
+    <Register name="ICR" description="SWPMI Interrupt Flag Clear register" start="+0x10" size="4" access="WriteOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CRXBFF" description="Clear receive buffer full flag" start="0" size="1" />
+      <BitField name="CTXBEF" description="Clear transmit buffer empty flag" start="1" size="1" />
+      <BitField name="CRXBERF" description="Clear receive CRC error flag" start="2" size="1" />
+      <BitField name="CRXOVRF" description="Clear receive overrun error flag" start="3" size="1" />
+      <BitField name="CTXUNRF" description="Clear transmit underrun error flag" start="4" size="1" />
+      <BitField name="CTCF" description="Clear transfer complete flag" start="7" size="1" />
+      <BitField name="CSRF" description="Clear slave resume flag" start="8" size="1" />
+      <BitField name="CRDYF" description="Clear transceiver ready flag" start="11" size="1" />
+    </Register>
+    <Register name="IER" description="SWPMI Interrupt Enable register" start="+0x14" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RXBFIE" description="Receive buffer full interrupt enable" start="0" size="1" />
+      <BitField name="TXBEIE" description="Transmit buffer empty interrupt enable" start="1" size="1" />
+      <BitField name="RXBERIE" description="Receive CRC error interrupt enable" start="2" size="1" />
+      <BitField name="RXOVRIE" description="Receive overrun error interrupt enable" start="3" size="1" />
+      <BitField name="TXUNRIE" description="Transmit underrun error interrupt enable" start="4" size="1" />
+      <BitField name="RIE" description="Receive interrupt enable" start="5" size="1" />
+      <BitField name="TIE" description="Transmit interrupt enable" start="6" size="1" />
+      <BitField name="TCIE" description="Transmit complete interrupt enable" start="7" size="1" />
+      <BitField name="SRIE" description="Slave resume interrupt enable" start="8" size="1" />
+      <BitField name="RDYIE" description="Transceiver ready interrupt enable" start="11" size="1" />
+    </Register>
+    <Register name="RFL" description="SWPMI Receive Frame Length register" start="+0x18" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RFL" description="Receive frame length" start="0" size="5" />
+    </Register>
+    <Register name="TDR" description="SWPMI Transmit data register" start="+0x1C" size="4" access="WriteOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TD" description="Transmit data" start="0" size="32" />
+    </Register>
+    <Register name="RDR" description="SWPMI Receive data register" start="+0x20" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="RD" description="received data" start="0" size="32" />
+    </Register>
+    <Register name="OR" description="SWPMI Option register" start="+0x24" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SWP_TBYP" description="SWP transceiver bypass" start="0" size="1" />
+      <BitField name="SWP_CLASS" description="SWP class selection" start="1" size="1" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="SYSCFG" description="System configuration controller" start="0x58000400">
+    <Register name="PMCR" description="peripheral mode configuration register" start="+0x4" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="I2C1FMP" description="I2C1 Fm+" start="0" size="1" />
+      <BitField name="I2C2FMP" description="I2C2 Fm+" start="1" size="1" />
+      <BitField name="I2C3FMP" description="I2C3 Fm+" start="2" size="1" />
+      <BitField name="I2C4FMP" description="I2C4 Fm+" start="3" size="1" />
+      <BitField name="PB6FMP" description="PB(6) Fm+" start="4" size="1" />
+      <BitField name="PB7FMP" description="PB(7) Fast Mode Plus" start="5" size="1" />
+      <BitField name="PB8FMP" description="PB(8) Fast Mode Plus" start="6" size="1" />
+      <BitField name="PB9FMP" description="PB(9) Fm+" start="7" size="1" />
+      <BitField name="BOOSTE" description="Booster Enable" start="8" size="1" />
+      <BitField name="EPIS" description="Ethernet PHY Interface Selection" start="21" size="3" />
+      <BitField name="PA0SO" description="PA0 Switch Open" start="24" size="1" />
+      <BitField name="PA1SO" description="PA1 Switch Open" start="25" size="1" />
+      <BitField name="PC2SO" description="PC2 Switch Open" start="26" size="1" />
+      <BitField name="PC3SO" description="PC3 Switch Open" start="27" size="1" />
+    </Register>
+    <Register name="EXTICR1" description="external interrupt configuration register 1" start="+0x8" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="EXTI3" description="EXTI x configuration (x = 0 to 3)" start="12" size="4" />
+      <BitField name="EXTI2" description="EXTI x configuration (x = 0 to 3)" start="8" size="4" />
+      <BitField name="EXTI1" description="EXTI x configuration (x = 0 to 3)" start="4" size="4" />
+      <BitField name="EXTI0" description="EXTI x configuration (x = 0 to 3)" start="0" size="4" />
+    </Register>
+    <Register name="EXTICR2" description="external interrupt configuration register 2" start="+0xC" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="EXTI7" description="EXTI x configuration (x = 4 to 7)" start="12" size="4" />
+      <BitField name="EXTI6" description="EXTI x configuration (x = 4 to 7)" start="8" size="4" />
+      <BitField name="EXTI5" description="EXTI x configuration (x = 4 to 7)" start="4" size="4" />
+      <BitField name="EXTI4" description="EXTI x configuration (x = 4 to 7)" start="0" size="4" />
+    </Register>
+    <Register name="EXTICR3" description="external interrupt configuration register 3" start="+0x10" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="EXTI11" description="EXTI x configuration (x = 8 to 11)" start="12" size="4" />
+      <BitField name="EXTI10" description="EXTI10" start="8" size="4" />
+      <BitField name="EXTI9" description="EXTI x configuration (x = 8 to 11)" start="4" size="4" />
+      <BitField name="EXTI8" description="EXTI x configuration (x = 8 to 11)" start="0" size="4" />
+    </Register>
+    <Register name="EXTICR4" description="external interrupt configuration register 4" start="+0x14" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="EXTI15" description="EXTI x configuration (x = 12 to 15)" start="12" size="4" />
+      <BitField name="EXTI14" description="EXTI x configuration (x = 12 to 15)" start="8" size="4" />
+      <BitField name="EXTI13" description="EXTI x configuration (x = 12 to 15)" start="4" size="4" />
+      <BitField name="EXTI12" description="EXTI x configuration (x = 12 to 15)" start="0" size="4" />
+    </Register>
+    <Register name="CCCSR" description="compensation cell control/status register" start="+0x20" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EN" description="enable" start="0" size="1" />
+      <BitField name="CS" description="Code selection" start="1" size="1" />
+      <BitField name="READY" description="Compensation cell ready flag" start="8" size="1" />
+      <BitField name="HSLV" description="High-speed at low-voltage" start="16" size="1" />
+    </Register>
+    <Register name="CCVR" description="SYSCFG compensation cell value register" start="+0x24" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="NCV" description="NMOS compensation value" start="0" size="4" />
+      <BitField name="PCV" description="PMOS compensation value" start="4" size="4" />
+    </Register>
+    <Register name="CCCR" description="SYSCFG compensation cell code register" start="+0x28" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="NCC" description="NMOS compensation code" start="0" size="4" />
+      <BitField name="PCC" description="PMOS compensation code" start="4" size="4" />
+    </Register>
+    <Register name="PKGR" description="SYSCFG package register" start="+0x124" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PKG" description="Package" start="0" size="4" />
+    </Register>
+    <Register name="UR0" description="SYSCFG user register 0" start="+0x300" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BKS" description="Bank Swap" start="0" size="1" />
+      <BitField name="RDP" description="Readout protection" start="16" size="8" />
+    </Register>
+    <Register name="UR2" description="SYSCFG user register 2" start="+0x308" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BORH" description="BOR_LVL Brownout Reset Threshold Level" start="0" size="2" />
+      <BitField name="BOOT_ADD0" description="Boot Address 0" start="16" size="16" />
+    </Register>
+    <Register name="UR3" description="SYSCFG user register 3" start="+0x30C" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="BOOT_ADD1" description="Boot Address 1" start="16" size="16" />
+    </Register>
+    <Register name="UR4" description="SYSCFG user register 4" start="+0x310" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MEPAD_1" description="Mass Erase Protected Area Disabled for bank 1" start="16" size="1" />
+    </Register>
+    <Register name="UR5" description="SYSCFG user register 5" start="+0x314" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MESAD_1" description="Mass erase secured area disabled for bank 1" start="0" size="1" />
+      <BitField name="WRPN_1" description="Write protection for flash bank 1" start="16" size="8" />
+    </Register>
+    <Register name="UR6" description="SYSCFG user register 6" start="+0x318" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PA_BEG_1" description="Protected area start address for bank 1" start="0" size="12" />
+      <BitField name="PA_END_1" description="Protected area end address for bank 1" start="16" size="12" />
+    </Register>
+    <Register name="UR7" description="SYSCFG user register 7" start="+0x31C" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SA_BEG_1" description="Secured area start address for bank 1" start="0" size="12" />
+      <BitField name="SA_END_1" description="Secured area end address for bank 1" start="16" size="12" />
+    </Register>
+    <Register name="UR8" description="SYSCFG user register 8" start="+0x320" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="MEPAD_2" description="Mass erase protected area disabled for bank 2" start="0" size="1" />
+      <BitField name="MESAD_2" description="Mass erase secured area disabled for bank 2" start="16" size="1" />
+    </Register>
+    <Register name="UR9" description="SYSCFG user register 9" start="+0x324" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="WRPN_2" description="Write protection for flash bank 2" start="0" size="8" />
+      <BitField name="PA_BEG_2" description="Protected area start address for bank 2" start="16" size="12" />
+    </Register>
+    <Register name="UR10" description="SYSCFG user register 10" start="+0x328" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="PA_END_2" description="Protected area end address for bank 2" start="0" size="12" />
+      <BitField name="SA_BEG_2" description="Secured area start address for bank 2" start="16" size="12" />
+    </Register>
+    <Register name="UR11" description="SYSCFG user register 11" start="+0x32C" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SA_END_2" description="Secured area end address for bank 2" start="0" size="12" />
+      <BitField name="IWDG1M" description="Independent Watchdog 1 mode" start="16" size="1" />
+    </Register>
+    <Register name="UR12" description="SYSCFG user register 12" start="+0x330" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SECURE" description="Secure mode" start="16" size="1" />
+    </Register>
+    <Register name="UR13" description="SYSCFG user register 13" start="+0x334" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="SDRS" description="Secured DTCM RAM Size" start="0" size="2" />
+      <BitField name="D1SBRST" description="D1 Standby reset" start="16" size="1" />
+    </Register>
+    <Register name="UR14" description="SYSCFG user register 14" start="+0x338" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="D1STPRST" description="D1 Stop Reset" start="0" size="1" />
+    </Register>
+    <Register name="UR15" description="SYSCFG user register 15" start="+0x33C" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FZIWDGSTB" description="Freeze independent watchdog in Standby mode" start="16" size="1" />
+    </Register>
+    <Register name="UR16" description="SYSCFG user register 16" start="+0x340" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="FZIWDGSTP" description="Freeze independent watchdog in Stop mode" start="0" size="1" />
+      <BitField name="PKP" description="Private key programmed" start="16" size="1" />
+    </Register>
+    <Register name="UR17" description="SYSCFG user register 17" start="+0x344" size="4" access="ReadOnly" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IO_HSLV" description="I/O high speed / low voltage" start="0" size="1" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="TIM1" description="Advanced-timers" start="0x40010000">
+    <Register name="CR1" description="control register 1" start="+0x0" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="CEN" description="Counter enable" start="0" size="1" />
+      <BitField name="UDIS" description="Update disable" start="1" size="1" />
+      <BitField name="URS" description="Update request source" start="2" size="1" />
+      <BitField name="OPM" description="One-pulse mode" start="3" size="1" />
+      <BitField name="DIR" description="Direction" start="4" size="1" />
+      <BitField name="CMS" description="Center-aligned mode selection" start="5" size="2" />
+      <BitField name="ARPE" description="Auto-reload preload enable" start="7" size="1" />
+      <BitField name="CKD" description="Clock division" start="8" size="2" />
+      <BitField name="UIFREMAP" description="UIF status bit remapping" start="11" size="1" />
+    </Register>
+    <Register name="CR2" description="control register 2" start="+0x4" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="MMS2" description="Master mode selection 2" start="20" size="4" />
+      <BitField name="OIS6" description="Output Idle state 6" start="18" size="1" />
+      <BitField name="OIS5" description="Output Idle state 5" start="16" size="1" />
+      <BitField name="OIS4" description="Output Idle state 4" start="14" size="1" />
+      <BitField name="OIS3N" description="Output Idle state 3" start="13" size="1" />
+      <BitField name="OIS3" description="Output Idle state 3" start="12" size="1" />
+      <BitField name="OIS2N" description="Output Idle state 2" start="11" size="1" />
+      <BitField name="OIS2" description="Output Idle state 2" start="10" size="1" />
+      <BitField name="OIS1N" description="Output Idle state 1" start="9" size="1" />
+      <BitField name="OIS1" description="Output Idle state 1" start="8" size="1" />
+      <BitField name="TI1S" description="TI1 selection" start="7" size="1" />
+      <BitField name="MMS" description="Master mode selection" start="4" size="3" />
+      <BitField name="CCDS" description="Capture/compare DMA selection" start="3" size="1" />
+      <BitField name="CCUS" description="Capture/compare control update selection" start="2" size="1" />
+      <BitField name="CCPC" description="Capture/compare preloaded control" start="0" size="1" />
+    </Register>
+    <Register name="SMCR" description="slave mode control register" start="+0x8" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="SMS" description="Slave mode selection" start="0" size="3" />
+      <BitField name="TS" description="Trigger selection" start="4" size="3" />
+      <BitField name="MSM" description="Master/Slave mode" start="7" size="1" />
+      <BitField name="ETF" description="External trigger filter" start="8" size="4" />
+      <BitField name="ETPS" description="External trigger prescaler" start="12" size="2" />
+      <BitField name="ECE" description="External clock enable" start="14" size="1" />
+      <BitField name="ETP" description="External trigger polarity" start="15" size="1" />
+      <BitField name="SMS_3" description="Slave mode selection - bit 3" start="16" size="1" />
+      <BitField name="TS_4_3" description="Trigger selection - bit 4:3" start="20" size="2" />
+    </Register>
+    <Register name="DIER" description="DMA/Interrupt enable register" start="+0xC" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="TDE" description="Trigger DMA request enable" start="14" size="1" />
+      <BitField name="COMDE" description="COM DMA request enable" start="13" size="1" />
+      <BitField name="CC4DE" description="Capture/Compare 4 DMA request enable" start="12" size="1" />
+      <BitField name="CC3DE" description="Capture/Compare 3 DMA request enable" start="11" size="1" />
+      <BitField name="CC2DE" description="Capture/Compare 2 DMA request enable" start="10" size="1" />
+      <BitField name="CC1DE" description="Capture/Compare 1 DMA request enable" start="9" size="1" />
+      <BitField name="UDE" description="Update DMA request enable" start="8" size="1" />
+      <BitField name="TIE" description="Trigger interrupt enable" start="6" size="1" />
+      <BitField name="CC4IE" description="Capture/Compare 4 interrupt enable" start="4" size="1" />
+      <BitField name="CC3IE" description="Capture/Compare 3 interrupt enable" start="3" size="1" />
+      <BitField name="CC2IE" description="Capture/Compare 2 interrupt enable" start="2" size="1" />
+      <BitField name="CC1IE" description="Capture/Compare 1 interrupt enable" start="1" size="1" />
+      <BitField name="UIE" description="Update interrupt enable" start="0" size="1" />
+      <BitField name="BIE" description="Break interrupt enable" start="7" size="1" />
+      <BitField name="COMIE" description="COM interrupt enable" start="5" size="1" />
+    </Register>
+    <Register name="SR" description="status register" start="+0x10" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="CC6IF" description="Compare 6 interrupt flag" start="17" size="1" />
+      <BitField name="CC5IF" description="Compare 5 interrupt flag" start="16" size="1" />
+      <BitField name="SBIF" description="System Break interrupt flag" start="13" size="1" />
+      <BitField name="CC4OF" description="Capture/Compare 4 overcapture flag" start="12" size="1" />
+      <BitField name="CC3OF" description="Capture/Compare 3 overcapture flag" start="11" size="1" />
+      <BitField name="CC2OF" description="Capture/compare 2 overcapture flag" start="10" size="1" />
+      <BitField name="CC1OF" description="Capture/Compare 1 overcapture flag" start="9" size="1" />
+      <BitField name="B2IF" description="Break 2 interrupt flag" start="8" size="1" />
+      <BitField name="BIF" description="Break interrupt flag" start="7" size="1" />
+      <BitField name="TIF" description="Trigger interrupt flag" start="6" size="1" />
+      <BitField name="COMIF" description="COM interrupt flag" start="5" size="1" />
+      <BitField name="CC4IF" description="Capture/Compare 4 interrupt flag" start="4" size="1" />
+      <BitField name="CC3IF" description="Capture/Compare 3 interrupt flag" start="3" size="1" />
+      <BitField name="CC2IF" description="Capture/Compare 2 interrupt flag" start="2" size="1" />
+      <BitField name="CC1IF" description="Capture/compare 1 interrupt flag" start="1" size="1" />
+      <BitField name="UIF" description="Update interrupt flag" start="0" size="1" />
+    </Register>
+    <Register name="EGR" description="event generation register" start="+0x14" size="4" access="WriteOnly" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="UG" description="Update generation" start="0" size="1" />
+      <BitField name="CC1G" description="Capture/compare 1 generation" start="1" size="1" />
+      <BitField name="CC2G" description="Capture/compare 2 generation" start="2" size="1" />
+      <BitField name="CC3G" description="Capture/compare 3 generation" start="3" size="1" />
+      <BitField name="CC4G" description="Capture/compare 4 generation" start="4" size="1" />
+      <BitField name="COMG" description="Capture/Compare control update generation" start="5" size="1" />
+      <BitField name="TG" description="Trigger generation" start="6" size="1" />
+      <BitField name="BG" description="Break generation" start="7" size="1" />
+      <BitField name="B2G" description="Break 2 generation" start="8" size="1" />
+    </Register>
+    <Register name="CCMR1_Output" description="capture/compare mode register 1 (output mode)" start="+0x18" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CC1S" description="Capture/Compare 1 selection" start="0" size="2" />
+      <BitField name="OC1FE" description="Output Compare 1 fast enable" start="2" size="1" />
+      <BitField name="OC1PE" description="Output Compare 1 preload enable" start="3" size="1" />
+      <BitField name="OC1M" description="Output Compare 1 mode" start="4" size="3" />
+      <BitField name="OC1CE" description="Output Compare 1 clear enable" start="7" size="1" />
+      <BitField name="CC2S" description="Capture/Compare 2 selection" start="8" size="2" />
+      <BitField name="OC2FE" description="Output Compare 2 fast enable" start="10" size="1" />
+      <BitField name="OC2PE" description="Output Compare 2 preload enable" start="11" size="1" />
+      <BitField name="OC2M" description="Output Compare 2 mode" start="12" size="3" />
+      <BitField name="OC2CE" description="Output Compare 2 clear enable" start="15" size="1" />
+      <BitField name="OC1M_3" description="Output Compare 1 mode - bit 3" start="16" size="1" />
+      <BitField name="OC2M_3" description="Output Compare 2 mode - bit 3" start="24" size="1" />
+    </Register>
+    <Register name="CCMR1_Input" description="capture/compare mode register 1 (input mode)" start="+0x18" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IC2F" description="Input capture 2 filter" start="12" size="4" />
+      <BitField name="IC2PCS" description="Input capture 2 prescaler" start="10" size="2" />
+      <BitField name="CC2S" description="Capture/Compare 2 selection" start="8" size="2" />
+      <BitField name="IC1F" description="Input capture 1 filter" start="4" size="4" />
+      <BitField name="ICPCS" description="Input capture 1 prescaler" start="2" size="2" />
+      <BitField name="CC1S" description="Capture/Compare 1 selection" start="0" size="2" />
+    </Register>
+    <Register name="CCMR2_Output" description="capture/compare mode register 2 (output mode)" start="+0x1C" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CC3S" description="Capture/Compare 3 selection" start="0" size="2" />
+      <BitField name="OC3FE" description="Output compare 3 fast enable" start="2" size="1" />
+      <BitField name="OC3PE" description="Output compare 3 preload enable" start="3" size="1" />
+      <BitField name="OC3M" description="Output compare 3 mode" start="4" size="3" />
+      <BitField name="OC3CE" description="Output compare 3 clear enable" start="7" size="1" />
+      <BitField name="CC4S" description="Capture/Compare 4 selection" start="8" size="2" />
+      <BitField name="OC4FE" description="Output compare 4 fast enable" start="10" size="1" />
+      <BitField name="OC4PE" description="Output compare 4 preload enable" start="11" size="1" />
+      <BitField name="OC4M" description="Output compare 4 mode" start="12" size="3" />
+      <BitField name="OC4CE" description="Output compare 4 clear enable" start="15" size="1" />
+      <BitField name="OC3M_3" description="Output Compare 3 mode - bit 3" start="16" size="1" />
+      <BitField name="OC4M_4" description="Output Compare 4 mode - bit 3" start="24" size="1" />
+    </Register>
+    <Register name="CCMR2_Input" description="capture/compare mode register 2 (input mode)" start="+0x1C" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IC4F" description="Input capture 4 filter" start="12" size="4" />
+      <BitField name="IC4PSC" description="Input capture 4 prescaler" start="10" size="2" />
+      <BitField name="CC4S" description="Capture/Compare 4 selection" start="8" size="2" />
+      <BitField name="IC3F" description="Input capture 3 filter" start="4" size="4" />
+      <BitField name="IC3PSC" description="Input capture 3 prescaler" start="2" size="2" />
+      <BitField name="CC3S" description="Capture/compare 3 selection" start="0" size="2" />
+    </Register>
+    <Register name="CCER" description="capture/compare enable register" start="+0x20" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="CC1E" description="Capture/Compare 1 output enable" start="0" size="1" />
+      <BitField name="CC1P" description="Capture/Compare 1 output Polarity" start="1" size="1" />
+      <BitField name="CC1NE" description="Capture/Compare 1 complementary output enable" start="2" size="1" />
+      <BitField name="CC1NP" description="Capture/Compare 1 output Polarity" start="3" size="1" />
+      <BitField name="CC2E" description="Capture/Compare 2 output enable" start="4" size="1" />
+      <BitField name="CC2P" description="Capture/Compare 2 output Polarity" start="5" size="1" />
+      <BitField name="CC2NE" description="Capture/Compare 2 complementary output enable" start="6" size="1" />
+      <BitField name="CC2NP" description="Capture/Compare 2 output Polarity" start="7" size="1" />
+      <BitField name="CC3E" description="Capture/Compare 3 output enable" start="8" size="1" />
+      <BitField name="CC3P" description="Capture/Compare 3 output Polarity" start="9" size="1" />
+      <BitField name="CC3NE" description="Capture/Compare 3 complementary output enable" start="10" size="1" />
+      <BitField name="CC3NP" description="Capture/Compare 3 output Polarity" start="11" size="1" />
+      <BitField name="CC4E" description="Capture/Compare 4 output enable" start="12" size="1" />
+      <BitField name="CC4P" description="Capture/Compare 3 output Polarity" start="13" size="1" />
+      <BitField name="CC4NP" description="Capture/Compare 4 complementary output polarity" start="15" size="1" />
+      <BitField name="CC5E" description="Capture/Compare 5 output enable" start="16" size="1" />
+      <BitField name="CC5P" description="Capture/Compare 5 output polarity" start="17" size="1" />
+      <BitField name="CC6E" description="Capture/Compare 6 output enable" start="20" size="1" />
+      <BitField name="CC6P" description="Capture/Compare 6 output polarity" start="21" size="1" />
+    </Register>
+    <Register name="CNT" description="counter" start="+0x24" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CNT" description="counter value" start="0" size="16" access="Read/Write" />
+      <BitField name="UIFCPY" description="UIF copy" start="31" size="1" access="ReadOnly" />
+    </Register>
+    <Register name="PSC" description="prescaler" start="+0x28" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="PSC" description="Prescaler value" start="0" size="16" />
+    </Register>
+    <Register name="ARR" description="auto-reload register" start="+0x2C" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ARR" description="Auto-reload value" start="0" size="16" />
+    </Register>
+    <Register name="CCR1" description="capture/compare register 1" start="+0x34" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCR1" description="Capture/Compare 1 value" start="0" size="16" />
+    </Register>
+    <Register name="CCR2" description="capture/compare register 2" start="+0x38" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCR2" description="Capture/Compare 2 value" start="0" size="16" />
+    </Register>
+    <Register name="CCR3" description="capture/compare register 3" start="+0x3C" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCR3" description="Capture/Compare value" start="0" size="16" />
+    </Register>
+    <Register name="CCR4" description="capture/compare register 4" start="+0x40" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCR4" description="Capture/Compare value" start="0" size="16" />
+    </Register>
+    <Register name="DCR" description="DMA control register" start="+0x48" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="DBL" description="DMA burst length" start="8" size="5" />
+      <BitField name="DBA" description="DMA base address" start="0" size="5" />
+    </Register>
+    <Register name="DMAR" description="DMA address for full transfer" start="+0x4C" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAB" description="DMA register for burst accesses" start="0" size="16" />
+    </Register>
+    <Register name="RCR" description="repetition counter register" start="+0x30" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="REP" description="Repetition counter value" start="0" size="8" />
+    </Register>
+    <Register name="BDTR" description="break and dead-time register" start="+0x44" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="DTG" description="Dead-time generator setup" start="0" size="8" />
+      <BitField name="LOCK" description="Lock configuration" start="8" size="2" />
+      <BitField name="OSSI" description="Off-state selection for Idle mode" start="10" size="1" />
+      <BitField name="OSSR" description="Off-state selection for Run mode" start="11" size="1" />
+      <BitField name="BKE" description="Break enable" start="12" size="1" />
+      <BitField name="BKP" description="Break polarity" start="13" size="1" />
+      <BitField name="AOE" description="Automatic output enable" start="14" size="1" />
+      <BitField name="MOE" description="Main output enable" start="15" size="1" />
+      <BitField name="BKF" description="Break filter" start="16" size="4" />
+      <BitField name="BK2F" description="Break 2 filter" start="20" size="4" />
+      <BitField name="BK2E" description="Break 2 enable" start="24" size="1" />
+      <BitField name="BK2P" description="Break 2 polarity" start="25" size="1" />
+    </Register>
+    <Register name="CCMR3_Output" description="capture/compare mode register 3 (output mode)" start="+0x54" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="OC5FE" description="Output compare 5 fast enable" start="2" size="1" />
+      <BitField name="OC5PE" description="Output compare 5 preload enable" start="3" size="1" />
+      <BitField name="OC5M" description="Output compare 5 mode" start="4" size="3" />
+      <BitField name="OC5CE" description="Output compare 5 clear enable" start="7" size="1" />
+      <BitField name="OC6FE" description="Output compare 6 fast enable" start="10" size="1" />
+      <BitField name="OC6PE" description="Output compare 6 preload enable" start="11" size="1" />
+      <BitField name="OC6M" description="Output compare 6 mode" start="12" size="3" />
+      <BitField name="OC6CE" description="Output compare 6 clear enable" start="15" size="1" />
+      <BitField name="OC5M3" description="Output Compare 5 mode" start="16" size="1" />
+      <BitField name="OC6M3" description="Output Compare 6 mode" start="24" size="1" />
+    </Register>
+    <Register name="CCR5" description="capture/compare register 5" start="+0x58" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCR5" description="Capture/Compare 5 value" start="0" size="16" />
+      <BitField name="GC5C1" description="Group Channel 5 and Channel 1" start="29" size="1" />
+      <BitField name="GC5C2" description="Group Channel 5 and Channel 2" start="30" size="1" />
+      <BitField name="GC5C3" description="Group Channel 5 and Channel 3" start="31" size="1" />
+    </Register>
+    <Register name="CRR6" description="capture/compare register 6" start="+0x5C" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCR6" description="Capture/Compare 6 value" start="0" size="16" />
+    </Register>
+    <Register name="AF1" description="TIM1 alternate function option register 1" start="+0x60" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="BKINE" description="BRK BKIN input enable" start="0" size="1" />
+      <BitField name="BKCMP1E" description="BRK COMP1 enable" start="1" size="1" />
+      <BitField name="BKCMP2E" description="BRK COMP2 enable" start="2" size="1" />
+      <BitField name="BKDF1BK0E" description="BRK dfsdm1_break[0] enable" start="8" size="1" />
+      <BitField name="BKINP" description="BRK BKIN input polarity" start="9" size="1" />
+      <BitField name="BKCMP1P" description="BRK COMP1 input polarity" start="10" size="1" />
+      <BitField name="BKCMP2P" description="BRK COMP2 input polarity" start="11" size="1" />
+      <BitField name="ETRSEL" description="ETR source selection" start="14" size="4" />
+    </Register>
+    <Register name="AF2" description="TIM1 Alternate function odfsdm1_breakster 2" start="+0x64" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="BK2INE" description="BRK2 BKIN input enable" start="0" size="1" />
+      <BitField name="BK2CMP1E" description="BRK2 COMP1 enable" start="1" size="1" />
+      <BitField name="BK2CMP2E" description="BRK2 COMP2 enable" start="2" size="1" />
+      <BitField name="BK2DF1BK1E" description="BRK2 dfsdm1_break[1] enable" start="8" size="1" />
+      <BitField name="BK2INP" description="BRK2 BKIN2 input polarity" start="9" size="1" />
+      <BitField name="BK2CMP1P" description="BRK2 COMP1 input polarit" start="10" size="1" />
+      <BitField name="BK2CMP2P" description="BRK2 COMP2 input polarity" start="11" size="1" />
+    </Register>
+    <Register name="TISEL" description="TIM1 timer input selection register" start="+0x68" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="TI1SEL" description="selects TI1[0] to TI1[15] input" start="0" size="4" />
+      <BitField name="TI2SEL" description="selects TI2[0] to TI2[15] input" start="8" size="4" />
+      <BitField name="TI3SEL" description="selects TI3[0] to TI3[15] input" start="16" size="4" />
+      <BitField name="TI4SEL" description="selects TI4[0] to TI4[15] input" start="24" size="4" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="TIM2" description="General purpose timers" start="0x40000000">
+    <Register name="CR1" description="control register 1" start="+0x0" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="UIFREMAP" description="UIF status bit remapping" start="11" size="1" />
+      <BitField name="CKD" description="Clock division" start="8" size="2" />
+      <BitField name="ARPE" description="Auto-reload preload enable" start="7" size="1" />
+      <BitField name="CMS" description="Center-aligned mode selection" start="5" size="2" />
+      <BitField name="DIR" description="Direction" start="4" size="1" />
+      <BitField name="OPM" description="One-pulse mode" start="3" size="1" />
+      <BitField name="URS" description="Update request source" start="2" size="1" />
+      <BitField name="UDIS" description="Update disable" start="1" size="1" />
+      <BitField name="CEN" description="Counter enable" start="0" size="1" />
+    </Register>
+    <Register name="CR2" description="control register 2" start="+0x4" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="TI1S" description="TI1 selection" start="7" size="1" />
+      <BitField name="MMS" description="Master mode selection" start="4" size="3" />
+      <BitField name="CCDS" description="Capture/compare DMA selection" start="3" size="1" />
+    </Register>
+    <Register name="SMCR" description="slave mode control register" start="+0x8" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="TS_4_3" description="Trigger selection" start="20" size="2" />
+      <BitField name="SMS_3" description="Slave mode selection - bit 3" start="16" size="1" />
+      <BitField name="ETP" description="External trigger polarity" start="15" size="1" />
+      <BitField name="ECE" description="External clock enable" start="14" size="1" />
+      <BitField name="ETPS" description="External trigger prescaler" start="12" size="2" />
+      <BitField name="ETF" description="External trigger filter" start="8" size="4" />
+      <BitField name="MSM" description="Master/Slave mode" start="7" size="1" />
+      <BitField name="TS" description="Trigger selection" start="4" size="3" />
+      <BitField name="SMS" description="Slave mode selection" start="0" size="3" />
+    </Register>
+    <Register name="DIER" description="DMA/Interrupt enable register" start="+0xC" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="TDE" description="Trigger DMA request enable" start="14" size="1" />
+      <BitField name="CC4DE" description="Capture/Compare 4 DMA request enable" start="12" size="1" />
+      <BitField name="CC3DE" description="Capture/Compare 3 DMA request enable" start="11" size="1" />
+      <BitField name="CC2DE" description="Capture/Compare 2 DMA request enable" start="10" size="1" />
+      <BitField name="CC1DE" description="Capture/Compare 1 DMA request enable" start="9" size="1" />
+      <BitField name="UDE" description="Update DMA request enable" start="8" size="1" />
+      <BitField name="TIE" description="Trigger interrupt enable" start="6" size="1" />
+      <BitField name="CC4IE" description="Capture/Compare 4 interrupt enable" start="4" size="1" />
+      <BitField name="CC3IE" description="Capture/Compare 3 interrupt enable" start="3" size="1" />
+      <BitField name="CC2IE" description="Capture/Compare 2 interrupt enable" start="2" size="1" />
+      <BitField name="CC1IE" description="Capture/Compare 1 interrupt enable" start="1" size="1" />
+      <BitField name="UIE" description="Update interrupt enable" start="0" size="1" />
+    </Register>
+    <Register name="SR" description="status register" start="+0x10" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="CC4OF" description="Capture/Compare 4 overcapture flag" start="12" size="1" />
+      <BitField name="CC3OF" description="Capture/Compare 3 overcapture flag" start="11" size="1" />
+      <BitField name="CC2OF" description="Capture/compare 2 overcapture flag" start="10" size="1" />
+      <BitField name="CC1OF" description="Capture/Compare 1 overcapture flag" start="9" size="1" />
+      <BitField name="TIF" description="Trigger interrupt flag" start="6" size="1" />
+      <BitField name="CC4IF" description="Capture/Compare 4 interrupt flag" start="4" size="1" />
+      <BitField name="CC3IF" description="Capture/Compare 3 interrupt flag" start="3" size="1" />
+      <BitField name="CC2IF" description="Capture/Compare 2 interrupt flag" start="2" size="1" />
+      <BitField name="CC1IF" description="Capture/compare 1 interrupt flag" start="1" size="1" />
+      <BitField name="UIF" description="Update interrupt flag" start="0" size="1" />
+    </Register>
+    <Register name="EGR" description="event generation register" start="+0x14" size="4" access="WriteOnly" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="TG" description="Trigger generation" start="6" size="1" />
+      <BitField name="CC4G" description="Capture/compare 4 generation" start="4" size="1" />
+      <BitField name="CC3G" description="Capture/compare 3 generation" start="3" size="1" />
+      <BitField name="CC2G" description="Capture/compare 2 generation" start="2" size="1" />
+      <BitField name="CC1G" description="Capture/compare 1 generation" start="1" size="1" />
+      <BitField name="UG" description="Update generation" start="0" size="1" />
+    </Register>
+    <Register name="CCMR1_Output" description="capture/compare mode register 1 (output mode)" start="+0x18" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CC1S" description="CC1S" start="0" size="2" />
+      <BitField name="OC1FE" description="OC1FE" start="2" size="1" />
+      <BitField name="OC1PE" description="OC1PE" start="3" size="1" />
+      <BitField name="OC1M" description="OC1M" start="4" size="3" />
+      <BitField name="OC1CE" description="OC1CE" start="7" size="1" />
+      <BitField name="CC2S" description="CC2S" start="8" size="2" />
+      <BitField name="OC2FE" description="OC2FE" start="10" size="1" />
+      <BitField name="OC2PE" description="OC2PE" start="11" size="1" />
+      <BitField name="OC2M" description="OC2M" start="12" size="3" />
+      <BitField name="OC2CE" description="OC2CE" start="15" size="1" />
+      <BitField name="OC1M_3" description="Output Compare 1 mode - bit 3" start="16" size="1" />
+      <BitField name="OC2M_3" description="Output Compare 2 mode - bit 3" start="24" size="1" />
+    </Register>
+    <Register name="CCMR1_Input" description="capture/compare mode register 1 (input mode)" start="+0x18" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IC2F" description="Input capture 2 filter" start="12" size="4" />
+      <BitField name="IC2PCS" description="Input capture 2 prescaler" start="10" size="2" />
+      <BitField name="CC2S" description="Capture/Compare 2 selection" start="8" size="2" />
+      <BitField name="IC1F" description="Input capture 1 filter" start="4" size="4" />
+      <BitField name="ICPCS" description="Input capture 1 prescaler" start="2" size="2" />
+      <BitField name="CC1S" description="Capture/Compare 1 selection" start="0" size="2" />
+    </Register>
+    <Register name="CCMR2_Output" description="capture/compare mode register 2 (output mode)" start="+0x1C" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OC4M_3" description="Output Compare 2 mode - bit 3" start="24" size="1" />
+      <BitField name="OC3M_3" description="Output Compare 1 mode - bit 3" start="16" size="1" />
+      <BitField name="OC4CE" description="OC4CE" start="15" size="1" />
+      <BitField name="OC4M" description="OC4M" start="12" size="3" />
+      <BitField name="OC4PE" description="OC4PE" start="11" size="1" />
+      <BitField name="OC4FE" description="OC4FE" start="10" size="1" />
+      <BitField name="CC4S" description="CC4S" start="8" size="2" />
+      <BitField name="OC3CE" description="OC3CE" start="7" size="1" />
+      <BitField name="OC3M" description="OC3M" start="4" size="3" />
+      <BitField name="OC3PE" description="OC3PE" start="3" size="1" />
+      <BitField name="OC3FE" description="OC3FE" start="2" size="1" />
+      <BitField name="CC3S" description="CC3S" start="0" size="2" />
+    </Register>
+    <Register name="CCMR2_Input" description="capture/compare mode register 2 (input mode)" start="+0x1C" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IC4F" description="Input capture 4 filter" start="12" size="4" />
+      <BitField name="IC4PSC" description="Input capture 4 prescaler" start="10" size="2" />
+      <BitField name="CC4S" description="Capture/Compare 4 selection" start="8" size="2" />
+      <BitField name="IC3F" description="Input capture 3 filter" start="4" size="4" />
+      <BitField name="IC3PSC" description="Input capture 3 prescaler" start="2" size="2" />
+      <BitField name="CC3S" description="Capture/compare 3 selection" start="0" size="2" />
+    </Register>
+    <Register name="CCER" description="capture/compare enable register" start="+0x20" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="CC4NP" description="Capture/Compare 4 output Polarity" start="15" size="1" />
+      <BitField name="CC4P" description="Capture/Compare 3 output Polarity" start="13" size="1" />
+      <BitField name="CC4E" description="Capture/Compare 4 output enable" start="12" size="1" />
+      <BitField name="CC3NP" description="Capture/Compare 3 output Polarity" start="11" size="1" />
+      <BitField name="CC3P" description="Capture/Compare 3 output Polarity" start="9" size="1" />
+      <BitField name="CC3E" description="Capture/Compare 3 output enable" start="8" size="1" />
+      <BitField name="CC2NP" description="Capture/Compare 2 output Polarity" start="7" size="1" />
+      <BitField name="CC2P" description="Capture/Compare 2 output Polarity" start="5" size="1" />
+      <BitField name="CC2E" description="Capture/Compare 2 output enable" start="4" size="1" />
+      <BitField name="CC1NP" description="Capture/Compare 1 output Polarity" start="3" size="1" />
+      <BitField name="CC1P" description="Capture/Compare 1 output Polarity" start="1" size="1" />
+      <BitField name="CC1E" description="Capture/Compare 1 output enable" start="0" size="1" />
+    </Register>
+    <Register name="CNT" description="counter" start="+0x24" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CNT_L" description="low counter value" start="0" size="16" />
+      <BitField name="CNT_H" description="High counter value" start="16" size="16" />
+    </Register>
+    <Register name="PSC" description="prescaler" start="+0x28" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="PSC" description="Prescaler value" start="0" size="16" />
+    </Register>
+    <Register name="ARR" description="auto-reload register" start="+0x2C" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ARR_H" description="High Auto-reload value" start="16" size="16" />
+      <BitField name="ARR_L" description="Low Auto-reload value" start="0" size="16" />
+    </Register>
+    <Register name="CCR1" description="capture/compare register 1" start="+0x34" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCR1_H" description="High Capture/Compare 1 value" start="16" size="16" />
+      <BitField name="CCR1_L" description="Low Capture/Compare 1 value" start="0" size="16" />
+    </Register>
+    <Register name="CCR2" description="capture/compare register 2" start="+0x38" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCR2_H" description="High Capture/Compare 2 value" start="16" size="16" />
+      <BitField name="CCR2_L" description="Low Capture/Compare 2 value" start="0" size="16" />
+    </Register>
+    <Register name="CCR3" description="capture/compare register 3" start="+0x3C" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCR3_H" description="High Capture/Compare value" start="16" size="16" />
+      <BitField name="CCR3_L" description="Low Capture/Compare value" start="0" size="16" />
+    </Register>
+    <Register name="CCR4" description="capture/compare register 4" start="+0x40" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCR4_H" description="High Capture/Compare value" start="16" size="16" />
+      <BitField name="CCR4_L" description="Low Capture/Compare value" start="0" size="16" />
+    </Register>
+    <Register name="DCR" description="DMA control register" start="+0x48" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="DBL" description="DMA burst length" start="8" size="5" />
+      <BitField name="DBA" description="DMA base address" start="0" size="5" />
+    </Register>
+    <Register name="DMAR" description="DMA address for full transfer" start="+0x4C" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAB" description="DMA register for burst accesses" start="0" size="16" />
+    </Register>
+    <Register name="AF1" description="TIM alternate function option register 1" start="+0x60" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="ETRSEL" description="ETR source selection" start="14" size="4" />
+    </Register>
+    <Register name="TISEL" description="TIM timer input selection register" start="+0x68" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="TI1SEL" description="TI1[0] to TI1[15] input selection" start="0" size="4" />
+      <BitField name="TI2SEL" description="TI2[0] to TI2[15] input selection" start="8" size="4" />
+      <BitField name="TI3SEL" description="TI3[0] to TI3[15] input selection" start="16" size="4" />
+      <BitField name="TI4SEL" description="TI4[0] to TI4[15] input selection" start="24" size="4" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="TIM3" description="General purpose timers" start="0x40000400">
+    <Register name="CR1" description="control register 1" start="+0x0" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="UIFREMAP" description="UIF status bit remapping" start="11" size="1" />
+      <BitField name="CKD" description="Clock division" start="8" size="2" />
+      <BitField name="ARPE" description="Auto-reload preload enable" start="7" size="1" />
+      <BitField name="CMS" description="Center-aligned mode selection" start="5" size="2" />
+      <BitField name="DIR" description="Direction" start="4" size="1" />
+      <BitField name="OPM" description="One-pulse mode" start="3" size="1" />
+      <BitField name="URS" description="Update request source" start="2" size="1" />
+      <BitField name="UDIS" description="Update disable" start="1" size="1" />
+      <BitField name="CEN" description="Counter enable" start="0" size="1" />
+    </Register>
+    <Register name="CR2" description="control register 2" start="+0x4" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="TI1S" description="TI1 selection" start="7" size="1" />
+      <BitField name="MMS" description="Master mode selection" start="4" size="3" />
+      <BitField name="CCDS" description="Capture/compare DMA selection" start="3" size="1" />
+    </Register>
+    <Register name="SMCR" description="slave mode control register" start="+0x8" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="TS_4_3" description="Trigger selection" start="20" size="2" />
+      <BitField name="SMS_3" description="Slave mode selection - bit 3" start="16" size="1" />
+      <BitField name="ETP" description="External trigger polarity" start="15" size="1" />
+      <BitField name="ECE" description="External clock enable" start="14" size="1" />
+      <BitField name="ETPS" description="External trigger prescaler" start="12" size="2" />
+      <BitField name="ETF" description="External trigger filter" start="8" size="4" />
+      <BitField name="MSM" description="Master/Slave mode" start="7" size="1" />
+      <BitField name="TS" description="Trigger selection" start="4" size="3" />
+      <BitField name="SMS" description="Slave mode selection" start="0" size="3" />
+    </Register>
+    <Register name="DIER" description="DMA/Interrupt enable register" start="+0xC" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="TDE" description="Trigger DMA request enable" start="14" size="1" />
+      <BitField name="CC4DE" description="Capture/Compare 4 DMA request enable" start="12" size="1" />
+      <BitField name="CC3DE" description="Capture/Compare 3 DMA request enable" start="11" size="1" />
+      <BitField name="CC2DE" description="Capture/Compare 2 DMA request enable" start="10" size="1" />
+      <BitField name="CC1DE" description="Capture/Compare 1 DMA request enable" start="9" size="1" />
+      <BitField name="UDE" description="Update DMA request enable" start="8" size="1" />
+      <BitField name="TIE" description="Trigger interrupt enable" start="6" size="1" />
+      <BitField name="CC4IE" description="Capture/Compare 4 interrupt enable" start="4" size="1" />
+      <BitField name="CC3IE" description="Capture/Compare 3 interrupt enable" start="3" size="1" />
+      <BitField name="CC2IE" description="Capture/Compare 2 interrupt enable" start="2" size="1" />
+      <BitField name="CC1IE" description="Capture/Compare 1 interrupt enable" start="1" size="1" />
+      <BitField name="UIE" description="Update interrupt enable" start="0" size="1" />
+    </Register>
+    <Register name="SR" description="status register" start="+0x10" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="CC4OF" description="Capture/Compare 4 overcapture flag" start="12" size="1" />
+      <BitField name="CC3OF" description="Capture/Compare 3 overcapture flag" start="11" size="1" />
+      <BitField name="CC2OF" description="Capture/compare 2 overcapture flag" start="10" size="1" />
+      <BitField name="CC1OF" description="Capture/Compare 1 overcapture flag" start="9" size="1" />
+      <BitField name="TIF" description="Trigger interrupt flag" start="6" size="1" />
+      <BitField name="CC4IF" description="Capture/Compare 4 interrupt flag" start="4" size="1" />
+      <BitField name="CC3IF" description="Capture/Compare 3 interrupt flag" start="3" size="1" />
+      <BitField name="CC2IF" description="Capture/Compare 2 interrupt flag" start="2" size="1" />
+      <BitField name="CC1IF" description="Capture/compare 1 interrupt flag" start="1" size="1" />
+      <BitField name="UIF" description="Update interrupt flag" start="0" size="1" />
+    </Register>
+    <Register name="EGR" description="event generation register" start="+0x14" size="4" access="WriteOnly" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="TG" description="Trigger generation" start="6" size="1" />
+      <BitField name="CC4G" description="Capture/compare 4 generation" start="4" size="1" />
+      <BitField name="CC3G" description="Capture/compare 3 generation" start="3" size="1" />
+      <BitField name="CC2G" description="Capture/compare 2 generation" start="2" size="1" />
+      <BitField name="CC1G" description="Capture/compare 1 generation" start="1" size="1" />
+      <BitField name="UG" description="Update generation" start="0" size="1" />
+    </Register>
+    <Register name="CCMR1_Output" description="capture/compare mode register 1 (output mode)" start="+0x18" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CC1S" description="CC1S" start="0" size="2" />
+      <BitField name="OC1FE" description="OC1FE" start="2" size="1" />
+      <BitField name="OC1PE" description="OC1PE" start="3" size="1" />
+      <BitField name="OC1M" description="OC1M" start="4" size="3" />
+      <BitField name="OC1CE" description="OC1CE" start="7" size="1" />
+      <BitField name="CC2S" description="CC2S" start="8" size="2" />
+      <BitField name="OC2FE" description="OC2FE" start="10" size="1" />
+      <BitField name="OC2PE" description="OC2PE" start="11" size="1" />
+      <BitField name="OC2M" description="OC2M" start="12" size="3" />
+      <BitField name="OC2CE" description="OC2CE" start="15" size="1" />
+      <BitField name="OC1M_3" description="Output Compare 1 mode - bit 3" start="16" size="1" />
+      <BitField name="OC2M_3" description="Output Compare 2 mode - bit 3" start="24" size="1" />
+    </Register>
+    <Register name="CCMR1_Input" description="capture/compare mode register 1 (input mode)" start="+0x18" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IC2F" description="Input capture 2 filter" start="12" size="4" />
+      <BitField name="IC2PCS" description="Input capture 2 prescaler" start="10" size="2" />
+      <BitField name="CC2S" description="Capture/Compare 2 selection" start="8" size="2" />
+      <BitField name="IC1F" description="Input capture 1 filter" start="4" size="4" />
+      <BitField name="ICPCS" description="Input capture 1 prescaler" start="2" size="2" />
+      <BitField name="CC1S" description="Capture/Compare 1 selection" start="0" size="2" />
+    </Register>
+    <Register name="CCMR2_Output" description="capture/compare mode register 2 (output mode)" start="+0x1C" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OC4M_3" description="Output Compare 2 mode - bit 3" start="24" size="1" />
+      <BitField name="OC3M_3" description="Output Compare 1 mode - bit 3" start="16" size="1" />
+      <BitField name="OC4CE" description="OC4CE" start="15" size="1" />
+      <BitField name="OC4M" description="OC4M" start="12" size="3" />
+      <BitField name="OC4PE" description="OC4PE" start="11" size="1" />
+      <BitField name="OC4FE" description="OC4FE" start="10" size="1" />
+      <BitField name="CC4S" description="CC4S" start="8" size="2" />
+      <BitField name="OC3CE" description="OC3CE" start="7" size="1" />
+      <BitField name="OC3M" description="OC3M" start="4" size="3" />
+      <BitField name="OC3PE" description="OC3PE" start="3" size="1" />
+      <BitField name="OC3FE" description="OC3FE" start="2" size="1" />
+      <BitField name="CC3S" description="CC3S" start="0" size="2" />
+    </Register>
+    <Register name="CCMR2_Input" description="capture/compare mode register 2 (input mode)" start="+0x1C" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IC4F" description="Input capture 4 filter" start="12" size="4" />
+      <BitField name="IC4PSC" description="Input capture 4 prescaler" start="10" size="2" />
+      <BitField name="CC4S" description="Capture/Compare 4 selection" start="8" size="2" />
+      <BitField name="IC3F" description="Input capture 3 filter" start="4" size="4" />
+      <BitField name="IC3PSC" description="Input capture 3 prescaler" start="2" size="2" />
+      <BitField name="CC3S" description="Capture/compare 3 selection" start="0" size="2" />
+    </Register>
+    <Register name="CCER" description="capture/compare enable register" start="+0x20" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="CC4NP" description="Capture/Compare 4 output Polarity" start="15" size="1" />
+      <BitField name="CC4P" description="Capture/Compare 3 output Polarity" start="13" size="1" />
+      <BitField name="CC4E" description="Capture/Compare 4 output enable" start="12" size="1" />
+      <BitField name="CC3NP" description="Capture/Compare 3 output Polarity" start="11" size="1" />
+      <BitField name="CC3P" description="Capture/Compare 3 output Polarity" start="9" size="1" />
+      <BitField name="CC3E" description="Capture/Compare 3 output enable" start="8" size="1" />
+      <BitField name="CC2NP" description="Capture/Compare 2 output Polarity" start="7" size="1" />
+      <BitField name="CC2P" description="Capture/Compare 2 output Polarity" start="5" size="1" />
+      <BitField name="CC2E" description="Capture/Compare 2 output enable" start="4" size="1" />
+      <BitField name="CC1NP" description="Capture/Compare 1 output Polarity" start="3" size="1" />
+      <BitField name="CC1P" description="Capture/Compare 1 output Polarity" start="1" size="1" />
+      <BitField name="CC1E" description="Capture/Compare 1 output enable" start="0" size="1" />
+    </Register>
+    <Register name="CNT" description="counter" start="+0x24" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CNT_L" description="low counter value" start="0" size="16" />
+      <BitField name="CNT_H" description="High counter value" start="16" size="16" />
+    </Register>
+    <Register name="PSC" description="prescaler" start="+0x28" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="PSC" description="Prescaler value" start="0" size="16" />
+    </Register>
+    <Register name="ARR" description="auto-reload register" start="+0x2C" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ARR_H" description="High Auto-reload value" start="16" size="16" />
+      <BitField name="ARR_L" description="Low Auto-reload value" start="0" size="16" />
+    </Register>
+    <Register name="CCR1" description="capture/compare register 1" start="+0x34" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCR1_H" description="High Capture/Compare 1 value" start="16" size="16" />
+      <BitField name="CCR1_L" description="Low Capture/Compare 1 value" start="0" size="16" />
+    </Register>
+    <Register name="CCR2" description="capture/compare register 2" start="+0x38" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCR2_H" description="High Capture/Compare 2 value" start="16" size="16" />
+      <BitField name="CCR2_L" description="Low Capture/Compare 2 value" start="0" size="16" />
+    </Register>
+    <Register name="CCR3" description="capture/compare register 3" start="+0x3C" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCR3_H" description="High Capture/Compare value" start="16" size="16" />
+      <BitField name="CCR3_L" description="Low Capture/Compare value" start="0" size="16" />
+    </Register>
+    <Register name="CCR4" description="capture/compare register 4" start="+0x40" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCR4_H" description="High Capture/Compare value" start="16" size="16" />
+      <BitField name="CCR4_L" description="Low Capture/Compare value" start="0" size="16" />
+    </Register>
+    <Register name="DCR" description="DMA control register" start="+0x48" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="DBL" description="DMA burst length" start="8" size="5" />
+      <BitField name="DBA" description="DMA base address" start="0" size="5" />
+    </Register>
+    <Register name="DMAR" description="DMA address for full transfer" start="+0x4C" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAB" description="DMA register for burst accesses" start="0" size="16" />
+    </Register>
+    <Register name="AF1" description="TIM alternate function option register 1" start="+0x60" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="ETRSEL" description="ETR source selection" start="14" size="4" />
+    </Register>
+    <Register name="TISEL" description="TIM timer input selection register" start="+0x68" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="TI1SEL" description="TI1[0] to TI1[15] input selection" start="0" size="4" />
+      <BitField name="TI2SEL" description="TI2[0] to TI2[15] input selection" start="8" size="4" />
+      <BitField name="TI3SEL" description="TI3[0] to TI3[15] input selection" start="16" size="4" />
+      <BitField name="TI4SEL" description="TI4[0] to TI4[15] input selection" start="24" size="4" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="TIM4" description="General purpose timers" start="0x40000800">
+    <Register name="CR1" description="control register 1" start="+0x0" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="UIFREMAP" description="UIF status bit remapping" start="11" size="1" />
+      <BitField name="CKD" description="Clock division" start="8" size="2" />
+      <BitField name="ARPE" description="Auto-reload preload enable" start="7" size="1" />
+      <BitField name="CMS" description="Center-aligned mode selection" start="5" size="2" />
+      <BitField name="DIR" description="Direction" start="4" size="1" />
+      <BitField name="OPM" description="One-pulse mode" start="3" size="1" />
+      <BitField name="URS" description="Update request source" start="2" size="1" />
+      <BitField name="UDIS" description="Update disable" start="1" size="1" />
+      <BitField name="CEN" description="Counter enable" start="0" size="1" />
+    </Register>
+    <Register name="CR2" description="control register 2" start="+0x4" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="TI1S" description="TI1 selection" start="7" size="1" />
+      <BitField name="MMS" description="Master mode selection" start="4" size="3" />
+      <BitField name="CCDS" description="Capture/compare DMA selection" start="3" size="1" />
+    </Register>
+    <Register name="SMCR" description="slave mode control register" start="+0x8" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="TS_4_3" description="Trigger selection" start="20" size="2" />
+      <BitField name="SMS_3" description="Slave mode selection - bit 3" start="16" size="1" />
+      <BitField name="ETP" description="External trigger polarity" start="15" size="1" />
+      <BitField name="ECE" description="External clock enable" start="14" size="1" />
+      <BitField name="ETPS" description="External trigger prescaler" start="12" size="2" />
+      <BitField name="ETF" description="External trigger filter" start="8" size="4" />
+      <BitField name="MSM" description="Master/Slave mode" start="7" size="1" />
+      <BitField name="TS" description="Trigger selection" start="4" size="3" />
+      <BitField name="SMS" description="Slave mode selection" start="0" size="3" />
+    </Register>
+    <Register name="DIER" description="DMA/Interrupt enable register" start="+0xC" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="TDE" description="Trigger DMA request enable" start="14" size="1" />
+      <BitField name="CC4DE" description="Capture/Compare 4 DMA request enable" start="12" size="1" />
+      <BitField name="CC3DE" description="Capture/Compare 3 DMA request enable" start="11" size="1" />
+      <BitField name="CC2DE" description="Capture/Compare 2 DMA request enable" start="10" size="1" />
+      <BitField name="CC1DE" description="Capture/Compare 1 DMA request enable" start="9" size="1" />
+      <BitField name="UDE" description="Update DMA request enable" start="8" size="1" />
+      <BitField name="TIE" description="Trigger interrupt enable" start="6" size="1" />
+      <BitField name="CC4IE" description="Capture/Compare 4 interrupt enable" start="4" size="1" />
+      <BitField name="CC3IE" description="Capture/Compare 3 interrupt enable" start="3" size="1" />
+      <BitField name="CC2IE" description="Capture/Compare 2 interrupt enable" start="2" size="1" />
+      <BitField name="CC1IE" description="Capture/Compare 1 interrupt enable" start="1" size="1" />
+      <BitField name="UIE" description="Update interrupt enable" start="0" size="1" />
+    </Register>
+    <Register name="SR" description="status register" start="+0x10" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="CC4OF" description="Capture/Compare 4 overcapture flag" start="12" size="1" />
+      <BitField name="CC3OF" description="Capture/Compare 3 overcapture flag" start="11" size="1" />
+      <BitField name="CC2OF" description="Capture/compare 2 overcapture flag" start="10" size="1" />
+      <BitField name="CC1OF" description="Capture/Compare 1 overcapture flag" start="9" size="1" />
+      <BitField name="TIF" description="Trigger interrupt flag" start="6" size="1" />
+      <BitField name="CC4IF" description="Capture/Compare 4 interrupt flag" start="4" size="1" />
+      <BitField name="CC3IF" description="Capture/Compare 3 interrupt flag" start="3" size="1" />
+      <BitField name="CC2IF" description="Capture/Compare 2 interrupt flag" start="2" size="1" />
+      <BitField name="CC1IF" description="Capture/compare 1 interrupt flag" start="1" size="1" />
+      <BitField name="UIF" description="Update interrupt flag" start="0" size="1" />
+    </Register>
+    <Register name="EGR" description="event generation register" start="+0x14" size="4" access="WriteOnly" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="TG" description="Trigger generation" start="6" size="1" />
+      <BitField name="CC4G" description="Capture/compare 4 generation" start="4" size="1" />
+      <BitField name="CC3G" description="Capture/compare 3 generation" start="3" size="1" />
+      <BitField name="CC2G" description="Capture/compare 2 generation" start="2" size="1" />
+      <BitField name="CC1G" description="Capture/compare 1 generation" start="1" size="1" />
+      <BitField name="UG" description="Update generation" start="0" size="1" />
+    </Register>
+    <Register name="CCMR1_Output" description="capture/compare mode register 1 (output mode)" start="+0x18" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CC1S" description="CC1S" start="0" size="2" />
+      <BitField name="OC1FE" description="OC1FE" start="2" size="1" />
+      <BitField name="OC1PE" description="OC1PE" start="3" size="1" />
+      <BitField name="OC1M" description="OC1M" start="4" size="3" />
+      <BitField name="OC1CE" description="OC1CE" start="7" size="1" />
+      <BitField name="CC2S" description="CC2S" start="8" size="2" />
+      <BitField name="OC2FE" description="OC2FE" start="10" size="1" />
+      <BitField name="OC2PE" description="OC2PE" start="11" size="1" />
+      <BitField name="OC2M" description="OC2M" start="12" size="3" />
+      <BitField name="OC2CE" description="OC2CE" start="15" size="1" />
+      <BitField name="OC1M_3" description="Output Compare 1 mode - bit 3" start="16" size="1" />
+      <BitField name="OC2M_3" description="Output Compare 2 mode - bit 3" start="24" size="1" />
+    </Register>
+    <Register name="CCMR1_Input" description="capture/compare mode register 1 (input mode)" start="+0x18" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IC2F" description="Input capture 2 filter" start="12" size="4" />
+      <BitField name="IC2PCS" description="Input capture 2 prescaler" start="10" size="2" />
+      <BitField name="CC2S" description="Capture/Compare 2 selection" start="8" size="2" />
+      <BitField name="IC1F" description="Input capture 1 filter" start="4" size="4" />
+      <BitField name="ICPCS" description="Input capture 1 prescaler" start="2" size="2" />
+      <BitField name="CC1S" description="Capture/Compare 1 selection" start="0" size="2" />
+    </Register>
+    <Register name="CCMR2_Output" description="capture/compare mode register 2 (output mode)" start="+0x1C" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OC4M_3" description="Output Compare 2 mode - bit 3" start="24" size="1" />
+      <BitField name="OC3M_3" description="Output Compare 1 mode - bit 3" start="16" size="1" />
+      <BitField name="OC4CE" description="OC4CE" start="15" size="1" />
+      <BitField name="OC4M" description="OC4M" start="12" size="3" />
+      <BitField name="OC4PE" description="OC4PE" start="11" size="1" />
+      <BitField name="OC4FE" description="OC4FE" start="10" size="1" />
+      <BitField name="CC4S" description="CC4S" start="8" size="2" />
+      <BitField name="OC3CE" description="OC3CE" start="7" size="1" />
+      <BitField name="OC3M" description="OC3M" start="4" size="3" />
+      <BitField name="OC3PE" description="OC3PE" start="3" size="1" />
+      <BitField name="OC3FE" description="OC3FE" start="2" size="1" />
+      <BitField name="CC3S" description="CC3S" start="0" size="2" />
+    </Register>
+    <Register name="CCMR2_Input" description="capture/compare mode register 2 (input mode)" start="+0x1C" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IC4F" description="Input capture 4 filter" start="12" size="4" />
+      <BitField name="IC4PSC" description="Input capture 4 prescaler" start="10" size="2" />
+      <BitField name="CC4S" description="Capture/Compare 4 selection" start="8" size="2" />
+      <BitField name="IC3F" description="Input capture 3 filter" start="4" size="4" />
+      <BitField name="IC3PSC" description="Input capture 3 prescaler" start="2" size="2" />
+      <BitField name="CC3S" description="Capture/compare 3 selection" start="0" size="2" />
+    </Register>
+    <Register name="CCER" description="capture/compare enable register" start="+0x20" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="CC4NP" description="Capture/Compare 4 output Polarity" start="15" size="1" />
+      <BitField name="CC4P" description="Capture/Compare 3 output Polarity" start="13" size="1" />
+      <BitField name="CC4E" description="Capture/Compare 4 output enable" start="12" size="1" />
+      <BitField name="CC3NP" description="Capture/Compare 3 output Polarity" start="11" size="1" />
+      <BitField name="CC3P" description="Capture/Compare 3 output Polarity" start="9" size="1" />
+      <BitField name="CC3E" description="Capture/Compare 3 output enable" start="8" size="1" />
+      <BitField name="CC2NP" description="Capture/Compare 2 output Polarity" start="7" size="1" />
+      <BitField name="CC2P" description="Capture/Compare 2 output Polarity" start="5" size="1" />
+      <BitField name="CC2E" description="Capture/Compare 2 output enable" start="4" size="1" />
+      <BitField name="CC1NP" description="Capture/Compare 1 output Polarity" start="3" size="1" />
+      <BitField name="CC1P" description="Capture/Compare 1 output Polarity" start="1" size="1" />
+      <BitField name="CC1E" description="Capture/Compare 1 output enable" start="0" size="1" />
+    </Register>
+    <Register name="CNT" description="counter" start="+0x24" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CNT_L" description="low counter value" start="0" size="16" />
+      <BitField name="CNT_H" description="High counter value" start="16" size="16" />
+    </Register>
+    <Register name="PSC" description="prescaler" start="+0x28" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="PSC" description="Prescaler value" start="0" size="16" />
+    </Register>
+    <Register name="ARR" description="auto-reload register" start="+0x2C" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ARR_H" description="High Auto-reload value" start="16" size="16" />
+      <BitField name="ARR_L" description="Low Auto-reload value" start="0" size="16" />
+    </Register>
+    <Register name="CCR1" description="capture/compare register 1" start="+0x34" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCR1_H" description="High Capture/Compare 1 value" start="16" size="16" />
+      <BitField name="CCR1_L" description="Low Capture/Compare 1 value" start="0" size="16" />
+    </Register>
+    <Register name="CCR2" description="capture/compare register 2" start="+0x38" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCR2_H" description="High Capture/Compare 2 value" start="16" size="16" />
+      <BitField name="CCR2_L" description="Low Capture/Compare 2 value" start="0" size="16" />
+    </Register>
+    <Register name="CCR3" description="capture/compare register 3" start="+0x3C" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCR3_H" description="High Capture/Compare value" start="16" size="16" />
+      <BitField name="CCR3_L" description="Low Capture/Compare value" start="0" size="16" />
+    </Register>
+    <Register name="CCR4" description="capture/compare register 4" start="+0x40" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCR4_H" description="High Capture/Compare value" start="16" size="16" />
+      <BitField name="CCR4_L" description="Low Capture/Compare value" start="0" size="16" />
+    </Register>
+    <Register name="DCR" description="DMA control register" start="+0x48" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="DBL" description="DMA burst length" start="8" size="5" />
+      <BitField name="DBA" description="DMA base address" start="0" size="5" />
+    </Register>
+    <Register name="DMAR" description="DMA address for full transfer" start="+0x4C" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAB" description="DMA register for burst accesses" start="0" size="16" />
+    </Register>
+    <Register name="AF1" description="TIM alternate function option register 1" start="+0x60" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="ETRSEL" description="ETR source selection" start="14" size="4" />
+    </Register>
+    <Register name="TISEL" description="TIM timer input selection register" start="+0x68" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="TI1SEL" description="TI1[0] to TI1[15] input selection" start="0" size="4" />
+      <BitField name="TI2SEL" description="TI2[0] to TI2[15] input selection" start="8" size="4" />
+      <BitField name="TI3SEL" description="TI3[0] to TI3[15] input selection" start="16" size="4" />
+      <BitField name="TI4SEL" description="TI4[0] to TI4[15] input selection" start="24" size="4" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="TIM5" description="General purpose timers" start="0x40000C00">
+    <Register name="CR1" description="control register 1" start="+0x0" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="UIFREMAP" description="UIF status bit remapping" start="11" size="1" />
+      <BitField name="CKD" description="Clock division" start="8" size="2" />
+      <BitField name="ARPE" description="Auto-reload preload enable" start="7" size="1" />
+      <BitField name="CMS" description="Center-aligned mode selection" start="5" size="2" />
+      <BitField name="DIR" description="Direction" start="4" size="1" />
+      <BitField name="OPM" description="One-pulse mode" start="3" size="1" />
+      <BitField name="URS" description="Update request source" start="2" size="1" />
+      <BitField name="UDIS" description="Update disable" start="1" size="1" />
+      <BitField name="CEN" description="Counter enable" start="0" size="1" />
+    </Register>
+    <Register name="CR2" description="control register 2" start="+0x4" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="TI1S" description="TI1 selection" start="7" size="1" />
+      <BitField name="MMS" description="Master mode selection" start="4" size="3" />
+      <BitField name="CCDS" description="Capture/compare DMA selection" start="3" size="1" />
+    </Register>
+    <Register name="SMCR" description="slave mode control register" start="+0x8" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="TS_4_3" description="Trigger selection" start="20" size="2" />
+      <BitField name="SMS_3" description="Slave mode selection - bit 3" start="16" size="1" />
+      <BitField name="ETP" description="External trigger polarity" start="15" size="1" />
+      <BitField name="ECE" description="External clock enable" start="14" size="1" />
+      <BitField name="ETPS" description="External trigger prescaler" start="12" size="2" />
+      <BitField name="ETF" description="External trigger filter" start="8" size="4" />
+      <BitField name="MSM" description="Master/Slave mode" start="7" size="1" />
+      <BitField name="TS" description="Trigger selection" start="4" size="3" />
+      <BitField name="SMS" description="Slave mode selection" start="0" size="3" />
+    </Register>
+    <Register name="DIER" description="DMA/Interrupt enable register" start="+0xC" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="TDE" description="Trigger DMA request enable" start="14" size="1" />
+      <BitField name="CC4DE" description="Capture/Compare 4 DMA request enable" start="12" size="1" />
+      <BitField name="CC3DE" description="Capture/Compare 3 DMA request enable" start="11" size="1" />
+      <BitField name="CC2DE" description="Capture/Compare 2 DMA request enable" start="10" size="1" />
+      <BitField name="CC1DE" description="Capture/Compare 1 DMA request enable" start="9" size="1" />
+      <BitField name="UDE" description="Update DMA request enable" start="8" size="1" />
+      <BitField name="TIE" description="Trigger interrupt enable" start="6" size="1" />
+      <BitField name="CC4IE" description="Capture/Compare 4 interrupt enable" start="4" size="1" />
+      <BitField name="CC3IE" description="Capture/Compare 3 interrupt enable" start="3" size="1" />
+      <BitField name="CC2IE" description="Capture/Compare 2 interrupt enable" start="2" size="1" />
+      <BitField name="CC1IE" description="Capture/Compare 1 interrupt enable" start="1" size="1" />
+      <BitField name="UIE" description="Update interrupt enable" start="0" size="1" />
+    </Register>
+    <Register name="SR" description="status register" start="+0x10" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="CC4OF" description="Capture/Compare 4 overcapture flag" start="12" size="1" />
+      <BitField name="CC3OF" description="Capture/Compare 3 overcapture flag" start="11" size="1" />
+      <BitField name="CC2OF" description="Capture/compare 2 overcapture flag" start="10" size="1" />
+      <BitField name="CC1OF" description="Capture/Compare 1 overcapture flag" start="9" size="1" />
+      <BitField name="TIF" description="Trigger interrupt flag" start="6" size="1" />
+      <BitField name="CC4IF" description="Capture/Compare 4 interrupt flag" start="4" size="1" />
+      <BitField name="CC3IF" description="Capture/Compare 3 interrupt flag" start="3" size="1" />
+      <BitField name="CC2IF" description="Capture/Compare 2 interrupt flag" start="2" size="1" />
+      <BitField name="CC1IF" description="Capture/compare 1 interrupt flag" start="1" size="1" />
+      <BitField name="UIF" description="Update interrupt flag" start="0" size="1" />
+    </Register>
+    <Register name="EGR" description="event generation register" start="+0x14" size="4" access="WriteOnly" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="TG" description="Trigger generation" start="6" size="1" />
+      <BitField name="CC4G" description="Capture/compare 4 generation" start="4" size="1" />
+      <BitField name="CC3G" description="Capture/compare 3 generation" start="3" size="1" />
+      <BitField name="CC2G" description="Capture/compare 2 generation" start="2" size="1" />
+      <BitField name="CC1G" description="Capture/compare 1 generation" start="1" size="1" />
+      <BitField name="UG" description="Update generation" start="0" size="1" />
+    </Register>
+    <Register name="CCMR1_Output" description="capture/compare mode register 1 (output mode)" start="+0x18" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CC1S" description="CC1S" start="0" size="2" />
+      <BitField name="OC1FE" description="OC1FE" start="2" size="1" />
+      <BitField name="OC1PE" description="OC1PE" start="3" size="1" />
+      <BitField name="OC1M" description="OC1M" start="4" size="3" />
+      <BitField name="OC1CE" description="OC1CE" start="7" size="1" />
+      <BitField name="CC2S" description="CC2S" start="8" size="2" />
+      <BitField name="OC2FE" description="OC2FE" start="10" size="1" />
+      <BitField name="OC2PE" description="OC2PE" start="11" size="1" />
+      <BitField name="OC2M" description="OC2M" start="12" size="3" />
+      <BitField name="OC2CE" description="OC2CE" start="15" size="1" />
+      <BitField name="OC1M_3" description="Output Compare 1 mode - bit 3" start="16" size="1" />
+      <BitField name="OC2M_3" description="Output Compare 2 mode - bit 3" start="24" size="1" />
+    </Register>
+    <Register name="CCMR1_Input" description="capture/compare mode register 1 (input mode)" start="+0x18" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IC2F" description="Input capture 2 filter" start="12" size="4" />
+      <BitField name="IC2PCS" description="Input capture 2 prescaler" start="10" size="2" />
+      <BitField name="CC2S" description="Capture/Compare 2 selection" start="8" size="2" />
+      <BitField name="IC1F" description="Input capture 1 filter" start="4" size="4" />
+      <BitField name="ICPCS" description="Input capture 1 prescaler" start="2" size="2" />
+      <BitField name="CC1S" description="Capture/Compare 1 selection" start="0" size="2" />
+    </Register>
+    <Register name="CCMR2_Output" description="capture/compare mode register 2 (output mode)" start="+0x1C" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OC4M_3" description="Output Compare 2 mode - bit 3" start="24" size="1" />
+      <BitField name="OC3M_3" description="Output Compare 1 mode - bit 3" start="16" size="1" />
+      <BitField name="OC4CE" description="OC4CE" start="15" size="1" />
+      <BitField name="OC4M" description="OC4M" start="12" size="3" />
+      <BitField name="OC4PE" description="OC4PE" start="11" size="1" />
+      <BitField name="OC4FE" description="OC4FE" start="10" size="1" />
+      <BitField name="CC4S" description="CC4S" start="8" size="2" />
+      <BitField name="OC3CE" description="OC3CE" start="7" size="1" />
+      <BitField name="OC3M" description="OC3M" start="4" size="3" />
+      <BitField name="OC3PE" description="OC3PE" start="3" size="1" />
+      <BitField name="OC3FE" description="OC3FE" start="2" size="1" />
+      <BitField name="CC3S" description="CC3S" start="0" size="2" />
+    </Register>
+    <Register name="CCMR2_Input" description="capture/compare mode register 2 (input mode)" start="+0x1C" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IC4F" description="Input capture 4 filter" start="12" size="4" />
+      <BitField name="IC4PSC" description="Input capture 4 prescaler" start="10" size="2" />
+      <BitField name="CC4S" description="Capture/Compare 4 selection" start="8" size="2" />
+      <BitField name="IC3F" description="Input capture 3 filter" start="4" size="4" />
+      <BitField name="IC3PSC" description="Input capture 3 prescaler" start="2" size="2" />
+      <BitField name="CC3S" description="Capture/compare 3 selection" start="0" size="2" />
+    </Register>
+    <Register name="CCER" description="capture/compare enable register" start="+0x20" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="CC4NP" description="Capture/Compare 4 output Polarity" start="15" size="1" />
+      <BitField name="CC4P" description="Capture/Compare 3 output Polarity" start="13" size="1" />
+      <BitField name="CC4E" description="Capture/Compare 4 output enable" start="12" size="1" />
+      <BitField name="CC3NP" description="Capture/Compare 3 output Polarity" start="11" size="1" />
+      <BitField name="CC3P" description="Capture/Compare 3 output Polarity" start="9" size="1" />
+      <BitField name="CC3E" description="Capture/Compare 3 output enable" start="8" size="1" />
+      <BitField name="CC2NP" description="Capture/Compare 2 output Polarity" start="7" size="1" />
+      <BitField name="CC2P" description="Capture/Compare 2 output Polarity" start="5" size="1" />
+      <BitField name="CC2E" description="Capture/Compare 2 output enable" start="4" size="1" />
+      <BitField name="CC1NP" description="Capture/Compare 1 output Polarity" start="3" size="1" />
+      <BitField name="CC1P" description="Capture/Compare 1 output Polarity" start="1" size="1" />
+      <BitField name="CC1E" description="Capture/Compare 1 output enable" start="0" size="1" />
+    </Register>
+    <Register name="CNT" description="counter" start="+0x24" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CNT_L" description="low counter value" start="0" size="16" />
+      <BitField name="CNT_H" description="High counter value" start="16" size="16" />
+    </Register>
+    <Register name="PSC" description="prescaler" start="+0x28" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="PSC" description="Prescaler value" start="0" size="16" />
+    </Register>
+    <Register name="ARR" description="auto-reload register" start="+0x2C" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ARR_H" description="High Auto-reload value" start="16" size="16" />
+      <BitField name="ARR_L" description="Low Auto-reload value" start="0" size="16" />
+    </Register>
+    <Register name="CCR1" description="capture/compare register 1" start="+0x34" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCR1_H" description="High Capture/Compare 1 value" start="16" size="16" />
+      <BitField name="CCR1_L" description="Low Capture/Compare 1 value" start="0" size="16" />
+    </Register>
+    <Register name="CCR2" description="capture/compare register 2" start="+0x38" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCR2_H" description="High Capture/Compare 2 value" start="16" size="16" />
+      <BitField name="CCR2_L" description="Low Capture/Compare 2 value" start="0" size="16" />
+    </Register>
+    <Register name="CCR3" description="capture/compare register 3" start="+0x3C" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCR3_H" description="High Capture/Compare value" start="16" size="16" />
+      <BitField name="CCR3_L" description="Low Capture/Compare value" start="0" size="16" />
+    </Register>
+    <Register name="CCR4" description="capture/compare register 4" start="+0x40" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCR4_H" description="High Capture/Compare value" start="16" size="16" />
+      <BitField name="CCR4_L" description="Low Capture/Compare value" start="0" size="16" />
+    </Register>
+    <Register name="DCR" description="DMA control register" start="+0x48" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="DBL" description="DMA burst length" start="8" size="5" />
+      <BitField name="DBA" description="DMA base address" start="0" size="5" />
+    </Register>
+    <Register name="DMAR" description="DMA address for full transfer" start="+0x4C" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAB" description="DMA register for burst accesses" start="0" size="16" />
+    </Register>
+    <Register name="AF1" description="TIM alternate function option register 1" start="+0x60" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="ETRSEL" description="ETR source selection" start="14" size="4" />
+    </Register>
+    <Register name="TISEL" description="TIM timer input selection register" start="+0x68" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="TI1SEL" description="TI1[0] to TI1[15] input selection" start="0" size="4" />
+      <BitField name="TI2SEL" description="TI2[0] to TI2[15] input selection" start="8" size="4" />
+      <BitField name="TI3SEL" description="TI3[0] to TI3[15] input selection" start="16" size="4" />
+      <BitField name="TI4SEL" description="TI4[0] to TI4[15] input selection" start="24" size="4" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="TIM6" description="Basic timers" start="0x40001000">
+    <Register name="CR1" description="control register 1" start="+0x0" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="UIFREMAP" description="UIF status bit remapping" start="11" size="1" />
+      <BitField name="ARPE" description="Auto-reload preload enable" start="7" size="1" />
+      <BitField name="OPM" description="One-pulse mode" start="3" size="1" />
+      <BitField name="URS" description="Update request source" start="2" size="1" />
+      <BitField name="UDIS" description="Update disable" start="1" size="1" />
+      <BitField name="CEN" description="Counter enable" start="0" size="1" />
+    </Register>
+    <Register name="CR2" description="control register 2" start="+0x4" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="MMS" description="Master mode selection" start="4" size="3" />
+    </Register>
+    <Register name="DIER" description="DMA/Interrupt enable register" start="+0xC" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="UDE" description="Update DMA request enable" start="8" size="1" />
+      <BitField name="UIE" description="Update interrupt enable" start="0" size="1" />
+    </Register>
+    <Register name="SR" description="status register" start="+0x10" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="UIF" description="Update interrupt flag" start="0" size="1" />
+    </Register>
+    <Register name="EGR" description="event generation register" start="+0x14" size="4" access="WriteOnly" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="UG" description="Update generation" start="0" size="1" />
+    </Register>
+    <Register name="CNT" description="counter" start="+0x24" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CNT" description="Low counter value" start="0" size="16" />
+      <BitField name="UIFCPY" description="UIF Copy" start="31" size="1" />
+    </Register>
+    <Register name="PSC" description="prescaler" start="+0x28" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="PSC" description="Prescaler value" start="0" size="16" />
+    </Register>
+    <Register name="ARR" description="auto-reload register" start="+0x2C" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ARR" description="Low Auto-reload value" start="0" size="16" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="TIM7" description="Basic timers" start="0x40001400">
+    <Register name="CR1" description="control register 1" start="+0x0" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="UIFREMAP" description="UIF status bit remapping" start="11" size="1" />
+      <BitField name="ARPE" description="Auto-reload preload enable" start="7" size="1" />
+      <BitField name="OPM" description="One-pulse mode" start="3" size="1" />
+      <BitField name="URS" description="Update request source" start="2" size="1" />
+      <BitField name="UDIS" description="Update disable" start="1" size="1" />
+      <BitField name="CEN" description="Counter enable" start="0" size="1" />
+    </Register>
+    <Register name="CR2" description="control register 2" start="+0x4" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="MMS" description="Master mode selection" start="4" size="3" />
+    </Register>
+    <Register name="DIER" description="DMA/Interrupt enable register" start="+0xC" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="UDE" description="Update DMA request enable" start="8" size="1" />
+      <BitField name="UIE" description="Update interrupt enable" start="0" size="1" />
+    </Register>
+    <Register name="SR" description="status register" start="+0x10" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="UIF" description="Update interrupt flag" start="0" size="1" />
+    </Register>
+    <Register name="EGR" description="event generation register" start="+0x14" size="4" access="WriteOnly" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="UG" description="Update generation" start="0" size="1" />
+    </Register>
+    <Register name="CNT" description="counter" start="+0x24" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CNT" description="Low counter value" start="0" size="16" />
+      <BitField name="UIFCPY" description="UIF Copy" start="31" size="1" />
+    </Register>
+    <Register name="PSC" description="prescaler" start="+0x28" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="PSC" description="Prescaler value" start="0" size="16" />
+    </Register>
+    <Register name="ARR" description="auto-reload register" start="+0x2C" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ARR" description="Low Auto-reload value" start="0" size="16" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="TIM8" description="Advanced-timers" start="0x40010400">
+    <Register name="CR1" description="control register 1" start="+0x0" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="CEN" description="Counter enable" start="0" size="1" />
+      <BitField name="UDIS" description="Update disable" start="1" size="1" />
+      <BitField name="URS" description="Update request source" start="2" size="1" />
+      <BitField name="OPM" description="One-pulse mode" start="3" size="1" />
+      <BitField name="DIR" description="Direction" start="4" size="1" />
+      <BitField name="CMS" description="Center-aligned mode selection" start="5" size="2" />
+      <BitField name="ARPE" description="Auto-reload preload enable" start="7" size="1" />
+      <BitField name="CKD" description="Clock division" start="8" size="2" />
+      <BitField name="UIFREMAP" description="UIF status bit remapping" start="11" size="1" />
+    </Register>
+    <Register name="CR2" description="control register 2" start="+0x4" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="MMS2" description="Master mode selection 2" start="20" size="4" />
+      <BitField name="OIS6" description="Output Idle state 6" start="18" size="1" />
+      <BitField name="OIS5" description="Output Idle state 5" start="16" size="1" />
+      <BitField name="OIS4" description="Output Idle state 4" start="14" size="1" />
+      <BitField name="OIS3N" description="Output Idle state 3" start="13" size="1" />
+      <BitField name="OIS3" description="Output Idle state 3" start="12" size="1" />
+      <BitField name="OIS2N" description="Output Idle state 2" start="11" size="1" />
+      <BitField name="OIS2" description="Output Idle state 2" start="10" size="1" />
+      <BitField name="OIS1N" description="Output Idle state 1" start="9" size="1" />
+      <BitField name="OIS1" description="Output Idle state 1" start="8" size="1" />
+      <BitField name="TI1S" description="TI1 selection" start="7" size="1" />
+      <BitField name="MMS" description="Master mode selection" start="4" size="3" />
+      <BitField name="CCDS" description="Capture/compare DMA selection" start="3" size="1" />
+      <BitField name="CCUS" description="Capture/compare control update selection" start="2" size="1" />
+      <BitField name="CCPC" description="Capture/compare preloaded control" start="0" size="1" />
+    </Register>
+    <Register name="SMCR" description="slave mode control register" start="+0x8" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="SMS" description="Slave mode selection" start="0" size="3" />
+      <BitField name="TS" description="Trigger selection" start="4" size="3" />
+      <BitField name="MSM" description="Master/Slave mode" start="7" size="1" />
+      <BitField name="ETF" description="External trigger filter" start="8" size="4" />
+      <BitField name="ETPS" description="External trigger prescaler" start="12" size="2" />
+      <BitField name="ECE" description="External clock enable" start="14" size="1" />
+      <BitField name="ETP" description="External trigger polarity" start="15" size="1" />
+      <BitField name="SMS_3" description="Slave mode selection - bit 3" start="16" size="1" />
+      <BitField name="TS_4_3" description="Trigger selection - bit 4:3" start="20" size="2" />
+    </Register>
+    <Register name="DIER" description="DMA/Interrupt enable register" start="+0xC" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="TDE" description="Trigger DMA request enable" start="14" size="1" />
+      <BitField name="COMDE" description="COM DMA request enable" start="13" size="1" />
+      <BitField name="CC4DE" description="Capture/Compare 4 DMA request enable" start="12" size="1" />
+      <BitField name="CC3DE" description="Capture/Compare 3 DMA request enable" start="11" size="1" />
+      <BitField name="CC2DE" description="Capture/Compare 2 DMA request enable" start="10" size="1" />
+      <BitField name="CC1DE" description="Capture/Compare 1 DMA request enable" start="9" size="1" />
+      <BitField name="UDE" description="Update DMA request enable" start="8" size="1" />
+      <BitField name="TIE" description="Trigger interrupt enable" start="6" size="1" />
+      <BitField name="CC4IE" description="Capture/Compare 4 interrupt enable" start="4" size="1" />
+      <BitField name="CC3IE" description="Capture/Compare 3 interrupt enable" start="3" size="1" />
+      <BitField name="CC2IE" description="Capture/Compare 2 interrupt enable" start="2" size="1" />
+      <BitField name="CC1IE" description="Capture/Compare 1 interrupt enable" start="1" size="1" />
+      <BitField name="UIE" description="Update interrupt enable" start="0" size="1" />
+      <BitField name="BIE" description="Break interrupt enable" start="7" size="1" />
+      <BitField name="COMIE" description="COM interrupt enable" start="5" size="1" />
+    </Register>
+    <Register name="SR" description="status register" start="+0x10" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="CC6IF" description="Compare 6 interrupt flag" start="17" size="1" />
+      <BitField name="CC5IF" description="Compare 5 interrupt flag" start="16" size="1" />
+      <BitField name="SBIF" description="System Break interrupt flag" start="13" size="1" />
+      <BitField name="CC4OF" description="Capture/Compare 4 overcapture flag" start="12" size="1" />
+      <BitField name="CC3OF" description="Capture/Compare 3 overcapture flag" start="11" size="1" />
+      <BitField name="CC2OF" description="Capture/compare 2 overcapture flag" start="10" size="1" />
+      <BitField name="CC1OF" description="Capture/Compare 1 overcapture flag" start="9" size="1" />
+      <BitField name="B2IF" description="Break 2 interrupt flag" start="8" size="1" />
+      <BitField name="BIF" description="Break interrupt flag" start="7" size="1" />
+      <BitField name="TIF" description="Trigger interrupt flag" start="6" size="1" />
+      <BitField name="COMIF" description="COM interrupt flag" start="5" size="1" />
+      <BitField name="CC4IF" description="Capture/Compare 4 interrupt flag" start="4" size="1" />
+      <BitField name="CC3IF" description="Capture/Compare 3 interrupt flag" start="3" size="1" />
+      <BitField name="CC2IF" description="Capture/Compare 2 interrupt flag" start="2" size="1" />
+      <BitField name="CC1IF" description="Capture/compare 1 interrupt flag" start="1" size="1" />
+      <BitField name="UIF" description="Update interrupt flag" start="0" size="1" />
+    </Register>
+    <Register name="EGR" description="event generation register" start="+0x14" size="4" access="WriteOnly" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="UG" description="Update generation" start="0" size="1" />
+      <BitField name="CC1G" description="Capture/compare 1 generation" start="1" size="1" />
+      <BitField name="CC2G" description="Capture/compare 2 generation" start="2" size="1" />
+      <BitField name="CC3G" description="Capture/compare 3 generation" start="3" size="1" />
+      <BitField name="CC4G" description="Capture/compare 4 generation" start="4" size="1" />
+      <BitField name="COMG" description="Capture/Compare control update generation" start="5" size="1" />
+      <BitField name="TG" description="Trigger generation" start="6" size="1" />
+      <BitField name="BG" description="Break generation" start="7" size="1" />
+      <BitField name="B2G" description="Break 2 generation" start="8" size="1" />
+    </Register>
+    <Register name="CCMR1_Output" description="capture/compare mode register 1 (output mode)" start="+0x18" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CC1S" description="Capture/Compare 1 selection" start="0" size="2" />
+      <BitField name="OC1FE" description="Output Compare 1 fast enable" start="2" size="1" />
+      <BitField name="OC1PE" description="Output Compare 1 preload enable" start="3" size="1" />
+      <BitField name="OC1M" description="Output Compare 1 mode" start="4" size="3" />
+      <BitField name="OC1CE" description="Output Compare 1 clear enable" start="7" size="1" />
+      <BitField name="CC2S" description="Capture/Compare 2 selection" start="8" size="2" />
+      <BitField name="OC2FE" description="Output Compare 2 fast enable" start="10" size="1" />
+      <BitField name="OC2PE" description="Output Compare 2 preload enable" start="11" size="1" />
+      <BitField name="OC2M" description="Output Compare 2 mode" start="12" size="3" />
+      <BitField name="OC2CE" description="Output Compare 2 clear enable" start="15" size="1" />
+      <BitField name="OC1M_3" description="Output Compare 1 mode - bit 3" start="16" size="1" />
+      <BitField name="OC2M_3" description="Output Compare 2 mode - bit 3" start="24" size="1" />
+    </Register>
+    <Register name="CCMR1_Input" description="capture/compare mode register 1 (input mode)" start="+0x18" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IC2F" description="Input capture 2 filter" start="12" size="4" />
+      <BitField name="IC2PCS" description="Input capture 2 prescaler" start="10" size="2" />
+      <BitField name="CC2S" description="Capture/Compare 2 selection" start="8" size="2" />
+      <BitField name="IC1F" description="Input capture 1 filter" start="4" size="4" />
+      <BitField name="ICPCS" description="Input capture 1 prescaler" start="2" size="2" />
+      <BitField name="CC1S" description="Capture/Compare 1 selection" start="0" size="2" />
+    </Register>
+    <Register name="CCMR2_Output" description="capture/compare mode register 2 (output mode)" start="+0x1C" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CC3S" description="Capture/Compare 3 selection" start="0" size="2" />
+      <BitField name="OC3FE" description="Output compare 3 fast enable" start="2" size="1" />
+      <BitField name="OC3PE" description="Output compare 3 preload enable" start="3" size="1" />
+      <BitField name="OC3M" description="Output compare 3 mode" start="4" size="3" />
+      <BitField name="OC3CE" description="Output compare 3 clear enable" start="7" size="1" />
+      <BitField name="CC4S" description="Capture/Compare 4 selection" start="8" size="2" />
+      <BitField name="OC4FE" description="Output compare 4 fast enable" start="10" size="1" />
+      <BitField name="OC4PE" description="Output compare 4 preload enable" start="11" size="1" />
+      <BitField name="OC4M" description="Output compare 4 mode" start="12" size="3" />
+      <BitField name="OC4CE" description="Output compare 4 clear enable" start="15" size="1" />
+      <BitField name="OC3M_3" description="Output Compare 3 mode - bit 3" start="16" size="1" />
+      <BitField name="OC4M_4" description="Output Compare 4 mode - bit 3" start="24" size="1" />
+    </Register>
+    <Register name="CCMR2_Input" description="capture/compare mode register 2 (input mode)" start="+0x1C" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IC4F" description="Input capture 4 filter" start="12" size="4" />
+      <BitField name="IC4PSC" description="Input capture 4 prescaler" start="10" size="2" />
+      <BitField name="CC4S" description="Capture/Compare 4 selection" start="8" size="2" />
+      <BitField name="IC3F" description="Input capture 3 filter" start="4" size="4" />
+      <BitField name="IC3PSC" description="Input capture 3 prescaler" start="2" size="2" />
+      <BitField name="CC3S" description="Capture/compare 3 selection" start="0" size="2" />
+    </Register>
+    <Register name="CCER" description="capture/compare enable register" start="+0x20" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="CC1E" description="Capture/Compare 1 output enable" start="0" size="1" />
+      <BitField name="CC1P" description="Capture/Compare 1 output Polarity" start="1" size="1" />
+      <BitField name="CC1NE" description="Capture/Compare 1 complementary output enable" start="2" size="1" />
+      <BitField name="CC1NP" description="Capture/Compare 1 output Polarity" start="3" size="1" />
+      <BitField name="CC2E" description="Capture/Compare 2 output enable" start="4" size="1" />
+      <BitField name="CC2P" description="Capture/Compare 2 output Polarity" start="5" size="1" />
+      <BitField name="CC2NE" description="Capture/Compare 2 complementary output enable" start="6" size="1" />
+      <BitField name="CC2NP" description="Capture/Compare 2 output Polarity" start="7" size="1" />
+      <BitField name="CC3E" description="Capture/Compare 3 output enable" start="8" size="1" />
+      <BitField name="CC3P" description="Capture/Compare 3 output Polarity" start="9" size="1" />
+      <BitField name="CC3NE" description="Capture/Compare 3 complementary output enable" start="10" size="1" />
+      <BitField name="CC3NP" description="Capture/Compare 3 output Polarity" start="11" size="1" />
+      <BitField name="CC4E" description="Capture/Compare 4 output enable" start="12" size="1" />
+      <BitField name="CC4P" description="Capture/Compare 3 output Polarity" start="13" size="1" />
+      <BitField name="CC4NP" description="Capture/Compare 4 complementary output polarity" start="15" size="1" />
+      <BitField name="CC5E" description="Capture/Compare 5 output enable" start="16" size="1" />
+      <BitField name="CC5P" description="Capture/Compare 5 output polarity" start="17" size="1" />
+      <BitField name="CC6E" description="Capture/Compare 6 output enable" start="20" size="1" />
+      <BitField name="CC6P" description="Capture/Compare 6 output polarity" start="21" size="1" />
+    </Register>
+    <Register name="CNT" description="counter" start="+0x24" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CNT" description="counter value" start="0" size="16" access="Read/Write" />
+      <BitField name="UIFCPY" description="UIF copy" start="31" size="1" access="ReadOnly" />
+    </Register>
+    <Register name="PSC" description="prescaler" start="+0x28" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="PSC" description="Prescaler value" start="0" size="16" />
+    </Register>
+    <Register name="ARR" description="auto-reload register" start="+0x2C" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ARR" description="Auto-reload value" start="0" size="16" />
+    </Register>
+    <Register name="CCR1" description="capture/compare register 1" start="+0x34" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCR1" description="Capture/Compare 1 value" start="0" size="16" />
+    </Register>
+    <Register name="CCR2" description="capture/compare register 2" start="+0x38" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCR2" description="Capture/Compare 2 value" start="0" size="16" />
+    </Register>
+    <Register name="CCR3" description="capture/compare register 3" start="+0x3C" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCR3" description="Capture/Compare value" start="0" size="16" />
+    </Register>
+    <Register name="CCR4" description="capture/compare register 4" start="+0x40" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCR4" description="Capture/Compare value" start="0" size="16" />
+    </Register>
+    <Register name="DCR" description="DMA control register" start="+0x48" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="DBL" description="DMA burst length" start="8" size="5" />
+      <BitField name="DBA" description="DMA base address" start="0" size="5" />
+    </Register>
+    <Register name="DMAR" description="DMA address for full transfer" start="+0x4C" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAB" description="DMA register for burst accesses" start="0" size="16" />
+    </Register>
+    <Register name="RCR" description="repetition counter register" start="+0x30" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="REP" description="Repetition counter value" start="0" size="8" />
+    </Register>
+    <Register name="BDTR" description="break and dead-time register" start="+0x44" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="DTG" description="Dead-time generator setup" start="0" size="8" />
+      <BitField name="LOCK" description="Lock configuration" start="8" size="2" />
+      <BitField name="OSSI" description="Off-state selection for Idle mode" start="10" size="1" />
+      <BitField name="OSSR" description="Off-state selection for Run mode" start="11" size="1" />
+      <BitField name="BKE" description="Break enable" start="12" size="1" />
+      <BitField name="BKP" description="Break polarity" start="13" size="1" />
+      <BitField name="AOE" description="Automatic output enable" start="14" size="1" />
+      <BitField name="MOE" description="Main output enable" start="15" size="1" />
+      <BitField name="BKF" description="Break filter" start="16" size="4" />
+      <BitField name="BK2F" description="Break 2 filter" start="20" size="4" />
+      <BitField name="BK2E" description="Break 2 enable" start="24" size="1" />
+      <BitField name="BK2P" description="Break 2 polarity" start="25" size="1" />
+    </Register>
+    <Register name="CCMR3_Output" description="capture/compare mode register 3 (output mode)" start="+0x54" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="OC5FE" description="Output compare 5 fast enable" start="2" size="1" />
+      <BitField name="OC5PE" description="Output compare 5 preload enable" start="3" size="1" />
+      <BitField name="OC5M" description="Output compare 5 mode" start="4" size="3" />
+      <BitField name="OC5CE" description="Output compare 5 clear enable" start="7" size="1" />
+      <BitField name="OC6FE" description="Output compare 6 fast enable" start="10" size="1" />
+      <BitField name="OC6PE" description="Output compare 6 preload enable" start="11" size="1" />
+      <BitField name="OC6M" description="Output compare 6 mode" start="12" size="3" />
+      <BitField name="OC6CE" description="Output compare 6 clear enable" start="15" size="1" />
+      <BitField name="OC5M3" description="Output Compare 5 mode" start="16" size="1" />
+      <BitField name="OC6M3" description="Output Compare 6 mode" start="24" size="1" />
+    </Register>
+    <Register name="CCR5" description="capture/compare register 5" start="+0x58" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCR5" description="Capture/Compare 5 value" start="0" size="16" />
+      <BitField name="GC5C1" description="Group Channel 5 and Channel 1" start="29" size="1" />
+      <BitField name="GC5C2" description="Group Channel 5 and Channel 2" start="30" size="1" />
+      <BitField name="GC5C3" description="Group Channel 5 and Channel 3" start="31" size="1" />
+    </Register>
+    <Register name="CRR6" description="capture/compare register 6" start="+0x5C" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCR6" description="Capture/Compare 6 value" start="0" size="16" />
+    </Register>
+    <Register name="AF1" description="TIM1 alternate function option register 1" start="+0x60" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="BKINE" description="BRK BKIN input enable" start="0" size="1" />
+      <BitField name="BKCMP1E" description="BRK COMP1 enable" start="1" size="1" />
+      <BitField name="BKCMP2E" description="BRK COMP2 enable" start="2" size="1" />
+      <BitField name="BKDF1BK0E" description="BRK dfsdm1_break[0] enable" start="8" size="1" />
+      <BitField name="BKINP" description="BRK BKIN input polarity" start="9" size="1" />
+      <BitField name="BKCMP1P" description="BRK COMP1 input polarity" start="10" size="1" />
+      <BitField name="BKCMP2P" description="BRK COMP2 input polarity" start="11" size="1" />
+      <BitField name="ETRSEL" description="ETR source selection" start="14" size="4" />
+    </Register>
+    <Register name="AF2" description="TIM1 Alternate function odfsdm1_breakster 2" start="+0x64" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="BK2INE" description="BRK2 BKIN input enable" start="0" size="1" />
+      <BitField name="BK2CMP1E" description="BRK2 COMP1 enable" start="1" size="1" />
+      <BitField name="BK2CMP2E" description="BRK2 COMP2 enable" start="2" size="1" />
+      <BitField name="BK2DF1BK1E" description="BRK2 dfsdm1_break[1] enable" start="8" size="1" />
+      <BitField name="BK2INP" description="BRK2 BKIN2 input polarity" start="9" size="1" />
+      <BitField name="BK2CMP1P" description="BRK2 COMP1 input polarit" start="10" size="1" />
+      <BitField name="BK2CMP2P" description="BRK2 COMP2 input polarity" start="11" size="1" />
+    </Register>
+    <Register name="TISEL" description="TIM1 timer input selection register" start="+0x68" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="TI1SEL" description="selects TI1[0] to TI1[15] input" start="0" size="4" />
+      <BitField name="TI2SEL" description="selects TI2[0] to TI2[15] input" start="8" size="4" />
+      <BitField name="TI3SEL" description="selects TI3[0] to TI3[15] input" start="16" size="4" />
+      <BitField name="TI4SEL" description="selects TI4[0] to TI4[15] input" start="24" size="4" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="TIM12" description="General purpose timers" start="0x40001800">
+    <Register name="CR1" description="control register 1" start="+0x0" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="UIFREMAP" description="UIF status bit remapping" start="11" size="1" />
+      <BitField name="CKD" description="Clock division" start="8" size="2" />
+      <BitField name="ARPE" description="Auto-reload preload enable" start="7" size="1" />
+      <BitField name="CMS" description="Center-aligned mode selection" start="5" size="2" />
+      <BitField name="DIR" description="Direction" start="4" size="1" />
+      <BitField name="OPM" description="One-pulse mode" start="3" size="1" />
+      <BitField name="URS" description="Update request source" start="2" size="1" />
+      <BitField name="UDIS" description="Update disable" start="1" size="1" />
+      <BitField name="CEN" description="Counter enable" start="0" size="1" />
+    </Register>
+    <Register name="CR2" description="control register 2" start="+0x4" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="TI1S" description="TI1 selection" start="7" size="1" />
+      <BitField name="MMS" description="Master mode selection" start="4" size="3" />
+      <BitField name="CCDS" description="Capture/compare DMA selection" start="3" size="1" />
+    </Register>
+    <Register name="SMCR" description="slave mode control register" start="+0x8" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="TS_4_3" description="Trigger selection" start="20" size="2" />
+      <BitField name="SMS_3" description="Slave mode selection - bit 3" start="16" size="1" />
+      <BitField name="ETP" description="External trigger polarity" start="15" size="1" />
+      <BitField name="ECE" description="External clock enable" start="14" size="1" />
+      <BitField name="ETPS" description="External trigger prescaler" start="12" size="2" />
+      <BitField name="ETF" description="External trigger filter" start="8" size="4" />
+      <BitField name="MSM" description="Master/Slave mode" start="7" size="1" />
+      <BitField name="TS" description="Trigger selection" start="4" size="3" />
+      <BitField name="SMS" description="Slave mode selection" start="0" size="3" />
+    </Register>
+    <Register name="DIER" description="DMA/Interrupt enable register" start="+0xC" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="TDE" description="Trigger DMA request enable" start="14" size="1" />
+      <BitField name="CC4DE" description="Capture/Compare 4 DMA request enable" start="12" size="1" />
+      <BitField name="CC3DE" description="Capture/Compare 3 DMA request enable" start="11" size="1" />
+      <BitField name="CC2DE" description="Capture/Compare 2 DMA request enable" start="10" size="1" />
+      <BitField name="CC1DE" description="Capture/Compare 1 DMA request enable" start="9" size="1" />
+      <BitField name="UDE" description="Update DMA request enable" start="8" size="1" />
+      <BitField name="TIE" description="Trigger interrupt enable" start="6" size="1" />
+      <BitField name="CC4IE" description="Capture/Compare 4 interrupt enable" start="4" size="1" />
+      <BitField name="CC3IE" description="Capture/Compare 3 interrupt enable" start="3" size="1" />
+      <BitField name="CC2IE" description="Capture/Compare 2 interrupt enable" start="2" size="1" />
+      <BitField name="CC1IE" description="Capture/Compare 1 interrupt enable" start="1" size="1" />
+      <BitField name="UIE" description="Update interrupt enable" start="0" size="1" />
+    </Register>
+    <Register name="SR" description="status register" start="+0x10" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="CC4OF" description="Capture/Compare 4 overcapture flag" start="12" size="1" />
+      <BitField name="CC3OF" description="Capture/Compare 3 overcapture flag" start="11" size="1" />
+      <BitField name="CC2OF" description="Capture/compare 2 overcapture flag" start="10" size="1" />
+      <BitField name="CC1OF" description="Capture/Compare 1 overcapture flag" start="9" size="1" />
+      <BitField name="TIF" description="Trigger interrupt flag" start="6" size="1" />
+      <BitField name="CC4IF" description="Capture/Compare 4 interrupt flag" start="4" size="1" />
+      <BitField name="CC3IF" description="Capture/Compare 3 interrupt flag" start="3" size="1" />
+      <BitField name="CC2IF" description="Capture/Compare 2 interrupt flag" start="2" size="1" />
+      <BitField name="CC1IF" description="Capture/compare 1 interrupt flag" start="1" size="1" />
+      <BitField name="UIF" description="Update interrupt flag" start="0" size="1" />
+    </Register>
+    <Register name="EGR" description="event generation register" start="+0x14" size="4" access="WriteOnly" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="TG" description="Trigger generation" start="6" size="1" />
+      <BitField name="CC4G" description="Capture/compare 4 generation" start="4" size="1" />
+      <BitField name="CC3G" description="Capture/compare 3 generation" start="3" size="1" />
+      <BitField name="CC2G" description="Capture/compare 2 generation" start="2" size="1" />
+      <BitField name="CC1G" description="Capture/compare 1 generation" start="1" size="1" />
+      <BitField name="UG" description="Update generation" start="0" size="1" />
+    </Register>
+    <Register name="CCMR1_Output" description="capture/compare mode register 1 (output mode)" start="+0x18" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CC1S" description="CC1S" start="0" size="2" />
+      <BitField name="OC1FE" description="OC1FE" start="2" size="1" />
+      <BitField name="OC1PE" description="OC1PE" start="3" size="1" />
+      <BitField name="OC1M" description="OC1M" start="4" size="3" />
+      <BitField name="OC1CE" description="OC1CE" start="7" size="1" />
+      <BitField name="CC2S" description="CC2S" start="8" size="2" />
+      <BitField name="OC2FE" description="OC2FE" start="10" size="1" />
+      <BitField name="OC2PE" description="OC2PE" start="11" size="1" />
+      <BitField name="OC2M" description="OC2M" start="12" size="3" />
+      <BitField name="OC2CE" description="OC2CE" start="15" size="1" />
+      <BitField name="OC1M_3" description="Output Compare 1 mode - bit 3" start="16" size="1" />
+      <BitField name="OC2M_3" description="Output Compare 2 mode - bit 3" start="24" size="1" />
+    </Register>
+    <Register name="CCMR1_Input" description="capture/compare mode register 1 (input mode)" start="+0x18" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IC2F" description="Input capture 2 filter" start="12" size="4" />
+      <BitField name="IC2PCS" description="Input capture 2 prescaler" start="10" size="2" />
+      <BitField name="CC2S" description="Capture/Compare 2 selection" start="8" size="2" />
+      <BitField name="IC1F" description="Input capture 1 filter" start="4" size="4" />
+      <BitField name="ICPCS" description="Input capture 1 prescaler" start="2" size="2" />
+      <BitField name="CC1S" description="Capture/Compare 1 selection" start="0" size="2" />
+    </Register>
+    <Register name="CCMR2_Output" description="capture/compare mode register 2 (output mode)" start="+0x1C" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OC4M_3" description="Output Compare 2 mode - bit 3" start="24" size="1" />
+      <BitField name="OC3M_3" description="Output Compare 1 mode - bit 3" start="16" size="1" />
+      <BitField name="OC4CE" description="OC4CE" start="15" size="1" />
+      <BitField name="OC4M" description="OC4M" start="12" size="3" />
+      <BitField name="OC4PE" description="OC4PE" start="11" size="1" />
+      <BitField name="OC4FE" description="OC4FE" start="10" size="1" />
+      <BitField name="CC4S" description="CC4S" start="8" size="2" />
+      <BitField name="OC3CE" description="OC3CE" start="7" size="1" />
+      <BitField name="OC3M" description="OC3M" start="4" size="3" />
+      <BitField name="OC3PE" description="OC3PE" start="3" size="1" />
+      <BitField name="OC3FE" description="OC3FE" start="2" size="1" />
+      <BitField name="CC3S" description="CC3S" start="0" size="2" />
+    </Register>
+    <Register name="CCMR2_Input" description="capture/compare mode register 2 (input mode)" start="+0x1C" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IC4F" description="Input capture 4 filter" start="12" size="4" />
+      <BitField name="IC4PSC" description="Input capture 4 prescaler" start="10" size="2" />
+      <BitField name="CC4S" description="Capture/Compare 4 selection" start="8" size="2" />
+      <BitField name="IC3F" description="Input capture 3 filter" start="4" size="4" />
+      <BitField name="IC3PSC" description="Input capture 3 prescaler" start="2" size="2" />
+      <BitField name="CC3S" description="Capture/compare 3 selection" start="0" size="2" />
+    </Register>
+    <Register name="CCER" description="capture/compare enable register" start="+0x20" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="CC4NP" description="Capture/Compare 4 output Polarity" start="15" size="1" />
+      <BitField name="CC4P" description="Capture/Compare 3 output Polarity" start="13" size="1" />
+      <BitField name="CC4E" description="Capture/Compare 4 output enable" start="12" size="1" />
+      <BitField name="CC3NP" description="Capture/Compare 3 output Polarity" start="11" size="1" />
+      <BitField name="CC3P" description="Capture/Compare 3 output Polarity" start="9" size="1" />
+      <BitField name="CC3E" description="Capture/Compare 3 output enable" start="8" size="1" />
+      <BitField name="CC2NP" description="Capture/Compare 2 output Polarity" start="7" size="1" />
+      <BitField name="CC2P" description="Capture/Compare 2 output Polarity" start="5" size="1" />
+      <BitField name="CC2E" description="Capture/Compare 2 output enable" start="4" size="1" />
+      <BitField name="CC1NP" description="Capture/Compare 1 output Polarity" start="3" size="1" />
+      <BitField name="CC1P" description="Capture/Compare 1 output Polarity" start="1" size="1" />
+      <BitField name="CC1E" description="Capture/Compare 1 output enable" start="0" size="1" />
+    </Register>
+    <Register name="CNT" description="counter" start="+0x24" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CNT_L" description="low counter value" start="0" size="16" />
+      <BitField name="CNT_H" description="High counter value" start="16" size="16" />
+    </Register>
+    <Register name="PSC" description="prescaler" start="+0x28" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="PSC" description="Prescaler value" start="0" size="16" />
+    </Register>
+    <Register name="ARR" description="auto-reload register" start="+0x2C" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ARR_H" description="High Auto-reload value" start="16" size="16" />
+      <BitField name="ARR_L" description="Low Auto-reload value" start="0" size="16" />
+    </Register>
+    <Register name="CCR1" description="capture/compare register 1" start="+0x34" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCR1_H" description="High Capture/Compare 1 value" start="16" size="16" />
+      <BitField name="CCR1_L" description="Low Capture/Compare 1 value" start="0" size="16" />
+    </Register>
+    <Register name="CCR2" description="capture/compare register 2" start="+0x38" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCR2_H" description="High Capture/Compare 2 value" start="16" size="16" />
+      <BitField name="CCR2_L" description="Low Capture/Compare 2 value" start="0" size="16" />
+    </Register>
+    <Register name="CCR3" description="capture/compare register 3" start="+0x3C" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCR3_H" description="High Capture/Compare value" start="16" size="16" />
+      <BitField name="CCR3_L" description="Low Capture/Compare value" start="0" size="16" />
+    </Register>
+    <Register name="CCR4" description="capture/compare register 4" start="+0x40" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCR4_H" description="High Capture/Compare value" start="16" size="16" />
+      <BitField name="CCR4_L" description="Low Capture/Compare value" start="0" size="16" />
+    </Register>
+    <Register name="DCR" description="DMA control register" start="+0x48" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="DBL" description="DMA burst length" start="8" size="5" />
+      <BitField name="DBA" description="DMA base address" start="0" size="5" />
+    </Register>
+    <Register name="DMAR" description="DMA address for full transfer" start="+0x4C" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAB" description="DMA register for burst accesses" start="0" size="16" />
+    </Register>
+    <Register name="AF1" description="TIM alternate function option register 1" start="+0x60" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="ETRSEL" description="ETR source selection" start="14" size="4" />
+    </Register>
+    <Register name="TISEL" description="TIM timer input selection register" start="+0x68" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="TI1SEL" description="TI1[0] to TI1[15] input selection" start="0" size="4" />
+      <BitField name="TI2SEL" description="TI2[0] to TI2[15] input selection" start="8" size="4" />
+      <BitField name="TI3SEL" description="TI3[0] to TI3[15] input selection" start="16" size="4" />
+      <BitField name="TI4SEL" description="TI4[0] to TI4[15] input selection" start="24" size="4" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="TIM13" description="General purpose timers" start="0x40001C00">
+    <Register name="CR1" description="control register 1" start="+0x0" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="UIFREMAP" description="UIF status bit remapping" start="11" size="1" />
+      <BitField name="CKD" description="Clock division" start="8" size="2" />
+      <BitField name="ARPE" description="Auto-reload preload enable" start="7" size="1" />
+      <BitField name="CMS" description="Center-aligned mode selection" start="5" size="2" />
+      <BitField name="DIR" description="Direction" start="4" size="1" />
+      <BitField name="OPM" description="One-pulse mode" start="3" size="1" />
+      <BitField name="URS" description="Update request source" start="2" size="1" />
+      <BitField name="UDIS" description="Update disable" start="1" size="1" />
+      <BitField name="CEN" description="Counter enable" start="0" size="1" />
+    </Register>
+    <Register name="CR2" description="control register 2" start="+0x4" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="TI1S" description="TI1 selection" start="7" size="1" />
+      <BitField name="MMS" description="Master mode selection" start="4" size="3" />
+      <BitField name="CCDS" description="Capture/compare DMA selection" start="3" size="1" />
+    </Register>
+    <Register name="SMCR" description="slave mode control register" start="+0x8" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="TS_4_3" description="Trigger selection" start="20" size="2" />
+      <BitField name="SMS_3" description="Slave mode selection - bit 3" start="16" size="1" />
+      <BitField name="ETP" description="External trigger polarity" start="15" size="1" />
+      <BitField name="ECE" description="External clock enable" start="14" size="1" />
+      <BitField name="ETPS" description="External trigger prescaler" start="12" size="2" />
+      <BitField name="ETF" description="External trigger filter" start="8" size="4" />
+      <BitField name="MSM" description="Master/Slave mode" start="7" size="1" />
+      <BitField name="TS" description="Trigger selection" start="4" size="3" />
+      <BitField name="SMS" description="Slave mode selection" start="0" size="3" />
+    </Register>
+    <Register name="DIER" description="DMA/Interrupt enable register" start="+0xC" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="TDE" description="Trigger DMA request enable" start="14" size="1" />
+      <BitField name="CC4DE" description="Capture/Compare 4 DMA request enable" start="12" size="1" />
+      <BitField name="CC3DE" description="Capture/Compare 3 DMA request enable" start="11" size="1" />
+      <BitField name="CC2DE" description="Capture/Compare 2 DMA request enable" start="10" size="1" />
+      <BitField name="CC1DE" description="Capture/Compare 1 DMA request enable" start="9" size="1" />
+      <BitField name="UDE" description="Update DMA request enable" start="8" size="1" />
+      <BitField name="TIE" description="Trigger interrupt enable" start="6" size="1" />
+      <BitField name="CC4IE" description="Capture/Compare 4 interrupt enable" start="4" size="1" />
+      <BitField name="CC3IE" description="Capture/Compare 3 interrupt enable" start="3" size="1" />
+      <BitField name="CC2IE" description="Capture/Compare 2 interrupt enable" start="2" size="1" />
+      <BitField name="CC1IE" description="Capture/Compare 1 interrupt enable" start="1" size="1" />
+      <BitField name="UIE" description="Update interrupt enable" start="0" size="1" />
+    </Register>
+    <Register name="SR" description="status register" start="+0x10" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="CC4OF" description="Capture/Compare 4 overcapture flag" start="12" size="1" />
+      <BitField name="CC3OF" description="Capture/Compare 3 overcapture flag" start="11" size="1" />
+      <BitField name="CC2OF" description="Capture/compare 2 overcapture flag" start="10" size="1" />
+      <BitField name="CC1OF" description="Capture/Compare 1 overcapture flag" start="9" size="1" />
+      <BitField name="TIF" description="Trigger interrupt flag" start="6" size="1" />
+      <BitField name="CC4IF" description="Capture/Compare 4 interrupt flag" start="4" size="1" />
+      <BitField name="CC3IF" description="Capture/Compare 3 interrupt flag" start="3" size="1" />
+      <BitField name="CC2IF" description="Capture/Compare 2 interrupt flag" start="2" size="1" />
+      <BitField name="CC1IF" description="Capture/compare 1 interrupt flag" start="1" size="1" />
+      <BitField name="UIF" description="Update interrupt flag" start="0" size="1" />
+    </Register>
+    <Register name="EGR" description="event generation register" start="+0x14" size="4" access="WriteOnly" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="TG" description="Trigger generation" start="6" size="1" />
+      <BitField name="CC4G" description="Capture/compare 4 generation" start="4" size="1" />
+      <BitField name="CC3G" description="Capture/compare 3 generation" start="3" size="1" />
+      <BitField name="CC2G" description="Capture/compare 2 generation" start="2" size="1" />
+      <BitField name="CC1G" description="Capture/compare 1 generation" start="1" size="1" />
+      <BitField name="UG" description="Update generation" start="0" size="1" />
+    </Register>
+    <Register name="CCMR1_Output" description="capture/compare mode register 1 (output mode)" start="+0x18" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CC1S" description="CC1S" start="0" size="2" />
+      <BitField name="OC1FE" description="OC1FE" start="2" size="1" />
+      <BitField name="OC1PE" description="OC1PE" start="3" size="1" />
+      <BitField name="OC1M" description="OC1M" start="4" size="3" />
+      <BitField name="OC1CE" description="OC1CE" start="7" size="1" />
+      <BitField name="CC2S" description="CC2S" start="8" size="2" />
+      <BitField name="OC2FE" description="OC2FE" start="10" size="1" />
+      <BitField name="OC2PE" description="OC2PE" start="11" size="1" />
+      <BitField name="OC2M" description="OC2M" start="12" size="3" />
+      <BitField name="OC2CE" description="OC2CE" start="15" size="1" />
+      <BitField name="OC1M_3" description="Output Compare 1 mode - bit 3" start="16" size="1" />
+      <BitField name="OC2M_3" description="Output Compare 2 mode - bit 3" start="24" size="1" />
+    </Register>
+    <Register name="CCMR1_Input" description="capture/compare mode register 1 (input mode)" start="+0x18" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IC2F" description="Input capture 2 filter" start="12" size="4" />
+      <BitField name="IC2PCS" description="Input capture 2 prescaler" start="10" size="2" />
+      <BitField name="CC2S" description="Capture/Compare 2 selection" start="8" size="2" />
+      <BitField name="IC1F" description="Input capture 1 filter" start="4" size="4" />
+      <BitField name="ICPCS" description="Input capture 1 prescaler" start="2" size="2" />
+      <BitField name="CC1S" description="Capture/Compare 1 selection" start="0" size="2" />
+    </Register>
+    <Register name="CCMR2_Output" description="capture/compare mode register 2 (output mode)" start="+0x1C" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OC4M_3" description="Output Compare 2 mode - bit 3" start="24" size="1" />
+      <BitField name="OC3M_3" description="Output Compare 1 mode - bit 3" start="16" size="1" />
+      <BitField name="OC4CE" description="OC4CE" start="15" size="1" />
+      <BitField name="OC4M" description="OC4M" start="12" size="3" />
+      <BitField name="OC4PE" description="OC4PE" start="11" size="1" />
+      <BitField name="OC4FE" description="OC4FE" start="10" size="1" />
+      <BitField name="CC4S" description="CC4S" start="8" size="2" />
+      <BitField name="OC3CE" description="OC3CE" start="7" size="1" />
+      <BitField name="OC3M" description="OC3M" start="4" size="3" />
+      <BitField name="OC3PE" description="OC3PE" start="3" size="1" />
+      <BitField name="OC3FE" description="OC3FE" start="2" size="1" />
+      <BitField name="CC3S" description="CC3S" start="0" size="2" />
+    </Register>
+    <Register name="CCMR2_Input" description="capture/compare mode register 2 (input mode)" start="+0x1C" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IC4F" description="Input capture 4 filter" start="12" size="4" />
+      <BitField name="IC4PSC" description="Input capture 4 prescaler" start="10" size="2" />
+      <BitField name="CC4S" description="Capture/Compare 4 selection" start="8" size="2" />
+      <BitField name="IC3F" description="Input capture 3 filter" start="4" size="4" />
+      <BitField name="IC3PSC" description="Input capture 3 prescaler" start="2" size="2" />
+      <BitField name="CC3S" description="Capture/compare 3 selection" start="0" size="2" />
+    </Register>
+    <Register name="CCER" description="capture/compare enable register" start="+0x20" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="CC4NP" description="Capture/Compare 4 output Polarity" start="15" size="1" />
+      <BitField name="CC4P" description="Capture/Compare 3 output Polarity" start="13" size="1" />
+      <BitField name="CC4E" description="Capture/Compare 4 output enable" start="12" size="1" />
+      <BitField name="CC3NP" description="Capture/Compare 3 output Polarity" start="11" size="1" />
+      <BitField name="CC3P" description="Capture/Compare 3 output Polarity" start="9" size="1" />
+      <BitField name="CC3E" description="Capture/Compare 3 output enable" start="8" size="1" />
+      <BitField name="CC2NP" description="Capture/Compare 2 output Polarity" start="7" size="1" />
+      <BitField name="CC2P" description="Capture/Compare 2 output Polarity" start="5" size="1" />
+      <BitField name="CC2E" description="Capture/Compare 2 output enable" start="4" size="1" />
+      <BitField name="CC1NP" description="Capture/Compare 1 output Polarity" start="3" size="1" />
+      <BitField name="CC1P" description="Capture/Compare 1 output Polarity" start="1" size="1" />
+      <BitField name="CC1E" description="Capture/Compare 1 output enable" start="0" size="1" />
+    </Register>
+    <Register name="CNT" description="counter" start="+0x24" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CNT_L" description="low counter value" start="0" size="16" />
+      <BitField name="CNT_H" description="High counter value" start="16" size="16" />
+    </Register>
+    <Register name="PSC" description="prescaler" start="+0x28" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="PSC" description="Prescaler value" start="0" size="16" />
+    </Register>
+    <Register name="ARR" description="auto-reload register" start="+0x2C" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ARR_H" description="High Auto-reload value" start="16" size="16" />
+      <BitField name="ARR_L" description="Low Auto-reload value" start="0" size="16" />
+    </Register>
+    <Register name="CCR1" description="capture/compare register 1" start="+0x34" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCR1_H" description="High Capture/Compare 1 value" start="16" size="16" />
+      <BitField name="CCR1_L" description="Low Capture/Compare 1 value" start="0" size="16" />
+    </Register>
+    <Register name="CCR2" description="capture/compare register 2" start="+0x38" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCR2_H" description="High Capture/Compare 2 value" start="16" size="16" />
+      <BitField name="CCR2_L" description="Low Capture/Compare 2 value" start="0" size="16" />
+    </Register>
+    <Register name="CCR3" description="capture/compare register 3" start="+0x3C" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCR3_H" description="High Capture/Compare value" start="16" size="16" />
+      <BitField name="CCR3_L" description="Low Capture/Compare value" start="0" size="16" />
+    </Register>
+    <Register name="CCR4" description="capture/compare register 4" start="+0x40" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCR4_H" description="High Capture/Compare value" start="16" size="16" />
+      <BitField name="CCR4_L" description="Low Capture/Compare value" start="0" size="16" />
+    </Register>
+    <Register name="DCR" description="DMA control register" start="+0x48" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="DBL" description="DMA burst length" start="8" size="5" />
+      <BitField name="DBA" description="DMA base address" start="0" size="5" />
+    </Register>
+    <Register name="DMAR" description="DMA address for full transfer" start="+0x4C" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAB" description="DMA register for burst accesses" start="0" size="16" />
+    </Register>
+    <Register name="AF1" description="TIM alternate function option register 1" start="+0x60" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="ETRSEL" description="ETR source selection" start="14" size="4" />
+    </Register>
+    <Register name="TISEL" description="TIM timer input selection register" start="+0x68" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="TI1SEL" description="TI1[0] to TI1[15] input selection" start="0" size="4" />
+      <BitField name="TI2SEL" description="TI2[0] to TI2[15] input selection" start="8" size="4" />
+      <BitField name="TI3SEL" description="TI3[0] to TI3[15] input selection" start="16" size="4" />
+      <BitField name="TI4SEL" description="TI4[0] to TI4[15] input selection" start="24" size="4" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="TIM14" description="General purpose timers" start="0x40002000">
+    <Register name="CR1" description="control register 1" start="+0x0" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="UIFREMAP" description="UIF status bit remapping" start="11" size="1" />
+      <BitField name="CKD" description="Clock division" start="8" size="2" />
+      <BitField name="ARPE" description="Auto-reload preload enable" start="7" size="1" />
+      <BitField name="CMS" description="Center-aligned mode selection" start="5" size="2" />
+      <BitField name="DIR" description="Direction" start="4" size="1" />
+      <BitField name="OPM" description="One-pulse mode" start="3" size="1" />
+      <BitField name="URS" description="Update request source" start="2" size="1" />
+      <BitField name="UDIS" description="Update disable" start="1" size="1" />
+      <BitField name="CEN" description="Counter enable" start="0" size="1" />
+    </Register>
+    <Register name="CR2" description="control register 2" start="+0x4" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="TI1S" description="TI1 selection" start="7" size="1" />
+      <BitField name="MMS" description="Master mode selection" start="4" size="3" />
+      <BitField name="CCDS" description="Capture/compare DMA selection" start="3" size="1" />
+    </Register>
+    <Register name="SMCR" description="slave mode control register" start="+0x8" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="TS_4_3" description="Trigger selection" start="20" size="2" />
+      <BitField name="SMS_3" description="Slave mode selection - bit 3" start="16" size="1" />
+      <BitField name="ETP" description="External trigger polarity" start="15" size="1" />
+      <BitField name="ECE" description="External clock enable" start="14" size="1" />
+      <BitField name="ETPS" description="External trigger prescaler" start="12" size="2" />
+      <BitField name="ETF" description="External trigger filter" start="8" size="4" />
+      <BitField name="MSM" description="Master/Slave mode" start="7" size="1" />
+      <BitField name="TS" description="Trigger selection" start="4" size="3" />
+      <BitField name="SMS" description="Slave mode selection" start="0" size="3" />
+    </Register>
+    <Register name="DIER" description="DMA/Interrupt enable register" start="+0xC" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="TDE" description="Trigger DMA request enable" start="14" size="1" />
+      <BitField name="CC4DE" description="Capture/Compare 4 DMA request enable" start="12" size="1" />
+      <BitField name="CC3DE" description="Capture/Compare 3 DMA request enable" start="11" size="1" />
+      <BitField name="CC2DE" description="Capture/Compare 2 DMA request enable" start="10" size="1" />
+      <BitField name="CC1DE" description="Capture/Compare 1 DMA request enable" start="9" size="1" />
+      <BitField name="UDE" description="Update DMA request enable" start="8" size="1" />
+      <BitField name="TIE" description="Trigger interrupt enable" start="6" size="1" />
+      <BitField name="CC4IE" description="Capture/Compare 4 interrupt enable" start="4" size="1" />
+      <BitField name="CC3IE" description="Capture/Compare 3 interrupt enable" start="3" size="1" />
+      <BitField name="CC2IE" description="Capture/Compare 2 interrupt enable" start="2" size="1" />
+      <BitField name="CC1IE" description="Capture/Compare 1 interrupt enable" start="1" size="1" />
+      <BitField name="UIE" description="Update interrupt enable" start="0" size="1" />
+    </Register>
+    <Register name="SR" description="status register" start="+0x10" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="CC4OF" description="Capture/Compare 4 overcapture flag" start="12" size="1" />
+      <BitField name="CC3OF" description="Capture/Compare 3 overcapture flag" start="11" size="1" />
+      <BitField name="CC2OF" description="Capture/compare 2 overcapture flag" start="10" size="1" />
+      <BitField name="CC1OF" description="Capture/Compare 1 overcapture flag" start="9" size="1" />
+      <BitField name="TIF" description="Trigger interrupt flag" start="6" size="1" />
+      <BitField name="CC4IF" description="Capture/Compare 4 interrupt flag" start="4" size="1" />
+      <BitField name="CC3IF" description="Capture/Compare 3 interrupt flag" start="3" size="1" />
+      <BitField name="CC2IF" description="Capture/Compare 2 interrupt flag" start="2" size="1" />
+      <BitField name="CC1IF" description="Capture/compare 1 interrupt flag" start="1" size="1" />
+      <BitField name="UIF" description="Update interrupt flag" start="0" size="1" />
+    </Register>
+    <Register name="EGR" description="event generation register" start="+0x14" size="4" access="WriteOnly" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="TG" description="Trigger generation" start="6" size="1" />
+      <BitField name="CC4G" description="Capture/compare 4 generation" start="4" size="1" />
+      <BitField name="CC3G" description="Capture/compare 3 generation" start="3" size="1" />
+      <BitField name="CC2G" description="Capture/compare 2 generation" start="2" size="1" />
+      <BitField name="CC1G" description="Capture/compare 1 generation" start="1" size="1" />
+      <BitField name="UG" description="Update generation" start="0" size="1" />
+    </Register>
+    <Register name="CCMR1_Output" description="capture/compare mode register 1 (output mode)" start="+0x18" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CC1S" description="CC1S" start="0" size="2" />
+      <BitField name="OC1FE" description="OC1FE" start="2" size="1" />
+      <BitField name="OC1PE" description="OC1PE" start="3" size="1" />
+      <BitField name="OC1M" description="OC1M" start="4" size="3" />
+      <BitField name="OC1CE" description="OC1CE" start="7" size="1" />
+      <BitField name="CC2S" description="CC2S" start="8" size="2" />
+      <BitField name="OC2FE" description="OC2FE" start="10" size="1" />
+      <BitField name="OC2PE" description="OC2PE" start="11" size="1" />
+      <BitField name="OC2M" description="OC2M" start="12" size="3" />
+      <BitField name="OC2CE" description="OC2CE" start="15" size="1" />
+      <BitField name="OC1M_3" description="Output Compare 1 mode - bit 3" start="16" size="1" />
+      <BitField name="OC2M_3" description="Output Compare 2 mode - bit 3" start="24" size="1" />
+    </Register>
+    <Register name="CCMR1_Input" description="capture/compare mode register 1 (input mode)" start="+0x18" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IC2F" description="Input capture 2 filter" start="12" size="4" />
+      <BitField name="IC2PCS" description="Input capture 2 prescaler" start="10" size="2" />
+      <BitField name="CC2S" description="Capture/Compare 2 selection" start="8" size="2" />
+      <BitField name="IC1F" description="Input capture 1 filter" start="4" size="4" />
+      <BitField name="ICPCS" description="Input capture 1 prescaler" start="2" size="2" />
+      <BitField name="CC1S" description="Capture/Compare 1 selection" start="0" size="2" />
+    </Register>
+    <Register name="CCMR2_Output" description="capture/compare mode register 2 (output mode)" start="+0x1C" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OC4M_3" description="Output Compare 2 mode - bit 3" start="24" size="1" />
+      <BitField name="OC3M_3" description="Output Compare 1 mode - bit 3" start="16" size="1" />
+      <BitField name="OC4CE" description="OC4CE" start="15" size="1" />
+      <BitField name="OC4M" description="OC4M" start="12" size="3" />
+      <BitField name="OC4PE" description="OC4PE" start="11" size="1" />
+      <BitField name="OC4FE" description="OC4FE" start="10" size="1" />
+      <BitField name="CC4S" description="CC4S" start="8" size="2" />
+      <BitField name="OC3CE" description="OC3CE" start="7" size="1" />
+      <BitField name="OC3M" description="OC3M" start="4" size="3" />
+      <BitField name="OC3PE" description="OC3PE" start="3" size="1" />
+      <BitField name="OC3FE" description="OC3FE" start="2" size="1" />
+      <BitField name="CC3S" description="CC3S" start="0" size="2" />
+    </Register>
+    <Register name="CCMR2_Input" description="capture/compare mode register 2 (input mode)" start="+0x1C" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IC4F" description="Input capture 4 filter" start="12" size="4" />
+      <BitField name="IC4PSC" description="Input capture 4 prescaler" start="10" size="2" />
+      <BitField name="CC4S" description="Capture/Compare 4 selection" start="8" size="2" />
+      <BitField name="IC3F" description="Input capture 3 filter" start="4" size="4" />
+      <BitField name="IC3PSC" description="Input capture 3 prescaler" start="2" size="2" />
+      <BitField name="CC3S" description="Capture/compare 3 selection" start="0" size="2" />
+    </Register>
+    <Register name="CCER" description="capture/compare enable register" start="+0x20" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="CC4NP" description="Capture/Compare 4 output Polarity" start="15" size="1" />
+      <BitField name="CC4P" description="Capture/Compare 3 output Polarity" start="13" size="1" />
+      <BitField name="CC4E" description="Capture/Compare 4 output enable" start="12" size="1" />
+      <BitField name="CC3NP" description="Capture/Compare 3 output Polarity" start="11" size="1" />
+      <BitField name="CC3P" description="Capture/Compare 3 output Polarity" start="9" size="1" />
+      <BitField name="CC3E" description="Capture/Compare 3 output enable" start="8" size="1" />
+      <BitField name="CC2NP" description="Capture/Compare 2 output Polarity" start="7" size="1" />
+      <BitField name="CC2P" description="Capture/Compare 2 output Polarity" start="5" size="1" />
+      <BitField name="CC2E" description="Capture/Compare 2 output enable" start="4" size="1" />
+      <BitField name="CC1NP" description="Capture/Compare 1 output Polarity" start="3" size="1" />
+      <BitField name="CC1P" description="Capture/Compare 1 output Polarity" start="1" size="1" />
+      <BitField name="CC1E" description="Capture/Compare 1 output enable" start="0" size="1" />
+    </Register>
+    <Register name="CNT" description="counter" start="+0x24" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CNT_L" description="low counter value" start="0" size="16" />
+      <BitField name="CNT_H" description="High counter value" start="16" size="16" />
+    </Register>
+    <Register name="PSC" description="prescaler" start="+0x28" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="PSC" description="Prescaler value" start="0" size="16" />
+    </Register>
+    <Register name="ARR" description="auto-reload register" start="+0x2C" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ARR_H" description="High Auto-reload value" start="16" size="16" />
+      <BitField name="ARR_L" description="Low Auto-reload value" start="0" size="16" />
+    </Register>
+    <Register name="CCR1" description="capture/compare register 1" start="+0x34" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCR1_H" description="High Capture/Compare 1 value" start="16" size="16" />
+      <BitField name="CCR1_L" description="Low Capture/Compare 1 value" start="0" size="16" />
+    </Register>
+    <Register name="CCR2" description="capture/compare register 2" start="+0x38" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCR2_H" description="High Capture/Compare 2 value" start="16" size="16" />
+      <BitField name="CCR2_L" description="Low Capture/Compare 2 value" start="0" size="16" />
+    </Register>
+    <Register name="CCR3" description="capture/compare register 3" start="+0x3C" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCR3_H" description="High Capture/Compare value" start="16" size="16" />
+      <BitField name="CCR3_L" description="Low Capture/Compare value" start="0" size="16" />
+    </Register>
+    <Register name="CCR4" description="capture/compare register 4" start="+0x40" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCR4_H" description="High Capture/Compare value" start="16" size="16" />
+      <BitField name="CCR4_L" description="Low Capture/Compare value" start="0" size="16" />
+    </Register>
+    <Register name="DCR" description="DMA control register" start="+0x48" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="DBL" description="DMA burst length" start="8" size="5" />
+      <BitField name="DBA" description="DMA base address" start="0" size="5" />
+    </Register>
+    <Register name="DMAR" description="DMA address for full transfer" start="+0x4C" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAB" description="DMA register for burst accesses" start="0" size="16" />
+    </Register>
+    <Register name="AF1" description="TIM alternate function option register 1" start="+0x60" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="ETRSEL" description="ETR source selection" start="14" size="4" />
+    </Register>
+    <Register name="TISEL" description="TIM timer input selection register" start="+0x68" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="TI1SEL" description="TI1[0] to TI1[15] input selection" start="0" size="4" />
+      <BitField name="TI2SEL" description="TI2[0] to TI2[15] input selection" start="8" size="4" />
+      <BitField name="TI3SEL" description="TI3[0] to TI3[15] input selection" start="16" size="4" />
+      <BitField name="TI4SEL" description="TI4[0] to TI4[15] input selection" start="24" size="4" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="TIM15" description="General purpose timers" start="0x40014000">
+    <Register name="CR1" description="control register 1" start="+0x0" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="CEN" description="Counter enable" start="0" size="1" />
+      <BitField name="UDIS" description="Update disable" start="1" size="1" />
+      <BitField name="URS" description="Update request source" start="2" size="1" />
+      <BitField name="OPM" description="One-pulse mode" start="3" size="1" />
+      <BitField name="ARPE" description="Auto-reload preload enable" start="7" size="1" />
+      <BitField name="CKD" description="Clock division" start="8" size="2" />
+      <BitField name="UIFREMAP" description="UIF status bit remapping" start="11" size="1" />
+    </Register>
+    <Register name="CR2" description="control register 2" start="+0x4" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCPC" description="Capture/compare preloaded control" start="0" size="1" />
+      <BitField name="CCUS" description="Capture/compare control update selection" start="2" size="1" />
+      <BitField name="CCDS" description="Capture/compare DMA selection" start="3" size="1" />
+      <BitField name="MMS" description="Master mode selection" start="4" size="3" />
+      <BitField name="TI1S" description="TI1 selection" start="7" size="1" />
+      <BitField name="OIS1" description="Output Idle state 1" start="8" size="1" />
+      <BitField name="OIS1N" description="Output Idle state 1" start="9" size="1" />
+      <BitField name="OIS2" description="Output Idle state 2" start="10" size="1" />
+    </Register>
+    <Register name="SMCR" description="slave mode control register" start="+0x8" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="SMS" description="Slave mode selection" start="0" size="3" />
+      <BitField name="TS_2_0" description="Trigger selection" start="4" size="3" />
+      <BitField name="MSM" description="Master/Slave mode" start="7" size="1" />
+      <BitField name="SMS_3" description="Slave mode selection bit 3" start="16" size="1" />
+      <BitField name="TS_4_3" description="Trigger selection - bit 4:3" start="20" size="2" />
+    </Register>
+    <Register name="DIER" description="DMA/Interrupt enable register" start="+0xC" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="UIE" description="Update interrupt enable" start="0" size="1" />
+      <BitField name="CC1IE" description="Capture/Compare 1 interrupt enable" start="1" size="1" />
+      <BitField name="CC2IE" description="Capture/Compare 2 interrupt enable" start="2" size="1" />
+      <BitField name="COMIE" description="COM interrupt enable" start="5" size="1" />
+      <BitField name="TIE" description="Trigger interrupt enable" start="6" size="1" />
+      <BitField name="BIE" description="Break interrupt enable" start="7" size="1" />
+      <BitField name="UDE" description="Update DMA request enable" start="8" size="1" />
+      <BitField name="CC1DE" description="Capture/Compare 1 DMA request enable" start="9" size="1" />
+      <BitField name="CC2DE" description="Capture/Compare 2 DMA request enable" start="10" size="1" />
+      <BitField name="COMDE" description="COM DMA request enable" start="13" size="1" />
+      <BitField name="TDE" description="Trigger DMA request enable" start="14" size="1" />
+    </Register>
+    <Register name="SR" description="status register" start="+0x10" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="CC2OF" description="Capture/compare 2 overcapture flag" start="10" size="1" />
+      <BitField name="CC1OF" description="Capture/Compare 1 overcapture flag" start="9" size="1" />
+      <BitField name="BIF" description="Break interrupt flag" start="7" size="1" />
+      <BitField name="TIF" description="Trigger interrupt flag" start="6" size="1" />
+      <BitField name="COMIF" description="COM interrupt flag" start="5" size="1" />
+      <BitField name="CC2IF" description="Capture/Compare 2 interrupt flag" start="2" size="1" />
+      <BitField name="CC1IF" description="Capture/compare 1 interrupt flag" start="1" size="1" />
+      <BitField name="UIF" description="Update interrupt flag" start="0" size="1" />
+    </Register>
+    <Register name="EGR" description="event generation register" start="+0x14" size="4" access="WriteOnly" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="BG" description="Break generation" start="7" size="1" />
+      <BitField name="TG" description="Trigger generation" start="6" size="1" />
+      <BitField name="COMG" description="Capture/Compare control update generation" start="5" size="1" />
+      <BitField name="CC2G" description="Capture/compare 2 generation" start="2" size="1" />
+      <BitField name="CC1G" description="Capture/compare 1 generation" start="1" size="1" />
+      <BitField name="UG" description="Update generation" start="0" size="1" />
+    </Register>
+    <Register name="CCMR1_Output" description="capture/compare mode register (output mode)" start="+0x18" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CC1S" description="Capture/Compare 1 selection" start="0" size="2" />
+      <BitField name="OC1FE" description="Output Compare 1 fast enable" start="2" size="1" />
+      <BitField name="OC1PE" description="Output Compare 1 preload enable" start="3" size="1" />
+      <BitField name="OC1M" description="Output Compare 1 mode" start="4" size="3" />
+      <BitField name="CC2S" description="Capture/Compare 2 selection" start="8" size="2" />
+      <BitField name="OC2FE" description="Output Compare 2 fast enable" start="10" size="1" />
+      <BitField name="OC2PE" description="Output Compare 2 preload enable" start="11" size="1" />
+      <BitField name="OC2M" description="Output Compare 2 mode" start="12" size="3" />
+      <BitField name="OC1M_3" description="Output Compare 1 mode bit 3" start="16" size="1" />
+      <BitField name="OC2M_3" description="Output Compare 2 mode bit 3" start="24" size="1" />
+    </Register>
+    <Register name="CCMR1_Input" description="capture/compare mode register 1 (input mode)" start="+0x18" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IC2F" description="Input capture 2 filter" start="12" size="4" />
+      <BitField name="IC2PSC" description="Input capture 2 prescaler" start="10" size="2" />
+      <BitField name="CC2S" description="Capture/Compare 2 selection" start="8" size="2" />
+      <BitField name="IC1F" description="Input capture 1 filter" start="4" size="4" />
+      <BitField name="IC1PSC" description="Input capture 1 prescaler" start="2" size="2" />
+      <BitField name="CC1S" description="Capture/Compare 1 selection" start="0" size="2" />
+    </Register>
+    <Register name="CCER" description="capture/compare enable register" start="+0x20" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="CC2NP" description="Capture/Compare 2 output Polarity" start="7" size="1" />
+      <BitField name="CC2P" description="Capture/Compare 2 output Polarity" start="5" size="1" />
+      <BitField name="CC2E" description="Capture/Compare 2 output enable" start="4" size="1" />
+      <BitField name="CC1NP" description="Capture/Compare 1 output Polarity" start="3" size="1" />
+      <BitField name="CC1NE" description="Capture/Compare 1 complementary output enable" start="2" size="1" />
+      <BitField name="CC1P" description="Capture/Compare 1 output Polarity" start="1" size="1" />
+      <BitField name="CC1E" description="Capture/Compare 1 output enable" start="0" size="1" />
+    </Register>
+    <Register name="CNT" description="counter" start="+0x24" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CNT" description="counter value" start="0" size="16" access="Read/Write" />
+      <BitField name="UIFCPY" description="UIF copy" start="31" size="1" access="ReadOnly" />
+    </Register>
+    <Register name="PSC" description="prescaler" start="+0x28" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="PSC" description="Prescaler value" start="0" size="16" />
+    </Register>
+    <Register name="ARR" description="auto-reload register" start="+0x2C" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ARR" description="Auto-reload value" start="0" size="16" />
+    </Register>
+    <Register name="RCR" description="repetition counter register" start="+0x30" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="REP" description="Repetition counter value" start="0" size="8" />
+    </Register>
+    <Register name="CCR1" description="capture/compare register 1" start="+0x34" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCR1" description="Capture/Compare 1 value" start="0" size="16" />
+    </Register>
+    <Register name="CCR2" description="capture/compare register 2" start="+0x38" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCR2" description="Capture/Compare 2 value" start="0" size="16" />
+    </Register>
+    <Register name="BDTR" description="break and dead-time register" start="+0x44" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="MOE" description="Main output enable" start="15" size="1" />
+      <BitField name="AOE" description="Automatic output enable" start="14" size="1" />
+      <BitField name="BKP" description="Break polarity" start="13" size="1" />
+      <BitField name="BKE" description="Break enable" start="12" size="1" />
+      <BitField name="OSSR" description="Off-state selection for Run mode" start="11" size="1" />
+      <BitField name="OSSI" description="Off-state selection for Idle mode" start="10" size="1" />
+      <BitField name="LOCK" description="Lock configuration" start="8" size="2" />
+      <BitField name="DTG" description="Dead-time generator setup" start="0" size="8" />
+      <BitField name="BKF" description="Break filter" start="16" size="4" />
+    </Register>
+    <Register name="DCR" description="DMA control register" start="+0x48" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="DBL" description="DMA burst length" start="8" size="5" />
+      <BitField name="DBA" description="DMA base address" start="0" size="5" />
+    </Register>
+    <Register name="DMAR" description="DMA address for full transfer" start="+0x4C" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAB" description="DMA register for burst accesses" start="0" size="16" />
+    </Register>
+    <Register name="AF1" description="TIM15 alternate fdfsdm1_breakon register 1" start="+0x60" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="BKINE" description="BRK BKIN input enable" start="0" size="1" />
+      <BitField name="BKCMP1E" description="BRK COMP1 enable" start="1" size="1" />
+      <BitField name="BKCMP2E" description="BRK COMP2 enable" start="2" size="1" />
+      <BitField name="BKDF1BK0E" description="BRK dfsdm1_break[0] enable" start="8" size="1" />
+      <BitField name="BKINP" description="BRK BKIN input polarity" start="9" size="1" />
+      <BitField name="BKCMP1P" description="BRK COMP1 input polarity" start="10" size="1" />
+      <BitField name="BKCMP2P" description="BRK COMP2 input polarity" start="11" size="1" />
+    </Register>
+    <Register name="TISEL" description="TIM15 input selection register" start="+0x68" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="TI1SEL" description="selects TI1[0] to TI1[15] input" start="0" size="4" />
+      <BitField name="TI2SEL" description="selects TI2[0] to TI2[15] input" start="8" size="4" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="TIM16" description="General-purpose-timers" start="0x40014400">
+    <Register name="CR1" description="control register 1" start="+0x0" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="CEN" description="Counter enable" start="0" size="1" />
+      <BitField name="UDIS" description="Update disable" start="1" size="1" />
+      <BitField name="URS" description="Update request source" start="2" size="1" />
+      <BitField name="OPM" description="One-pulse mode" start="3" size="1" />
+      <BitField name="ARPE" description="Auto-reload preload enable" start="7" size="1" />
+      <BitField name="CKD" description="Clock division" start="8" size="2" />
+      <BitField name="UIFREMAP" description="UIF status bit remapping" start="11" size="1" />
+    </Register>
+    <Register name="CR2" description="control register 2" start="+0x4" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="OIS1N" description="Output Idle state 1" start="9" size="1" />
+      <BitField name="OIS1" description="Output Idle state 1" start="8" size="1" />
+      <BitField name="CCDS" description="Capture/compare DMA selection" start="3" size="1" />
+      <BitField name="CCUS" description="Capture/compare control update selection" start="2" size="1" />
+      <BitField name="CCPC" description="Capture/compare preloaded control" start="0" size="1" />
+    </Register>
+    <Register name="DIER" description="DMA/Interrupt enable register" start="+0xC" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="UIE" description="Update interrupt enable" start="0" size="1" />
+      <BitField name="CC1IE" description="Capture/Compare 1 interrupt enable" start="1" size="1" />
+      <BitField name="COMIE" description="COM interrupt enable" start="5" size="1" />
+      <BitField name="BIE" description="Break interrupt enable" start="7" size="1" />
+      <BitField name="UDE" description="Update DMA request enable" start="8" size="1" />
+      <BitField name="CC1DE" description="Capture/Compare 1 DMA request enable" start="9" size="1" />
+      <BitField name="COMDE" description="COM DMA request enable" start="13" size="1" />
+    </Register>
+    <Register name="SR" description="status register" start="+0x10" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="CC1OF" description="Capture/Compare 1 overcapture flag" start="9" size="1" />
+      <BitField name="BIF" description="Break interrupt flag" start="7" size="1" />
+      <BitField name="COMIF" description="COM interrupt flag" start="5" size="1" />
+      <BitField name="CC1IF" description="Capture/compare 1 interrupt flag" start="1" size="1" />
+      <BitField name="UIF" description="Update interrupt flag" start="0" size="1" />
+    </Register>
+    <Register name="EGR" description="event generation register" start="+0x14" size="4" access="WriteOnly" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="BG" description="Break generation" start="7" size="1" />
+      <BitField name="COMG" description="Capture/Compare control update generation" start="5" size="1" />
+      <BitField name="CC1G" description="Capture/compare 1 generation" start="1" size="1" />
+      <BitField name="UG" description="Update generation" start="0" size="1" />
+    </Register>
+    <Register name="CCMR1_Output" description="capture/compare mode register (output mode)" start="+0x18" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CC1S" description="Capture/Compare 1 selection" start="0" size="2" />
+      <BitField name="OC1FE" description="Output Compare 1 fast enable" start="2" size="1" />
+      <BitField name="OC1PE" description="Output Compare 1 preload enable" start="3" size="1" />
+      <BitField name="OC1M" description="Output Compare 1 mode" start="4" size="3" />
+      <BitField name="OC1M_3" description="Output Compare 1 mode" start="16" size="1" />
+    </Register>
+    <Register name="CCMR1_Input" description="capture/compare mode register 1 (input mode)" start="+0x18" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IC1F" description="Input capture 1 filter" start="4" size="4" />
+      <BitField name="IC1PSC" description="Input capture 1 prescaler" start="2" size="2" />
+      <BitField name="CC1S" description="Capture/Compare 1 selection" start="0" size="2" />
+    </Register>
+    <Register name="CCER" description="capture/compare enable register" start="+0x20" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="CC1NP" description="Capture/Compare 1 output Polarity" start="3" size="1" />
+      <BitField name="CC1NE" description="Capture/Compare 1 complementary output enable" start="2" size="1" />
+      <BitField name="CC1P" description="Capture/Compare 1 output Polarity" start="1" size="1" />
+      <BitField name="CC1E" description="Capture/Compare 1 output enable" start="0" size="1" />
+    </Register>
+    <Register name="CNT" description="counter" start="+0x24" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CNT" description="counter value" start="0" size="16" access="Read/Write" />
+      <BitField name="UIFCPY" description="UIF Copy" start="31" size="1" access="ReadOnly" />
+    </Register>
+    <Register name="PSC" description="prescaler" start="+0x28" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="PSC" description="Prescaler value" start="0" size="16" />
+    </Register>
+    <Register name="ARR" description="auto-reload register" start="+0x2C" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ARR" description="Auto-reload value" start="0" size="16" />
+    </Register>
+    <Register name="RCR" description="repetition counter register" start="+0x30" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="REP" description="Repetition counter value" start="0" size="8" />
+    </Register>
+    <Register name="CCR1" description="capture/compare register 1" start="+0x34" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCR1" description="Capture/Compare 1 value" start="0" size="16" />
+    </Register>
+    <Register name="BDTR" description="break and dead-time register" start="+0x44" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="DTG" description="Dead-time generator setup" start="0" size="8" />
+      <BitField name="LOCK" description="Lock configuration" start="8" size="2" />
+      <BitField name="OSSI" description="Off-state selection for Idle mode" start="10" size="1" />
+      <BitField name="OSSR" description="Off-state selection for Run mode" start="11" size="1" />
+      <BitField name="BKE" description="Break enable" start="12" size="1" />
+      <BitField name="BKP" description="Break polarity" start="13" size="1" />
+      <BitField name="AOE" description="Automatic output enable" start="14" size="1" />
+      <BitField name="MOE" description="Main output enable" start="15" size="1" />
+      <BitField name="BKF" description="Break filter" start="16" size="4" />
+    </Register>
+    <Register name="DCR" description="DMA control register" start="+0x48" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="DBL" description="DMA burst length" start="8" size="5" />
+      <BitField name="DBA" description="DMA base address" start="0" size="5" />
+    </Register>
+    <Register name="DMAR" description="DMA address for full transfer" start="+0x4C" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAB" description="DMA register for burst accesses" start="0" size="16" />
+    </Register>
+    <Register name="TIM16_AF1" description="TIM16 alternate function register 1" start="+0x60" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="BKINE" description="BRK BKIN input enable" start="0" size="1" />
+      <BitField name="BKCMP1E" description="BRK COMP1 enable" start="1" size="1" />
+      <BitField name="BKCMP2E" description="BRK COMP2 enable" start="2" size="1" />
+      <BitField name="BKDFBK1E" description="BRK dfsdm1_break[1] enable" start="8" size="1" />
+      <BitField name="BKINP" description="BRK BKIN input polarity" start="9" size="1" />
+      <BitField name="BKCMP1P" description="BRK COMP1 input polarity" start="10" size="1" />
+      <BitField name="BKCMP2P" description="BRK COMP2 input polarity" start="11" size="1" />
+    </Register>
+    <Register name="TIM16_TISEL" description="TIM16 input selection register" start="+0x68" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="TI1SEL" description="selects TI1[0] to TI1[15] input" start="0" size="4" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="TIM17" description="General-purpose-timers" start="0x40014800">
+    <Register name="CR1" description="control register 1" start="+0x0" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="CEN" description="Counter enable" start="0" size="1" />
+      <BitField name="UDIS" description="Update disable" start="1" size="1" />
+      <BitField name="URS" description="Update request source" start="2" size="1" />
+      <BitField name="OPM" description="One-pulse mode" start="3" size="1" />
+      <BitField name="ARPE" description="Auto-reload preload enable" start="7" size="1" />
+      <BitField name="CKD" description="Clock division" start="8" size="2" />
+      <BitField name="UIFREMAP" description="UIF status bit remapping" start="11" size="1" />
+    </Register>
+    <Register name="CR2" description="control register 2" start="+0x4" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="OIS1N" description="Output Idle state 1" start="9" size="1" />
+      <BitField name="OIS1" description="Output Idle state 1" start="8" size="1" />
+      <BitField name="CCDS" description="Capture/compare DMA selection" start="3" size="1" />
+      <BitField name="CCUS" description="Capture/compare control update selection" start="2" size="1" />
+      <BitField name="CCPC" description="Capture/compare preloaded control" start="0" size="1" />
+    </Register>
+    <Register name="DIER" description="DMA/Interrupt enable register" start="+0xC" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="UIE" description="Update interrupt enable" start="0" size="1" />
+      <BitField name="CC1IE" description="Capture/Compare 1 interrupt enable" start="1" size="1" />
+      <BitField name="COMIE" description="COM interrupt enable" start="5" size="1" />
+      <BitField name="BIE" description="Break interrupt enable" start="7" size="1" />
+      <BitField name="UDE" description="Update DMA request enable" start="8" size="1" />
+      <BitField name="CC1DE" description="Capture/Compare 1 DMA request enable" start="9" size="1" />
+      <BitField name="COMDE" description="COM DMA request enable" start="13" size="1" />
+    </Register>
+    <Register name="SR" description="status register" start="+0x10" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="CC1OF" description="Capture/Compare 1 overcapture flag" start="9" size="1" />
+      <BitField name="BIF" description="Break interrupt flag" start="7" size="1" />
+      <BitField name="COMIF" description="COM interrupt flag" start="5" size="1" />
+      <BitField name="CC1IF" description="Capture/compare 1 interrupt flag" start="1" size="1" />
+      <BitField name="UIF" description="Update interrupt flag" start="0" size="1" />
+    </Register>
+    <Register name="EGR" description="event generation register" start="+0x14" size="4" access="WriteOnly" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="BG" description="Break generation" start="7" size="1" />
+      <BitField name="COMG" description="Capture/Compare control update generation" start="5" size="1" />
+      <BitField name="CC1G" description="Capture/compare 1 generation" start="1" size="1" />
+      <BitField name="UG" description="Update generation" start="0" size="1" />
+    </Register>
+    <Register name="CCMR1_Output" description="capture/compare mode register (output mode)" start="+0x18" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CC1S" description="Capture/Compare 1 selection" start="0" size="2" />
+      <BitField name="OC1FE" description="Output Compare 1 fast enable" start="2" size="1" />
+      <BitField name="OC1PE" description="Output Compare 1 preload enable" start="3" size="1" />
+      <BitField name="OC1M" description="Output Compare 1 mode" start="4" size="3" />
+      <BitField name="OC1M_3" description="Output Compare 1 mode" start="16" size="1" />
+    </Register>
+    <Register name="CCMR1_Input" description="capture/compare mode register 1 (input mode)" start="+0x18" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IC1F" description="Input capture 1 filter" start="4" size="4" />
+      <BitField name="IC1PSC" description="Input capture 1 prescaler" start="2" size="2" />
+      <BitField name="CC1S" description="Capture/Compare 1 selection" start="0" size="2" />
+    </Register>
+    <Register name="CCER" description="capture/compare enable register" start="+0x20" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="CC1NP" description="Capture/Compare 1 output Polarity" start="3" size="1" />
+      <BitField name="CC1NE" description="Capture/Compare 1 complementary output enable" start="2" size="1" />
+      <BitField name="CC1P" description="Capture/Compare 1 output Polarity" start="1" size="1" />
+      <BitField name="CC1E" description="Capture/Compare 1 output enable" start="0" size="1" />
+    </Register>
+    <Register name="CNT" description="counter" start="+0x24" size="4" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CNT" description="counter value" start="0" size="16" access="Read/Write" />
+      <BitField name="UIFCPY" description="UIF Copy" start="31" size="1" access="ReadOnly" />
+    </Register>
+    <Register name="PSC" description="prescaler" start="+0x28" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="PSC" description="Prescaler value" start="0" size="16" />
+    </Register>
+    <Register name="ARR" description="auto-reload register" start="+0x2C" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ARR" description="Auto-reload value" start="0" size="16" />
+    </Register>
+    <Register name="RCR" description="repetition counter register" start="+0x30" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="REP" description="Repetition counter value" start="0" size="8" />
+    </Register>
+    <Register name="CCR1" description="capture/compare register 1" start="+0x34" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCR1" description="Capture/Compare 1 value" start="0" size="16" />
+    </Register>
+    <Register name="BDTR" description="break and dead-time register" start="+0x44" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="DTG" description="Dead-time generator setup" start="0" size="8" />
+      <BitField name="LOCK" description="Lock configuration" start="8" size="2" />
+      <BitField name="OSSI" description="Off-state selection for Idle mode" start="10" size="1" />
+      <BitField name="OSSR" description="Off-state selection for Run mode" start="11" size="1" />
+      <BitField name="BKE" description="Break enable" start="12" size="1" />
+      <BitField name="BKP" description="Break polarity" start="13" size="1" />
+      <BitField name="AOE" description="Automatic output enable" start="14" size="1" />
+      <BitField name="MOE" description="Main output enable" start="15" size="1" />
+      <BitField name="BKF" description="Break filter" start="16" size="4" />
+    </Register>
+    <Register name="DCR" description="DMA control register" start="+0x48" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="DBL" description="DMA burst length" start="8" size="5" />
+      <BitField name="DBA" description="DMA base address" start="0" size="5" />
+    </Register>
+    <Register name="DMAR" description="DMA address for full transfer" start="+0x4C" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAB" description="DMA register for burst accesses" start="0" size="16" />
+    </Register>
+    <Register name="TIM17_AF1" description="TIM17 alternate function register 1" start="+0x60" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="BKINE" description="BRK BKIN input enable" start="0" size="1" />
+      <BitField name="BKCMP1E" description="BRK COMP1 enable" start="1" size="1" />
+      <BitField name="BKCMP2E" description="BRK COMP2 enable" start="2" size="1" />
+      <BitField name="BKDFBK1E" description="BRK dfsdm1_break[1] enable" start="8" size="1" />
+      <BitField name="BKINP" description="BRK BKIN input polarity" start="9" size="1" />
+      <BitField name="BKCMP1P" description="BRK COMP1 input polarity" start="10" size="1" />
+      <BitField name="BKCMP2P" description="BRK COMP2 input polarity" start="11" size="1" />
+    </Register>
+    <Register name="TIM17_TISEL" description="TIM17 input selection register" start="+0x68" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="TI1SEL" description="selects TI1[0] to TI1[15] input" start="0" size="4" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="TIM23" description="General purpose timers" start="0x4000E000">
+    <Register name="CR1" description="control register 1" start="+0x0" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="UIFREMAP" description="UIF status bit remapping" start="11" size="1" />
+      <BitField name="CKD" description="Clock division" start="8" size="2" />
+      <BitField name="ARPE" description="Auto-reload preload enable" start="7" size="1" />
+      <BitField name="CMS" description="Center-aligned mode selection" start="5" size="2" />
+      <BitField name="DIR" description="Direction" start="4" size="1" />
+      <BitField name="OPM" description="One-pulse mode" start="3" size="1" />
+      <BitField name="URS" description="Update request source" start="2" size="1" />
+      <BitField name="UDIS" description="Update disable" start="1" size="1" />
+      <BitField name="CEN" description="Counter enable" start="0" size="1" />
+    </Register>
+    <Register name="CR2" description="control register 2" start="+0x4" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="TI1S" description="TI1 selection" start="7" size="1" />
+      <BitField name="MMS" description="Master mode selection" start="4" size="3" />
+      <BitField name="CCDS" description="Capture/compare DMA selection" start="3" size="1" />
+    </Register>
+    <Register name="SMCR" description="slave mode control register" start="+0x8" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="TS_4_3" description="Trigger selection" start="20" size="2" />
+      <BitField name="SMS_3" description="Slave mode selection - bit 3" start="16" size="1" />
+      <BitField name="ETP" description="External trigger polarity" start="15" size="1" />
+      <BitField name="ECE" description="External clock enable" start="14" size="1" />
+      <BitField name="ETPS" description="External trigger prescaler" start="12" size="2" />
+      <BitField name="ETF" description="External trigger filter" start="8" size="4" />
+      <BitField name="MSM" description="Master/Slave mode" start="7" size="1" />
+      <BitField name="TS" description="Trigger selection" start="4" size="3" />
+      <BitField name="SMS" description="Slave mode selection" start="0" size="3" />
+    </Register>
+    <Register name="DIER" description="DMA/Interrupt enable register" start="+0xC" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="TDE" description="Trigger DMA request enable" start="14" size="1" />
+      <BitField name="CC4DE" description="Capture/Compare 4 DMA request enable" start="12" size="1" />
+      <BitField name="CC3DE" description="Capture/Compare 3 DMA request enable" start="11" size="1" />
+      <BitField name="CC2DE" description="Capture/Compare 2 DMA request enable" start="10" size="1" />
+      <BitField name="CC1DE" description="Capture/Compare 1 DMA request enable" start="9" size="1" />
+      <BitField name="UDE" description="Update DMA request enable" start="8" size="1" />
+      <BitField name="TIE" description="Trigger interrupt enable" start="6" size="1" />
+      <BitField name="CC4IE" description="Capture/Compare 4 interrupt enable" start="4" size="1" />
+      <BitField name="CC3IE" description="Capture/Compare 3 interrupt enable" start="3" size="1" />
+      <BitField name="CC2IE" description="Capture/Compare 2 interrupt enable" start="2" size="1" />
+      <BitField name="CC1IE" description="Capture/Compare 1 interrupt enable" start="1" size="1" />
+      <BitField name="UIE" description="Update interrupt enable" start="0" size="1" />
+    </Register>
+    <Register name="SR" description="status register" start="+0x10" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="CC4OF" description="Capture/Compare 4 overcapture flag" start="12" size="1" />
+      <BitField name="CC3OF" description="Capture/Compare 3 overcapture flag" start="11" size="1" />
+      <BitField name="CC2OF" description="Capture/compare 2 overcapture flag" start="10" size="1" />
+      <BitField name="CC1OF" description="Capture/Compare 1 overcapture flag" start="9" size="1" />
+      <BitField name="TIF" description="Trigger interrupt flag" start="6" size="1" />
+      <BitField name="CC4IF" description="Capture/Compare 4 interrupt flag" start="4" size="1" />
+      <BitField name="CC3IF" description="Capture/Compare 3 interrupt flag" start="3" size="1" />
+      <BitField name="CC2IF" description="Capture/Compare 2 interrupt flag" start="2" size="1" />
+      <BitField name="CC1IF" description="Capture/compare 1 interrupt flag" start="1" size="1" />
+      <BitField name="UIF" description="Update interrupt flag" start="0" size="1" />
+    </Register>
+    <Register name="EGR" description="event generation register" start="+0x14" size="4" access="WriteOnly" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="TG" description="Trigger generation" start="6" size="1" />
+      <BitField name="CC4G" description="Capture/compare 4 generation" start="4" size="1" />
+      <BitField name="CC3G" description="Capture/compare 3 generation" start="3" size="1" />
+      <BitField name="CC2G" description="Capture/compare 2 generation" start="2" size="1" />
+      <BitField name="CC1G" description="Capture/compare 1 generation" start="1" size="1" />
+      <BitField name="UG" description="Update generation" start="0" size="1" />
+    </Register>
+    <Register name="CCMR1_Output" description="capture/compare mode register 1 (output mode)" start="+0x18" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CC1S" description="CC1S" start="0" size="2" />
+      <BitField name="OC1FE" description="OC1FE" start="2" size="1" />
+      <BitField name="OC1PE" description="OC1PE" start="3" size="1" />
+      <BitField name="OC1M" description="OC1M" start="4" size="3" />
+      <BitField name="OC1CE" description="OC1CE" start="7" size="1" />
+      <BitField name="CC2S" description="CC2S" start="8" size="2" />
+      <BitField name="OC2FE" description="OC2FE" start="10" size="1" />
+      <BitField name="OC2PE" description="OC2PE" start="11" size="1" />
+      <BitField name="OC2M" description="OC2M" start="12" size="3" />
+      <BitField name="OC2CE" description="OC2CE" start="15" size="1" />
+      <BitField name="OC1M_3" description="Output Compare 1 mode - bit 3" start="16" size="1" />
+      <BitField name="OC2M_3" description="Output Compare 2 mode - bit 3" start="24" size="1" />
+    </Register>
+    <Register name="CCMR1_Input" description="capture/compare mode register 1 (input mode)" start="+0x18" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IC2F" description="Input capture 2 filter" start="12" size="4" />
+      <BitField name="IC2PCS" description="Input capture 2 prescaler" start="10" size="2" />
+      <BitField name="CC2S" description="Capture/Compare 2 selection" start="8" size="2" />
+      <BitField name="IC1F" description="Input capture 1 filter" start="4" size="4" />
+      <BitField name="ICPCS" description="Input capture 1 prescaler" start="2" size="2" />
+      <BitField name="CC1S" description="Capture/Compare 1 selection" start="0" size="2" />
+    </Register>
+    <Register name="CCMR2_Output" description="capture/compare mode register 2 (output mode)" start="+0x1C" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OC4M_3" description="Output Compare 2 mode - bit 3" start="24" size="1" />
+      <BitField name="OC3M_3" description="Output Compare 1 mode - bit 3" start="16" size="1" />
+      <BitField name="OC4CE" description="OC4CE" start="15" size="1" />
+      <BitField name="OC4M" description="OC4M" start="12" size="3" />
+      <BitField name="OC4PE" description="OC4PE" start="11" size="1" />
+      <BitField name="OC4FE" description="OC4FE" start="10" size="1" />
+      <BitField name="CC4S" description="CC4S" start="8" size="2" />
+      <BitField name="OC3CE" description="OC3CE" start="7" size="1" />
+      <BitField name="OC3M" description="OC3M" start="4" size="3" />
+      <BitField name="OC3PE" description="OC3PE" start="3" size="1" />
+      <BitField name="OC3FE" description="OC3FE" start="2" size="1" />
+      <BitField name="CC3S" description="CC3S" start="0" size="2" />
+    </Register>
+    <Register name="CCMR2_Input" description="capture/compare mode register 2 (input mode)" start="+0x1C" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IC4F" description="Input capture 4 filter" start="12" size="4" />
+      <BitField name="IC4PSC" description="Input capture 4 prescaler" start="10" size="2" />
+      <BitField name="CC4S" description="Capture/Compare 4 selection" start="8" size="2" />
+      <BitField name="IC3F" description="Input capture 3 filter" start="4" size="4" />
+      <BitField name="IC3PSC" description="Input capture 3 prescaler" start="2" size="2" />
+      <BitField name="CC3S" description="Capture/compare 3 selection" start="0" size="2" />
+    </Register>
+    <Register name="CCER" description="capture/compare enable register" start="+0x20" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="CC4NP" description="Capture/Compare 4 output Polarity" start="15" size="1" />
+      <BitField name="CC4P" description="Capture/Compare 3 output Polarity" start="13" size="1" />
+      <BitField name="CC4E" description="Capture/Compare 4 output enable" start="12" size="1" />
+      <BitField name="CC3NP" description="Capture/Compare 3 output Polarity" start="11" size="1" />
+      <BitField name="CC3P" description="Capture/Compare 3 output Polarity" start="9" size="1" />
+      <BitField name="CC3E" description="Capture/Compare 3 output enable" start="8" size="1" />
+      <BitField name="CC2NP" description="Capture/Compare 2 output Polarity" start="7" size="1" />
+      <BitField name="CC2P" description="Capture/Compare 2 output Polarity" start="5" size="1" />
+      <BitField name="CC2E" description="Capture/Compare 2 output enable" start="4" size="1" />
+      <BitField name="CC1NP" description="Capture/Compare 1 output Polarity" start="3" size="1" />
+      <BitField name="CC1P" description="Capture/Compare 1 output Polarity" start="1" size="1" />
+      <BitField name="CC1E" description="Capture/Compare 1 output enable" start="0" size="1" />
+    </Register>
+    <Register name="CNT" description="counter" start="+0x24" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CNT_L" description="low counter value" start="0" size="16" />
+      <BitField name="CNT_H" description="High counter value" start="16" size="16" />
+    </Register>
+    <Register name="PSC" description="prescaler" start="+0x28" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="PSC" description="Prescaler value" start="0" size="16" />
+    </Register>
+    <Register name="ARR" description="auto-reload register" start="+0x2C" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ARR_H" description="High Auto-reload value" start="16" size="16" />
+      <BitField name="ARR_L" description="Low Auto-reload value" start="0" size="16" />
+    </Register>
+    <Register name="CCR1" description="capture/compare register 1" start="+0x34" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCR1_H" description="High Capture/Compare 1 value" start="16" size="16" />
+      <BitField name="CCR1_L" description="Low Capture/Compare 1 value" start="0" size="16" />
+    </Register>
+    <Register name="CCR2" description="capture/compare register 2" start="+0x38" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCR2_H" description="High Capture/Compare 2 value" start="16" size="16" />
+      <BitField name="CCR2_L" description="Low Capture/Compare 2 value" start="0" size="16" />
+    </Register>
+    <Register name="CCR3" description="capture/compare register 3" start="+0x3C" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCR3_H" description="High Capture/Compare value" start="16" size="16" />
+      <BitField name="CCR3_L" description="Low Capture/Compare value" start="0" size="16" />
+    </Register>
+    <Register name="CCR4" description="capture/compare register 4" start="+0x40" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCR4_H" description="High Capture/Compare value" start="16" size="16" />
+      <BitField name="CCR4_L" description="Low Capture/Compare value" start="0" size="16" />
+    </Register>
+    <Register name="DCR" description="DMA control register" start="+0x48" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="DBL" description="DMA burst length" start="8" size="5" />
+      <BitField name="DBA" description="DMA base address" start="0" size="5" />
+    </Register>
+    <Register name="DMAR" description="DMA address for full transfer" start="+0x4C" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAB" description="DMA register for burst accesses" start="0" size="16" />
+    </Register>
+    <Register name="AF1" description="TIM alternate function option register 1" start="+0x60" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="ETRSEL" description="ETR source selection" start="14" size="4" />
+    </Register>
+    <Register name="TISEL" description="TIM timer input selection register" start="+0x68" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="TI1SEL" description="TI1[0] to TI1[15] input selection" start="0" size="4" />
+      <BitField name="TI2SEL" description="TI2[0] to TI2[15] input selection" start="8" size="4" />
+      <BitField name="TI3SEL" description="TI3[0] to TI3[15] input selection" start="16" size="4" />
+      <BitField name="TI4SEL" description="TI4[0] to TI4[15] input selection" start="24" size="4" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="TIM24" description="General purpose timers" start="0x4000E400">
+    <Register name="CR1" description="control register 1" start="+0x0" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="UIFREMAP" description="UIF status bit remapping" start="11" size="1" />
+      <BitField name="CKD" description="Clock division" start="8" size="2" />
+      <BitField name="ARPE" description="Auto-reload preload enable" start="7" size="1" />
+      <BitField name="CMS" description="Center-aligned mode selection" start="5" size="2" />
+      <BitField name="DIR" description="Direction" start="4" size="1" />
+      <BitField name="OPM" description="One-pulse mode" start="3" size="1" />
+      <BitField name="URS" description="Update request source" start="2" size="1" />
+      <BitField name="UDIS" description="Update disable" start="1" size="1" />
+      <BitField name="CEN" description="Counter enable" start="0" size="1" />
+    </Register>
+    <Register name="CR2" description="control register 2" start="+0x4" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="TI1S" description="TI1 selection" start="7" size="1" />
+      <BitField name="MMS" description="Master mode selection" start="4" size="3" />
+      <BitField name="CCDS" description="Capture/compare DMA selection" start="3" size="1" />
+    </Register>
+    <Register name="SMCR" description="slave mode control register" start="+0x8" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="TS_4_3" description="Trigger selection" start="20" size="2" />
+      <BitField name="SMS_3" description="Slave mode selection - bit 3" start="16" size="1" />
+      <BitField name="ETP" description="External trigger polarity" start="15" size="1" />
+      <BitField name="ECE" description="External clock enable" start="14" size="1" />
+      <BitField name="ETPS" description="External trigger prescaler" start="12" size="2" />
+      <BitField name="ETF" description="External trigger filter" start="8" size="4" />
+      <BitField name="MSM" description="Master/Slave mode" start="7" size="1" />
+      <BitField name="TS" description="Trigger selection" start="4" size="3" />
+      <BitField name="SMS" description="Slave mode selection" start="0" size="3" />
+    </Register>
+    <Register name="DIER" description="DMA/Interrupt enable register" start="+0xC" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="TDE" description="Trigger DMA request enable" start="14" size="1" />
+      <BitField name="CC4DE" description="Capture/Compare 4 DMA request enable" start="12" size="1" />
+      <BitField name="CC3DE" description="Capture/Compare 3 DMA request enable" start="11" size="1" />
+      <BitField name="CC2DE" description="Capture/Compare 2 DMA request enable" start="10" size="1" />
+      <BitField name="CC1DE" description="Capture/Compare 1 DMA request enable" start="9" size="1" />
+      <BitField name="UDE" description="Update DMA request enable" start="8" size="1" />
+      <BitField name="TIE" description="Trigger interrupt enable" start="6" size="1" />
+      <BitField name="CC4IE" description="Capture/Compare 4 interrupt enable" start="4" size="1" />
+      <BitField name="CC3IE" description="Capture/Compare 3 interrupt enable" start="3" size="1" />
+      <BitField name="CC2IE" description="Capture/Compare 2 interrupt enable" start="2" size="1" />
+      <BitField name="CC1IE" description="Capture/Compare 1 interrupt enable" start="1" size="1" />
+      <BitField name="UIE" description="Update interrupt enable" start="0" size="1" />
+    </Register>
+    <Register name="SR" description="status register" start="+0x10" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="CC4OF" description="Capture/Compare 4 overcapture flag" start="12" size="1" />
+      <BitField name="CC3OF" description="Capture/Compare 3 overcapture flag" start="11" size="1" />
+      <BitField name="CC2OF" description="Capture/compare 2 overcapture flag" start="10" size="1" />
+      <BitField name="CC1OF" description="Capture/Compare 1 overcapture flag" start="9" size="1" />
+      <BitField name="TIF" description="Trigger interrupt flag" start="6" size="1" />
+      <BitField name="CC4IF" description="Capture/Compare 4 interrupt flag" start="4" size="1" />
+      <BitField name="CC3IF" description="Capture/Compare 3 interrupt flag" start="3" size="1" />
+      <BitField name="CC2IF" description="Capture/Compare 2 interrupt flag" start="2" size="1" />
+      <BitField name="CC1IF" description="Capture/compare 1 interrupt flag" start="1" size="1" />
+      <BitField name="UIF" description="Update interrupt flag" start="0" size="1" />
+    </Register>
+    <Register name="EGR" description="event generation register" start="+0x14" size="4" access="WriteOnly" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="TG" description="Trigger generation" start="6" size="1" />
+      <BitField name="CC4G" description="Capture/compare 4 generation" start="4" size="1" />
+      <BitField name="CC3G" description="Capture/compare 3 generation" start="3" size="1" />
+      <BitField name="CC2G" description="Capture/compare 2 generation" start="2" size="1" />
+      <BitField name="CC1G" description="Capture/compare 1 generation" start="1" size="1" />
+      <BitField name="UG" description="Update generation" start="0" size="1" />
+    </Register>
+    <Register name="CCMR1_Output" description="capture/compare mode register 1 (output mode)" start="+0x18" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CC1S" description="CC1S" start="0" size="2" />
+      <BitField name="OC1FE" description="OC1FE" start="2" size="1" />
+      <BitField name="OC1PE" description="OC1PE" start="3" size="1" />
+      <BitField name="OC1M" description="OC1M" start="4" size="3" />
+      <BitField name="OC1CE" description="OC1CE" start="7" size="1" />
+      <BitField name="CC2S" description="CC2S" start="8" size="2" />
+      <BitField name="OC2FE" description="OC2FE" start="10" size="1" />
+      <BitField name="OC2PE" description="OC2PE" start="11" size="1" />
+      <BitField name="OC2M" description="OC2M" start="12" size="3" />
+      <BitField name="OC2CE" description="OC2CE" start="15" size="1" />
+      <BitField name="OC1M_3" description="Output Compare 1 mode - bit 3" start="16" size="1" />
+      <BitField name="OC2M_3" description="Output Compare 2 mode - bit 3" start="24" size="1" />
+    </Register>
+    <Register name="CCMR1_Input" description="capture/compare mode register 1 (input mode)" start="+0x18" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IC2F" description="Input capture 2 filter" start="12" size="4" />
+      <BitField name="IC2PCS" description="Input capture 2 prescaler" start="10" size="2" />
+      <BitField name="CC2S" description="Capture/Compare 2 selection" start="8" size="2" />
+      <BitField name="IC1F" description="Input capture 1 filter" start="4" size="4" />
+      <BitField name="ICPCS" description="Input capture 1 prescaler" start="2" size="2" />
+      <BitField name="CC1S" description="Capture/Compare 1 selection" start="0" size="2" />
+    </Register>
+    <Register name="CCMR2_Output" description="capture/compare mode register 2 (output mode)" start="+0x1C" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="OC4M_3" description="Output Compare 2 mode - bit 3" start="24" size="1" />
+      <BitField name="OC3M_3" description="Output Compare 1 mode - bit 3" start="16" size="1" />
+      <BitField name="OC4CE" description="OC4CE" start="15" size="1" />
+      <BitField name="OC4M" description="OC4M" start="12" size="3" />
+      <BitField name="OC4PE" description="OC4PE" start="11" size="1" />
+      <BitField name="OC4FE" description="OC4FE" start="10" size="1" />
+      <BitField name="CC4S" description="CC4S" start="8" size="2" />
+      <BitField name="OC3CE" description="OC3CE" start="7" size="1" />
+      <BitField name="OC3M" description="OC3M" start="4" size="3" />
+      <BitField name="OC3PE" description="OC3PE" start="3" size="1" />
+      <BitField name="OC3FE" description="OC3FE" start="2" size="1" />
+      <BitField name="CC3S" description="CC3S" start="0" size="2" />
+    </Register>
+    <Register name="CCMR2_Input" description="capture/compare mode register 2 (input mode)" start="+0x1C" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="IC4F" description="Input capture 4 filter" start="12" size="4" />
+      <BitField name="IC4PSC" description="Input capture 4 prescaler" start="10" size="2" />
+      <BitField name="CC4S" description="Capture/Compare 4 selection" start="8" size="2" />
+      <BitField name="IC3F" description="Input capture 3 filter" start="4" size="4" />
+      <BitField name="IC3PSC" description="Input capture 3 prescaler" start="2" size="2" />
+      <BitField name="CC3S" description="Capture/compare 3 selection" start="0" size="2" />
+    </Register>
+    <Register name="CCER" description="capture/compare enable register" start="+0x20" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="CC4NP" description="Capture/Compare 4 output Polarity" start="15" size="1" />
+      <BitField name="CC4P" description="Capture/Compare 3 output Polarity" start="13" size="1" />
+      <BitField name="CC4E" description="Capture/Compare 4 output enable" start="12" size="1" />
+      <BitField name="CC3NP" description="Capture/Compare 3 output Polarity" start="11" size="1" />
+      <BitField name="CC3P" description="Capture/Compare 3 output Polarity" start="9" size="1" />
+      <BitField name="CC3E" description="Capture/Compare 3 output enable" start="8" size="1" />
+      <BitField name="CC2NP" description="Capture/Compare 2 output Polarity" start="7" size="1" />
+      <BitField name="CC2P" description="Capture/Compare 2 output Polarity" start="5" size="1" />
+      <BitField name="CC2E" description="Capture/Compare 2 output enable" start="4" size="1" />
+      <BitField name="CC1NP" description="Capture/Compare 1 output Polarity" start="3" size="1" />
+      <BitField name="CC1P" description="Capture/Compare 1 output Polarity" start="1" size="1" />
+      <BitField name="CC1E" description="Capture/Compare 1 output enable" start="0" size="1" />
+    </Register>
+    <Register name="CNT" description="counter" start="+0x24" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CNT_L" description="low counter value" start="0" size="16" />
+      <BitField name="CNT_H" description="High counter value" start="16" size="16" />
+    </Register>
+    <Register name="PSC" description="prescaler" start="+0x28" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="PSC" description="Prescaler value" start="0" size="16" />
+    </Register>
+    <Register name="ARR" description="auto-reload register" start="+0x2C" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="ARR_H" description="High Auto-reload value" start="16" size="16" />
+      <BitField name="ARR_L" description="Low Auto-reload value" start="0" size="16" />
+    </Register>
+    <Register name="CCR1" description="capture/compare register 1" start="+0x34" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCR1_H" description="High Capture/Compare 1 value" start="16" size="16" />
+      <BitField name="CCR1_L" description="Low Capture/Compare 1 value" start="0" size="16" />
+    </Register>
+    <Register name="CCR2" description="capture/compare register 2" start="+0x38" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCR2_H" description="High Capture/Compare 2 value" start="16" size="16" />
+      <BitField name="CCR2_L" description="Low Capture/Compare 2 value" start="0" size="16" />
+    </Register>
+    <Register name="CCR3" description="capture/compare register 3" start="+0x3C" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCR3_H" description="High Capture/Compare value" start="16" size="16" />
+      <BitField name="CCR3_L" description="Low Capture/Compare value" start="0" size="16" />
+    </Register>
+    <Register name="CCR4" description="capture/compare register 4" start="+0x40" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="CCR4_H" description="High Capture/Compare value" start="16" size="16" />
+      <BitField name="CCR4_L" description="Low Capture/Compare value" start="0" size="16" />
+    </Register>
+    <Register name="DCR" description="DMA control register" start="+0x48" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="DBL" description="DMA burst length" start="8" size="5" />
+      <BitField name="DBA" description="DMA base address" start="0" size="5" />
+    </Register>
+    <Register name="DMAR" description="DMA address for full transfer" start="+0x4C" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="DMAB" description="DMA register for burst accesses" start="0" size="16" />
+    </Register>
+    <Register name="AF1" description="TIM alternate function option register 1" start="+0x60" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="ETRSEL" description="ETR source selection" start="14" size="4" />
+    </Register>
+    <Register name="TISEL" description="TIM timer input selection register" start="+0x68" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="TI1SEL" description="TI1[0] to TI1[15] input selection" start="0" size="4" />
+      <BitField name="TI2SEL" description="TI2[0] to TI2[15] input selection" start="8" size="4" />
+      <BitField name="TI3SEL" description="TI3[0] to TI3[15] input selection" start="16" size="4" />
+      <BitField name="TI4SEL" description="TI4[0] to TI4[15] input selection" start="24" size="4" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="USART1" description="Universal synchronous asynchronous receiver transmitter" start="0x40011000">
+    <Register name="CR1" description="Control register 1" start="+0x0" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="RXFFIE" description="RXFIFO Full interrupt enable" start="31" size="1" />
+      <BitField name="TXFEIE" description="TXFIFO empty interrupt enable" start="30" size="1" />
+      <BitField name="FIFOEN" description="FIFO mode enable" start="29" size="1" />
+      <BitField name="M1" description="Word length" start="28" size="1" />
+      <BitField name="EOBIE" description="End of Block interrupt enable" start="27" size="1" />
+      <BitField name="RTOIE" description="Receiver timeout interrupt enable" start="26" size="1" />
+      <BitField name="DEAT4" description="Driver Enable assertion time" start="25" size="1" />
+      <BitField name="DEAT3" description="DEAT3" start="24" size="1" />
+      <BitField name="DEAT2" description="DEAT2" start="23" size="1" />
+      <BitField name="DEAT1" description="DEAT1" start="22" size="1" />
+      <BitField name="DEAT0" description="DEAT0" start="21" size="1" />
+      <BitField name="DEDT4" description="Driver Enable de-assertion time" start="20" size="1" />
+      <BitField name="DEDT3" description="DEDT3" start="19" size="1" />
+      <BitField name="DEDT2" description="DEDT2" start="18" size="1" />
+      <BitField name="DEDT1" description="DEDT1" start="17" size="1" />
+      <BitField name="DEDT0" description="DEDT0" start="16" size="1" />
+      <BitField name="OVER8" description="Oversampling mode" start="15" size="1" />
+      <BitField name="CMIE" description="Character match interrupt enable" start="14" size="1" />
+      <BitField name="MME" description="Mute mode enable" start="13" size="1" />
+      <BitField name="M0" description="Word length" start="12" size="1" />
+      <BitField name="WAKE" description="Receiver wakeup method" start="11" size="1" />
+      <BitField name="PCE" description="Parity control enable" start="10" size="1" />
+      <BitField name="PS" description="Parity selection" start="9" size="1" />
+      <BitField name="PEIE" description="PE interrupt enable" start="8" size="1" />
+      <BitField name="TXEIE" description="interrupt enable" start="7" size="1" />
+      <BitField name="TCIE" description="Transmission complete interrupt enable" start="6" size="1" />
+      <BitField name="RXNEIE" description="RXNE interrupt enable" start="5" size="1" />
+      <BitField name="IDLEIE" description="IDLE interrupt enable" start="4" size="1" />
+      <BitField name="TE" description="Transmitter enable" start="3" size="1" />
+      <BitField name="RE" description="Receiver enable" start="2" size="1" />
+      <BitField name="UESM" description="USART enable in Stop mode" start="1" size="1" />
+      <BitField name="UE" description="USART enable" start="0" size="1" />
+    </Register>
+    <Register name="CR2" description="Control register 2" start="+0x4" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="ADD4_7" description="Address of the USART node" start="28" size="4" />
+      <BitField name="ADD0_3" description="Address of the USART node" start="24" size="4" />
+      <BitField name="RTOEN" description="Receiver timeout enable" start="23" size="1" />
+      <BitField name="ABRMOD1" description="Auto baud rate mode" start="22" size="1" />
+      <BitField name="ABRMOD0" description="ABRMOD0" start="21" size="1" />
+      <BitField name="ABREN" description="Auto baud rate enable" start="20" size="1" />
+      <BitField name="MSBFIRST" description="Most significant bit first" start="19" size="1" />
+      <BitField name="TAINV" description="Binary data inversion" start="18" size="1" />
+      <BitField name="TXINV" description="TX pin active level inversion" start="17" size="1" />
+      <BitField name="RXINV" description="RX pin active level inversion" start="16" size="1" />
+      <BitField name="SWAP" description="Swap TX/RX pins" start="15" size="1" />
+      <BitField name="LINEN" description="LIN mode enable" start="14" size="1" />
+      <BitField name="STOP" description="STOP bits" start="12" size="2" />
+      <BitField name="CLKEN" description="Clock enable" start="11" size="1" />
+      <BitField name="CPOL" description="Clock polarity" start="10" size="1" />
+      <BitField name="CPHA" description="Clock phase" start="9" size="1" />
+      <BitField name="LBCL" description="Last bit clock pulse" start="8" size="1" />
+      <BitField name="LBDIE" description="LIN break detection interrupt enable" start="6" size="1" />
+      <BitField name="LBDL" description="LIN break detection length" start="5" size="1" />
+      <BitField name="ADDM7" description="7-bit Address Detection/4-bit Address Detection" start="4" size="1" />
+      <BitField name="DIS_NSS" description="When the DSI_NSS bit is set, the NSS pin input is ignored" start="3" size="1" />
+      <BitField name="SLVEN" description="Synchronous Slave mode enable" start="0" size="1" />
+    </Register>
+    <Register name="CR3" description="Control register 3" start="+0x8" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="TXFTCFG" description="TXFIFO threshold configuration" start="29" size="3" />
+      <BitField name="RXFTIE" description="RXFIFO threshold interrupt enable" start="28" size="1" />
+      <BitField name="RXFTCFG" description="Receive FIFO threshold configuration" start="25" size="3" />
+      <BitField name="TCBGTIE" description="Transmission Complete before guard time, interrupt enable" start="24" size="1" />
+      <BitField name="TXFTIE" description="TXFIFO threshold interrupt enable" start="23" size="1" />
+      <BitField name="WUFIE" description="Wakeup from Stop mode interrupt enable" start="22" size="1" />
+      <BitField name="WUS" description="Wakeup from Stop mode interrupt flag selection" start="20" size="2" />
+      <BitField name="SCARCNT" description="Smartcard auto-retry count" start="17" size="3" />
+      <BitField name="DEP" description="Driver enable polarity selection" start="15" size="1" />
+      <BitField name="DEM" description="Driver enable mode" start="14" size="1" />
+      <BitField name="DDRE" description="DMA Disable on Reception Error" start="13" size="1" />
+      <BitField name="OVRDIS" description="Overrun Disable" start="12" size="1" />
+      <BitField name="ONEBIT" description="One sample bit method enable" start="11" size="1" />
+      <BitField name="CTSIE" description="CTS interrupt enable" start="10" size="1" />
+      <BitField name="CTSE" description="CTS enable" start="9" size="1" />
+      <BitField name="RTSE" description="RTS enable" start="8" size="1" />
+      <BitField name="DMAT" description="DMA enable transmitter" start="7" size="1" />
+      <BitField name="DMAR" description="DMA enable receiver" start="6" size="1" />
+      <BitField name="SCEN" description="Smartcard mode enable" start="5" size="1" />
+      <BitField name="NACK" description="Smartcard NACK enable" start="4" size="1" />
+      <BitField name="HDSEL" description="Half-duplex selection" start="3" size="1" />
+      <BitField name="IRLP" description="Ir low-power" start="2" size="1" />
+      <BitField name="IREN" description="Ir mode enable" start="1" size="1" />
+      <BitField name="EIE" description="Error interrupt enable" start="0" size="1" />
+    </Register>
+    <Register name="BRR" description="Baud rate register" start="+0xC" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="BRR_4_15" description="DIV_Mantissa" start="4" size="12" />
+      <BitField name="BRR_0_3" description="DIV_Fraction" start="0" size="4" />
+    </Register>
+    <Register name="GTPR" description="Guard time and prescaler register" start="+0x10" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="GT" description="Guard time value" start="8" size="8" />
+      <BitField name="PSC" description="Prescaler value" start="0" size="8" />
+    </Register>
+    <Register name="RTOR" description="Receiver timeout register" start="+0x14" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="BLEN" description="Block Length" start="24" size="8" />
+      <BitField name="RTO" description="Receiver timeout value" start="0" size="24" />
+    </Register>
+    <Register name="RQR" description="Request register" start="+0x18" size="4" access="WriteOnly" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="TXFRQ" description="Transmit data flush request" start="4" size="1" />
+      <BitField name="RXFRQ" description="Receive data flush request" start="3" size="1" />
+      <BitField name="MMRQ" description="Mute mode request" start="2" size="1" />
+      <BitField name="SBKRQ" description="Send break request" start="1" size="1" />
+      <BitField name="ABRRQ" description="Auto baud rate request" start="0" size="1" />
+    </Register>
+    <Register name="ISR" description="Interrupt &amp; status register" start="+0x1C" size="4" access="ReadOnly" reset_value="0x00C0" reset_mask="0xFFFFFFFF">
+      <BitField name="TXFT" description="TXFIFO threshold flag" start="27" size="1" />
+      <BitField name="RXFT" description="RXFIFO threshold flag" start="26" size="1" />
+      <BitField name="TCBGT" description="Transmission complete before guard time flag" start="25" size="1" />
+      <BitField name="RXFF" description="RXFIFO Full" start="24" size="1" />
+      <BitField name="TXFE" description="TXFIFO Empty" start="23" size="1" />
+      <BitField name="REACK" description="REACK" start="22" size="1" />
+      <BitField name="TEACK" description="TEACK" start="21" size="1" />
+      <BitField name="WUF" description="WUF" start="20" size="1" />
+      <BitField name="RWU" description="RWU" start="19" size="1" />
+      <BitField name="SBKF" description="SBKF" start="18" size="1" />
+      <BitField name="CMF" description="CMF" start="17" size="1" />
+      <BitField name="BUSY" description="BUSY" start="16" size="1" />
+      <BitField name="ABRF" description="ABRF" start="15" size="1" />
+      <BitField name="ABRE" description="ABRE" start="14" size="1" />
+      <BitField name="UDR" description="SPI slave underrun error flag" start="13" size="1" />
+      <BitField name="EOBF" description="EOBF" start="12" size="1" />
+      <BitField name="RTOF" description="RTOF" start="11" size="1" />
+      <BitField name="CTS" description="CTS" start="10" size="1" />
+      <BitField name="CTSIF" description="CTSIF" start="9" size="1" />
+      <BitField name="LBDF" description="LBDF" start="8" size="1" />
+      <BitField name="TXE" description="TXE" start="7" size="1" />
+      <BitField name="TC" description="TC" start="6" size="1" />
+      <BitField name="RXNE" description="RXNE" start="5" size="1" />
+      <BitField name="IDLE" description="IDLE" start="4" size="1" />
+      <BitField name="ORE" description="ORE" start="3" size="1" />
+      <BitField name="NF" description="NF" start="2" size="1" />
+      <BitField name="FE" description="FE" start="1" size="1" />
+      <BitField name="PE" description="PE" start="0" size="1" />
+    </Register>
+    <Register name="ICR" description="Interrupt flag clear register" start="+0x20" size="4" access="WriteOnly" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="WUCF" description="Wakeup from Stop mode clear flag" start="20" size="1" />
+      <BitField name="CMCF" description="Character match clear flag" start="17" size="1" />
+      <BitField name="UDRCF" description="SPI slave underrun clear flag" start="13" size="1" />
+      <BitField name="EOBCF" description="End of block clear flag" start="12" size="1" />
+      <BitField name="RTOCF" description="Receiver timeout clear flag" start="11" size="1" />
+      <BitField name="CTSCF" description="CTS clear flag" start="9" size="1" />
+      <BitField name="LBDCF" description="LIN break detection clear flag" start="8" size="1" />
+      <BitField name="TCBGTC" description="Transmission complete before Guard time clear flag" start="7" size="1" />
+      <BitField name="TCCF" description="Transmission complete clear flag" start="6" size="1" />
+      <BitField name="TXFECF" description="TXFIFO empty clear flag" start="5" size="1" />
+      <BitField name="IDLECF" description="Idle line detected clear flag" start="4" size="1" />
+      <BitField name="ORECF" description="Overrun error clear flag" start="3" size="1" />
+      <BitField name="NCF" description="Noise detected clear flag" start="2" size="1" />
+      <BitField name="FECF" description="Framing error clear flag" start="1" size="1" />
+      <BitField name="PECF" description="Parity error clear flag" start="0" size="1" />
+    </Register>
+    <Register name="RDR" description="Receive data register" start="+0x24" size="4" access="ReadOnly" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="RDR" description="Receive data value" start="0" size="9" />
+    </Register>
+    <Register name="TDR" description="Transmit data register" start="+0x28" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="TDR" description="Transmit data value" start="0" size="9" />
+    </Register>
+    <Register name="PRESC" description="USART prescaler register" start="+0x2C" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="PRESCALER" description="Clock prescaler" start="0" size="4" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="USART2" description="Universal synchronous asynchronous receiver transmitter" start="0x40004400">
+    <Register name="CR1" description="Control register 1" start="+0x0" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="RXFFIE" description="RXFIFO Full interrupt enable" start="31" size="1" />
+      <BitField name="TXFEIE" description="TXFIFO empty interrupt enable" start="30" size="1" />
+      <BitField name="FIFOEN" description="FIFO mode enable" start="29" size="1" />
+      <BitField name="M1" description="Word length" start="28" size="1" />
+      <BitField name="EOBIE" description="End of Block interrupt enable" start="27" size="1" />
+      <BitField name="RTOIE" description="Receiver timeout interrupt enable" start="26" size="1" />
+      <BitField name="DEAT4" description="Driver Enable assertion time" start="25" size="1" />
+      <BitField name="DEAT3" description="DEAT3" start="24" size="1" />
+      <BitField name="DEAT2" description="DEAT2" start="23" size="1" />
+      <BitField name="DEAT1" description="DEAT1" start="22" size="1" />
+      <BitField name="DEAT0" description="DEAT0" start="21" size="1" />
+      <BitField name="DEDT4" description="Driver Enable de-assertion time" start="20" size="1" />
+      <BitField name="DEDT3" description="DEDT3" start="19" size="1" />
+      <BitField name="DEDT2" description="DEDT2" start="18" size="1" />
+      <BitField name="DEDT1" description="DEDT1" start="17" size="1" />
+      <BitField name="DEDT0" description="DEDT0" start="16" size="1" />
+      <BitField name="OVER8" description="Oversampling mode" start="15" size="1" />
+      <BitField name="CMIE" description="Character match interrupt enable" start="14" size="1" />
+      <BitField name="MME" description="Mute mode enable" start="13" size="1" />
+      <BitField name="M0" description="Word length" start="12" size="1" />
+      <BitField name="WAKE" description="Receiver wakeup method" start="11" size="1" />
+      <BitField name="PCE" description="Parity control enable" start="10" size="1" />
+      <BitField name="PS" description="Parity selection" start="9" size="1" />
+      <BitField name="PEIE" description="PE interrupt enable" start="8" size="1" />
+      <BitField name="TXEIE" description="interrupt enable" start="7" size="1" />
+      <BitField name="TCIE" description="Transmission complete interrupt enable" start="6" size="1" />
+      <BitField name="RXNEIE" description="RXNE interrupt enable" start="5" size="1" />
+      <BitField name="IDLEIE" description="IDLE interrupt enable" start="4" size="1" />
+      <BitField name="TE" description="Transmitter enable" start="3" size="1" />
+      <BitField name="RE" description="Receiver enable" start="2" size="1" />
+      <BitField name="UESM" description="USART enable in Stop mode" start="1" size="1" />
+      <BitField name="UE" description="USART enable" start="0" size="1" />
+    </Register>
+    <Register name="CR2" description="Control register 2" start="+0x4" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="ADD4_7" description="Address of the USART node" start="28" size="4" />
+      <BitField name="ADD0_3" description="Address of the USART node" start="24" size="4" />
+      <BitField name="RTOEN" description="Receiver timeout enable" start="23" size="1" />
+      <BitField name="ABRMOD1" description="Auto baud rate mode" start="22" size="1" />
+      <BitField name="ABRMOD0" description="ABRMOD0" start="21" size="1" />
+      <BitField name="ABREN" description="Auto baud rate enable" start="20" size="1" />
+      <BitField name="MSBFIRST" description="Most significant bit first" start="19" size="1" />
+      <BitField name="TAINV" description="Binary data inversion" start="18" size="1" />
+      <BitField name="TXINV" description="TX pin active level inversion" start="17" size="1" />
+      <BitField name="RXINV" description="RX pin active level inversion" start="16" size="1" />
+      <BitField name="SWAP" description="Swap TX/RX pins" start="15" size="1" />
+      <BitField name="LINEN" description="LIN mode enable" start="14" size="1" />
+      <BitField name="STOP" description="STOP bits" start="12" size="2" />
+      <BitField name="CLKEN" description="Clock enable" start="11" size="1" />
+      <BitField name="CPOL" description="Clock polarity" start="10" size="1" />
+      <BitField name="CPHA" description="Clock phase" start="9" size="1" />
+      <BitField name="LBCL" description="Last bit clock pulse" start="8" size="1" />
+      <BitField name="LBDIE" description="LIN break detection interrupt enable" start="6" size="1" />
+      <BitField name="LBDL" description="LIN break detection length" start="5" size="1" />
+      <BitField name="ADDM7" description="7-bit Address Detection/4-bit Address Detection" start="4" size="1" />
+      <BitField name="DIS_NSS" description="When the DSI_NSS bit is set, the NSS pin input is ignored" start="3" size="1" />
+      <BitField name="SLVEN" description="Synchronous Slave mode enable" start="0" size="1" />
+    </Register>
+    <Register name="CR3" description="Control register 3" start="+0x8" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="TXFTCFG" description="TXFIFO threshold configuration" start="29" size="3" />
+      <BitField name="RXFTIE" description="RXFIFO threshold interrupt enable" start="28" size="1" />
+      <BitField name="RXFTCFG" description="Receive FIFO threshold configuration" start="25" size="3" />
+      <BitField name="TCBGTIE" description="Transmission Complete before guard time, interrupt enable" start="24" size="1" />
+      <BitField name="TXFTIE" description="TXFIFO threshold interrupt enable" start="23" size="1" />
+      <BitField name="WUFIE" description="Wakeup from Stop mode interrupt enable" start="22" size="1" />
+      <BitField name="WUS" description="Wakeup from Stop mode interrupt flag selection" start="20" size="2" />
+      <BitField name="SCARCNT" description="Smartcard auto-retry count" start="17" size="3" />
+      <BitField name="DEP" description="Driver enable polarity selection" start="15" size="1" />
+      <BitField name="DEM" description="Driver enable mode" start="14" size="1" />
+      <BitField name="DDRE" description="DMA Disable on Reception Error" start="13" size="1" />
+      <BitField name="OVRDIS" description="Overrun Disable" start="12" size="1" />
+      <BitField name="ONEBIT" description="One sample bit method enable" start="11" size="1" />
+      <BitField name="CTSIE" description="CTS interrupt enable" start="10" size="1" />
+      <BitField name="CTSE" description="CTS enable" start="9" size="1" />
+      <BitField name="RTSE" description="RTS enable" start="8" size="1" />
+      <BitField name="DMAT" description="DMA enable transmitter" start="7" size="1" />
+      <BitField name="DMAR" description="DMA enable receiver" start="6" size="1" />
+      <BitField name="SCEN" description="Smartcard mode enable" start="5" size="1" />
+      <BitField name="NACK" description="Smartcard NACK enable" start="4" size="1" />
+      <BitField name="HDSEL" description="Half-duplex selection" start="3" size="1" />
+      <BitField name="IRLP" description="Ir low-power" start="2" size="1" />
+      <BitField name="IREN" description="Ir mode enable" start="1" size="1" />
+      <BitField name="EIE" description="Error interrupt enable" start="0" size="1" />
+    </Register>
+    <Register name="BRR" description="Baud rate register" start="+0xC" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="BRR_4_15" description="DIV_Mantissa" start="4" size="12" />
+      <BitField name="BRR_0_3" description="DIV_Fraction" start="0" size="4" />
+    </Register>
+    <Register name="GTPR" description="Guard time and prescaler register" start="+0x10" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="GT" description="Guard time value" start="8" size="8" />
+      <BitField name="PSC" description="Prescaler value" start="0" size="8" />
+    </Register>
+    <Register name="RTOR" description="Receiver timeout register" start="+0x14" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="BLEN" description="Block Length" start="24" size="8" />
+      <BitField name="RTO" description="Receiver timeout value" start="0" size="24" />
+    </Register>
+    <Register name="RQR" description="Request register" start="+0x18" size="4" access="WriteOnly" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="TXFRQ" description="Transmit data flush request" start="4" size="1" />
+      <BitField name="RXFRQ" description="Receive data flush request" start="3" size="1" />
+      <BitField name="MMRQ" description="Mute mode request" start="2" size="1" />
+      <BitField name="SBKRQ" description="Send break request" start="1" size="1" />
+      <BitField name="ABRRQ" description="Auto baud rate request" start="0" size="1" />
+    </Register>
+    <Register name="ISR" description="Interrupt &amp; status register" start="+0x1C" size="4" access="ReadOnly" reset_value="0x00C0" reset_mask="0xFFFFFFFF">
+      <BitField name="TXFT" description="TXFIFO threshold flag" start="27" size="1" />
+      <BitField name="RXFT" description="RXFIFO threshold flag" start="26" size="1" />
+      <BitField name="TCBGT" description="Transmission complete before guard time flag" start="25" size="1" />
+      <BitField name="RXFF" description="RXFIFO Full" start="24" size="1" />
+      <BitField name="TXFE" description="TXFIFO Empty" start="23" size="1" />
+      <BitField name="REACK" description="REACK" start="22" size="1" />
+      <BitField name="TEACK" description="TEACK" start="21" size="1" />
+      <BitField name="WUF" description="WUF" start="20" size="1" />
+      <BitField name="RWU" description="RWU" start="19" size="1" />
+      <BitField name="SBKF" description="SBKF" start="18" size="1" />
+      <BitField name="CMF" description="CMF" start="17" size="1" />
+      <BitField name="BUSY" description="BUSY" start="16" size="1" />
+      <BitField name="ABRF" description="ABRF" start="15" size="1" />
+      <BitField name="ABRE" description="ABRE" start="14" size="1" />
+      <BitField name="UDR" description="SPI slave underrun error flag" start="13" size="1" />
+      <BitField name="EOBF" description="EOBF" start="12" size="1" />
+      <BitField name="RTOF" description="RTOF" start="11" size="1" />
+      <BitField name="CTS" description="CTS" start="10" size="1" />
+      <BitField name="CTSIF" description="CTSIF" start="9" size="1" />
+      <BitField name="LBDF" description="LBDF" start="8" size="1" />
+      <BitField name="TXE" description="TXE" start="7" size="1" />
+      <BitField name="TC" description="TC" start="6" size="1" />
+      <BitField name="RXNE" description="RXNE" start="5" size="1" />
+      <BitField name="IDLE" description="IDLE" start="4" size="1" />
+      <BitField name="ORE" description="ORE" start="3" size="1" />
+      <BitField name="NF" description="NF" start="2" size="1" />
+      <BitField name="FE" description="FE" start="1" size="1" />
+      <BitField name="PE" description="PE" start="0" size="1" />
+    </Register>
+    <Register name="ICR" description="Interrupt flag clear register" start="+0x20" size="4" access="WriteOnly" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="WUCF" description="Wakeup from Stop mode clear flag" start="20" size="1" />
+      <BitField name="CMCF" description="Character match clear flag" start="17" size="1" />
+      <BitField name="UDRCF" description="SPI slave underrun clear flag" start="13" size="1" />
+      <BitField name="EOBCF" description="End of block clear flag" start="12" size="1" />
+      <BitField name="RTOCF" description="Receiver timeout clear flag" start="11" size="1" />
+      <BitField name="CTSCF" description="CTS clear flag" start="9" size="1" />
+      <BitField name="LBDCF" description="LIN break detection clear flag" start="8" size="1" />
+      <BitField name="TCBGTC" description="Transmission complete before Guard time clear flag" start="7" size="1" />
+      <BitField name="TCCF" description="Transmission complete clear flag" start="6" size="1" />
+      <BitField name="TXFECF" description="TXFIFO empty clear flag" start="5" size="1" />
+      <BitField name="IDLECF" description="Idle line detected clear flag" start="4" size="1" />
+      <BitField name="ORECF" description="Overrun error clear flag" start="3" size="1" />
+      <BitField name="NCF" description="Noise detected clear flag" start="2" size="1" />
+      <BitField name="FECF" description="Framing error clear flag" start="1" size="1" />
+      <BitField name="PECF" description="Parity error clear flag" start="0" size="1" />
+    </Register>
+    <Register name="RDR" description="Receive data register" start="+0x24" size="4" access="ReadOnly" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="RDR" description="Receive data value" start="0" size="9" />
+    </Register>
+    <Register name="TDR" description="Transmit data register" start="+0x28" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="TDR" description="Transmit data value" start="0" size="9" />
+    </Register>
+    <Register name="PRESC" description="USART prescaler register" start="+0x2C" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="PRESCALER" description="Clock prescaler" start="0" size="4" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="USART3" description="Universal synchronous asynchronous receiver transmitter" start="0x40004800">
+    <Register name="CR1" description="Control register 1" start="+0x0" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="RXFFIE" description="RXFIFO Full interrupt enable" start="31" size="1" />
+      <BitField name="TXFEIE" description="TXFIFO empty interrupt enable" start="30" size="1" />
+      <BitField name="FIFOEN" description="FIFO mode enable" start="29" size="1" />
+      <BitField name="M1" description="Word length" start="28" size="1" />
+      <BitField name="EOBIE" description="End of Block interrupt enable" start="27" size="1" />
+      <BitField name="RTOIE" description="Receiver timeout interrupt enable" start="26" size="1" />
+      <BitField name="DEAT4" description="Driver Enable assertion time" start="25" size="1" />
+      <BitField name="DEAT3" description="DEAT3" start="24" size="1" />
+      <BitField name="DEAT2" description="DEAT2" start="23" size="1" />
+      <BitField name="DEAT1" description="DEAT1" start="22" size="1" />
+      <BitField name="DEAT0" description="DEAT0" start="21" size="1" />
+      <BitField name="DEDT4" description="Driver Enable de-assertion time" start="20" size="1" />
+      <BitField name="DEDT3" description="DEDT3" start="19" size="1" />
+      <BitField name="DEDT2" description="DEDT2" start="18" size="1" />
+      <BitField name="DEDT1" description="DEDT1" start="17" size="1" />
+      <BitField name="DEDT0" description="DEDT0" start="16" size="1" />
+      <BitField name="OVER8" description="Oversampling mode" start="15" size="1" />
+      <BitField name="CMIE" description="Character match interrupt enable" start="14" size="1" />
+      <BitField name="MME" description="Mute mode enable" start="13" size="1" />
+      <BitField name="M0" description="Word length" start="12" size="1" />
+      <BitField name="WAKE" description="Receiver wakeup method" start="11" size="1" />
+      <BitField name="PCE" description="Parity control enable" start="10" size="1" />
+      <BitField name="PS" description="Parity selection" start="9" size="1" />
+      <BitField name="PEIE" description="PE interrupt enable" start="8" size="1" />
+      <BitField name="TXEIE" description="interrupt enable" start="7" size="1" />
+      <BitField name="TCIE" description="Transmission complete interrupt enable" start="6" size="1" />
+      <BitField name="RXNEIE" description="RXNE interrupt enable" start="5" size="1" />
+      <BitField name="IDLEIE" description="IDLE interrupt enable" start="4" size="1" />
+      <BitField name="TE" description="Transmitter enable" start="3" size="1" />
+      <BitField name="RE" description="Receiver enable" start="2" size="1" />
+      <BitField name="UESM" description="USART enable in Stop mode" start="1" size="1" />
+      <BitField name="UE" description="USART enable" start="0" size="1" />
+    </Register>
+    <Register name="CR2" description="Control register 2" start="+0x4" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="ADD4_7" description="Address of the USART node" start="28" size="4" />
+      <BitField name="ADD0_3" description="Address of the USART node" start="24" size="4" />
+      <BitField name="RTOEN" description="Receiver timeout enable" start="23" size="1" />
+      <BitField name="ABRMOD1" description="Auto baud rate mode" start="22" size="1" />
+      <BitField name="ABRMOD0" description="ABRMOD0" start="21" size="1" />
+      <BitField name="ABREN" description="Auto baud rate enable" start="20" size="1" />
+      <BitField name="MSBFIRST" description="Most significant bit first" start="19" size="1" />
+      <BitField name="TAINV" description="Binary data inversion" start="18" size="1" />
+      <BitField name="TXINV" description="TX pin active level inversion" start="17" size="1" />
+      <BitField name="RXINV" description="RX pin active level inversion" start="16" size="1" />
+      <BitField name="SWAP" description="Swap TX/RX pins" start="15" size="1" />
+      <BitField name="LINEN" description="LIN mode enable" start="14" size="1" />
+      <BitField name="STOP" description="STOP bits" start="12" size="2" />
+      <BitField name="CLKEN" description="Clock enable" start="11" size="1" />
+      <BitField name="CPOL" description="Clock polarity" start="10" size="1" />
+      <BitField name="CPHA" description="Clock phase" start="9" size="1" />
+      <BitField name="LBCL" description="Last bit clock pulse" start="8" size="1" />
+      <BitField name="LBDIE" description="LIN break detection interrupt enable" start="6" size="1" />
+      <BitField name="LBDL" description="LIN break detection length" start="5" size="1" />
+      <BitField name="ADDM7" description="7-bit Address Detection/4-bit Address Detection" start="4" size="1" />
+      <BitField name="DIS_NSS" description="When the DSI_NSS bit is set, the NSS pin input is ignored" start="3" size="1" />
+      <BitField name="SLVEN" description="Synchronous Slave mode enable" start="0" size="1" />
+    </Register>
+    <Register name="CR3" description="Control register 3" start="+0x8" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="TXFTCFG" description="TXFIFO threshold configuration" start="29" size="3" />
+      <BitField name="RXFTIE" description="RXFIFO threshold interrupt enable" start="28" size="1" />
+      <BitField name="RXFTCFG" description="Receive FIFO threshold configuration" start="25" size="3" />
+      <BitField name="TCBGTIE" description="Transmission Complete before guard time, interrupt enable" start="24" size="1" />
+      <BitField name="TXFTIE" description="TXFIFO threshold interrupt enable" start="23" size="1" />
+      <BitField name="WUFIE" description="Wakeup from Stop mode interrupt enable" start="22" size="1" />
+      <BitField name="WUS" description="Wakeup from Stop mode interrupt flag selection" start="20" size="2" />
+      <BitField name="SCARCNT" description="Smartcard auto-retry count" start="17" size="3" />
+      <BitField name="DEP" description="Driver enable polarity selection" start="15" size="1" />
+      <BitField name="DEM" description="Driver enable mode" start="14" size="1" />
+      <BitField name="DDRE" description="DMA Disable on Reception Error" start="13" size="1" />
+      <BitField name="OVRDIS" description="Overrun Disable" start="12" size="1" />
+      <BitField name="ONEBIT" description="One sample bit method enable" start="11" size="1" />
+      <BitField name="CTSIE" description="CTS interrupt enable" start="10" size="1" />
+      <BitField name="CTSE" description="CTS enable" start="9" size="1" />
+      <BitField name="RTSE" description="RTS enable" start="8" size="1" />
+      <BitField name="DMAT" description="DMA enable transmitter" start="7" size="1" />
+      <BitField name="DMAR" description="DMA enable receiver" start="6" size="1" />
+      <BitField name="SCEN" description="Smartcard mode enable" start="5" size="1" />
+      <BitField name="NACK" description="Smartcard NACK enable" start="4" size="1" />
+      <BitField name="HDSEL" description="Half-duplex selection" start="3" size="1" />
+      <BitField name="IRLP" description="Ir low-power" start="2" size="1" />
+      <BitField name="IREN" description="Ir mode enable" start="1" size="1" />
+      <BitField name="EIE" description="Error interrupt enable" start="0" size="1" />
+    </Register>
+    <Register name="BRR" description="Baud rate register" start="+0xC" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="BRR_4_15" description="DIV_Mantissa" start="4" size="12" />
+      <BitField name="BRR_0_3" description="DIV_Fraction" start="0" size="4" />
+    </Register>
+    <Register name="GTPR" description="Guard time and prescaler register" start="+0x10" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="GT" description="Guard time value" start="8" size="8" />
+      <BitField name="PSC" description="Prescaler value" start="0" size="8" />
+    </Register>
+    <Register name="RTOR" description="Receiver timeout register" start="+0x14" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="BLEN" description="Block Length" start="24" size="8" />
+      <BitField name="RTO" description="Receiver timeout value" start="0" size="24" />
+    </Register>
+    <Register name="RQR" description="Request register" start="+0x18" size="4" access="WriteOnly" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="TXFRQ" description="Transmit data flush request" start="4" size="1" />
+      <BitField name="RXFRQ" description="Receive data flush request" start="3" size="1" />
+      <BitField name="MMRQ" description="Mute mode request" start="2" size="1" />
+      <BitField name="SBKRQ" description="Send break request" start="1" size="1" />
+      <BitField name="ABRRQ" description="Auto baud rate request" start="0" size="1" />
+    </Register>
+    <Register name="ISR" description="Interrupt &amp; status register" start="+0x1C" size="4" access="ReadOnly" reset_value="0x00C0" reset_mask="0xFFFFFFFF">
+      <BitField name="TXFT" description="TXFIFO threshold flag" start="27" size="1" />
+      <BitField name="RXFT" description="RXFIFO threshold flag" start="26" size="1" />
+      <BitField name="TCBGT" description="Transmission complete before guard time flag" start="25" size="1" />
+      <BitField name="RXFF" description="RXFIFO Full" start="24" size="1" />
+      <BitField name="TXFE" description="TXFIFO Empty" start="23" size="1" />
+      <BitField name="REACK" description="REACK" start="22" size="1" />
+      <BitField name="TEACK" description="TEACK" start="21" size="1" />
+      <BitField name="WUF" description="WUF" start="20" size="1" />
+      <BitField name="RWU" description="RWU" start="19" size="1" />
+      <BitField name="SBKF" description="SBKF" start="18" size="1" />
+      <BitField name="CMF" description="CMF" start="17" size="1" />
+      <BitField name="BUSY" description="BUSY" start="16" size="1" />
+      <BitField name="ABRF" description="ABRF" start="15" size="1" />
+      <BitField name="ABRE" description="ABRE" start="14" size="1" />
+      <BitField name="UDR" description="SPI slave underrun error flag" start="13" size="1" />
+      <BitField name="EOBF" description="EOBF" start="12" size="1" />
+      <BitField name="RTOF" description="RTOF" start="11" size="1" />
+      <BitField name="CTS" description="CTS" start="10" size="1" />
+      <BitField name="CTSIF" description="CTSIF" start="9" size="1" />
+      <BitField name="LBDF" description="LBDF" start="8" size="1" />
+      <BitField name="TXE" description="TXE" start="7" size="1" />
+      <BitField name="TC" description="TC" start="6" size="1" />
+      <BitField name="RXNE" description="RXNE" start="5" size="1" />
+      <BitField name="IDLE" description="IDLE" start="4" size="1" />
+      <BitField name="ORE" description="ORE" start="3" size="1" />
+      <BitField name="NF" description="NF" start="2" size="1" />
+      <BitField name="FE" description="FE" start="1" size="1" />
+      <BitField name="PE" description="PE" start="0" size="1" />
+    </Register>
+    <Register name="ICR" description="Interrupt flag clear register" start="+0x20" size="4" access="WriteOnly" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="WUCF" description="Wakeup from Stop mode clear flag" start="20" size="1" />
+      <BitField name="CMCF" description="Character match clear flag" start="17" size="1" />
+      <BitField name="UDRCF" description="SPI slave underrun clear flag" start="13" size="1" />
+      <BitField name="EOBCF" description="End of block clear flag" start="12" size="1" />
+      <BitField name="RTOCF" description="Receiver timeout clear flag" start="11" size="1" />
+      <BitField name="CTSCF" description="CTS clear flag" start="9" size="1" />
+      <BitField name="LBDCF" description="LIN break detection clear flag" start="8" size="1" />
+      <BitField name="TCBGTC" description="Transmission complete before Guard time clear flag" start="7" size="1" />
+      <BitField name="TCCF" description="Transmission complete clear flag" start="6" size="1" />
+      <BitField name="TXFECF" description="TXFIFO empty clear flag" start="5" size="1" />
+      <BitField name="IDLECF" description="Idle line detected clear flag" start="4" size="1" />
+      <BitField name="ORECF" description="Overrun error clear flag" start="3" size="1" />
+      <BitField name="NCF" description="Noise detected clear flag" start="2" size="1" />
+      <BitField name="FECF" description="Framing error clear flag" start="1" size="1" />
+      <BitField name="PECF" description="Parity error clear flag" start="0" size="1" />
+    </Register>
+    <Register name="RDR" description="Receive data register" start="+0x24" size="4" access="ReadOnly" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="RDR" description="Receive data value" start="0" size="9" />
+    </Register>
+    <Register name="TDR" description="Transmit data register" start="+0x28" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="TDR" description="Transmit data value" start="0" size="9" />
+    </Register>
+    <Register name="PRESC" description="USART prescaler register" start="+0x2C" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="PRESCALER" description="Clock prescaler" start="0" size="4" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="UART4" description="Universal synchronous asynchronous receiver transmitter" start="0x40004C00">
+    <Register name="CR1" description="Control register 1" start="+0x0" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="RXFFIE" description="RXFIFO Full interrupt enable" start="31" size="1" />
+      <BitField name="TXFEIE" description="TXFIFO empty interrupt enable" start="30" size="1" />
+      <BitField name="FIFOEN" description="FIFO mode enable" start="29" size="1" />
+      <BitField name="M1" description="Word length" start="28" size="1" />
+      <BitField name="EOBIE" description="End of Block interrupt enable" start="27" size="1" />
+      <BitField name="RTOIE" description="Receiver timeout interrupt enable" start="26" size="1" />
+      <BitField name="DEAT4" description="Driver Enable assertion time" start="25" size="1" />
+      <BitField name="DEAT3" description="DEAT3" start="24" size="1" />
+      <BitField name="DEAT2" description="DEAT2" start="23" size="1" />
+      <BitField name="DEAT1" description="DEAT1" start="22" size="1" />
+      <BitField name="DEAT0" description="DEAT0" start="21" size="1" />
+      <BitField name="DEDT4" description="Driver Enable de-assertion time" start="20" size="1" />
+      <BitField name="DEDT3" description="DEDT3" start="19" size="1" />
+      <BitField name="DEDT2" description="DEDT2" start="18" size="1" />
+      <BitField name="DEDT1" description="DEDT1" start="17" size="1" />
+      <BitField name="DEDT0" description="DEDT0" start="16" size="1" />
+      <BitField name="OVER8" description="Oversampling mode" start="15" size="1" />
+      <BitField name="CMIE" description="Character match interrupt enable" start="14" size="1" />
+      <BitField name="MME" description="Mute mode enable" start="13" size="1" />
+      <BitField name="M0" description="Word length" start="12" size="1" />
+      <BitField name="WAKE" description="Receiver wakeup method" start="11" size="1" />
+      <BitField name="PCE" description="Parity control enable" start="10" size="1" />
+      <BitField name="PS" description="Parity selection" start="9" size="1" />
+      <BitField name="PEIE" description="PE interrupt enable" start="8" size="1" />
+      <BitField name="TXEIE" description="interrupt enable" start="7" size="1" />
+      <BitField name="TCIE" description="Transmission complete interrupt enable" start="6" size="1" />
+      <BitField name="RXNEIE" description="RXNE interrupt enable" start="5" size="1" />
+      <BitField name="IDLEIE" description="IDLE interrupt enable" start="4" size="1" />
+      <BitField name="TE" description="Transmitter enable" start="3" size="1" />
+      <BitField name="RE" description="Receiver enable" start="2" size="1" />
+      <BitField name="UESM" description="USART enable in Stop mode" start="1" size="1" />
+      <BitField name="UE" description="USART enable" start="0" size="1" />
+    </Register>
+    <Register name="CR2" description="Control register 2" start="+0x4" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="ADD4_7" description="Address of the USART node" start="28" size="4" />
+      <BitField name="ADD0_3" description="Address of the USART node" start="24" size="4" />
+      <BitField name="RTOEN" description="Receiver timeout enable" start="23" size="1" />
+      <BitField name="ABRMOD1" description="Auto baud rate mode" start="22" size="1" />
+      <BitField name="ABRMOD0" description="ABRMOD0" start="21" size="1" />
+      <BitField name="ABREN" description="Auto baud rate enable" start="20" size="1" />
+      <BitField name="MSBFIRST" description="Most significant bit first" start="19" size="1" />
+      <BitField name="TAINV" description="Binary data inversion" start="18" size="1" />
+      <BitField name="TXINV" description="TX pin active level inversion" start="17" size="1" />
+      <BitField name="RXINV" description="RX pin active level inversion" start="16" size="1" />
+      <BitField name="SWAP" description="Swap TX/RX pins" start="15" size="1" />
+      <BitField name="LINEN" description="LIN mode enable" start="14" size="1" />
+      <BitField name="STOP" description="STOP bits" start="12" size="2" />
+      <BitField name="CLKEN" description="Clock enable" start="11" size="1" />
+      <BitField name="CPOL" description="Clock polarity" start="10" size="1" />
+      <BitField name="CPHA" description="Clock phase" start="9" size="1" />
+      <BitField name="LBCL" description="Last bit clock pulse" start="8" size="1" />
+      <BitField name="LBDIE" description="LIN break detection interrupt enable" start="6" size="1" />
+      <BitField name="LBDL" description="LIN break detection length" start="5" size="1" />
+      <BitField name="ADDM7" description="7-bit Address Detection/4-bit Address Detection" start="4" size="1" />
+      <BitField name="DIS_NSS" description="When the DSI_NSS bit is set, the NSS pin input is ignored" start="3" size="1" />
+      <BitField name="SLVEN" description="Synchronous Slave mode enable" start="0" size="1" />
+    </Register>
+    <Register name="CR3" description="Control register 3" start="+0x8" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="TXFTCFG" description="TXFIFO threshold configuration" start="29" size="3" />
+      <BitField name="RXFTIE" description="RXFIFO threshold interrupt enable" start="28" size="1" />
+      <BitField name="RXFTCFG" description="Receive FIFO threshold configuration" start="25" size="3" />
+      <BitField name="TCBGTIE" description="Transmission Complete before guard time, interrupt enable" start="24" size="1" />
+      <BitField name="TXFTIE" description="TXFIFO threshold interrupt enable" start="23" size="1" />
+      <BitField name="WUFIE" description="Wakeup from Stop mode interrupt enable" start="22" size="1" />
+      <BitField name="WUS" description="Wakeup from Stop mode interrupt flag selection" start="20" size="2" />
+      <BitField name="SCARCNT" description="Smartcard auto-retry count" start="17" size="3" />
+      <BitField name="DEP" description="Driver enable polarity selection" start="15" size="1" />
+      <BitField name="DEM" description="Driver enable mode" start="14" size="1" />
+      <BitField name="DDRE" description="DMA Disable on Reception Error" start="13" size="1" />
+      <BitField name="OVRDIS" description="Overrun Disable" start="12" size="1" />
+      <BitField name="ONEBIT" description="One sample bit method enable" start="11" size="1" />
+      <BitField name="CTSIE" description="CTS interrupt enable" start="10" size="1" />
+      <BitField name="CTSE" description="CTS enable" start="9" size="1" />
+      <BitField name="RTSE" description="RTS enable" start="8" size="1" />
+      <BitField name="DMAT" description="DMA enable transmitter" start="7" size="1" />
+      <BitField name="DMAR" description="DMA enable receiver" start="6" size="1" />
+      <BitField name="SCEN" description="Smartcard mode enable" start="5" size="1" />
+      <BitField name="NACK" description="Smartcard NACK enable" start="4" size="1" />
+      <BitField name="HDSEL" description="Half-duplex selection" start="3" size="1" />
+      <BitField name="IRLP" description="Ir low-power" start="2" size="1" />
+      <BitField name="IREN" description="Ir mode enable" start="1" size="1" />
+      <BitField name="EIE" description="Error interrupt enable" start="0" size="1" />
+    </Register>
+    <Register name="BRR" description="Baud rate register" start="+0xC" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="BRR_4_15" description="DIV_Mantissa" start="4" size="12" />
+      <BitField name="BRR_0_3" description="DIV_Fraction" start="0" size="4" />
+    </Register>
+    <Register name="GTPR" description="Guard time and prescaler register" start="+0x10" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="GT" description="Guard time value" start="8" size="8" />
+      <BitField name="PSC" description="Prescaler value" start="0" size="8" />
+    </Register>
+    <Register name="RTOR" description="Receiver timeout register" start="+0x14" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="BLEN" description="Block Length" start="24" size="8" />
+      <BitField name="RTO" description="Receiver timeout value" start="0" size="24" />
+    </Register>
+    <Register name="RQR" description="Request register" start="+0x18" size="4" access="WriteOnly" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="TXFRQ" description="Transmit data flush request" start="4" size="1" />
+      <BitField name="RXFRQ" description="Receive data flush request" start="3" size="1" />
+      <BitField name="MMRQ" description="Mute mode request" start="2" size="1" />
+      <BitField name="SBKRQ" description="Send break request" start="1" size="1" />
+      <BitField name="ABRRQ" description="Auto baud rate request" start="0" size="1" />
+    </Register>
+    <Register name="ISR" description="Interrupt &amp; status register" start="+0x1C" size="4" access="ReadOnly" reset_value="0x00C0" reset_mask="0xFFFFFFFF">
+      <BitField name="TXFT" description="TXFIFO threshold flag" start="27" size="1" />
+      <BitField name="RXFT" description="RXFIFO threshold flag" start="26" size="1" />
+      <BitField name="TCBGT" description="Transmission complete before guard time flag" start="25" size="1" />
+      <BitField name="RXFF" description="RXFIFO Full" start="24" size="1" />
+      <BitField name="TXFE" description="TXFIFO Empty" start="23" size="1" />
+      <BitField name="REACK" description="REACK" start="22" size="1" />
+      <BitField name="TEACK" description="TEACK" start="21" size="1" />
+      <BitField name="WUF" description="WUF" start="20" size="1" />
+      <BitField name="RWU" description="RWU" start="19" size="1" />
+      <BitField name="SBKF" description="SBKF" start="18" size="1" />
+      <BitField name="CMF" description="CMF" start="17" size="1" />
+      <BitField name="BUSY" description="BUSY" start="16" size="1" />
+      <BitField name="ABRF" description="ABRF" start="15" size="1" />
+      <BitField name="ABRE" description="ABRE" start="14" size="1" />
+      <BitField name="UDR" description="SPI slave underrun error flag" start="13" size="1" />
+      <BitField name="EOBF" description="EOBF" start="12" size="1" />
+      <BitField name="RTOF" description="RTOF" start="11" size="1" />
+      <BitField name="CTS" description="CTS" start="10" size="1" />
+      <BitField name="CTSIF" description="CTSIF" start="9" size="1" />
+      <BitField name="LBDF" description="LBDF" start="8" size="1" />
+      <BitField name="TXE" description="TXE" start="7" size="1" />
+      <BitField name="TC" description="TC" start="6" size="1" />
+      <BitField name="RXNE" description="RXNE" start="5" size="1" />
+      <BitField name="IDLE" description="IDLE" start="4" size="1" />
+      <BitField name="ORE" description="ORE" start="3" size="1" />
+      <BitField name="NF" description="NF" start="2" size="1" />
+      <BitField name="FE" description="FE" start="1" size="1" />
+      <BitField name="PE" description="PE" start="0" size="1" />
+    </Register>
+    <Register name="ICR" description="Interrupt flag clear register" start="+0x20" size="4" access="WriteOnly" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="WUCF" description="Wakeup from Stop mode clear flag" start="20" size="1" />
+      <BitField name="CMCF" description="Character match clear flag" start="17" size="1" />
+      <BitField name="UDRCF" description="SPI slave underrun clear flag" start="13" size="1" />
+      <BitField name="EOBCF" description="End of block clear flag" start="12" size="1" />
+      <BitField name="RTOCF" description="Receiver timeout clear flag" start="11" size="1" />
+      <BitField name="CTSCF" description="CTS clear flag" start="9" size="1" />
+      <BitField name="LBDCF" description="LIN break detection clear flag" start="8" size="1" />
+      <BitField name="TCBGTC" description="Transmission complete before Guard time clear flag" start="7" size="1" />
+      <BitField name="TCCF" description="Transmission complete clear flag" start="6" size="1" />
+      <BitField name="TXFECF" description="TXFIFO empty clear flag" start="5" size="1" />
+      <BitField name="IDLECF" description="Idle line detected clear flag" start="4" size="1" />
+      <BitField name="ORECF" description="Overrun error clear flag" start="3" size="1" />
+      <BitField name="NCF" description="Noise detected clear flag" start="2" size="1" />
+      <BitField name="FECF" description="Framing error clear flag" start="1" size="1" />
+      <BitField name="PECF" description="Parity error clear flag" start="0" size="1" />
+    </Register>
+    <Register name="RDR" description="Receive data register" start="+0x24" size="4" access="ReadOnly" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="RDR" description="Receive data value" start="0" size="9" />
+    </Register>
+    <Register name="TDR" description="Transmit data register" start="+0x28" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="TDR" description="Transmit data value" start="0" size="9" />
+    </Register>
+    <Register name="PRESC" description="USART prescaler register" start="+0x2C" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="PRESCALER" description="Clock prescaler" start="0" size="4" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="UART5" description="Universal synchronous asynchronous receiver transmitter" start="0x40005000">
+    <Register name="CR1" description="Control register 1" start="+0x0" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="RXFFIE" description="RXFIFO Full interrupt enable" start="31" size="1" />
+      <BitField name="TXFEIE" description="TXFIFO empty interrupt enable" start="30" size="1" />
+      <BitField name="FIFOEN" description="FIFO mode enable" start="29" size="1" />
+      <BitField name="M1" description="Word length" start="28" size="1" />
+      <BitField name="EOBIE" description="End of Block interrupt enable" start="27" size="1" />
+      <BitField name="RTOIE" description="Receiver timeout interrupt enable" start="26" size="1" />
+      <BitField name="DEAT4" description="Driver Enable assertion time" start="25" size="1" />
+      <BitField name="DEAT3" description="DEAT3" start="24" size="1" />
+      <BitField name="DEAT2" description="DEAT2" start="23" size="1" />
+      <BitField name="DEAT1" description="DEAT1" start="22" size="1" />
+      <BitField name="DEAT0" description="DEAT0" start="21" size="1" />
+      <BitField name="DEDT4" description="Driver Enable de-assertion time" start="20" size="1" />
+      <BitField name="DEDT3" description="DEDT3" start="19" size="1" />
+      <BitField name="DEDT2" description="DEDT2" start="18" size="1" />
+      <BitField name="DEDT1" description="DEDT1" start="17" size="1" />
+      <BitField name="DEDT0" description="DEDT0" start="16" size="1" />
+      <BitField name="OVER8" description="Oversampling mode" start="15" size="1" />
+      <BitField name="CMIE" description="Character match interrupt enable" start="14" size="1" />
+      <BitField name="MME" description="Mute mode enable" start="13" size="1" />
+      <BitField name="M0" description="Word length" start="12" size="1" />
+      <BitField name="WAKE" description="Receiver wakeup method" start="11" size="1" />
+      <BitField name="PCE" description="Parity control enable" start="10" size="1" />
+      <BitField name="PS" description="Parity selection" start="9" size="1" />
+      <BitField name="PEIE" description="PE interrupt enable" start="8" size="1" />
+      <BitField name="TXEIE" description="interrupt enable" start="7" size="1" />
+      <BitField name="TCIE" description="Transmission complete interrupt enable" start="6" size="1" />
+      <BitField name="RXNEIE" description="RXNE interrupt enable" start="5" size="1" />
+      <BitField name="IDLEIE" description="IDLE interrupt enable" start="4" size="1" />
+      <BitField name="TE" description="Transmitter enable" start="3" size="1" />
+      <BitField name="RE" description="Receiver enable" start="2" size="1" />
+      <BitField name="UESM" description="USART enable in Stop mode" start="1" size="1" />
+      <BitField name="UE" description="USART enable" start="0" size="1" />
+    </Register>
+    <Register name="CR2" description="Control register 2" start="+0x4" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="ADD4_7" description="Address of the USART node" start="28" size="4" />
+      <BitField name="ADD0_3" description="Address of the USART node" start="24" size="4" />
+      <BitField name="RTOEN" description="Receiver timeout enable" start="23" size="1" />
+      <BitField name="ABRMOD1" description="Auto baud rate mode" start="22" size="1" />
+      <BitField name="ABRMOD0" description="ABRMOD0" start="21" size="1" />
+      <BitField name="ABREN" description="Auto baud rate enable" start="20" size="1" />
+      <BitField name="MSBFIRST" description="Most significant bit first" start="19" size="1" />
+      <BitField name="TAINV" description="Binary data inversion" start="18" size="1" />
+      <BitField name="TXINV" description="TX pin active level inversion" start="17" size="1" />
+      <BitField name="RXINV" description="RX pin active level inversion" start="16" size="1" />
+      <BitField name="SWAP" description="Swap TX/RX pins" start="15" size="1" />
+      <BitField name="LINEN" description="LIN mode enable" start="14" size="1" />
+      <BitField name="STOP" description="STOP bits" start="12" size="2" />
+      <BitField name="CLKEN" description="Clock enable" start="11" size="1" />
+      <BitField name="CPOL" description="Clock polarity" start="10" size="1" />
+      <BitField name="CPHA" description="Clock phase" start="9" size="1" />
+      <BitField name="LBCL" description="Last bit clock pulse" start="8" size="1" />
+      <BitField name="LBDIE" description="LIN break detection interrupt enable" start="6" size="1" />
+      <BitField name="LBDL" description="LIN break detection length" start="5" size="1" />
+      <BitField name="ADDM7" description="7-bit Address Detection/4-bit Address Detection" start="4" size="1" />
+      <BitField name="DIS_NSS" description="When the DSI_NSS bit is set, the NSS pin input is ignored" start="3" size="1" />
+      <BitField name="SLVEN" description="Synchronous Slave mode enable" start="0" size="1" />
+    </Register>
+    <Register name="CR3" description="Control register 3" start="+0x8" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="TXFTCFG" description="TXFIFO threshold configuration" start="29" size="3" />
+      <BitField name="RXFTIE" description="RXFIFO threshold interrupt enable" start="28" size="1" />
+      <BitField name="RXFTCFG" description="Receive FIFO threshold configuration" start="25" size="3" />
+      <BitField name="TCBGTIE" description="Transmission Complete before guard time, interrupt enable" start="24" size="1" />
+      <BitField name="TXFTIE" description="TXFIFO threshold interrupt enable" start="23" size="1" />
+      <BitField name="WUFIE" description="Wakeup from Stop mode interrupt enable" start="22" size="1" />
+      <BitField name="WUS" description="Wakeup from Stop mode interrupt flag selection" start="20" size="2" />
+      <BitField name="SCARCNT" description="Smartcard auto-retry count" start="17" size="3" />
+      <BitField name="DEP" description="Driver enable polarity selection" start="15" size="1" />
+      <BitField name="DEM" description="Driver enable mode" start="14" size="1" />
+      <BitField name="DDRE" description="DMA Disable on Reception Error" start="13" size="1" />
+      <BitField name="OVRDIS" description="Overrun Disable" start="12" size="1" />
+      <BitField name="ONEBIT" description="One sample bit method enable" start="11" size="1" />
+      <BitField name="CTSIE" description="CTS interrupt enable" start="10" size="1" />
+      <BitField name="CTSE" description="CTS enable" start="9" size="1" />
+      <BitField name="RTSE" description="RTS enable" start="8" size="1" />
+      <BitField name="DMAT" description="DMA enable transmitter" start="7" size="1" />
+      <BitField name="DMAR" description="DMA enable receiver" start="6" size="1" />
+      <BitField name="SCEN" description="Smartcard mode enable" start="5" size="1" />
+      <BitField name="NACK" description="Smartcard NACK enable" start="4" size="1" />
+      <BitField name="HDSEL" description="Half-duplex selection" start="3" size="1" />
+      <BitField name="IRLP" description="Ir low-power" start="2" size="1" />
+      <BitField name="IREN" description="Ir mode enable" start="1" size="1" />
+      <BitField name="EIE" description="Error interrupt enable" start="0" size="1" />
+    </Register>
+    <Register name="BRR" description="Baud rate register" start="+0xC" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="BRR_4_15" description="DIV_Mantissa" start="4" size="12" />
+      <BitField name="BRR_0_3" description="DIV_Fraction" start="0" size="4" />
+    </Register>
+    <Register name="GTPR" description="Guard time and prescaler register" start="+0x10" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="GT" description="Guard time value" start="8" size="8" />
+      <BitField name="PSC" description="Prescaler value" start="0" size="8" />
+    </Register>
+    <Register name="RTOR" description="Receiver timeout register" start="+0x14" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="BLEN" description="Block Length" start="24" size="8" />
+      <BitField name="RTO" description="Receiver timeout value" start="0" size="24" />
+    </Register>
+    <Register name="RQR" description="Request register" start="+0x18" size="4" access="WriteOnly" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="TXFRQ" description="Transmit data flush request" start="4" size="1" />
+      <BitField name="RXFRQ" description="Receive data flush request" start="3" size="1" />
+      <BitField name="MMRQ" description="Mute mode request" start="2" size="1" />
+      <BitField name="SBKRQ" description="Send break request" start="1" size="1" />
+      <BitField name="ABRRQ" description="Auto baud rate request" start="0" size="1" />
+    </Register>
+    <Register name="ISR" description="Interrupt &amp; status register" start="+0x1C" size="4" access="ReadOnly" reset_value="0x00C0" reset_mask="0xFFFFFFFF">
+      <BitField name="TXFT" description="TXFIFO threshold flag" start="27" size="1" />
+      <BitField name="RXFT" description="RXFIFO threshold flag" start="26" size="1" />
+      <BitField name="TCBGT" description="Transmission complete before guard time flag" start="25" size="1" />
+      <BitField name="RXFF" description="RXFIFO Full" start="24" size="1" />
+      <BitField name="TXFE" description="TXFIFO Empty" start="23" size="1" />
+      <BitField name="REACK" description="REACK" start="22" size="1" />
+      <BitField name="TEACK" description="TEACK" start="21" size="1" />
+      <BitField name="WUF" description="WUF" start="20" size="1" />
+      <BitField name="RWU" description="RWU" start="19" size="1" />
+      <BitField name="SBKF" description="SBKF" start="18" size="1" />
+      <BitField name="CMF" description="CMF" start="17" size="1" />
+      <BitField name="BUSY" description="BUSY" start="16" size="1" />
+      <BitField name="ABRF" description="ABRF" start="15" size="1" />
+      <BitField name="ABRE" description="ABRE" start="14" size="1" />
+      <BitField name="UDR" description="SPI slave underrun error flag" start="13" size="1" />
+      <BitField name="EOBF" description="EOBF" start="12" size="1" />
+      <BitField name="RTOF" description="RTOF" start="11" size="1" />
+      <BitField name="CTS" description="CTS" start="10" size="1" />
+      <BitField name="CTSIF" description="CTSIF" start="9" size="1" />
+      <BitField name="LBDF" description="LBDF" start="8" size="1" />
+      <BitField name="TXE" description="TXE" start="7" size="1" />
+      <BitField name="TC" description="TC" start="6" size="1" />
+      <BitField name="RXNE" description="RXNE" start="5" size="1" />
+      <BitField name="IDLE" description="IDLE" start="4" size="1" />
+      <BitField name="ORE" description="ORE" start="3" size="1" />
+      <BitField name="NF" description="NF" start="2" size="1" />
+      <BitField name="FE" description="FE" start="1" size="1" />
+      <BitField name="PE" description="PE" start="0" size="1" />
+    </Register>
+    <Register name="ICR" description="Interrupt flag clear register" start="+0x20" size="4" access="WriteOnly" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="WUCF" description="Wakeup from Stop mode clear flag" start="20" size="1" />
+      <BitField name="CMCF" description="Character match clear flag" start="17" size="1" />
+      <BitField name="UDRCF" description="SPI slave underrun clear flag" start="13" size="1" />
+      <BitField name="EOBCF" description="End of block clear flag" start="12" size="1" />
+      <BitField name="RTOCF" description="Receiver timeout clear flag" start="11" size="1" />
+      <BitField name="CTSCF" description="CTS clear flag" start="9" size="1" />
+      <BitField name="LBDCF" description="LIN break detection clear flag" start="8" size="1" />
+      <BitField name="TCBGTC" description="Transmission complete before Guard time clear flag" start="7" size="1" />
+      <BitField name="TCCF" description="Transmission complete clear flag" start="6" size="1" />
+      <BitField name="TXFECF" description="TXFIFO empty clear flag" start="5" size="1" />
+      <BitField name="IDLECF" description="Idle line detected clear flag" start="4" size="1" />
+      <BitField name="ORECF" description="Overrun error clear flag" start="3" size="1" />
+      <BitField name="NCF" description="Noise detected clear flag" start="2" size="1" />
+      <BitField name="FECF" description="Framing error clear flag" start="1" size="1" />
+      <BitField name="PECF" description="Parity error clear flag" start="0" size="1" />
+    </Register>
+    <Register name="RDR" description="Receive data register" start="+0x24" size="4" access="ReadOnly" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="RDR" description="Receive data value" start="0" size="9" />
+    </Register>
+    <Register name="TDR" description="Transmit data register" start="+0x28" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="TDR" description="Transmit data value" start="0" size="9" />
+    </Register>
+    <Register name="PRESC" description="USART prescaler register" start="+0x2C" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="PRESCALER" description="Clock prescaler" start="0" size="4" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="USART6" description="Universal synchronous asynchronous receiver transmitter" start="0x40011400">
+    <Register name="CR1" description="Control register 1" start="+0x0" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="RXFFIE" description="RXFIFO Full interrupt enable" start="31" size="1" />
+      <BitField name="TXFEIE" description="TXFIFO empty interrupt enable" start="30" size="1" />
+      <BitField name="FIFOEN" description="FIFO mode enable" start="29" size="1" />
+      <BitField name="M1" description="Word length" start="28" size="1" />
+      <BitField name="EOBIE" description="End of Block interrupt enable" start="27" size="1" />
+      <BitField name="RTOIE" description="Receiver timeout interrupt enable" start="26" size="1" />
+      <BitField name="DEAT4" description="Driver Enable assertion time" start="25" size="1" />
+      <BitField name="DEAT3" description="DEAT3" start="24" size="1" />
+      <BitField name="DEAT2" description="DEAT2" start="23" size="1" />
+      <BitField name="DEAT1" description="DEAT1" start="22" size="1" />
+      <BitField name="DEAT0" description="DEAT0" start="21" size="1" />
+      <BitField name="DEDT4" description="Driver Enable de-assertion time" start="20" size="1" />
+      <BitField name="DEDT3" description="DEDT3" start="19" size="1" />
+      <BitField name="DEDT2" description="DEDT2" start="18" size="1" />
+      <BitField name="DEDT1" description="DEDT1" start="17" size="1" />
+      <BitField name="DEDT0" description="DEDT0" start="16" size="1" />
+      <BitField name="OVER8" description="Oversampling mode" start="15" size="1" />
+      <BitField name="CMIE" description="Character match interrupt enable" start="14" size="1" />
+      <BitField name="MME" description="Mute mode enable" start="13" size="1" />
+      <BitField name="M0" description="Word length" start="12" size="1" />
+      <BitField name="WAKE" description="Receiver wakeup method" start="11" size="1" />
+      <BitField name="PCE" description="Parity control enable" start="10" size="1" />
+      <BitField name="PS" description="Parity selection" start="9" size="1" />
+      <BitField name="PEIE" description="PE interrupt enable" start="8" size="1" />
+      <BitField name="TXEIE" description="interrupt enable" start="7" size="1" />
+      <BitField name="TCIE" description="Transmission complete interrupt enable" start="6" size="1" />
+      <BitField name="RXNEIE" description="RXNE interrupt enable" start="5" size="1" />
+      <BitField name="IDLEIE" description="IDLE interrupt enable" start="4" size="1" />
+      <BitField name="TE" description="Transmitter enable" start="3" size="1" />
+      <BitField name="RE" description="Receiver enable" start="2" size="1" />
+      <BitField name="UESM" description="USART enable in Stop mode" start="1" size="1" />
+      <BitField name="UE" description="USART enable" start="0" size="1" />
+    </Register>
+    <Register name="CR2" description="Control register 2" start="+0x4" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="ADD4_7" description="Address of the USART node" start="28" size="4" />
+      <BitField name="ADD0_3" description="Address of the USART node" start="24" size="4" />
+      <BitField name="RTOEN" description="Receiver timeout enable" start="23" size="1" />
+      <BitField name="ABRMOD1" description="Auto baud rate mode" start="22" size="1" />
+      <BitField name="ABRMOD0" description="ABRMOD0" start="21" size="1" />
+      <BitField name="ABREN" description="Auto baud rate enable" start="20" size="1" />
+      <BitField name="MSBFIRST" description="Most significant bit first" start="19" size="1" />
+      <BitField name="TAINV" description="Binary data inversion" start="18" size="1" />
+      <BitField name="TXINV" description="TX pin active level inversion" start="17" size="1" />
+      <BitField name="RXINV" description="RX pin active level inversion" start="16" size="1" />
+      <BitField name="SWAP" description="Swap TX/RX pins" start="15" size="1" />
+      <BitField name="LINEN" description="LIN mode enable" start="14" size="1" />
+      <BitField name="STOP" description="STOP bits" start="12" size="2" />
+      <BitField name="CLKEN" description="Clock enable" start="11" size="1" />
+      <BitField name="CPOL" description="Clock polarity" start="10" size="1" />
+      <BitField name="CPHA" description="Clock phase" start="9" size="1" />
+      <BitField name="LBCL" description="Last bit clock pulse" start="8" size="1" />
+      <BitField name="LBDIE" description="LIN break detection interrupt enable" start="6" size="1" />
+      <BitField name="LBDL" description="LIN break detection length" start="5" size="1" />
+      <BitField name="ADDM7" description="7-bit Address Detection/4-bit Address Detection" start="4" size="1" />
+      <BitField name="DIS_NSS" description="When the DSI_NSS bit is set, the NSS pin input is ignored" start="3" size="1" />
+      <BitField name="SLVEN" description="Synchronous Slave mode enable" start="0" size="1" />
+    </Register>
+    <Register name="CR3" description="Control register 3" start="+0x8" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="TXFTCFG" description="TXFIFO threshold configuration" start="29" size="3" />
+      <BitField name="RXFTIE" description="RXFIFO threshold interrupt enable" start="28" size="1" />
+      <BitField name="RXFTCFG" description="Receive FIFO threshold configuration" start="25" size="3" />
+      <BitField name="TCBGTIE" description="Transmission Complete before guard time, interrupt enable" start="24" size="1" />
+      <BitField name="TXFTIE" description="TXFIFO threshold interrupt enable" start="23" size="1" />
+      <BitField name="WUFIE" description="Wakeup from Stop mode interrupt enable" start="22" size="1" />
+      <BitField name="WUS" description="Wakeup from Stop mode interrupt flag selection" start="20" size="2" />
+      <BitField name="SCARCNT" description="Smartcard auto-retry count" start="17" size="3" />
+      <BitField name="DEP" description="Driver enable polarity selection" start="15" size="1" />
+      <BitField name="DEM" description="Driver enable mode" start="14" size="1" />
+      <BitField name="DDRE" description="DMA Disable on Reception Error" start="13" size="1" />
+      <BitField name="OVRDIS" description="Overrun Disable" start="12" size="1" />
+      <BitField name="ONEBIT" description="One sample bit method enable" start="11" size="1" />
+      <BitField name="CTSIE" description="CTS interrupt enable" start="10" size="1" />
+      <BitField name="CTSE" description="CTS enable" start="9" size="1" />
+      <BitField name="RTSE" description="RTS enable" start="8" size="1" />
+      <BitField name="DMAT" description="DMA enable transmitter" start="7" size="1" />
+      <BitField name="DMAR" description="DMA enable receiver" start="6" size="1" />
+      <BitField name="SCEN" description="Smartcard mode enable" start="5" size="1" />
+      <BitField name="NACK" description="Smartcard NACK enable" start="4" size="1" />
+      <BitField name="HDSEL" description="Half-duplex selection" start="3" size="1" />
+      <BitField name="IRLP" description="Ir low-power" start="2" size="1" />
+      <BitField name="IREN" description="Ir mode enable" start="1" size="1" />
+      <BitField name="EIE" description="Error interrupt enable" start="0" size="1" />
+    </Register>
+    <Register name="BRR" description="Baud rate register" start="+0xC" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="BRR_4_15" description="DIV_Mantissa" start="4" size="12" />
+      <BitField name="BRR_0_3" description="DIV_Fraction" start="0" size="4" />
+    </Register>
+    <Register name="GTPR" description="Guard time and prescaler register" start="+0x10" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="GT" description="Guard time value" start="8" size="8" />
+      <BitField name="PSC" description="Prescaler value" start="0" size="8" />
+    </Register>
+    <Register name="RTOR" description="Receiver timeout register" start="+0x14" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="BLEN" description="Block Length" start="24" size="8" />
+      <BitField name="RTO" description="Receiver timeout value" start="0" size="24" />
+    </Register>
+    <Register name="RQR" description="Request register" start="+0x18" size="4" access="WriteOnly" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="TXFRQ" description="Transmit data flush request" start="4" size="1" />
+      <BitField name="RXFRQ" description="Receive data flush request" start="3" size="1" />
+      <BitField name="MMRQ" description="Mute mode request" start="2" size="1" />
+      <BitField name="SBKRQ" description="Send break request" start="1" size="1" />
+      <BitField name="ABRRQ" description="Auto baud rate request" start="0" size="1" />
+    </Register>
+    <Register name="ISR" description="Interrupt &amp; status register" start="+0x1C" size="4" access="ReadOnly" reset_value="0x00C0" reset_mask="0xFFFFFFFF">
+      <BitField name="TXFT" description="TXFIFO threshold flag" start="27" size="1" />
+      <BitField name="RXFT" description="RXFIFO threshold flag" start="26" size="1" />
+      <BitField name="TCBGT" description="Transmission complete before guard time flag" start="25" size="1" />
+      <BitField name="RXFF" description="RXFIFO Full" start="24" size="1" />
+      <BitField name="TXFE" description="TXFIFO Empty" start="23" size="1" />
+      <BitField name="REACK" description="REACK" start="22" size="1" />
+      <BitField name="TEACK" description="TEACK" start="21" size="1" />
+      <BitField name="WUF" description="WUF" start="20" size="1" />
+      <BitField name="RWU" description="RWU" start="19" size="1" />
+      <BitField name="SBKF" description="SBKF" start="18" size="1" />
+      <BitField name="CMF" description="CMF" start="17" size="1" />
+      <BitField name="BUSY" description="BUSY" start="16" size="1" />
+      <BitField name="ABRF" description="ABRF" start="15" size="1" />
+      <BitField name="ABRE" description="ABRE" start="14" size="1" />
+      <BitField name="UDR" description="SPI slave underrun error flag" start="13" size="1" />
+      <BitField name="EOBF" description="EOBF" start="12" size="1" />
+      <BitField name="RTOF" description="RTOF" start="11" size="1" />
+      <BitField name="CTS" description="CTS" start="10" size="1" />
+      <BitField name="CTSIF" description="CTSIF" start="9" size="1" />
+      <BitField name="LBDF" description="LBDF" start="8" size="1" />
+      <BitField name="TXE" description="TXE" start="7" size="1" />
+      <BitField name="TC" description="TC" start="6" size="1" />
+      <BitField name="RXNE" description="RXNE" start="5" size="1" />
+      <BitField name="IDLE" description="IDLE" start="4" size="1" />
+      <BitField name="ORE" description="ORE" start="3" size="1" />
+      <BitField name="NF" description="NF" start="2" size="1" />
+      <BitField name="FE" description="FE" start="1" size="1" />
+      <BitField name="PE" description="PE" start="0" size="1" />
+    </Register>
+    <Register name="ICR" description="Interrupt flag clear register" start="+0x20" size="4" access="WriteOnly" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="WUCF" description="Wakeup from Stop mode clear flag" start="20" size="1" />
+      <BitField name="CMCF" description="Character match clear flag" start="17" size="1" />
+      <BitField name="UDRCF" description="SPI slave underrun clear flag" start="13" size="1" />
+      <BitField name="EOBCF" description="End of block clear flag" start="12" size="1" />
+      <BitField name="RTOCF" description="Receiver timeout clear flag" start="11" size="1" />
+      <BitField name="CTSCF" description="CTS clear flag" start="9" size="1" />
+      <BitField name="LBDCF" description="LIN break detection clear flag" start="8" size="1" />
+      <BitField name="TCBGTC" description="Transmission complete before Guard time clear flag" start="7" size="1" />
+      <BitField name="TCCF" description="Transmission complete clear flag" start="6" size="1" />
+      <BitField name="TXFECF" description="TXFIFO empty clear flag" start="5" size="1" />
+      <BitField name="IDLECF" description="Idle line detected clear flag" start="4" size="1" />
+      <BitField name="ORECF" description="Overrun error clear flag" start="3" size="1" />
+      <BitField name="NCF" description="Noise detected clear flag" start="2" size="1" />
+      <BitField name="FECF" description="Framing error clear flag" start="1" size="1" />
+      <BitField name="PECF" description="Parity error clear flag" start="0" size="1" />
+    </Register>
+    <Register name="RDR" description="Receive data register" start="+0x24" size="4" access="ReadOnly" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="RDR" description="Receive data value" start="0" size="9" />
+    </Register>
+    <Register name="TDR" description="Transmit data register" start="+0x28" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="TDR" description="Transmit data value" start="0" size="9" />
+    </Register>
+    <Register name="PRESC" description="USART prescaler register" start="+0x2C" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="PRESCALER" description="Clock prescaler" start="0" size="4" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="UART7" description="Universal synchronous asynchronous receiver transmitter" start="0x40007800">
+    <Register name="CR1" description="Control register 1" start="+0x0" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="RXFFIE" description="RXFIFO Full interrupt enable" start="31" size="1" />
+      <BitField name="TXFEIE" description="TXFIFO empty interrupt enable" start="30" size="1" />
+      <BitField name="FIFOEN" description="FIFO mode enable" start="29" size="1" />
+      <BitField name="M1" description="Word length" start="28" size="1" />
+      <BitField name="EOBIE" description="End of Block interrupt enable" start="27" size="1" />
+      <BitField name="RTOIE" description="Receiver timeout interrupt enable" start="26" size="1" />
+      <BitField name="DEAT4" description="Driver Enable assertion time" start="25" size="1" />
+      <BitField name="DEAT3" description="DEAT3" start="24" size="1" />
+      <BitField name="DEAT2" description="DEAT2" start="23" size="1" />
+      <BitField name="DEAT1" description="DEAT1" start="22" size="1" />
+      <BitField name="DEAT0" description="DEAT0" start="21" size="1" />
+      <BitField name="DEDT4" description="Driver Enable de-assertion time" start="20" size="1" />
+      <BitField name="DEDT3" description="DEDT3" start="19" size="1" />
+      <BitField name="DEDT2" description="DEDT2" start="18" size="1" />
+      <BitField name="DEDT1" description="DEDT1" start="17" size="1" />
+      <BitField name="DEDT0" description="DEDT0" start="16" size="1" />
+      <BitField name="OVER8" description="Oversampling mode" start="15" size="1" />
+      <BitField name="CMIE" description="Character match interrupt enable" start="14" size="1" />
+      <BitField name="MME" description="Mute mode enable" start="13" size="1" />
+      <BitField name="M0" description="Word length" start="12" size="1" />
+      <BitField name="WAKE" description="Receiver wakeup method" start="11" size="1" />
+      <BitField name="PCE" description="Parity control enable" start="10" size="1" />
+      <BitField name="PS" description="Parity selection" start="9" size="1" />
+      <BitField name="PEIE" description="PE interrupt enable" start="8" size="1" />
+      <BitField name="TXEIE" description="interrupt enable" start="7" size="1" />
+      <BitField name="TCIE" description="Transmission complete interrupt enable" start="6" size="1" />
+      <BitField name="RXNEIE" description="RXNE interrupt enable" start="5" size="1" />
+      <BitField name="IDLEIE" description="IDLE interrupt enable" start="4" size="1" />
+      <BitField name="TE" description="Transmitter enable" start="3" size="1" />
+      <BitField name="RE" description="Receiver enable" start="2" size="1" />
+      <BitField name="UESM" description="USART enable in Stop mode" start="1" size="1" />
+      <BitField name="UE" description="USART enable" start="0" size="1" />
+    </Register>
+    <Register name="CR2" description="Control register 2" start="+0x4" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="ADD4_7" description="Address of the USART node" start="28" size="4" />
+      <BitField name="ADD0_3" description="Address of the USART node" start="24" size="4" />
+      <BitField name="RTOEN" description="Receiver timeout enable" start="23" size="1" />
+      <BitField name="ABRMOD1" description="Auto baud rate mode" start="22" size="1" />
+      <BitField name="ABRMOD0" description="ABRMOD0" start="21" size="1" />
+      <BitField name="ABREN" description="Auto baud rate enable" start="20" size="1" />
+      <BitField name="MSBFIRST" description="Most significant bit first" start="19" size="1" />
+      <BitField name="TAINV" description="Binary data inversion" start="18" size="1" />
+      <BitField name="TXINV" description="TX pin active level inversion" start="17" size="1" />
+      <BitField name="RXINV" description="RX pin active level inversion" start="16" size="1" />
+      <BitField name="SWAP" description="Swap TX/RX pins" start="15" size="1" />
+      <BitField name="LINEN" description="LIN mode enable" start="14" size="1" />
+      <BitField name="STOP" description="STOP bits" start="12" size="2" />
+      <BitField name="CLKEN" description="Clock enable" start="11" size="1" />
+      <BitField name="CPOL" description="Clock polarity" start="10" size="1" />
+      <BitField name="CPHA" description="Clock phase" start="9" size="1" />
+      <BitField name="LBCL" description="Last bit clock pulse" start="8" size="1" />
+      <BitField name="LBDIE" description="LIN break detection interrupt enable" start="6" size="1" />
+      <BitField name="LBDL" description="LIN break detection length" start="5" size="1" />
+      <BitField name="ADDM7" description="7-bit Address Detection/4-bit Address Detection" start="4" size="1" />
+      <BitField name="DIS_NSS" description="When the DSI_NSS bit is set, the NSS pin input is ignored" start="3" size="1" />
+      <BitField name="SLVEN" description="Synchronous Slave mode enable" start="0" size="1" />
+    </Register>
+    <Register name="CR3" description="Control register 3" start="+0x8" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="TXFTCFG" description="TXFIFO threshold configuration" start="29" size="3" />
+      <BitField name="RXFTIE" description="RXFIFO threshold interrupt enable" start="28" size="1" />
+      <BitField name="RXFTCFG" description="Receive FIFO threshold configuration" start="25" size="3" />
+      <BitField name="TCBGTIE" description="Transmission Complete before guard time, interrupt enable" start="24" size="1" />
+      <BitField name="TXFTIE" description="TXFIFO threshold interrupt enable" start="23" size="1" />
+      <BitField name="WUFIE" description="Wakeup from Stop mode interrupt enable" start="22" size="1" />
+      <BitField name="WUS" description="Wakeup from Stop mode interrupt flag selection" start="20" size="2" />
+      <BitField name="SCARCNT" description="Smartcard auto-retry count" start="17" size="3" />
+      <BitField name="DEP" description="Driver enable polarity selection" start="15" size="1" />
+      <BitField name="DEM" description="Driver enable mode" start="14" size="1" />
+      <BitField name="DDRE" description="DMA Disable on Reception Error" start="13" size="1" />
+      <BitField name="OVRDIS" description="Overrun Disable" start="12" size="1" />
+      <BitField name="ONEBIT" description="One sample bit method enable" start="11" size="1" />
+      <BitField name="CTSIE" description="CTS interrupt enable" start="10" size="1" />
+      <BitField name="CTSE" description="CTS enable" start="9" size="1" />
+      <BitField name="RTSE" description="RTS enable" start="8" size="1" />
+      <BitField name="DMAT" description="DMA enable transmitter" start="7" size="1" />
+      <BitField name="DMAR" description="DMA enable receiver" start="6" size="1" />
+      <BitField name="SCEN" description="Smartcard mode enable" start="5" size="1" />
+      <BitField name="NACK" description="Smartcard NACK enable" start="4" size="1" />
+      <BitField name="HDSEL" description="Half-duplex selection" start="3" size="1" />
+      <BitField name="IRLP" description="Ir low-power" start="2" size="1" />
+      <BitField name="IREN" description="Ir mode enable" start="1" size="1" />
+      <BitField name="EIE" description="Error interrupt enable" start="0" size="1" />
+    </Register>
+    <Register name="BRR" description="Baud rate register" start="+0xC" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="BRR_4_15" description="DIV_Mantissa" start="4" size="12" />
+      <BitField name="BRR_0_3" description="DIV_Fraction" start="0" size="4" />
+    </Register>
+    <Register name="GTPR" description="Guard time and prescaler register" start="+0x10" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="GT" description="Guard time value" start="8" size="8" />
+      <BitField name="PSC" description="Prescaler value" start="0" size="8" />
+    </Register>
+    <Register name="RTOR" description="Receiver timeout register" start="+0x14" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="BLEN" description="Block Length" start="24" size="8" />
+      <BitField name="RTO" description="Receiver timeout value" start="0" size="24" />
+    </Register>
+    <Register name="RQR" description="Request register" start="+0x18" size="4" access="WriteOnly" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="TXFRQ" description="Transmit data flush request" start="4" size="1" />
+      <BitField name="RXFRQ" description="Receive data flush request" start="3" size="1" />
+      <BitField name="MMRQ" description="Mute mode request" start="2" size="1" />
+      <BitField name="SBKRQ" description="Send break request" start="1" size="1" />
+      <BitField name="ABRRQ" description="Auto baud rate request" start="0" size="1" />
+    </Register>
+    <Register name="ISR" description="Interrupt &amp; status register" start="+0x1C" size="4" access="ReadOnly" reset_value="0x00C0" reset_mask="0xFFFFFFFF">
+      <BitField name="TXFT" description="TXFIFO threshold flag" start="27" size="1" />
+      <BitField name="RXFT" description="RXFIFO threshold flag" start="26" size="1" />
+      <BitField name="TCBGT" description="Transmission complete before guard time flag" start="25" size="1" />
+      <BitField name="RXFF" description="RXFIFO Full" start="24" size="1" />
+      <BitField name="TXFE" description="TXFIFO Empty" start="23" size="1" />
+      <BitField name="REACK" description="REACK" start="22" size="1" />
+      <BitField name="TEACK" description="TEACK" start="21" size="1" />
+      <BitField name="WUF" description="WUF" start="20" size="1" />
+      <BitField name="RWU" description="RWU" start="19" size="1" />
+      <BitField name="SBKF" description="SBKF" start="18" size="1" />
+      <BitField name="CMF" description="CMF" start="17" size="1" />
+      <BitField name="BUSY" description="BUSY" start="16" size="1" />
+      <BitField name="ABRF" description="ABRF" start="15" size="1" />
+      <BitField name="ABRE" description="ABRE" start="14" size="1" />
+      <BitField name="UDR" description="SPI slave underrun error flag" start="13" size="1" />
+      <BitField name="EOBF" description="EOBF" start="12" size="1" />
+      <BitField name="RTOF" description="RTOF" start="11" size="1" />
+      <BitField name="CTS" description="CTS" start="10" size="1" />
+      <BitField name="CTSIF" description="CTSIF" start="9" size="1" />
+      <BitField name="LBDF" description="LBDF" start="8" size="1" />
+      <BitField name="TXE" description="TXE" start="7" size="1" />
+      <BitField name="TC" description="TC" start="6" size="1" />
+      <BitField name="RXNE" description="RXNE" start="5" size="1" />
+      <BitField name="IDLE" description="IDLE" start="4" size="1" />
+      <BitField name="ORE" description="ORE" start="3" size="1" />
+      <BitField name="NF" description="NF" start="2" size="1" />
+      <BitField name="FE" description="FE" start="1" size="1" />
+      <BitField name="PE" description="PE" start="0" size="1" />
+    </Register>
+    <Register name="ICR" description="Interrupt flag clear register" start="+0x20" size="4" access="WriteOnly" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="WUCF" description="Wakeup from Stop mode clear flag" start="20" size="1" />
+      <BitField name="CMCF" description="Character match clear flag" start="17" size="1" />
+      <BitField name="UDRCF" description="SPI slave underrun clear flag" start="13" size="1" />
+      <BitField name="EOBCF" description="End of block clear flag" start="12" size="1" />
+      <BitField name="RTOCF" description="Receiver timeout clear flag" start="11" size="1" />
+      <BitField name="CTSCF" description="CTS clear flag" start="9" size="1" />
+      <BitField name="LBDCF" description="LIN break detection clear flag" start="8" size="1" />
+      <BitField name="TCBGTC" description="Transmission complete before Guard time clear flag" start="7" size="1" />
+      <BitField name="TCCF" description="Transmission complete clear flag" start="6" size="1" />
+      <BitField name="TXFECF" description="TXFIFO empty clear flag" start="5" size="1" />
+      <BitField name="IDLECF" description="Idle line detected clear flag" start="4" size="1" />
+      <BitField name="ORECF" description="Overrun error clear flag" start="3" size="1" />
+      <BitField name="NCF" description="Noise detected clear flag" start="2" size="1" />
+      <BitField name="FECF" description="Framing error clear flag" start="1" size="1" />
+      <BitField name="PECF" description="Parity error clear flag" start="0" size="1" />
+    </Register>
+    <Register name="RDR" description="Receive data register" start="+0x24" size="4" access="ReadOnly" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="RDR" description="Receive data value" start="0" size="9" />
+    </Register>
+    <Register name="TDR" description="Transmit data register" start="+0x28" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="TDR" description="Transmit data value" start="0" size="9" />
+    </Register>
+    <Register name="PRESC" description="USART prescaler register" start="+0x2C" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="PRESCALER" description="Clock prescaler" start="0" size="4" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="UART8" description="Universal synchronous asynchronous receiver transmitter" start="0x40007C00">
+    <Register name="CR1" description="Control register 1" start="+0x0" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="RXFFIE" description="RXFIFO Full interrupt enable" start="31" size="1" />
+      <BitField name="TXFEIE" description="TXFIFO empty interrupt enable" start="30" size="1" />
+      <BitField name="FIFOEN" description="FIFO mode enable" start="29" size="1" />
+      <BitField name="M1" description="Word length" start="28" size="1" />
+      <BitField name="EOBIE" description="End of Block interrupt enable" start="27" size="1" />
+      <BitField name="RTOIE" description="Receiver timeout interrupt enable" start="26" size="1" />
+      <BitField name="DEAT4" description="Driver Enable assertion time" start="25" size="1" />
+      <BitField name="DEAT3" description="DEAT3" start="24" size="1" />
+      <BitField name="DEAT2" description="DEAT2" start="23" size="1" />
+      <BitField name="DEAT1" description="DEAT1" start="22" size="1" />
+      <BitField name="DEAT0" description="DEAT0" start="21" size="1" />
+      <BitField name="DEDT4" description="Driver Enable de-assertion time" start="20" size="1" />
+      <BitField name="DEDT3" description="DEDT3" start="19" size="1" />
+      <BitField name="DEDT2" description="DEDT2" start="18" size="1" />
+      <BitField name="DEDT1" description="DEDT1" start="17" size="1" />
+      <BitField name="DEDT0" description="DEDT0" start="16" size="1" />
+      <BitField name="OVER8" description="Oversampling mode" start="15" size="1" />
+      <BitField name="CMIE" description="Character match interrupt enable" start="14" size="1" />
+      <BitField name="MME" description="Mute mode enable" start="13" size="1" />
+      <BitField name="M0" description="Word length" start="12" size="1" />
+      <BitField name="WAKE" description="Receiver wakeup method" start="11" size="1" />
+      <BitField name="PCE" description="Parity control enable" start="10" size="1" />
+      <BitField name="PS" description="Parity selection" start="9" size="1" />
+      <BitField name="PEIE" description="PE interrupt enable" start="8" size="1" />
+      <BitField name="TXEIE" description="interrupt enable" start="7" size="1" />
+      <BitField name="TCIE" description="Transmission complete interrupt enable" start="6" size="1" />
+      <BitField name="RXNEIE" description="RXNE interrupt enable" start="5" size="1" />
+      <BitField name="IDLEIE" description="IDLE interrupt enable" start="4" size="1" />
+      <BitField name="TE" description="Transmitter enable" start="3" size="1" />
+      <BitField name="RE" description="Receiver enable" start="2" size="1" />
+      <BitField name="UESM" description="USART enable in Stop mode" start="1" size="1" />
+      <BitField name="UE" description="USART enable" start="0" size="1" />
+    </Register>
+    <Register name="CR2" description="Control register 2" start="+0x4" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="ADD4_7" description="Address of the USART node" start="28" size="4" />
+      <BitField name="ADD0_3" description="Address of the USART node" start="24" size="4" />
+      <BitField name="RTOEN" description="Receiver timeout enable" start="23" size="1" />
+      <BitField name="ABRMOD1" description="Auto baud rate mode" start="22" size="1" />
+      <BitField name="ABRMOD0" description="ABRMOD0" start="21" size="1" />
+      <BitField name="ABREN" description="Auto baud rate enable" start="20" size="1" />
+      <BitField name="MSBFIRST" description="Most significant bit first" start="19" size="1" />
+      <BitField name="TAINV" description="Binary data inversion" start="18" size="1" />
+      <BitField name="TXINV" description="TX pin active level inversion" start="17" size="1" />
+      <BitField name="RXINV" description="RX pin active level inversion" start="16" size="1" />
+      <BitField name="SWAP" description="Swap TX/RX pins" start="15" size="1" />
+      <BitField name="LINEN" description="LIN mode enable" start="14" size="1" />
+      <BitField name="STOP" description="STOP bits" start="12" size="2" />
+      <BitField name="CLKEN" description="Clock enable" start="11" size="1" />
+      <BitField name="CPOL" description="Clock polarity" start="10" size="1" />
+      <BitField name="CPHA" description="Clock phase" start="9" size="1" />
+      <BitField name="LBCL" description="Last bit clock pulse" start="8" size="1" />
+      <BitField name="LBDIE" description="LIN break detection interrupt enable" start="6" size="1" />
+      <BitField name="LBDL" description="LIN break detection length" start="5" size="1" />
+      <BitField name="ADDM7" description="7-bit Address Detection/4-bit Address Detection" start="4" size="1" />
+      <BitField name="DIS_NSS" description="When the DSI_NSS bit is set, the NSS pin input is ignored" start="3" size="1" />
+      <BitField name="SLVEN" description="Synchronous Slave mode enable" start="0" size="1" />
+    </Register>
+    <Register name="CR3" description="Control register 3" start="+0x8" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="TXFTCFG" description="TXFIFO threshold configuration" start="29" size="3" />
+      <BitField name="RXFTIE" description="RXFIFO threshold interrupt enable" start="28" size="1" />
+      <BitField name="RXFTCFG" description="Receive FIFO threshold configuration" start="25" size="3" />
+      <BitField name="TCBGTIE" description="Transmission Complete before guard time, interrupt enable" start="24" size="1" />
+      <BitField name="TXFTIE" description="TXFIFO threshold interrupt enable" start="23" size="1" />
+      <BitField name="WUFIE" description="Wakeup from Stop mode interrupt enable" start="22" size="1" />
+      <BitField name="WUS" description="Wakeup from Stop mode interrupt flag selection" start="20" size="2" />
+      <BitField name="SCARCNT" description="Smartcard auto-retry count" start="17" size="3" />
+      <BitField name="DEP" description="Driver enable polarity selection" start="15" size="1" />
+      <BitField name="DEM" description="Driver enable mode" start="14" size="1" />
+      <BitField name="DDRE" description="DMA Disable on Reception Error" start="13" size="1" />
+      <BitField name="OVRDIS" description="Overrun Disable" start="12" size="1" />
+      <BitField name="ONEBIT" description="One sample bit method enable" start="11" size="1" />
+      <BitField name="CTSIE" description="CTS interrupt enable" start="10" size="1" />
+      <BitField name="CTSE" description="CTS enable" start="9" size="1" />
+      <BitField name="RTSE" description="RTS enable" start="8" size="1" />
+      <BitField name="DMAT" description="DMA enable transmitter" start="7" size="1" />
+      <BitField name="DMAR" description="DMA enable receiver" start="6" size="1" />
+      <BitField name="SCEN" description="Smartcard mode enable" start="5" size="1" />
+      <BitField name="NACK" description="Smartcard NACK enable" start="4" size="1" />
+      <BitField name="HDSEL" description="Half-duplex selection" start="3" size="1" />
+      <BitField name="IRLP" description="Ir low-power" start="2" size="1" />
+      <BitField name="IREN" description="Ir mode enable" start="1" size="1" />
+      <BitField name="EIE" description="Error interrupt enable" start="0" size="1" />
+    </Register>
+    <Register name="BRR" description="Baud rate register" start="+0xC" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="BRR_4_15" description="DIV_Mantissa" start="4" size="12" />
+      <BitField name="BRR_0_3" description="DIV_Fraction" start="0" size="4" />
+    </Register>
+    <Register name="GTPR" description="Guard time and prescaler register" start="+0x10" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="GT" description="Guard time value" start="8" size="8" />
+      <BitField name="PSC" description="Prescaler value" start="0" size="8" />
+    </Register>
+    <Register name="RTOR" description="Receiver timeout register" start="+0x14" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="BLEN" description="Block Length" start="24" size="8" />
+      <BitField name="RTO" description="Receiver timeout value" start="0" size="24" />
+    </Register>
+    <Register name="RQR" description="Request register" start="+0x18" size="4" access="WriteOnly" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="TXFRQ" description="Transmit data flush request" start="4" size="1" />
+      <BitField name="RXFRQ" description="Receive data flush request" start="3" size="1" />
+      <BitField name="MMRQ" description="Mute mode request" start="2" size="1" />
+      <BitField name="SBKRQ" description="Send break request" start="1" size="1" />
+      <BitField name="ABRRQ" description="Auto baud rate request" start="0" size="1" />
+    </Register>
+    <Register name="ISR" description="Interrupt &amp; status register" start="+0x1C" size="4" access="ReadOnly" reset_value="0x00C0" reset_mask="0xFFFFFFFF">
+      <BitField name="TXFT" description="TXFIFO threshold flag" start="27" size="1" />
+      <BitField name="RXFT" description="RXFIFO threshold flag" start="26" size="1" />
+      <BitField name="TCBGT" description="Transmission complete before guard time flag" start="25" size="1" />
+      <BitField name="RXFF" description="RXFIFO Full" start="24" size="1" />
+      <BitField name="TXFE" description="TXFIFO Empty" start="23" size="1" />
+      <BitField name="REACK" description="REACK" start="22" size="1" />
+      <BitField name="TEACK" description="TEACK" start="21" size="1" />
+      <BitField name="WUF" description="WUF" start="20" size="1" />
+      <BitField name="RWU" description="RWU" start="19" size="1" />
+      <BitField name="SBKF" description="SBKF" start="18" size="1" />
+      <BitField name="CMF" description="CMF" start="17" size="1" />
+      <BitField name="BUSY" description="BUSY" start="16" size="1" />
+      <BitField name="ABRF" description="ABRF" start="15" size="1" />
+      <BitField name="ABRE" description="ABRE" start="14" size="1" />
+      <BitField name="UDR" description="SPI slave underrun error flag" start="13" size="1" />
+      <BitField name="EOBF" description="EOBF" start="12" size="1" />
+      <BitField name="RTOF" description="RTOF" start="11" size="1" />
+      <BitField name="CTS" description="CTS" start="10" size="1" />
+      <BitField name="CTSIF" description="CTSIF" start="9" size="1" />
+      <BitField name="LBDF" description="LBDF" start="8" size="1" />
+      <BitField name="TXE" description="TXE" start="7" size="1" />
+      <BitField name="TC" description="TC" start="6" size="1" />
+      <BitField name="RXNE" description="RXNE" start="5" size="1" />
+      <BitField name="IDLE" description="IDLE" start="4" size="1" />
+      <BitField name="ORE" description="ORE" start="3" size="1" />
+      <BitField name="NF" description="NF" start="2" size="1" />
+      <BitField name="FE" description="FE" start="1" size="1" />
+      <BitField name="PE" description="PE" start="0" size="1" />
+    </Register>
+    <Register name="ICR" description="Interrupt flag clear register" start="+0x20" size="4" access="WriteOnly" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="WUCF" description="Wakeup from Stop mode clear flag" start="20" size="1" />
+      <BitField name="CMCF" description="Character match clear flag" start="17" size="1" />
+      <BitField name="UDRCF" description="SPI slave underrun clear flag" start="13" size="1" />
+      <BitField name="EOBCF" description="End of block clear flag" start="12" size="1" />
+      <BitField name="RTOCF" description="Receiver timeout clear flag" start="11" size="1" />
+      <BitField name="CTSCF" description="CTS clear flag" start="9" size="1" />
+      <BitField name="LBDCF" description="LIN break detection clear flag" start="8" size="1" />
+      <BitField name="TCBGTC" description="Transmission complete before Guard time clear flag" start="7" size="1" />
+      <BitField name="TCCF" description="Transmission complete clear flag" start="6" size="1" />
+      <BitField name="TXFECF" description="TXFIFO empty clear flag" start="5" size="1" />
+      <BitField name="IDLECF" description="Idle line detected clear flag" start="4" size="1" />
+      <BitField name="ORECF" description="Overrun error clear flag" start="3" size="1" />
+      <BitField name="NCF" description="Noise detected clear flag" start="2" size="1" />
+      <BitField name="FECF" description="Framing error clear flag" start="1" size="1" />
+      <BitField name="PECF" description="Parity error clear flag" start="0" size="1" />
+    </Register>
+    <Register name="RDR" description="Receive data register" start="+0x24" size="4" access="ReadOnly" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="RDR" description="Receive data value" start="0" size="9" />
+    </Register>
+    <Register name="TDR" description="Transmit data register" start="+0x28" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="TDR" description="Transmit data value" start="0" size="9" />
+    </Register>
+    <Register name="PRESC" description="USART prescaler register" start="+0x2C" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="PRESCALER" description="Clock prescaler" start="0" size="4" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="UART9" description="Universal synchronous asynchronous receiver transmitter" start="0x40011800">
+    <Register name="CR1" description="Control register 1" start="+0x0" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="RXFFIE" description="RXFIFO Full interrupt enable" start="31" size="1" />
+      <BitField name="TXFEIE" description="TXFIFO empty interrupt enable" start="30" size="1" />
+      <BitField name="FIFOEN" description="FIFO mode enable" start="29" size="1" />
+      <BitField name="M1" description="Word length" start="28" size="1" />
+      <BitField name="EOBIE" description="End of Block interrupt enable" start="27" size="1" />
+      <BitField name="RTOIE" description="Receiver timeout interrupt enable" start="26" size="1" />
+      <BitField name="DEAT4" description="Driver Enable assertion time" start="25" size="1" />
+      <BitField name="DEAT3" description="DEAT3" start="24" size="1" />
+      <BitField name="DEAT2" description="DEAT2" start="23" size="1" />
+      <BitField name="DEAT1" description="DEAT1" start="22" size="1" />
+      <BitField name="DEAT0" description="DEAT0" start="21" size="1" />
+      <BitField name="DEDT4" description="Driver Enable de-assertion time" start="20" size="1" />
+      <BitField name="DEDT3" description="DEDT3" start="19" size="1" />
+      <BitField name="DEDT2" description="DEDT2" start="18" size="1" />
+      <BitField name="DEDT1" description="DEDT1" start="17" size="1" />
+      <BitField name="DEDT0" description="DEDT0" start="16" size="1" />
+      <BitField name="OVER8" description="Oversampling mode" start="15" size="1" />
+      <BitField name="CMIE" description="Character match interrupt enable" start="14" size="1" />
+      <BitField name="MME" description="Mute mode enable" start="13" size="1" />
+      <BitField name="M0" description="Word length" start="12" size="1" />
+      <BitField name="WAKE" description="Receiver wakeup method" start="11" size="1" />
+      <BitField name="PCE" description="Parity control enable" start="10" size="1" />
+      <BitField name="PS" description="Parity selection" start="9" size="1" />
+      <BitField name="PEIE" description="PE interrupt enable" start="8" size="1" />
+      <BitField name="TXEIE" description="interrupt enable" start="7" size="1" />
+      <BitField name="TCIE" description="Transmission complete interrupt enable" start="6" size="1" />
+      <BitField name="RXNEIE" description="RXNE interrupt enable" start="5" size="1" />
+      <BitField name="IDLEIE" description="IDLE interrupt enable" start="4" size="1" />
+      <BitField name="TE" description="Transmitter enable" start="3" size="1" />
+      <BitField name="RE" description="Receiver enable" start="2" size="1" />
+      <BitField name="UESM" description="USART enable in Stop mode" start="1" size="1" />
+      <BitField name="UE" description="USART enable" start="0" size="1" />
+    </Register>
+    <Register name="CR2" description="Control register 2" start="+0x4" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="ADD4_7" description="Address of the USART node" start="28" size="4" />
+      <BitField name="ADD0_3" description="Address of the USART node" start="24" size="4" />
+      <BitField name="RTOEN" description="Receiver timeout enable" start="23" size="1" />
+      <BitField name="ABRMOD1" description="Auto baud rate mode" start="22" size="1" />
+      <BitField name="ABRMOD0" description="ABRMOD0" start="21" size="1" />
+      <BitField name="ABREN" description="Auto baud rate enable" start="20" size="1" />
+      <BitField name="MSBFIRST" description="Most significant bit first" start="19" size="1" />
+      <BitField name="TAINV" description="Binary data inversion" start="18" size="1" />
+      <BitField name="TXINV" description="TX pin active level inversion" start="17" size="1" />
+      <BitField name="RXINV" description="RX pin active level inversion" start="16" size="1" />
+      <BitField name="SWAP" description="Swap TX/RX pins" start="15" size="1" />
+      <BitField name="LINEN" description="LIN mode enable" start="14" size="1" />
+      <BitField name="STOP" description="STOP bits" start="12" size="2" />
+      <BitField name="CLKEN" description="Clock enable" start="11" size="1" />
+      <BitField name="CPOL" description="Clock polarity" start="10" size="1" />
+      <BitField name="CPHA" description="Clock phase" start="9" size="1" />
+      <BitField name="LBCL" description="Last bit clock pulse" start="8" size="1" />
+      <BitField name="LBDIE" description="LIN break detection interrupt enable" start="6" size="1" />
+      <BitField name="LBDL" description="LIN break detection length" start="5" size="1" />
+      <BitField name="ADDM7" description="7-bit Address Detection/4-bit Address Detection" start="4" size="1" />
+      <BitField name="DIS_NSS" description="When the DSI_NSS bit is set, the NSS pin input is ignored" start="3" size="1" />
+      <BitField name="SLVEN" description="Synchronous Slave mode enable" start="0" size="1" />
+    </Register>
+    <Register name="CR3" description="Control register 3" start="+0x8" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="TXFTCFG" description="TXFIFO threshold configuration" start="29" size="3" />
+      <BitField name="RXFTIE" description="RXFIFO threshold interrupt enable" start="28" size="1" />
+      <BitField name="RXFTCFG" description="Receive FIFO threshold configuration" start="25" size="3" />
+      <BitField name="TCBGTIE" description="Transmission Complete before guard time, interrupt enable" start="24" size="1" />
+      <BitField name="TXFTIE" description="TXFIFO threshold interrupt enable" start="23" size="1" />
+      <BitField name="WUFIE" description="Wakeup from Stop mode interrupt enable" start="22" size="1" />
+      <BitField name="WUS" description="Wakeup from Stop mode interrupt flag selection" start="20" size="2" />
+      <BitField name="SCARCNT" description="Smartcard auto-retry count" start="17" size="3" />
+      <BitField name="DEP" description="Driver enable polarity selection" start="15" size="1" />
+      <BitField name="DEM" description="Driver enable mode" start="14" size="1" />
+      <BitField name="DDRE" description="DMA Disable on Reception Error" start="13" size="1" />
+      <BitField name="OVRDIS" description="Overrun Disable" start="12" size="1" />
+      <BitField name="ONEBIT" description="One sample bit method enable" start="11" size="1" />
+      <BitField name="CTSIE" description="CTS interrupt enable" start="10" size="1" />
+      <BitField name="CTSE" description="CTS enable" start="9" size="1" />
+      <BitField name="RTSE" description="RTS enable" start="8" size="1" />
+      <BitField name="DMAT" description="DMA enable transmitter" start="7" size="1" />
+      <BitField name="DMAR" description="DMA enable receiver" start="6" size="1" />
+      <BitField name="SCEN" description="Smartcard mode enable" start="5" size="1" />
+      <BitField name="NACK" description="Smartcard NACK enable" start="4" size="1" />
+      <BitField name="HDSEL" description="Half-duplex selection" start="3" size="1" />
+      <BitField name="IRLP" description="Ir low-power" start="2" size="1" />
+      <BitField name="IREN" description="Ir mode enable" start="1" size="1" />
+      <BitField name="EIE" description="Error interrupt enable" start="0" size="1" />
+    </Register>
+    <Register name="BRR" description="Baud rate register" start="+0xC" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="BRR_4_15" description="DIV_Mantissa" start="4" size="12" />
+      <BitField name="BRR_0_3" description="DIV_Fraction" start="0" size="4" />
+    </Register>
+    <Register name="GTPR" description="Guard time and prescaler register" start="+0x10" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="GT" description="Guard time value" start="8" size="8" />
+      <BitField name="PSC" description="Prescaler value" start="0" size="8" />
+    </Register>
+    <Register name="RTOR" description="Receiver timeout register" start="+0x14" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="BLEN" description="Block Length" start="24" size="8" />
+      <BitField name="RTO" description="Receiver timeout value" start="0" size="24" />
+    </Register>
+    <Register name="RQR" description="Request register" start="+0x18" size="4" access="WriteOnly" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="TXFRQ" description="Transmit data flush request" start="4" size="1" />
+      <BitField name="RXFRQ" description="Receive data flush request" start="3" size="1" />
+      <BitField name="MMRQ" description="Mute mode request" start="2" size="1" />
+      <BitField name="SBKRQ" description="Send break request" start="1" size="1" />
+      <BitField name="ABRRQ" description="Auto baud rate request" start="0" size="1" />
+    </Register>
+    <Register name="ISR" description="Interrupt &amp; status register" start="+0x1C" size="4" access="ReadOnly" reset_value="0x00C0" reset_mask="0xFFFFFFFF">
+      <BitField name="TXFT" description="TXFIFO threshold flag" start="27" size="1" />
+      <BitField name="RXFT" description="RXFIFO threshold flag" start="26" size="1" />
+      <BitField name="TCBGT" description="Transmission complete before guard time flag" start="25" size="1" />
+      <BitField name="RXFF" description="RXFIFO Full" start="24" size="1" />
+      <BitField name="TXFE" description="TXFIFO Empty" start="23" size="1" />
+      <BitField name="REACK" description="REACK" start="22" size="1" />
+      <BitField name="TEACK" description="TEACK" start="21" size="1" />
+      <BitField name="WUF" description="WUF" start="20" size="1" />
+      <BitField name="RWU" description="RWU" start="19" size="1" />
+      <BitField name="SBKF" description="SBKF" start="18" size="1" />
+      <BitField name="CMF" description="CMF" start="17" size="1" />
+      <BitField name="BUSY" description="BUSY" start="16" size="1" />
+      <BitField name="ABRF" description="ABRF" start="15" size="1" />
+      <BitField name="ABRE" description="ABRE" start="14" size="1" />
+      <BitField name="UDR" description="SPI slave underrun error flag" start="13" size="1" />
+      <BitField name="EOBF" description="EOBF" start="12" size="1" />
+      <BitField name="RTOF" description="RTOF" start="11" size="1" />
+      <BitField name="CTS" description="CTS" start="10" size="1" />
+      <BitField name="CTSIF" description="CTSIF" start="9" size="1" />
+      <BitField name="LBDF" description="LBDF" start="8" size="1" />
+      <BitField name="TXE" description="TXE" start="7" size="1" />
+      <BitField name="TC" description="TC" start="6" size="1" />
+      <BitField name="RXNE" description="RXNE" start="5" size="1" />
+      <BitField name="IDLE" description="IDLE" start="4" size="1" />
+      <BitField name="ORE" description="ORE" start="3" size="1" />
+      <BitField name="NF" description="NF" start="2" size="1" />
+      <BitField name="FE" description="FE" start="1" size="1" />
+      <BitField name="PE" description="PE" start="0" size="1" />
+    </Register>
+    <Register name="ICR" description="Interrupt flag clear register" start="+0x20" size="4" access="WriteOnly" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="WUCF" description="Wakeup from Stop mode clear flag" start="20" size="1" />
+      <BitField name="CMCF" description="Character match clear flag" start="17" size="1" />
+      <BitField name="UDRCF" description="SPI slave underrun clear flag" start="13" size="1" />
+      <BitField name="EOBCF" description="End of block clear flag" start="12" size="1" />
+      <BitField name="RTOCF" description="Receiver timeout clear flag" start="11" size="1" />
+      <BitField name="CTSCF" description="CTS clear flag" start="9" size="1" />
+      <BitField name="LBDCF" description="LIN break detection clear flag" start="8" size="1" />
+      <BitField name="TCBGTC" description="Transmission complete before Guard time clear flag" start="7" size="1" />
+      <BitField name="TCCF" description="Transmission complete clear flag" start="6" size="1" />
+      <BitField name="TXFECF" description="TXFIFO empty clear flag" start="5" size="1" />
+      <BitField name="IDLECF" description="Idle line detected clear flag" start="4" size="1" />
+      <BitField name="ORECF" description="Overrun error clear flag" start="3" size="1" />
+      <BitField name="NCF" description="Noise detected clear flag" start="2" size="1" />
+      <BitField name="FECF" description="Framing error clear flag" start="1" size="1" />
+      <BitField name="PECF" description="Parity error clear flag" start="0" size="1" />
+    </Register>
+    <Register name="RDR" description="Receive data register" start="+0x24" size="4" access="ReadOnly" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="RDR" description="Receive data value" start="0" size="9" />
+    </Register>
+    <Register name="TDR" description="Transmit data register" start="+0x28" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="TDR" description="Transmit data value" start="0" size="9" />
+    </Register>
+    <Register name="PRESC" description="USART prescaler register" start="+0x2C" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="PRESCALER" description="Clock prescaler" start="0" size="4" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="USART10" description="Universal synchronous asynchronous receiver transmitter" start="0x40011C00">
+    <Register name="CR1" description="Control register 1" start="+0x0" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="RXFFIE" description="RXFIFO Full interrupt enable" start="31" size="1" />
+      <BitField name="TXFEIE" description="TXFIFO empty interrupt enable" start="30" size="1" />
+      <BitField name="FIFOEN" description="FIFO mode enable" start="29" size="1" />
+      <BitField name="M1" description="Word length" start="28" size="1" />
+      <BitField name="EOBIE" description="End of Block interrupt enable" start="27" size="1" />
+      <BitField name="RTOIE" description="Receiver timeout interrupt enable" start="26" size="1" />
+      <BitField name="DEAT4" description="Driver Enable assertion time" start="25" size="1" />
+      <BitField name="DEAT3" description="DEAT3" start="24" size="1" />
+      <BitField name="DEAT2" description="DEAT2" start="23" size="1" />
+      <BitField name="DEAT1" description="DEAT1" start="22" size="1" />
+      <BitField name="DEAT0" description="DEAT0" start="21" size="1" />
+      <BitField name="DEDT4" description="Driver Enable de-assertion time" start="20" size="1" />
+      <BitField name="DEDT3" description="DEDT3" start="19" size="1" />
+      <BitField name="DEDT2" description="DEDT2" start="18" size="1" />
+      <BitField name="DEDT1" description="DEDT1" start="17" size="1" />
+      <BitField name="DEDT0" description="DEDT0" start="16" size="1" />
+      <BitField name="OVER8" description="Oversampling mode" start="15" size="1" />
+      <BitField name="CMIE" description="Character match interrupt enable" start="14" size="1" />
+      <BitField name="MME" description="Mute mode enable" start="13" size="1" />
+      <BitField name="M0" description="Word length" start="12" size="1" />
+      <BitField name="WAKE" description="Receiver wakeup method" start="11" size="1" />
+      <BitField name="PCE" description="Parity control enable" start="10" size="1" />
+      <BitField name="PS" description="Parity selection" start="9" size="1" />
+      <BitField name="PEIE" description="PE interrupt enable" start="8" size="1" />
+      <BitField name="TXEIE" description="interrupt enable" start="7" size="1" />
+      <BitField name="TCIE" description="Transmission complete interrupt enable" start="6" size="1" />
+      <BitField name="RXNEIE" description="RXNE interrupt enable" start="5" size="1" />
+      <BitField name="IDLEIE" description="IDLE interrupt enable" start="4" size="1" />
+      <BitField name="TE" description="Transmitter enable" start="3" size="1" />
+      <BitField name="RE" description="Receiver enable" start="2" size="1" />
+      <BitField name="UESM" description="USART enable in Stop mode" start="1" size="1" />
+      <BitField name="UE" description="USART enable" start="0" size="1" />
+    </Register>
+    <Register name="CR2" description="Control register 2" start="+0x4" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="ADD4_7" description="Address of the USART node" start="28" size="4" />
+      <BitField name="ADD0_3" description="Address of the USART node" start="24" size="4" />
+      <BitField name="RTOEN" description="Receiver timeout enable" start="23" size="1" />
+      <BitField name="ABRMOD1" description="Auto baud rate mode" start="22" size="1" />
+      <BitField name="ABRMOD0" description="ABRMOD0" start="21" size="1" />
+      <BitField name="ABREN" description="Auto baud rate enable" start="20" size="1" />
+      <BitField name="MSBFIRST" description="Most significant bit first" start="19" size="1" />
+      <BitField name="TAINV" description="Binary data inversion" start="18" size="1" />
+      <BitField name="TXINV" description="TX pin active level inversion" start="17" size="1" />
+      <BitField name="RXINV" description="RX pin active level inversion" start="16" size="1" />
+      <BitField name="SWAP" description="Swap TX/RX pins" start="15" size="1" />
+      <BitField name="LINEN" description="LIN mode enable" start="14" size="1" />
+      <BitField name="STOP" description="STOP bits" start="12" size="2" />
+      <BitField name="CLKEN" description="Clock enable" start="11" size="1" />
+      <BitField name="CPOL" description="Clock polarity" start="10" size="1" />
+      <BitField name="CPHA" description="Clock phase" start="9" size="1" />
+      <BitField name="LBCL" description="Last bit clock pulse" start="8" size="1" />
+      <BitField name="LBDIE" description="LIN break detection interrupt enable" start="6" size="1" />
+      <BitField name="LBDL" description="LIN break detection length" start="5" size="1" />
+      <BitField name="ADDM7" description="7-bit Address Detection/4-bit Address Detection" start="4" size="1" />
+      <BitField name="DIS_NSS" description="When the DSI_NSS bit is set, the NSS pin input is ignored" start="3" size="1" />
+      <BitField name="SLVEN" description="Synchronous Slave mode enable" start="0" size="1" />
+    </Register>
+    <Register name="CR3" description="Control register 3" start="+0x8" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="TXFTCFG" description="TXFIFO threshold configuration" start="29" size="3" />
+      <BitField name="RXFTIE" description="RXFIFO threshold interrupt enable" start="28" size="1" />
+      <BitField name="RXFTCFG" description="Receive FIFO threshold configuration" start="25" size="3" />
+      <BitField name="TCBGTIE" description="Transmission Complete before guard time, interrupt enable" start="24" size="1" />
+      <BitField name="TXFTIE" description="TXFIFO threshold interrupt enable" start="23" size="1" />
+      <BitField name="WUFIE" description="Wakeup from Stop mode interrupt enable" start="22" size="1" />
+      <BitField name="WUS" description="Wakeup from Stop mode interrupt flag selection" start="20" size="2" />
+      <BitField name="SCARCNT" description="Smartcard auto-retry count" start="17" size="3" />
+      <BitField name="DEP" description="Driver enable polarity selection" start="15" size="1" />
+      <BitField name="DEM" description="Driver enable mode" start="14" size="1" />
+      <BitField name="DDRE" description="DMA Disable on Reception Error" start="13" size="1" />
+      <BitField name="OVRDIS" description="Overrun Disable" start="12" size="1" />
+      <BitField name="ONEBIT" description="One sample bit method enable" start="11" size="1" />
+      <BitField name="CTSIE" description="CTS interrupt enable" start="10" size="1" />
+      <BitField name="CTSE" description="CTS enable" start="9" size="1" />
+      <BitField name="RTSE" description="RTS enable" start="8" size="1" />
+      <BitField name="DMAT" description="DMA enable transmitter" start="7" size="1" />
+      <BitField name="DMAR" description="DMA enable receiver" start="6" size="1" />
+      <BitField name="SCEN" description="Smartcard mode enable" start="5" size="1" />
+      <BitField name="NACK" description="Smartcard NACK enable" start="4" size="1" />
+      <BitField name="HDSEL" description="Half-duplex selection" start="3" size="1" />
+      <BitField name="IRLP" description="Ir low-power" start="2" size="1" />
+      <BitField name="IREN" description="Ir mode enable" start="1" size="1" />
+      <BitField name="EIE" description="Error interrupt enable" start="0" size="1" />
+    </Register>
+    <Register name="BRR" description="Baud rate register" start="+0xC" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="BRR_4_15" description="DIV_Mantissa" start="4" size="12" />
+      <BitField name="BRR_0_3" description="DIV_Fraction" start="0" size="4" />
+    </Register>
+    <Register name="GTPR" description="Guard time and prescaler register" start="+0x10" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="GT" description="Guard time value" start="8" size="8" />
+      <BitField name="PSC" description="Prescaler value" start="0" size="8" />
+    </Register>
+    <Register name="RTOR" description="Receiver timeout register" start="+0x14" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="BLEN" description="Block Length" start="24" size="8" />
+      <BitField name="RTO" description="Receiver timeout value" start="0" size="24" />
+    </Register>
+    <Register name="RQR" description="Request register" start="+0x18" size="4" access="WriteOnly" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="TXFRQ" description="Transmit data flush request" start="4" size="1" />
+      <BitField name="RXFRQ" description="Receive data flush request" start="3" size="1" />
+      <BitField name="MMRQ" description="Mute mode request" start="2" size="1" />
+      <BitField name="SBKRQ" description="Send break request" start="1" size="1" />
+      <BitField name="ABRRQ" description="Auto baud rate request" start="0" size="1" />
+    </Register>
+    <Register name="ISR" description="Interrupt &amp; status register" start="+0x1C" size="4" access="ReadOnly" reset_value="0x00C0" reset_mask="0xFFFFFFFF">
+      <BitField name="TXFT" description="TXFIFO threshold flag" start="27" size="1" />
+      <BitField name="RXFT" description="RXFIFO threshold flag" start="26" size="1" />
+      <BitField name="TCBGT" description="Transmission complete before guard time flag" start="25" size="1" />
+      <BitField name="RXFF" description="RXFIFO Full" start="24" size="1" />
+      <BitField name="TXFE" description="TXFIFO Empty" start="23" size="1" />
+      <BitField name="REACK" description="REACK" start="22" size="1" />
+      <BitField name="TEACK" description="TEACK" start="21" size="1" />
+      <BitField name="WUF" description="WUF" start="20" size="1" />
+      <BitField name="RWU" description="RWU" start="19" size="1" />
+      <BitField name="SBKF" description="SBKF" start="18" size="1" />
+      <BitField name="CMF" description="CMF" start="17" size="1" />
+      <BitField name="BUSY" description="BUSY" start="16" size="1" />
+      <BitField name="ABRF" description="ABRF" start="15" size="1" />
+      <BitField name="ABRE" description="ABRE" start="14" size="1" />
+      <BitField name="UDR" description="SPI slave underrun error flag" start="13" size="1" />
+      <BitField name="EOBF" description="EOBF" start="12" size="1" />
+      <BitField name="RTOF" description="RTOF" start="11" size="1" />
+      <BitField name="CTS" description="CTS" start="10" size="1" />
+      <BitField name="CTSIF" description="CTSIF" start="9" size="1" />
+      <BitField name="LBDF" description="LBDF" start="8" size="1" />
+      <BitField name="TXE" description="TXE" start="7" size="1" />
+      <BitField name="TC" description="TC" start="6" size="1" />
+      <BitField name="RXNE" description="RXNE" start="5" size="1" />
+      <BitField name="IDLE" description="IDLE" start="4" size="1" />
+      <BitField name="ORE" description="ORE" start="3" size="1" />
+      <BitField name="NF" description="NF" start="2" size="1" />
+      <BitField name="FE" description="FE" start="1" size="1" />
+      <BitField name="PE" description="PE" start="0" size="1" />
+    </Register>
+    <Register name="ICR" description="Interrupt flag clear register" start="+0x20" size="4" access="WriteOnly" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="WUCF" description="Wakeup from Stop mode clear flag" start="20" size="1" />
+      <BitField name="CMCF" description="Character match clear flag" start="17" size="1" />
+      <BitField name="UDRCF" description="SPI slave underrun clear flag" start="13" size="1" />
+      <BitField name="EOBCF" description="End of block clear flag" start="12" size="1" />
+      <BitField name="RTOCF" description="Receiver timeout clear flag" start="11" size="1" />
+      <BitField name="CTSCF" description="CTS clear flag" start="9" size="1" />
+      <BitField name="LBDCF" description="LIN break detection clear flag" start="8" size="1" />
+      <BitField name="TCBGTC" description="Transmission complete before Guard time clear flag" start="7" size="1" />
+      <BitField name="TCCF" description="Transmission complete clear flag" start="6" size="1" />
+      <BitField name="TXFECF" description="TXFIFO empty clear flag" start="5" size="1" />
+      <BitField name="IDLECF" description="Idle line detected clear flag" start="4" size="1" />
+      <BitField name="ORECF" description="Overrun error clear flag" start="3" size="1" />
+      <BitField name="NCF" description="Noise detected clear flag" start="2" size="1" />
+      <BitField name="FECF" description="Framing error clear flag" start="1" size="1" />
+      <BitField name="PECF" description="Parity error clear flag" start="0" size="1" />
+    </Register>
+    <Register name="RDR" description="Receive data register" start="+0x24" size="4" access="ReadOnly" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="RDR" description="Receive data value" start="0" size="9" />
+    </Register>
+    <Register name="TDR" description="Transmit data register" start="+0x28" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="TDR" description="Transmit data value" start="0" size="9" />
+    </Register>
+    <Register name="PRESC" description="USART prescaler register" start="+0x2C" size="4" access="Read/Write" reset_value="0x0000" reset_mask="0xFFFFFFFF">
+      <BitField name="PRESCALER" description="Clock prescaler" start="0" size="4" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="VREFBUF" description="VREFBUF" start="0x58003C00">
+    <Register name="CSR" description="VREFBUF control and status register" start="+0x0" size="4" reset_value="0x00000002" reset_mask="0xFFFFFFFF">
+      <BitField name="ENVR" description="Voltage reference buffer mode enable This bit is used to enable the voltage reference buffer mode." start="0" size="1" access="Read/Write" />
+      <BitField name="HIZ" description="High impedance mode This bit controls the analog switch to connect or not the VREF+ pin. Refer to Table196: VREF buffer modes for the mode descriptions depending on ENVR bit configuration." start="1" size="1" access="Read/Write" />
+      <BitField name="VRR" description="Voltage reference buffer ready" start="3" size="1" access="ReadOnly" />
+      <BitField name="VRS" description="Voltage reference scale These bits select the value generated by the voltage reference buffer. Other: Reserved" start="4" size="3" access="Read/Write" />
+    </Register>
+    <Register name="CCR" description="VREFBUF calibration control register" start="+0x4" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="TRIM" description="Trimming code These bits are automatically initialized after reset with the trimming value stored in the Flash memory during the production test. Writing into these bits allows to tune the internal reference buffer voltage." start="0" size="6" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="WWDG1" description="WWDG" start="0x50003000">
+    <Register name="CR" description="Control register" start="+0x0" size="4" access="Read/Write" reset_value="0x0000007F" reset_mask="0xFFFFFFFF">
+      <BitField name="T" description="7-bit counter (MSB to LSB) These bits contain the value of the watchdog counter. It is decremented every (4096 x 2WDGTB[1:0]) PCLK cycles. A reset is produced when it is decremented from 0x40 to 0x3F (T6 becomes cleared)." start="0" size="7" />
+      <BitField name="WDGA" description="Activation bit This bit is set by software and only cleared by hardware after a reset. When WDGA=1, the watchdog can generate a reset." start="7" size="1" />
+    </Register>
+    <Register name="CFR" description="Configuration register" start="+0x4" size="4" access="Read/Write" reset_value="0x0000007F" reset_mask="0xFFFFFFFF">
+      <BitField name="W" description="7-bit window value These bits contain the window value to be compared to the downcounter." start="0" size="7" />
+      <BitField name="WDGTB" description="Timer base The time base of the prescaler can be modified as follows:" start="11" size="2" />
+      <BitField name="EWI" description="Early wakeup interrupt When set, an interrupt occurs whenever the counter reaches the value 0x40. This interrupt is only cleared by hardware after a reset." start="9" size="1" />
+    </Register>
+    <Register name="SR" description="Status register" start="+0x8" size="4" access="Read/Write" reset_value="0x00000000" reset_mask="0xFFFFFFFF">
+      <BitField name="EWIF" description="Early wakeup interrupt flag This bit is set by hardware when the counter has reached the value 0x40. It must be cleared by software by writing 0. A write of 1 has no effect. This bit is also set if the interrupt is not enabled." start="0" size="1" />
+    </Register>
+  </RegisterGroup>
+  <RegisterGroup name="SysTick" start="0xE000E010" description="24-bit System Timer">
+    <Register name="SYST_CSR" start="0xE000E010" description="SysTick Control and Status Register">
+      <BitField start="0" size="1" name="ENABLE" description="Enable SysTick Timer" />
+      <BitField start="1" size="1" name="TICKINT" description="Tick Interrupt Enable" />
+      <BitField start="2" size="1" name="CLKSOURCE" description="Timer Clock Source" />
+      <BitField start="16" size="1" name="COUNTFLAG" description="Counter Flag" />
+    </Register>
+    <Register name="SYST_RVR" start="0xE000E014" description="SysTick Reload Value Register">
+      <BitField start="0" size="24" name="RELOAD" description="Value to load into the SYST_CVR when the counter is enabled and when it reaches 0" />
+    </Register>
+    <Register name="SYST_CVR" start="0xE000E018" description="SysTick Current Value Register Register">
+      <BitField start="0" size="24" name="CURRENT" description="The current value of the SysTick counter" />
+    </Register>
+    <Register name="SYST_CALIB" start="0xE000E01C" description="SysTick Calibration Value Register" access="ReadOnly">
+      <BitField start="0" size="24" name="TENMS" description="Reload value for 10ms (100Hz) timing, subject to system clock skew errors" />
+      <BitField start="30" size="1" name="SKEW" description="Indicates whether the TENMS value is exact" />
+      <BitField start="31" size="1" name="NOREF" description="Indicates whether the device provides a reference clock to the processor" />
+    </Register>
+  </RegisterGroup>
+</Processor>
Index: /ctrl/firmware/Main/SES/STM32H7xx/Source/stm32h723xx_Vectors.s
===================================================================
--- /ctrl/firmware/Main/SES/STM32H7xx/Source/stm32h723xx_Vectors.s	(revision 10)
+++ /ctrl/firmware/Main/SES/STM32H7xx/Source/stm32h723xx_Vectors.s	(revision 10)
@@ -0,0 +1,396 @@
+/*********************************************************************
+*                    SEGGER Microcontroller GmbH                     *
+*                        The Embedded Experts                        *
+**********************************************************************
+*                                                                    *
+*            (c) 2014 - 2024 SEGGER Microcontroller GmbH             *
+*                                                                    *
+*       www.segger.com     Support: support@segger.com               *
+*                                                                    *
+**********************************************************************
+*                                                                    *
+* All rights reserved.                                               *
+*                                                                    *
+* Redistribution and use in source and binary forms, with or         *
+* without modification, are permitted provided that the following    *
+* condition is met:                                                  *
+*                                                                    *
+* - Redistributions of source code must retain the above copyright   *
+*   notice, this condition and the following disclaimer.             *
+*                                                                    *
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND             *
+* CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,        *
+* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF           *
+* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE           *
+* DISCLAIMED. IN NO EVENT SHALL SEGGER Microcontroller BE LIABLE FOR *
+* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR           *
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT  *
+* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;    *
+* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF      *
+* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT          *
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE  *
+* USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH   *
+* DAMAGE.                                                            *
+*                                                                    *
+**********************************************************************
+
+-------------------------- END-OF-HEADER -----------------------------
+
+File      : stm32h723xx_Vectors.s
+Purpose   : Exception and interrupt vectors for stm32h723xx devices.
+
+Additional information:
+  Preprocessor Definitions
+    __NO_EXTERNAL_INTERRUPTS
+      If defined,
+        the vector table will contain only the internal exceptions
+        and interrupts.
+    __VECTORS_IN_RAM
+      If defined,
+        an area of RAM, large enough to store the vector table,
+        will be reserved.
+
+    __OPTIMIZATION_SMALL
+      If defined,
+        all weak definitions of interrupt handlers will share the
+        same implementation.
+      If not defined,
+        all weak definitions of interrupt handlers will be defined
+        with their own implementation.
+*/
+        .syntax unified
+
+/*********************************************************************
+*
+*       Macros
+*
+**********************************************************************
+*/
+
+//
+// Directly place a vector (word) in the vector table
+//
+.macro VECTOR Name=
+        .section .vectors, "ax"
+        .code 16
+        .word \Name
+.endm
+
+//
+// Declare an exception handler with a weak definition
+//
+.macro EXC_HANDLER Name=
+        //
+        // Insert vector in vector table
+        //
+        .section .vectors, "ax"
+        .word \Name
+        //
+        // Insert dummy handler in init section
+        //
+        .section .init.\Name, "ax"
+        .thumb_func
+        .weak \Name
+        .balign 2
+\Name:
+        1: b 1b   // Endless loop
+.endm
+
+//
+// Declare an interrupt handler with a weak definition
+//
+.macro ISR_HANDLER Name=
+        //
+        // Insert vector in vector table
+        //
+        .section .vectors, "ax"
+        .word \Name
+        //
+        // Insert dummy handler in init section
+        //
+#if defined(__OPTIMIZATION_SMALL)
+        .section .init, "ax"
+        .weak \Name
+        .thumb_set \Name,Dummy_Handler
+#else
+        .section .init.\Name, "ax"
+        .thumb_func
+        .weak \Name
+        .balign 2
+\Name:
+        1: b 1b   // Endless loop
+#endif
+.endm
+
+//
+// Place a reserved vector in vector table
+//
+.macro ISR_RESERVED
+        .section .vectors, "ax"
+        .word 0
+.endm
+
+//
+// Place a reserved vector in vector table
+//
+.macro ISR_RESERVED_DUMMY
+        .section .vectors, "ax"
+        .word Dummy_Handler
+.endm
+
+/*********************************************************************
+*
+*       Externals
+*
+**********************************************************************
+*/
+        .extern __stack_end__
+        .extern Reset_Handler
+        .extern HardFault_Handler
+
+/*********************************************************************
+*
+*       Global functions
+*
+**********************************************************************
+*/
+
+/*********************************************************************
+*
+*  Setup of the vector table and weak definition of interrupt handlers
+*
+*/
+        .section .vectors, "ax"
+        .code 16
+        .balign 1024
+        .global _vectors
+_vectors:
+        //
+        // Internal exceptions and interrupts
+        //
+        VECTOR __stack_end__
+        VECTOR Reset_Handler
+        EXC_HANDLER NMI_Handler
+        VECTOR HardFault_Handler
+#ifdef __ARM_ARCH_6M__
+        ISR_RESERVED
+        ISR_RESERVED
+        ISR_RESERVED
+#else
+        EXC_HANDLER MemManage_Handler
+        EXC_HANDLER BusFault_Handler
+        EXC_HANDLER UsageFault_Handler
+#endif
+        ISR_RESERVED
+        ISR_RESERVED
+        ISR_RESERVED
+        ISR_RESERVED
+        EXC_HANDLER SVC_Handler
+#ifdef __ARM_ARCH_6M__
+        ISR_RESERVED
+#else
+        EXC_HANDLER DebugMon_Handler
+#endif
+        ISR_RESERVED
+        EXC_HANDLER PendSV_Handler
+        EXC_HANDLER SysTick_Handler
+        //
+        // External interrupts
+        //
+#ifndef __NO_EXTERNAL_INTERRUPTS
+        ISR_HANDLER WWDG_IRQHandler
+        ISR_HANDLER PVD_AVD_IRQHandler
+        ISR_HANDLER TAMP_STAMP_IRQHandler
+        ISR_HANDLER RTC_WKUP_IRQHandler
+        ISR_HANDLER FLASH_IRQHandler
+        ISR_HANDLER RCC_IRQHandler
+        ISR_HANDLER EXTI0_IRQHandler
+        ISR_HANDLER EXTI1_IRQHandler
+        ISR_HANDLER EXTI2_IRQHandler
+        ISR_HANDLER EXTI3_IRQHandler
+        ISR_HANDLER EXTI4_IRQHandler
+        ISR_HANDLER DMA1_Stream0_IRQHandler
+        ISR_HANDLER DMA1_Stream1_IRQHandler
+        ISR_HANDLER DMA1_Stream2_IRQHandler
+        ISR_HANDLER DMA1_Stream3_IRQHandler
+        ISR_HANDLER DMA1_Stream4_IRQHandler
+        ISR_HANDLER DMA1_Stream5_IRQHandler
+        ISR_HANDLER DMA1_Stream6_IRQHandler
+        ISR_HANDLER ADC_IRQHandler
+        ISR_HANDLER FDCAN1_IT0_IRQHandler
+        ISR_HANDLER FDCAN2_IT0_IRQHandler
+        ISR_HANDLER FDCAN1_IT1_IRQHandler
+        ISR_HANDLER FDCAN2_IT1_IRQHandler
+        ISR_HANDLER EXTI9_5_IRQHandler
+        ISR_HANDLER TIM1_BRK_IRQHandler
+        ISR_HANDLER TIM1_UP_IRQHandler
+        ISR_HANDLER TIM1_TRG_COM_IRQHandler
+        ISR_HANDLER TIM1_CC_IRQHandler
+        ISR_HANDLER TIM2_IRQHandler
+        ISR_HANDLER TIM3_IRQHandler
+        ISR_HANDLER TIM4_IRQHandler
+        ISR_HANDLER I2C1_EV_IRQHandler
+        ISR_HANDLER I2C1_ER_IRQHandler
+        ISR_HANDLER I2C2_EV_IRQHandler
+        ISR_HANDLER I2C2_ER_IRQHandler
+        ISR_HANDLER SPI1_IRQHandler
+        ISR_HANDLER SPI2_IRQHandler
+        ISR_HANDLER USART1_IRQHandler
+        ISR_HANDLER USART2_IRQHandler
+        ISR_HANDLER USART3_IRQHandler
+        ISR_HANDLER EXTI15_10_IRQHandler
+        ISR_HANDLER RTC_Alarm_IRQHandler
+        ISR_RESERVED
+        ISR_HANDLER TIM8_BRK_TIM12_IRQHandler
+        ISR_HANDLER TIM8_UP_TIM13_IRQHandler
+        ISR_HANDLER TIM8_TRG_COM_TIM14_IRQHandler
+        ISR_HANDLER TIM8_CC_IRQHandler
+        ISR_HANDLER DMA1_Stream7_IRQHandler
+        ISR_HANDLER FMC_IRQHandler
+        ISR_HANDLER SDMMC1_IRQHandler
+        ISR_HANDLER TIM5_IRQHandler
+        ISR_HANDLER SPI3_IRQHandler
+        ISR_HANDLER UART4_IRQHandler
+        ISR_HANDLER UART5_IRQHandler
+        ISR_HANDLER TIM6_DAC_IRQHandler
+        ISR_HANDLER TIM7_IRQHandler
+        ISR_HANDLER DMA2_Stream0_IRQHandler
+        ISR_HANDLER DMA2_Stream1_IRQHandler
+        ISR_HANDLER DMA2_Stream2_IRQHandler
+        ISR_HANDLER DMA2_Stream3_IRQHandler
+        ISR_HANDLER DMA2_Stream4_IRQHandler
+        ISR_HANDLER ETH_IRQHandler
+        ISR_HANDLER ETH_WKUP_IRQHandler
+        ISR_HANDLER FDCAN_CAL_IRQHandler
+        ISR_RESERVED
+        ISR_RESERVED
+        ISR_RESERVED
+        ISR_RESERVED
+        ISR_HANDLER DMA2_Stream5_IRQHandler
+        ISR_HANDLER DMA2_Stream6_IRQHandler
+        ISR_HANDLER DMA2_Stream7_IRQHandler
+        ISR_HANDLER USART6_IRQHandler
+        ISR_HANDLER I2C3_EV_IRQHandler
+        ISR_HANDLER I2C3_ER_IRQHandler
+        ISR_HANDLER OTG_HS_EP1_OUT_IRQHandler
+        ISR_HANDLER OTG_HS_EP1_IN_IRQHandler
+        ISR_HANDLER OTG_HS_WKUP_IRQHandler
+        ISR_HANDLER OTG_HS_IRQHandler
+        ISR_HANDLER DCMI_PSSI_IRQHandler
+        ISR_RESERVED
+        ISR_HANDLER RNG_IRQHandler
+        ISR_HANDLER FPU_IRQHandler
+        ISR_HANDLER UART7_IRQHandler
+        ISR_HANDLER UART8_IRQHandler
+        ISR_HANDLER SPI4_IRQHandler
+        ISR_HANDLER SPI5_IRQHandler
+        ISR_HANDLER SPI6_IRQHandler
+        ISR_HANDLER SAI1_IRQHandler
+        ISR_HANDLER LTDC_IRQHandler
+        ISR_HANDLER LTDC_ER_IRQHandler
+        ISR_HANDLER DMA2D_IRQHandler
+        ISR_RESERVED
+        ISR_HANDLER OCTOSPI1_IRQHandler
+        ISR_HANDLER LPTIM1_IRQHandler
+        ISR_HANDLER CEC_IRQHandler
+        ISR_HANDLER I2C4_EV_IRQHandler
+        ISR_HANDLER I2C4_ER_IRQHandler
+        ISR_HANDLER SPDIF_RX_IRQHandler
+        ISR_RESERVED
+        ISR_RESERVED
+        ISR_RESERVED
+        ISR_RESERVED
+        ISR_HANDLER DMAMUX1_OVR_IRQHandler
+        ISR_RESERVED
+        ISR_RESERVED
+        ISR_RESERVED
+        ISR_RESERVED
+        ISR_RESERVED
+        ISR_RESERVED
+        ISR_RESERVED
+        ISR_HANDLER DFSDM1_FLT0_IRQHandler
+        ISR_HANDLER DFSDM1_FLT1_IRQHandler
+        ISR_HANDLER DFSDM1_FLT2_IRQHandler
+        ISR_HANDLER DFSDM1_FLT3_IRQHandler
+        ISR_RESERVED
+        ISR_HANDLER SWPMI1_IRQHandler
+        ISR_HANDLER TIM15_IRQHandler
+        ISR_HANDLER TIM16_IRQHandler
+        ISR_HANDLER TIM17_IRQHandler
+        ISR_HANDLER MDIOS_WKUP_IRQHandler
+        ISR_HANDLER MDIOS_IRQHandler
+        ISR_RESERVED
+        ISR_HANDLER MDMA_IRQHandler
+        ISR_RESERVED
+        ISR_HANDLER SDMMC2_IRQHandler
+        ISR_HANDLER HSEM1_IRQHandler
+        ISR_RESERVED
+        ISR_HANDLER ADC3_IRQHandler
+        ISR_HANDLER DMAMUX2_OVR_IRQHandler
+        ISR_HANDLER BDMA_Channel0_IRQHandler
+        ISR_HANDLER BDMA_Channel1_IRQHandler
+        ISR_HANDLER BDMA_Channel2_IRQHandler
+        ISR_HANDLER BDMA_Channel3_IRQHandler
+        ISR_HANDLER BDMA_Channel4_IRQHandler
+        ISR_HANDLER BDMA_Channel5_IRQHandler
+        ISR_HANDLER BDMA_Channel6_IRQHandler
+        ISR_HANDLER BDMA_Channel7_IRQHandler
+        ISR_HANDLER COMP1_IRQHandler
+        ISR_HANDLER LPTIM2_IRQHandler
+        ISR_HANDLER LPTIM3_IRQHandler
+        ISR_HANDLER LPTIM4_IRQHandler
+        ISR_HANDLER LPTIM5_IRQHandler
+        ISR_HANDLER LPUART1_IRQHandler
+        ISR_RESERVED
+        ISR_HANDLER CRS_IRQHandler
+        ISR_HANDLER ECC_IRQHandler
+        ISR_HANDLER SAI4_IRQHandler
+        ISR_HANDLER DTS_IRQHandler
+        ISR_RESERVED
+        ISR_HANDLER WAKEUP_PIN_IRQHandler
+        ISR_HANDLER OCTOSPI2_IRQHandler
+        ISR_RESERVED
+        ISR_RESERVED
+        ISR_HANDLER FMAC_IRQHandler
+        ISR_HANDLER CORDIC_IRQHandler
+        ISR_HANDLER UART9_IRQHandler
+        ISR_HANDLER USART10_IRQHandler
+        ISR_HANDLER I2C5_EV_IRQHandler
+        ISR_HANDLER I2C5_ER_IRQHandler
+        ISR_HANDLER FDCAN3_IT0_IRQHandler
+        ISR_HANDLER FDCAN3_IT1_IRQHandler
+        ISR_HANDLER TIM23_IRQHandler
+        ISR_HANDLER TIM24_IRQHandler
+#endif
+        //
+        .section .vectors, "ax"
+_vectors_end:
+
+#ifdef __VECTORS_IN_RAM
+        //
+        // Reserve space with the size of the vector table
+        // in the designated RAM section.
+        //
+        .section .vectors_ram, "ax"
+        .balign 1024
+        .global _vectors_ram
+
+_vectors_ram:
+        .space _vectors_end - _vectors, 0
+#endif
+
+/*********************************************************************
+*
+*  Dummy handler to be used for reserved interrupt vectors
+*  and weak implementation of interrupts.
+*
+*/
+        .section .init.Dummy_Handler, "ax"
+        .thumb_func
+        .weak Dummy_Handler
+        .balign 2
+Dummy_Handler:
+        1: b 1b   // Endless loop
+
+
+/*************************** End of file ****************************/
Index: /ctrl/firmware/Main/SES/Setup/SEGGER_Flash.icf
===================================================================
--- /ctrl/firmware/Main/SES/Setup/SEGGER_Flash.icf	(revision 10)
+++ /ctrl/firmware/Main/SES/Setup/SEGGER_Flash.icf	(revision 10)
@@ -0,0 +1,129 @@
+/*********************************************************************
+*                    SEGGER Microcontroller GmbH                     *
+*                        The Embedded Experts                        *
+**********************************************************************
+*                                                                    *
+*            (c) 2014 - 2024 SEGGER Microcontroller GmbH             *
+*                                                                    *
+*       www.segger.com     Support: support@segger.com               *
+*                                                                    *
+**********************************************************************
+*                                                                    *
+* All rights reserved.                                               *
+*                                                                    *
+* Redistribution and use in source and binary forms, with or         *
+* without modification, are permitted provided that the following    *
+* condition is met:                                                  *
+*                                                                    *
+* - Redistributions of source code must retain the above copyright   *
+*   notice, this condition and the following disclaimer.             *
+*                                                                    *
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND             *
+* CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,        *
+* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF           *
+* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE           *
+* DISCLAIMED. IN NO EVENT SHALL SEGGER Microcontroller BE LIABLE FOR *
+* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR           *
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT  *
+* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;    *
+* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF      *
+* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT          *
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE  *
+* USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH   *
+* DAMAGE.                                                            *
+*                                                                    *
+**********************************************************************
+-------------------------- END-OF-HEADER -----------------------------
+
+File    : SEGGER_Flash.icf
+Purpose : Generic linker script for application placement in Flash,
+          for use with the SEGGER Linker.
+Literature:
+  [1]  SEGGER Linker User Guide (https://www.segger.com/doc/UM20005_Linker.html)
+  [2]  SEGGER Linker Section Placement (https://wiki.segger.com/SEGGER_Linker_Script_Files)
+*/
+
+define memory with size = 4G;
+
+//
+// Combined regions per memory type
+//
+define region FLASH = FLASH1;
+define region RAM   = RAM1;
+
+//
+// Block definitions
+//
+define block vectors                        { section .vectors };                                   // Vector table section
+define block vectors_ram                    { section .vectors_ram };                               // Vector table section
+define block ctors                          { section .ctors,     section .ctors.*, block with         alphabetical order { init_array } };
+define block dtors                          { section .dtors,     section .dtors.*, block with reverse alphabetical order { fini_array } };
+define block exidx                          { section .ARM.exidx, section .ARM.exidx.* };
+define block tbss                           { section .tbss,      section .tbss.*  };
+define block tdata                          { section .tdata,     section .tdata.* };
+define block tls with fixed order           { block tbss, block tdata };
+define block tdata_load                     { copy of block tdata };
+define block heap           with auto size = __HEAPSIZE__,  alignment = 8, /* fill =0x00, */ readwrite access { };
+define block stack          with      size = __STACKSIZE__, alignment = 8, /* fill =0xCD, */ readwrite access { };
+define block stack_process  with      size = __STACKSIZE_PROCESS__, alignment = 8, /* fill =0xCD, */ readwrite access { };
+//
+// Explicit initialization settings for sections
+// Packing options for initialize by copy: packing=auto/lzss/zpak/packbits
+//
+do not initialize                           { section .non_init, section .non_init.*, section .*.non_init, section .*.non_init.* };
+do not initialize                           { section .no_init, section .no_init.*, section .*.no_init, section .*.no_init.* };   // Legacy sections, kept for backwards compatibility
+do not initialize                           { section .noinit, section .noinit.*, section .*.noinit, section .*.noinit.* };       // Legacy sections, used by some SDKs/HALs
+do not initialize                           { block vectors_ram };
+initialize by copy with packing=auto        { section .data, section .data.*, section .*.data, section .*.data.* };               // Static data sections
+initialize by copy with packing=auto        { section .fast, section .fast.*, section .*.fast, section .*.fast.* };               // "RAM Code" sections
+
+initialize by calling __SEGGER_STOP_X_InitLimits    { section .data.stop.* };
+
+#define USES_ALLOC_FUNC                                   \
+  linked symbol malloc || linked symbol aligned_alloc ||  \
+  linked symbol calloc || linked symbol realloc
+
+initialize by calling __SEGGER_init_heap if USES_ALLOC_FUNC { block heap };                        // Init the heap if one is required
+initialize by calling __SEGGER_init_ctors    { block ctors };                                      // Call constructors for global objects which need to be constructed before reaching main (if any). Make sure this is done after setting up heap.
+
+//assert with warning "free() linked into application but there are no calls to an allocation function!" {
+//  linked symbol free => USES_ALLOC_FUNC
+//};
+
+assert with error "heap is too small!"              { USES_ALLOC_FUNC => size  of block heap >= 48 };
+assert with error "heap size not a multiple of 8!"  { USES_ALLOC_FUNC => size  of block heap % 8 == 0 };
+assert with error "heap not correctly aligned!"     { USES_ALLOC_FUNC => start of block heap % 8 == 0 };
+
+
+//
+// Explicit placement in FLASHn
+//
+place in FLASH1                             { section .FLASH1, section .FLASH1.* };
+//
+// FLASH Placement
+//
+place at start of FLASH                     { block vectors };                                      // Vector table section
+place in FLASH with minimum size order      { block tdata_load,                                     // Thread-local-storage load image
+                                              block exidx,                                          // ARM exception unwinding block
+                                              block ctors,                                          // Constructors block
+                                              block dtors,                                          // Destructors block
+                                              readonly,                                             // Catch-all for readonly data (e.g. .rodata, .srodata)
+                                              readexec                                              // Catch-all for (readonly) executable code (e.g. .text)
+                                            };
+
+//
+// Explicit placement in RAMn
+//
+place in RAM1                               { section .RAM1, section .RAM1.* };
+//
+// RAM Placement
+//
+place at start of RAM                       { block vectors_ram };
+place in RAM with auto order                { section .fast, section .fast.*,                       // "ramfunc" section
+                                              block tls,                                            // Thread-local-storage block
+                                              readwrite,                                            // Catch-all for initialized/uninitialized data sections (e.g. .data, .noinit)
+                                              zeroinit                                              // Catch-all for zero-initialized data sections (e.g. .bss)
+                                            };
+place in RAM                                { block heap };                                         // Heap reserved block
+place at end of RAM with fixed order        { block stack_process, 
+                                              block stack };                                        // Stack reserved block at the end
Index: /ctrl/firmware/Main/SES/System/Cortex_M_Startup.s
===================================================================
--- /ctrl/firmware/Main/SES/System/Cortex_M_Startup.s	(revision 10)
+++ /ctrl/firmware/Main/SES/System/Cortex_M_Startup.s	(revision 10)
@@ -0,0 +1,316 @@
+/*********************************************************************
+*                    SEGGER Microcontroller GmbH                     *
+*                        The Embedded Experts                        *
+**********************************************************************
+*                                                                    *
+*            (c) 2014 - 2024 SEGGER Microcontroller GmbH             *
+*                                                                    *
+*       www.segger.com     Support: support@segger.com               *
+*                                                                    *
+**********************************************************************
+*                                                                    *
+* All rights reserved.                                               *
+*                                                                    *
+* Redistribution and use in source and binary forms, with or         *
+* without modification, are permitted provided that the following    *
+* condition is met:                                                  *
+*                                                                    *
+* - Redistributions of source code must retain the above copyright   *
+*   notice, this condition and the following disclaimer.             *
+*                                                                    *
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND             *
+* CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,        *
+* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF           *
+* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE           *
+* DISCLAIMED. IN NO EVENT SHALL SEGGER Microcontroller BE LIABLE FOR *
+* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR           *
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT  *
+* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;    *
+* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF      *
+* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT          *
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE  *
+* USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH   *
+* DAMAGE.                                                            *
+*                                                                    *
+**********************************************************************
+
+-------------------------- END-OF-HEADER -----------------------------
+
+File      : Cortex_M_Startup.s
+Purpose   : Generic startup and exception handlers for Cortex-M devices.
+
+Additional information:
+  Preprocessor Definitions
+    __NO_SYSTEM_INIT
+      If defined, 
+        SystemInit is not called.
+      If not defined,
+        SystemInit is called.
+        SystemInit is usually supplied by the CMSIS files.
+        This file declares a weak implementation as fallback.
+        
+    __SUPPORT_RESET_HALT_AFTER_BTL
+      If != 0
+        Support J-Link's reset strategy Reset and Halt After Bootloader.
+        https://wiki.segger.com/Reset_and_Halt_After_Bootloader
+      If == 0 (default),
+        Disable support for Reset and Halt After Bootloader.
+
+    __SOFTFP__
+      Defined by the build system.
+      If not defined, the FPU is enabled for floating point operations.
+*/
+
+        .syntax unified  
+
+        
+#ifndef   __SUPPORT_RESET_HALT_AFTER_BTL
+  #define __SUPPORT_RESET_HALT_AFTER_BTL  0
+#endif
+        
+/*********************************************************************
+*
+*       Macros
+*
+**********************************************************************
+*/
+//
+// Just place a vector (word) in the table
+//
+.macro VECTOR Name=
+        .section .vectors, "a"
+        .word \Name
+.endm
+//
+// Declare an interrupt handler
+//
+.macro ISR_HANDLER Name=
+        //
+        // Insert vector in vector table
+        //
+        .section .vectors, "a"
+        .word \Name
+        //
+        // Insert dummy handler in init section
+        //
+        .section .init.\Name, "ax"
+        .thumb_func
+        .weak \Name
+        .balign 2
+\Name:
+        1: b 1b   // Endless loop
+        END_FUNC \Name
+.endm
+
+//
+// Place a reserved vector in vector table
+//
+.macro ISR_RESERVED
+        .section .vectors, "a"
+        .word 0
+.endm
+
+//
+// Mark the end of a function and calculate its size
+//
+.macro END_FUNC name
+        .size \name,.-\name
+.endm
+
+/*********************************************************************
+*
+*       Global data
+*
+**********************************************************************
+*/
+/*********************************************************************
+*
+*  Setup of the vector table and weak definition of interrupt handlers
+*
+*/
+        .section .vectors, "a"
+        .code 16
+        .balign 4
+        .weak _vectors
+_vectors:
+        VECTOR __stack_end__
+        VECTOR Reset_Handler
+        ISR_HANDLER NMI_Handler
+        VECTOR HardFault_Handler
+        ISR_HANDLER MemManage_Handler 
+        ISR_HANDLER BusFault_Handler
+        ISR_HANDLER UsageFault_Handler
+        ISR_RESERVED
+        ISR_RESERVED
+        ISR_RESERVED
+        ISR_RESERVED
+        ISR_HANDLER SVC_Handler
+        ISR_HANDLER DebugMon_Handler
+        ISR_RESERVED
+        ISR_HANDLER PendSV_Handler
+        ISR_HANDLER SysTick_Handler
+        //
+        // Add external interrupt vectors here.
+        // Example:
+        //   ISR_HANDLER ExternalISR0
+        //   ISR_HANDLER ExternalISR1
+        //   ISR_HANDLER ExternalISR2
+        //   ISR_HANDLER ExternalISR3
+        //
+
+        .section .vectors, "a"
+        .size _vectors, .-_vectors
+_vectors_end:
+
+/*********************************************************************
+*
+*       Global functions
+*
+**********************************************************************
+*/
+/*********************************************************************
+*
+*       Reset_Handler
+*
+*  Function description
+*    Exception handler for reset.
+*    Generic bringup of a Cortex-M system.
+*
+*  Additional information
+*    The stack pointer is expected to be initialized by hardware,
+*    i.e. read from vectortable[0].
+*    For manual initialization add
+*      ldr R0, =__stack_end__
+*      mov SP, R0
+*/
+        .global reset_handler
+        .global Reset_Handler
+        .equ reset_handler, Reset_Handler
+        .section .init.Reset_Handler, "ax"
+        .balign 2
+        .thumb_func
+Reset_Handler:
+#if __SUPPORT_RESET_HALT_AFTER_BTL != 0
+        //
+        // Perform a dummy read access from address 0x00000008 followed by two nop's
+        // This is needed to support J-Links reset strategy: Reset and Halt After Bootloader.
+        // https://wiki.segger.com/Reset_and_Halt_After_Bootloader
+        //
+        movs    R0, #8
+        ldr     R0, [R0]
+        nop
+        nop
+#endif
+#ifdef __SEGGER_STOP
+        .extern __SEGGER_STOP_Limit_MSP
+        //
+        // Initialize main stack limit to 0 to disable stack checks before runtime init
+        //
+        movs    R0, #0
+        ldr     R1, =__SEGGER_STOP_Limit_MSP
+        str     R0, [R1]
+#endif
+#ifndef __NO_SYSTEM_INIT
+        //
+        // Call SystemInit
+        //
+        bl      SystemInit
+#endif
+#if !defined(__SOFTFP__)
+        //
+        // Enable CP11 and CP10 with CPACR |= (0xf<<20)
+        //
+        movw    R0, 0xED88
+        movt    R0, 0xE000
+        ldr     R1, [R0]
+        orrs    R1, R1, #(0xf << 20)
+        str     R1, [R0]
+#endif
+        //
+        // Call runtime initialization, which calls main().
+        //
+        bl      _start
+END_FUNC Reset_Handler
+
+        //
+        // Weak only declaration of SystemInit enables Linker to replace bl SystemInit with a NOP,
+        // when there is no strong definition of SystemInit.
+        //
+        .weak SystemInit
+
+/*********************************************************************
+*
+*       HardFault_Handler
+*
+*  Function description
+*    Simple exception handler for HardFault.
+*    In case of a HardFault caused by BKPT instruction without 
+*    debugger attached, return execution, otherwise stay in loop.
+*
+*  Additional information
+*    The stack pointer is expected to be initialized by hardware,
+*    i.e. read from vectortable[0].
+*    For manual initialization add
+*      ldr R0, =__stack_end__
+*      mov SP, R0
+*/
+
+#undef L
+#define L(label) .LHardFault_Handler_##label
+
+        .weak HardFault_Handler
+        .section .init.HardFault_Handler, "ax"
+        .balign 2
+        .thumb_func
+HardFault_Handler:
+        //
+        // Check if HardFault is caused by BKPT instruction
+        //
+        ldr     R1, =0xE000ED2C         // Load NVIC_HFSR
+        ldr     R2, [R1]
+        cmp     R2, #0                  // Check NVIC_HFSR[31]
+
+L(hfLoop):
+        bmi     L(hfLoop)               // Not set? Stay in HardFault Handler.
+        //
+        // Continue execution after BKPT instruction
+        //
+#if defined(__thumb__) && !defined(__thumb2__)
+        movs    R0, #4
+        mov     R1, LR
+        tst     R0, R1                  // Check EXC_RETURN in Link register bit 2.
+        bne     L(Uses_PSP)
+        mrs     R0, MSP                 // Stacking was using MSP.
+        b       L(Pass_StackPtr)
+L(Uses_PSP):
+        mrs     R0, PSP                 // Stacking was using PSP.
+L(Pass_StackPtr):
+#else
+        tst     LR, #4                  // Check EXC_RETURN[2] in link register to get the return stack
+        ite     eq
+        mrseq   R0, MSP                 // Frame stored on MSP
+        mrsne   R0, PSP                 // Frame stored on PSP
+#endif
+        //
+        // Reset HardFault Status
+        //
+#if defined(__thumb__) && !defined(__thumb2__)
+        movs    R3, #1
+        lsls    R3, R3, #31
+        orrs    R2, R3
+        str     R2, [R1]
+#else
+        orr R2, R2, #0x80000000
+        str R2, [R1]
+#endif
+        //
+        // Adjust return address
+        //
+        ldr     R1, [R0, #24]           // Get stored PC from stack
+        adds    R1, #2                  // Adjust PC by 2 to skip current BKPT
+        str     R1, [R0, #24]           // Write back adjusted PC to stack
+        //
+        bx      LR                      // Return
+END_FUNC HardFault_Handler
+
+/*************************** End of file ****************************/
Index: /ctrl/firmware/Main/SES/System/SEGGER_THUMB_Startup.s
===================================================================
--- /ctrl/firmware/Main/SES/System/SEGGER_THUMB_Startup.s	(revision 10)
+++ /ctrl/firmware/Main/SES/System/SEGGER_THUMB_Startup.s	(revision 10)
@@ -0,0 +1,288 @@
+/*********************************************************************
+*                    SEGGER Microcontroller GmbH                     *
+*                        The Embedded Experts                        *
+**********************************************************************
+*                                                                    *
+*            (c) 2014 - 2024 SEGGER Microcontroller GmbH             *
+*                                                                    *
+*       www.segger.com     Support: support@segger.com               *
+*                                                                    *
+**********************************************************************
+*                                                                    *
+* All rights reserved.                                               *
+*                                                                    *
+* Redistribution and use in source and binary forms, with or         *
+* without modification, are permitted provided that the following    *
+* condition is met:                                                  *
+*                                                                    *
+* - Redistributions of source code must retain the above copyright   *
+*   notice, this condition and the following disclaimer.             *
+*                                                                    *
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND             *
+* CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,        *
+* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF           *
+* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE           *
+* DISCLAIMED. IN NO EVENT SHALL SEGGER Microcontroller BE LIABLE FOR *
+* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR           *
+* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT  *
+* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;    *
+* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF      *
+* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT          *
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE  *
+* USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH   *
+* DAMAGE.                                                            *
+*                                                                    *
+**********************************************************************
+
+-------------------------- END-OF-HEADER -----------------------------
+
+File      : SEGGER_THUMB_Startup.s
+Purpose   : Generic runtime init startup code for ARM CPUs running 
+            in THUMB mode.
+            Designed to work with the SEGGER linker to produce 
+            smallest possible executables.
+            
+            This file does not normally require any customization.
+
+Additional information:
+  Preprocessor Definitions
+    FULL_LIBRARY
+      If defined then 
+        - argc, argv are set up by calling SEGGER_SEMIHOST_GetArgs().
+        - the exit symbol is defined and executes on return from main.
+        - the exit symbol calls destructors, atexit functions and then
+          calls SEGGER_SEMIHOST_Exit().
+    
+      If not defined then
+        - argc and argv are not valid (main is assumed to not take parameters)
+        - the exit symbol is defined, executes on return from main and
+          halts in a loop.
+*/
+
+        .syntax unified  
+
+/*********************************************************************
+*
+*       Defines, configurable
+*
+**********************************************************************
+*/
+
+#ifndef   APP_ENTRY_POINT
+  #define APP_ENTRY_POINT main
+#endif
+
+#ifndef   ARGSSPACE
+  #define ARGSSPACE 128
+#endif
+
+/*********************************************************************
+*
+*       Macros
+*
+**********************************************************************
+*/
+//
+// Declare a label as function symbol (without switching sections)
+//
+.macro MARK_FUNC Name
+        .global \Name
+        .thumb_func
+        .code 16
+\Name:
+.endm
+//
+// Declare a regular function.
+// Functions from the startup are placed in the init section.
+//
+.macro START_FUNC Name
+        .section .init.\Name, "ax"
+        .global \Name
+        .balign 2
+        .thumb_func
+        .code 16
+\Name:
+.endm
+
+//
+// Declare a weak function
+//
+.macro WEAK_FUNC Name
+        .section .init.\Name, "ax", %progbits
+        .weak \Name
+        .balign 2
+        .thumb_func
+        .code 16
+\Name:
+.endm
+
+//
+// Mark the end of a function and calculate its size
+//
+.macro END_FUNC name
+        .size \name,.-\name
+.endm
+
+/*********************************************************************
+*
+*       Externals
+*
+**********************************************************************
+*/
+        .extern APP_ENTRY_POINT     // typically main
+
+/*********************************************************************
+*
+*       Global functions
+*
+**********************************************************************
+*/
+/*********************************************************************
+*
+*       _start
+*
+*  Function description
+*    Entry point for the startup code. 
+*    Usually called by the reset handler.
+*    Performs all initialisation, based on the entries in the 
+*    linker-generated init table, then calls main().
+*    It is device independent, so there should not be any need for an 
+*    end-user to modify it.
+*
+*  Additional information
+*    At this point, the stack pointer should already have been 
+*    initialized 
+*      - by hardware (such as on Cortex-M),
+*      - by the device-specific reset handler,
+*      - or by the debugger (such as for RAM Code).
+*/
+#undef L
+#define L(label) .L_start_##label
+
+START_FUNC _start
+        //
+        // Call linker init functions which in turn performs the following:
+        // * Perform segment init
+        // * Perform heap init (if used)
+        // * Call constructors of global Objects (if any exist)
+        //
+        ldr     R4, =__SEGGER_init_table__      // Set table pointer to start of initialization table
+L(RunInit): 
+        ldr     R0, [R4]                        // Get next initialization function from table
+        adds    R4, R4, #4                      // Increment table pointer to point to function arguments
+        blx     R0                              // Call initialization function
+        b       L(RunInit)
+        //
+MARK_FUNC __SEGGER_init_done
+MARK_FUNC __startup_complete
+        //
+        // Time to call main(), the application entry point.
+        //
+#ifndef FULL_LIBRARY
+        //
+        // In a real embedded application ("Free-standing environment"), 
+        // main() does not get any arguments,
+        // which means it is not necessary to init R0 and R1.
+        //
+        bl      APP_ENTRY_POINT                 // Call to application entry point (usually main())
+
+END_FUNC _start
+        //
+        // end of _start
+        // Fall-through to exit if main ever returns.
+        //
+MARK_FUNC exit
+        //
+        // In a free-standing environment, if returned from application:
+        // Loop forever.
+        //
+        b       .
+        .size exit,.-exit
+#else
+        //
+        // In a hosted environment, 
+        // we need to load R0 and R1 with argc and argv, in order to handle 
+        // the command line arguments.
+        // This is required for some programs running under control of a 
+        // debugger, such as automated tests.
+        //
+        movs    R0, #ARGSSPACE
+        ldr     R1, =__SEGGER_init_arg_data
+        bl      SEGGER_SEMIHOST_GetArgs
+        ldr     R1, =__SEGGER_init_arg_data
+        bl      APP_ENTRY_POINT                 // Call to application entry point (usually main())
+        bl      exit                            // Call exit function
+        b       .                               // If we unexpectedly return from exit, hang.
+END_FUNC _start
+#endif
+        // 
+#ifdef FULL_LIBRARY
+/*********************************************************************
+*
+*       exit
+*
+*  Function description
+*    Exit of the system.
+*    Called on return from application entry point or explicit call 
+*    to exit.
+*
+*  Additional information
+*    In a hosted environment exit gracefully, by
+*    saving the return value,
+*    calling destructurs of global objects, 
+*    calling registered atexit functions, 
+*    and notifying the host/debugger.
+*/
+#undef L
+#define L(label) .L_exit_##label
+
+WEAK_FUNC exit
+        mov     R5, R0                  // Save the exit parameter/return result
+        //
+        // Call destructors
+        //
+        ldr     R0, =__dtors_start__    // Pointer to destructor list
+        ldr     R1, =__dtors_end__
+L(Loop):
+        cmp     R0, R1
+        beq     L(End)                  // Reached end of destructor list? => Done
+        ldr     R2, [R0]                // Load current destructor address into R2
+        adds    R0, R0, #4              // Increment pointer
+        push    {R0-R1}                 // Save R0 and R1
+        blx     R2                      // Call destructor
+        pop     {R0-R1}                 // Restore R0 and R1
+        b       L(Loop)
+L(End):
+        //
+        // Call atexit functions
+        //
+        bl      __SEGGER_RTL_execute_at_exit_fns
+        //
+        // Call debug_exit with return result/exit parameter
+        //
+        mov     R0, R5
+        //
+        // Entry points for _exit and _Exit, which terminate immediately.
+        // Note: Destructors and registered atexit functions are not called. File descriptors are not closed.
+        //
+MARK_FUNC _exit
+MARK_FUNC _Exit
+        bl      SEGGER_SEMIHOST_Exit
+        //
+        // If execution is not terminated, loop forever
+        //
+L(ExitLoop):
+        b       L(ExitLoop) // Loop forever.
+END_FUNC exit
+#endif
+
+#ifdef FULL_LIBRARY
+        .bss
+        .balign 4
+__SEGGER_init_arg_data:
+        .space ARGSSPACE
+        .size __SEGGER_init_arg_data, .-__SEGGER_init_arg_data
+        .type __SEGGER_init_arg_data, %object
+#endif
+
+/*************************** End of file ****************************/
Index: /ctrl/firmware/Main/SES/charger.emProject
===================================================================
--- /ctrl/firmware/Main/SES/charger.emProject	(revision 10)
+++ /ctrl/firmware/Main/SES/charger.emProject	(revision 10)
@@ -0,0 +1,86 @@
+<!DOCTYPE CrossStudio_Project_File>
+<solution Name="charger" version="2" target="8">
+  <configuration
+    Name="Debug"
+    c_preprocessor_definitions="DEBUG"
+    gcc_debugging_level="Level 3"
+    gcc_omit_frame_pointer="Yes"
+    gcc_optimization_level="None" />
+  <configuration
+    Name="Release"
+    c_preprocessor_definitions="NDEBUG"
+    gcc_debugging_level="Level 2"
+    gcc_omit_frame_pointer="Yes"
+    gcc_optimization_level="Level 2 balanced" />
+  <configuration
+    LIBRARY_HEAP_TYPE="Minimal"
+    LIBRARY_IO_TYPE="SEMIHOST (host-formatted)"
+    LIBRARY_LOCALES="Minimal"
+    Name="Release_MinSize"
+    arm_library_optimization="Small"
+    c_preprocessor_definitions="NDEBUG;__OPTIMIZATION_SMALL"
+    cpp_enable_exceptions="No"
+    gcc_debugging_level="None"
+    gcc_omit_frame_pointer="Yes"
+    gcc_optimization_level="Level 2 for size"
+    gcc_short_enum="Minimal Container Size"
+    libcxx="Yes (No Exceptions)"
+    link_dedupe_code="Yes"
+    link_dedupe_data="Yes"
+    link_merge_strings="Yes"
+    link_time_optimization="Yes"
+    linker_printf_fmt_level="int"
+    linker_printf_fp_enabled="No"
+    linker_printf_width_precision_supported="No" />
+  <project Name="charger">
+    <configuration
+      LIBRARY_IO_TYPE="RTT"
+      Name="Common"
+      Target="STM32H723ZETx"
+      arm_architecture="v7EM"
+      arm_compiler_variant="SEGGER"
+      arm_core_type="Cortex-M7"
+      arm_endian="Little"
+      arm_fp_abi="Hard"
+      arm_fpu_type="FPv5-D16"
+      arm_linker_heap_size="2048"
+      arm_linker_process_stack_size="0"
+      arm_linker_stack_size="2048"
+      arm_linker_variant="SEGGER"
+      arm_simulator_memory_simulation_parameter="RAM;0x00000000;0x00010000;ROM;0x08000000;0x00080000;RAM;0x20000000;0x00020000;RAM;0x24000000;0x00020000;RAM;0x30000000;0x00008000;RAM;0x38000000;0x00004000;RAM;0x38800000;0x00001000"
+      arm_target_device_name="STM32H723ZE"
+      arm_target_interface_type="SWD"
+      debug_register_definition_file="$(ProjectDir)/STM32H723_Registers.xml"
+      debug_stack_pointer_start="__stack_end__"
+      debug_target_connection="J-Link"
+      gcc_entry_point="Reset_Handler"
+      link_dedupe_code="Yes"
+      link_linker_script_file="Setup/SEGGER_Flash.icf"
+      linker_memory_map_file="$(ProjectDir)/STM32H723ZETx_MemoryMap.xml"
+      linker_output_format="hex"
+      linker_section_placements_segments="FLASH1 RX 0x00000000 0x00100000;RAM1 RWX 0x20000000 0x00010000"
+      macros="DeviceHeaderFile=$(PackagesDir)/STM32H7xx/Device/Include/stm32h7xx.h;DeviceSystemFile=$(PackagesDir)/STM32H7xx/Device/Source/system_stm32h7xx.c;DeviceVectorsFile=$(PackagesDir)/STM32H7xx/Source/stm32h723xx_Vectors.s;DeviceFamily=STM32H7xx;DeviceSubFamily=STM32H723"
+      project_directory=""
+      project_type="Executable" />
+    <configuration Name="Release" link_dedupe_code="Yes" />
+    <configuration
+      LIBRARY_IO_TYPE="SEMIHOST (host-formatted)"
+      Name="Release_MinSize" />
+    <folder Name="Core">
+      <folder Name="Inc">
+        <file file_name="../CubeMX/Core/Inc/main.h" />
+      </folder>
+      <folder Name="Src">
+        <file file_name="../CubeMX/Core/Src/main.c" />
+      </folder>
+    </folder>
+    <folder Name="Setup">
+      <file file_name="Setup/SEGGER_Flash.icf" />
+    </folder>
+    <folder Name="System">
+      <file file_name="System/Cortex_M_Startup.s" />
+      <file file_name="System/SEGGER_THUMB_Startup.s" />
+      <file file_name="STM32H7xx/Source/stm32h723xx_Vectors.s" />
+    </folder>
+  </project>
+</solution>