| 1 | /* USER CODE BEGIN Header */
|
|---|
| 2 | /**
|
|---|
| 3 | ******************************************************************************
|
|---|
| 4 | * @file dma.c
|
|---|
| 5 | * @brief This file provides code for the configuration
|
|---|
| 6 | * of all the requested memory to memory DMA transfers.
|
|---|
| 7 | ******************************************************************************
|
|---|
| 8 | * @attention
|
|---|
| 9 | *
|
|---|
| 10 | * Copyright (c) 2024 STMicroelectronics.
|
|---|
| 11 | * All rights reserved.
|
|---|
| 12 | *
|
|---|
| 13 | * This software is licensed under terms that can be found in the LICENSE file
|
|---|
| 14 | * in the root directory of this software component.
|
|---|
| 15 | * If no LICENSE file comes with this software, it is provided AS-IS.
|
|---|
| 16 | *
|
|---|
| 17 | ******************************************************************************
|
|---|
| 18 | */
|
|---|
| 19 | /* USER CODE END Header */
|
|---|
| 20 |
|
|---|
| 21 | /* Includes ------------------------------------------------------------------*/
|
|---|
| 22 | #include "dma.h"
|
|---|
| 23 |
|
|---|
| 24 | /* USER CODE BEGIN 0 */
|
|---|
| 25 |
|
|---|
| 26 | /* USER CODE END 0 */
|
|---|
| 27 |
|
|---|
| 28 | /*----------------------------------------------------------------------------*/
|
|---|
| 29 | /* Configure DMA */
|
|---|
| 30 | /*----------------------------------------------------------------------------*/
|
|---|
| 31 |
|
|---|
| 32 | /* USER CODE BEGIN 1 */
|
|---|
| 33 |
|
|---|
| 34 | /* USER CODE END 1 */
|
|---|
| 35 |
|
|---|
| 36 | /**
|
|---|
| 37 | * Enable DMA controller clock
|
|---|
| 38 | */
|
|---|
| 39 | void MX_DMA_Init(void)
|
|---|
| 40 | {
|
|---|
| 41 |
|
|---|
| 42 | /* DMA controller clock enable */
|
|---|
| 43 | __HAL_RCC_DMA1_CLK_ENABLE();
|
|---|
| 44 |
|
|---|
| 45 | /* DMA interrupt init */
|
|---|
| 46 | /* DMA1_Stream0_IRQn interrupt configuration */
|
|---|
| 47 | HAL_NVIC_SetPriority(DMA1_Stream0_IRQn, 5, 0);
|
|---|
| 48 | HAL_NVIC_EnableIRQ(DMA1_Stream0_IRQn);
|
|---|
| 49 | /* DMA1_Stream1_IRQn interrupt configuration */
|
|---|
| 50 | HAL_NVIC_SetPriority(DMA1_Stream1_IRQn, 5, 0);
|
|---|
| 51 | HAL_NVIC_EnableIRQ(DMA1_Stream1_IRQn);
|
|---|
| 52 | /* DMA1_Stream2_IRQn interrupt configuration */
|
|---|
| 53 | HAL_NVIC_SetPriority(DMA1_Stream2_IRQn, 5, 0);
|
|---|
| 54 | HAL_NVIC_EnableIRQ(DMA1_Stream2_IRQn);
|
|---|
| 55 | /* DMA1_Stream3_IRQn interrupt configuration */
|
|---|
| 56 | HAL_NVIC_SetPriority(DMA1_Stream3_IRQn, 5, 0);
|
|---|
| 57 | HAL_NVIC_EnableIRQ(DMA1_Stream3_IRQn);
|
|---|
| 58 | /* DMA1_Stream4_IRQn interrupt configuration */
|
|---|
| 59 | HAL_NVIC_SetPriority(DMA1_Stream4_IRQn, 5, 0);
|
|---|
| 60 | HAL_NVIC_EnableIRQ(DMA1_Stream4_IRQn);
|
|---|
| 61 | /* DMA1_Stream5_IRQn interrupt configuration */
|
|---|
| 62 | HAL_NVIC_SetPriority(DMA1_Stream5_IRQn, 5, 0);
|
|---|
| 63 | HAL_NVIC_EnableIRQ(DMA1_Stream5_IRQn);
|
|---|
| 64 |
|
|---|
| 65 | }
|
|---|
| 66 |
|
|---|
| 67 | /* USER CODE BEGIN 2 */
|
|---|
| 68 |
|
|---|
| 69 | /* USER CODE END 2 */
|
|---|
| 70 |
|
|---|
